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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , , Jiri Pirko , Amit Cohen , Simon Horman Subject: [PATCH net v2 1/3] mlxsw: core: Unregister EMAD trap using FORWARD action Date: Thu, 18 Apr 2024 15:46:06 +0200 Message-ID: <753a89e14008fde08cb4a2c1e5f537b81d8eb2d6.1713446092.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AC:EE_|MN2PR12MB4205:EE_ X-MS-Office365-Filtering-Correlation-Id: ab809236-a77d-4c7e-954a-08dc5fae49b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 68JgVCA2kUqq2i/dCY0TmA+kio98z0DeJ55nO79HywR+vVk/v4zjelrUWgVmuo4Gsi6X+KCIhYWvpdTh5FMQiCRk8ej2fOcZFYCPIlyWf55e6UIWJ6PzO5tcrJVGKFEwi3abu2uB852jYsZ0Q+MDIN0BVK/6113l+uycNq3ZhHRMKZnRUjVyUGQCiG76tTPPO7Ocw65RXIctyG9Xseokye0M9DJo1OP0/yxUEYtoIrn9ZbJEaz/lSmFOQ/D4uWPku8tWo3VcfibnBaz86wmMOeLBcoS1R10B26vJS72YuxlQDJ0Za+EC15un5SeJe9LErs200SSxbHFTTXLkVWUVUSCTS8lo1qAzITcrswXablt+XjFn6Ss/shrBygpNmgjRDKpfRErCU7BxIiPkT2UXr+e4IqgeSG5yjwyLXCYOq3dJAZZnYCvZ4Q3u5O5cL4kYJkkPn3vvfPc9icoYUkNrpTOxEYjOzOKVit6aXAfBmbPPKFItcreuV3pev+gvl2CPte76TuYwj3fOF4l7V0J1qVR15GAUsXyqWexOfZU9Vkx+Gt9BXyiEEPTp9qkykHfG3kWfW8ZmibKcyytCKZx8zWBWLukaz2T8C80VjXTSgPj0hfjh3tLDBlChGYFqkEDzNIXWSCBVyRmpCodE2DwM2sQe1l5UaNhVNeU8GBUmbx9IMBSyxq8IuiYSnGM8ZR81OLwWCJgtIEah5+gLDOZYs+IFoptNlyCrgf6Q5l/tO+6IO0tUL8KuiOQGgNzqHKvk X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(82310400014)(1800799015)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2024 13:48:54.4208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab809236-a77d-4c7e-954a-08dc5fae49b9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4205 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel The device's manual (PRM - Programmer's Reference Manual) classifies the trap that is used to deliver EMAD responses as an "event trap". Among other things, it means that the only actions that can be associated with the trap are TRAP and FORWARD (NOP). Currently, during driver de-initialization the driver unregisters the trap by setting its action to DISCARD, which violates the above guideline. Future firmware versions will prevent such misuses by returning an error. This does not prevent the driver from working, but an error will be printed to the kernel log during module removal / devlink reload: mlxsw_spectrum 0000:03:00.0: Reg cmd access status failed (status=7(bad parameter)) mlxsw_spectrum 0000:03:00.0: Reg cmd access failed (reg_id=7003(hpkt),type=write) Suppress the error message by aligning the driver to the manual and use a FORWARD (NOP) action when unregistering the trap. Fixes: 4ec14b7634b2 ("mlxsw: Add interface to access registers and process events") Cc: Jiri Pirko Cc: Amit Cohen Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Reviewed-by: Simon Horman Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c index e4d7739bd7c8..4a79c0d7e7ad 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core.c @@ -849,7 +849,7 @@ static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u16 local_port, static const struct mlxsw_listener mlxsw_emad_rx_listener = MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, - EMAD, DISCARD); + EMAD, FORWARD); static int mlxsw_emad_tlv_enable(struct mlxsw_core *mlxsw_core) { From patchwork Thu Apr 18 13:46:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13634773 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2068.outbound.protection.outlook.com [40.107.93.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6338F1635C5 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , , Simon Horman , Tim 'mithro' Ansell Subject: [PATCH net v2 2/3] mlxsw: core_env: Fix driver initialization with old firmware Date: Thu, 18 Apr 2024 15:46:07 +0200 Message-ID: <0afa8b2e8bac178f5f88211344429176dcc72281.1713446092.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|BL1PR12MB5851:EE_ X-MS-Office365-Filtering-Correlation-Id: fe50a6e0-e11d-4063-6e46-08dc5fae47f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pLwOIyBAch86oyI+oADUKuDOkXfRiGQ3bSQWd8gscvpw5BjzSBSfNBUx+4qES7/kmqYfyMedJRpTGwsn6uRrhWc4mifpSNSgs31byPkxTNLpKAAdZuMTY+X0Xmy26jrnKXrX21l+4NRfc8Q7TBH2TEKRaIC8887mR9RlB5py5bF38O1shfR60eTM9S0jXPQ+IXH7ioKEGqGhgZBO//CoYy9jboID9BRlLlDEdql9Y3OSzEtOyx7dYNjfOiGV767HSftV0xnGCeKfddzqf+CKnXqOGo78WsCvBTAPe6UJ5QI/aj5OFSW8J7tDXGyW83+gUiXRrlBjZuYvr1swSM2/FSAH6RNoatEqJEq2Fvbo+TpUmpAIyrxMjeJ4XRWEwTCMg0I9mAhMlR4qHeRCiii+DQU5g+L4VmcgA+Y9xf3bX9AcVZ2zMW3ev89b1sOPQJj+gPpfvEktXR618+Tm3QElgPuoQ0ruX5QMmmgqXvm5zWQHxdWmSXkgtNleGfFRbGXTd1GEMqj2evHgkri3tok+RSlTlpJU/O5UIEHXJ/BE8FTbK2gnN+R30pB+bqeyNQaMBkbknUz+lWnLNCzv/q6YhwRqM7eJKjGBjOZ2ASs2SL1rvNoaKdoce11iFZL9uTjspZt8k+G7B09jyWb0LD8yKOq6+pdFmjGtBrzQWTlmHKHPMbDfqYhriQeG9JSAIeDvkcUeEsh/4ZhxhgMMW94U6WI8vjY2+J1+ahr063/W+aJnRCzrjAYJPgsYGq4AQTW2 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(82310400014)(376005)(36860700004)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2024 13:48:51.3623 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe50a6e0-e11d-4063-6e46-08dc5fae47f0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5851 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel The driver queries the Management Capabilities Mask (MCAM) register during initialization to understand if it can read up to 128 bytes from transceiver modules. However, not all firmware versions support this register, leading to the driver failing to load. Fix by treating an error in the register query as an indication that the feature is not supported. Fixes: 1f4aea1f72da ("mlxsw: core_env: Read transceiver module EEPROM in 128 bytes chunks") Cc: Simon Horman Reported-by: Tim 'mithro' Ansell Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- Notes: v2: - Make mlxsw_env_max_module_eeprom_len_query() void .../net/ethernet/mellanox/mlxsw/core_env.c | 20 ++++++------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_env.c b/drivers/net/ethernet/mellanox/mlxsw/core_env.c index 53b150b7ae4e..6c06b0592760 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core_env.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core_env.c @@ -1357,24 +1357,20 @@ static struct mlxsw_linecards_event_ops mlxsw_env_event_ops = { .got_inactive = mlxsw_env_got_inactive, }; -static int mlxsw_env_max_module_eeprom_len_query(struct mlxsw_env *mlxsw_env) +static void mlxsw_env_max_module_eeprom_len_query(struct mlxsw_env *mlxsw_env) { char mcam_pl[MLXSW_REG_MCAM_LEN]; - bool mcia_128b_supported; + bool mcia_128b_supported = false; int err; mlxsw_reg_mcam_pack(mcam_pl, MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES); err = mlxsw_reg_query(mlxsw_env->core, MLXSW_REG(mcam), mcam_pl); - if (err) - return err; - - mlxsw_reg_mcam_unpack(mcam_pl, MLXSW_REG_MCAM_MCIA_128B, - &mcia_128b_supported); + if (!err) + mlxsw_reg_mcam_unpack(mcam_pl, MLXSW_REG_MCAM_MCIA_128B, + &mcia_128b_supported); mlxsw_env->max_eeprom_len = mcia_128b_supported ? 128 : 48; - - return 0; } int mlxsw_env_init(struct mlxsw_core *mlxsw_core, @@ -1445,15 +1441,11 @@ int mlxsw_env_init(struct mlxsw_core *mlxsw_core, if (err) goto err_type_set; - err = mlxsw_env_max_module_eeprom_len_query(env); - if (err) - goto err_eeprom_len_query; - + mlxsw_env_max_module_eeprom_len_query(env); env->line_cards[0]->active = true; return 0; -err_eeprom_len_query: err_type_set: mlxsw_env_module_event_disable(env, 0); err_mlxsw_env_module_event_enable: From patchwork Thu Apr 18 13:46:08 2024 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , , Tim 'mithro' Ansell , Simon Horman , Kalesh AP Subject: [PATCH net v2 3/3] mlxsw: pci: Fix driver initialization with old firmware Date: Thu, 18 Apr 2024 15:46:08 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A0:EE_|SN7PR12MB8003:EE_ X-MS-Office365-Filtering-Correlation-Id: b26ae776-4b66-46f4-974d-08dc5fae4c8b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: myrGi9aupow5ahrdVuBnedQw1Y3dJ1g5LEyYHg8rwxYUrI8r4iH3mBR2Yy4vqnvhjfhqhdXDFmOL5uS+p0DTglLyTQPJRj041uH5p59OB0O+5E0usm+Lxoa8uS1NFi0ztvRSqbsvkG09D4aX0BKi+4HTbjCsD1NEcyJgfddBSjU95bBlaPDRexy1VSexDNY2OAiCZj3+0omlQruVEkX9lPh1SAGvxK5jyCLi4VYId8HZXgYK3R1tyEbYhwwVcV2AZJqT388DDNzZPGLXJwpNy7gwLFBflBNhkPzXjVMEjIZFt6hmoHHjsSJkN5q2R6F8FTULWIrr219ajWgqTE4yGH3gR8/qemF8yTh9jcYC6fIqygLoQln445Sdxkx5itqn51Tw+kAoJFOreP71ZZuujMLjCyaYA5WBDyTPCJZeuvdrn1wLNdty04/aYQ3G3W5OPU++BuAEuN/EfVFk+t2iesTJayFA4r+ne9FikxJdyGQGYT6QPWiw09RpIRTzIVkuQbJ0RMpUpZru+AxubxVGHjuAuh1pvANwiRM1yRk9yMK/hpaoWIvgwE3rxaoXwESSxnhGMB2EVdoHFFSE+S0K1yX17I+HRVvt2vyTPYldGfBi3LzefgXjJF0Oyu+ZIH78gv5JcdVSLqB6md1QzC7cZe1fcOnEG5ind/xli9sg5oPtZQaWWKj50+TlfpywhSZD+noGrO00g0cMIGPP/VAxY1Kq1HQETDdD7EFq2N3jNeGK9KNkhXJqui5vHte0NJtk X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(36860700004)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2024 13:48:59.0901 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b26ae776-4b66-46f4-974d-08dc5fae4c8b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8003 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel The driver queries the Management Capabilities Mask (MCAM) register during initialization to understand if a new and deeper reset flow is supported. However, not all firmware versions support this register, leading to the driver failing to load. Fix by treating an error in the register query as an indication that the feature is not supported. Fixes: f257c73e5356 ("mlxsw: pci: Add support for new reset flow") Reported-by: Tim 'mithro' Ansell Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Reviewed-by: Simon Horman Reviewed-by: Kalesh AP Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 4d617057af25..13fd067c39ed 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -1545,7 +1545,7 @@ mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) { struct pci_dev *pdev = mlxsw_pci->pdev; char mcam_pl[MLXSW_REG_MCAM_LEN]; - bool pci_reset_supported; + bool pci_reset_supported = false; u32 sys_status; int err; @@ -1563,11 +1563,9 @@ mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) mlxsw_reg_mcam_pack(mcam_pl, MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES); err = mlxsw_reg_query(mlxsw_pci->core, MLXSW_REG(mcam), mcam_pl); - if (err) - return err; - - mlxsw_reg_mcam_unpack(mcam_pl, MLXSW_REG_MCAM_PCI_RESET, - &pci_reset_supported); + if (!err) + mlxsw_reg_mcam_unpack(mcam_pl, MLXSW_REG_MCAM_PCI_RESET, + &pci_reset_supported); if (pci_reset_supported) { pci_dbg(pdev, "Starting PCI reset flow\n");