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Change "clocks" and "clock-names" properties to allow for this case. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/dsp/fsl,dsp.yaml | 51 ++++++++++++++----- 1 file changed, 39 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml index 9af40da5688e..4a39d57b1cc6 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -30,22 +30,12 @@ properties: maxItems: 1 clocks: - items: - - description: ipg clock - - description: ocram clock - - description: core clock - - description: debug interface clock - - description: message unit clock minItems: 3 + maxItems: 5 clock-names: - items: - - const: ipg - - const: ocram - - const: core - - const: debug - - const: mu minItems: 3 + maxItems: 5 power-domains: description: @@ -93,6 +83,43 @@ required: - memory-region allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8ulp-hifi4 + then: + properties: + clocks: + items: + - description: ipg clock + - description: ocram clock + - description: core clock + - description: message unit clock + clock-names: + items: + - const: ipg + - const: ocram + - const: core + - const: mu + else: + properties: + clocks: + items: + - description: ipg clock + - description: ocram clock + - description: core clock + - description: debug interface clock + - description: message unit clock + minItems: 3 + clock-names: + items: + - const: ipg + - const: ocram + - const: core + - const: debug + - const: mu + minItems: 3 - if: properties: compatible: From patchwork Thu Apr 18 20:37:19 2024 Content-Type: text/plain; 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Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- .../bindings/mfd/fsl,imx8ulp-avd-sim.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8ulp-avd-sim.yaml diff --git a/Documentation/devicetree/bindings/mfd/fsl,imx8ulp-avd-sim.yaml b/Documentation/devicetree/bindings/mfd/fsl,imx8ulp-avd-sim.yaml new file mode 100644 index 000000000000..4020c6e37f80 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/fsl,imx8ulp-avd-sim.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/fsl,imx8ulp-avd-sim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP Audio-Video Domain System Integration Module + +maintainers: + - Liu Ying + +description: | + The AVD-SIM module provides configuration options for components of AVD. + +properties: + compatible: + items: + - const: fsl,imx8ulp-avd-sim + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + avd_sim: syscon@2da50000 { + compatible = "fsl,imx8ulp-avd-sim", "syscon", "simple-mfd"; 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Thu, 18 Apr 2024 13:38:22 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Daniel Baluta , Shengjiu Wang , Liu Ying Cc: Laurentiu Mihalcea , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] arm64: dts: imx8ulp: add DSP node Date: Thu, 18 Apr 2024 23:37:20 +0300 Message-Id: <20240418203720.8492-4-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240418203720.8492-1-laurentiumihalcea111@gmail.com> References: <20240418203720.8492-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Laurentiu Mihalcea Add node for i.MX8ULP's DSP core and its dependencies. Signed-off-by: Shengjiu Wang Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 39 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 22 +++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 24bb253b938d..5dadcbba370d 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -67,6 +67,32 @@ vdevbuffer: vdevbuffer@a8400000 { reg = <0 0xa8400000 0 0x100000>; no-map; }; + + dsp_reserved: dsp_reserved@8e000000 { + reg = <0 0x8e000000 0 0x1000000>; + no-map; + }; + + dsp_reserved_heap: dsp_reserved_heap@8f000000 { + reg = <0 0x8f000000 0 0xef0000>; + no-map; + }; + + dsp_vdev0vring0: vdev0vring0@8fef0000 { + reg = <0 0x8fef0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: vdev0vring1@8fef8000 { + reg = <0 0x8fef8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: vdev0buffer@8ff00000 { + compatible = "shared-dma-pool"; + reg = <0 0x8ff00000 0 0x100000>; + no-map; + }; }; clock_ext_rmii: clock-ext-rmii { @@ -95,6 +121,15 @@ &cm33 { status = "okay"; }; +&dsp { + assigned-clocks = <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0>; + assigned-clock-rates = <0>, <475200000>; + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status = "okay"; +}; + &flexspi2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_flexspi2_ptd>; @@ -176,6 +211,10 @@ &mu { status = "okay"; }; +&mu3 { + status = "okay"; +}; + &iomuxc1 { pinctrl_enet: enetgrp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index c4a0082f30d3..99ed8c1ee57c 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -198,6 +198,22 @@ soc: soc@0 { ranges = <0x0 0x0 0x0 0x40000000>, <0x60000000 0x0 0x60000000 0x1000000>; + dsp: dsp@21170000 { + compatible = "fsl,imx8ulp-hifi4"; + reg = <0x21170000 0x20000>; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&pcc5 IMX8ULP_CLK_MU3_B>; + clock-names = "ipg", "ocram", "core", "mu"; + power-domains = <&scmi_devpd IMX8ULP_PD_HIFI4>; + firmware-name = "imx/dsp/hifi4.bin"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu3 0 0>, <&mu3 1 0>, <&mu3 3 0>; + fsl,dsp-ctrl = <&avd_sim>; + status = "disabled"; + }; + s4muap: mailbox@27020000 { compatible = "fsl,imx8ulp-mu-s4"; reg = <0x27020000 0x10000>; @@ -520,6 +536,12 @@ per_bridge5: bus@2d800000 { #size-cells = <1>; ranges; + avd_sim: syscon@2da50000 { + compatible = "fsl,imx8ulp-avd-sim", "syscon", "simple-mfd"; + reg = <0x2da50000 0x38>; + clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>;