From patchwork Fri Apr 19 08:16:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 764CBC04FFF for ; Fri, 19 Apr 2024 08:17:57 +0000 (UTC) Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) by mx.groups.io with SMTP id smtpd.web10.15280.1713514667101796297 for ; Fri, 19 Apr 2024 01:17:47 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=jBbOwi8W; spf=pass (domain: tuxon.dev, ip: 209.85.208.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-565c6cf4819so5006940a12.1 for ; Fri, 19 Apr 2024 01:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514665; x=1714119465; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+1amMR8EPWpnlnfA7KuX/3/FmNZgNSEd9tib+5jAE4o=; b=jBbOwi8WM9JT0/GObKrmwPehsG3qDdH9QukHYaNJCHD1bs1bN4DHjDX9AZ7NNiyCDK X2DbbUI5RyrAc+/G9a/mWKryPuk9YuyGDbRcvzkSYVxvFj3AxdWYfvG1gaczvFOq/1+F itVqkUsgS/lpPt7d9XfRBVkfzIGaIUVJHrSVgMpVAGeF0+QpzHqW76oGXL2VIiy3Rdxp HYkaP+PNch+Q5+0pnZIf2H7YN6+TaB/yMIAix0vsVk+msJenvzJk6+np9nOz8I7Nw4qA jc5VEKDCEqUoIqP8VPTLP0NZnDvdlXyec8BiMzscad+gdKukC3VpO65AgFmBecw1FzYJ jQKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514665; x=1714119465; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+1amMR8EPWpnlnfA7KuX/3/FmNZgNSEd9tib+5jAE4o=; b=hW74nxkrWFxciPg12BgDD2f0avsFLhvHkVmcT8RAFrE88fG1X7M7hYMW6CzryyQva3 0KeXnTDs4hGtddIc7t9HL/s3w5XfVdn2YmLv5p93WkcGDtnZMaZ/bEKPT5tzHyvjgfil 2UKAqRD67rTDraX+s75ruLEUA0gOWJ1trUamrwekVXNRgoScef9I4LYrdv4b4Lm+iU3R f4N2DRkpdCLeYsUJgtfOspn0XZOs+aEDBg/vx4HM0zLVM4WioMcj73UrWCo5ZFFp2JSe 4/6TWmKjRYXiaUp6PHqbxyTk4MU2gvsWI959G8lvTq1fJZKDj7FP7muaTyJzlChKoiuq qqFg== X-Gm-Message-State: AOJu0Yw+BgKxGvILDwX9Uiz//xPqrareBV2n0gphCBhyQRX4wRPxBoQn M7TFgFWGjnaepKLCyjMwTJd05VywN8XEQo7CK00qBbkVETjgJ3L8A6Xd8xipRSU= X-Google-Smtp-Source: AGHT+IH+1vdx2W9NNaq/5dy+9v6otHDBNVsvmReEJIraxEZVyuhGIaDZKVeUkyhWtUC2n2dLAKHN8Q== X-Received: by 2002:a17:906:3ad1:b0:a52:54f2:6d0 with SMTP id z17-20020a1709063ad100b00a5254f206d0mr1397391ejd.15.1713514665221; Fri, 19 Apr 2024 01:17:45 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:44 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 01/53] clk: renesas: rzg2l: Wait for status bit of SD mux before continuing Date: Fri, 19 Apr 2024 11:16:50 +0300 Message-Id: <20240419081742.3496709-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:17:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15588 From: Claudiu Beznea commit 549f4ae2601f968e2474c6031fb4799468882f64 upstream. The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf, chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL for SD clock switching status. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-3-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 77513ceaaf2d..da81059d4bd8 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -192,7 +192,8 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) u32 off = GET_REG_OFFSET(hwdata->conf); u32 shift = GET_SHIFT(hwdata->conf); const u32 clk_src_266 = 2; - u32 bitmask; + u32 msk, val, bitmask; + int ret; /* * As per the HW manual, we should not directly switch from 533 MHz to @@ -206,14 +207,10 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) * the index to value mapping is done by adding 1 to the index. */ bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16; + msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; if (index != clk_src_266) { - u32 msk, val; - int ret; - writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off); - msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val, !(val & msk), 100, CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); @@ -225,7 +222,13 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) writel(bitmask | ((index + 1) << shift), priv->base + off); - return 0; + ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val, + !(val & msk), 100, + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); + if (ret) + dev_err(priv->dev, "failed to switch clk source\n"); + + return ret; } static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) From patchwork Fri Apr 19 08:16:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74FB7C4345F for ; Fri, 19 Apr 2024 08:17:57 +0000 (UTC) Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) by mx.groups.io with SMTP id smtpd.web11.15252.1713514670162408090 for ; Fri, 19 Apr 2024 01:17:50 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=XKc0lE7A; spf=pass (domain: tuxon.dev, ip: 209.85.218.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-a4715991c32so186129666b.1 for ; Fri, 19 Apr 2024 01:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514668; x=1714119468; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=im9BhV8e+mg0Pd+K2yFeYFHTd+RD8vwsP2TzyvVWPV4=; b=XKc0lE7AW7ns3/kvbKEf9I4s+v8KLx2H3KjmhzBS1JpYE7NH4y8VKScOxDQffIvCMr dl0yJPghL93fZc8GD1BR8YRzzKv8ohYrnXKbVZA5n5hCJJcbtiNWcMllRBl8USA8gyRG wcTExlq17Ho7N1FU8LlPJ+v5dtq2wyijrL0htZgU7BY/Eg34vNN+fXJxg/xIldrpuZKY tbNLLmxVqKy8rERb1DxmbT/rPngbEQsL2raPg0vC99XSbTJShHC9kfI3Dc794eGsFloT MyPn1IBUYVaI7PE0/bkEYIggtAcrI2SqpqIF73VTydtKa411+H/y5St4n7F1zDQqtZvs h6gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514668; x=1714119468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=im9BhV8e+mg0Pd+K2yFeYFHTd+RD8vwsP2TzyvVWPV4=; b=FgFA2MHOSVicYUIQI5KmJipaBnUvNqs3CNfeEaDW1Xh28RSjzMIHTl16XFJOp26hx9 qrYGWO2MTWZO77P9DYy2S4vtfcl1AZ5fPxXUB4t4v6+1Fg1ZmssNHn+2MyHq1lmSJHd3 jMKAxlW34hhlfdxRkIB21mM1qaddn66rIc6b2aRgKs0o0UW0z+uvGyRNzj5LSCIiYp+D P/eveTu/yzfecaUiOsd2fd9i4SIHYjB6A5bS+KlSe+/wAt5CsNwDDD0Bn4+/XGh8kmkI PED5Og+nxW7QNfVEIm85GWECM9KwtgSUyBwnmi8qGKDqHp+uFz2XbiVztXkrU+8BqijU 1c3g== X-Gm-Message-State: AOJu0YyTHBg1ot4JgPz53PrTZ5+/vq+m/PN55aIrKqAw/ap2w03nr8VW PDXnZ2pwuvuxMAimJr4gvj3shfTjDXhlDHyq3kpJGr+Sx735hMlM4XUeFZKafr0= X-Google-Smtp-Source: AGHT+IGC0lXmdUNw3fnT95mVo1NhOY8lx9BkXrJcseuHT3HmOcJRXHW+TFSn0MnWThVMXdH4jkpFlg== X-Received: by 2002:a17:906:4555:b0:a52:5460:a1d1 with SMTP id s21-20020a170906455500b00a525460a1d1mr1032816ejq.60.1713514668640; Fri, 19 Apr 2024 01:17:48 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:48 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 02/53] clk: renesas: rzg2l: Lock around writes to mux register Date: Fri, 19 Apr 2024 11:16:51 +0300 Message-Id: <20240419081742.3496709-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:17:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15589 From: Claudiu Beznea commit d2692ed490e680a41401cef879adebcfafb4298f upstream. The SD MUX output (SD0) is further divided by 4 in G2{L,UL}. The divided clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which means a rate request for it is propagated to the MUX and could reach rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0. Add proper locking to avoid concurrent accesses on SD MUX set rate registers. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-4-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 23 +++++++++++++---------- drivers/clk/renesas/rzg2l-cpg.h | 2 +- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index da81059d4bd8..fcbb0e2d2123 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -193,6 +193,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) u32 shift = GET_SHIFT(hwdata->conf); const u32 clk_src_266 = 2; u32 msk, val, bitmask; + unsigned long flags; int ret; /* @@ -208,23 +209,25 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) */ bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16; msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; + spin_lock_irqsave(&priv->rmw_lock, flags); if (index != clk_src_266) { writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off); - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val, - !(val & msk), 100, - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); - if (ret) { - dev_err(priv->dev, "failed to switch clk source\n"); - return ret; - } + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val, + !(val & msk), 10, + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); + if (ret) + goto unlock; } writel(bitmask | ((index + 1) << shift), priv->base + off); - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val, - !(val & msk), 100, - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val, + !(val & msk), 10, + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); +unlock: + spin_unlock_irqrestore(&priv->rmw_lock, flags); + if (ret) dev_err(priv->dev, "failed to switch clk source\n"); diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index b33a3e79161b..aefa53a90059 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -43,7 +43,7 @@ #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) -#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000 +#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 200 /* n = 0/1/2 for PLL1/4/6 */ #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) From patchwork Fri Apr 19 08:16:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83EC8C04FF6 for ; Fri, 19 Apr 2024 08:17:57 +0000 (UTC) Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) by mx.groups.io with SMTP id smtpd.web10.15281.1713514671815579808 for ; Fri, 19 Apr 2024 01:17:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=nUXL1ONO; spf=pass (domain: tuxon.dev, ip: 209.85.167.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-51abd9fcbf6so638075e87.1 for ; Fri, 19 Apr 2024 01:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514670; x=1714119470; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N44mTATHDnjbI2lgGO1YblTU01V/FkQm4BHSFQHsSd4=; b=nUXL1ONOjY+OEL3+zL2Eq4rErRang8nfGXhYbOu4OeOclfnoCYEHKyxjHCXcSuRq8r JhAgidKV0/aXd2a1hklaj2cR2w36NSdNdp7xXsn+4962B6tQ49JhwhkPvgLzjyCL54RD 1xJZOnp0hSFt4flW+9FotVLAz+0J0ImvxK+W9C4Eq3AB0BABAbwqXdHYgGOH11c3auhW SE6/+nwYmgbZPkd4WrhZrzoWmc8sTdFyp6+pW8Ss/27MCy3+tclWDhXsBfrF92uQ69CT 1hX+hGURPcJHa4TKm2pYNTXmCDxYVsIaRtqEoQBtSyJh60AE0uLUjtN6SSc9+hGiQyfP hdew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514670; x=1714119470; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N44mTATHDnjbI2lgGO1YblTU01V/FkQm4BHSFQHsSd4=; b=aF3GImMYg+iYYkBJ7ylMmWvrP2MmhZbtHgEoEYQ7u0+QoHMrdKPA4wtf+QF/i5kWFZ MDWsh+vlM3qHqq4kztBO5lFW8pKIZnPRKIhPKzuErLF/P2syKOTsoIOEBbFfNRXrbR+g ztX28ZJAthaA7jwWfbuEPjdBlHRdwj8jA+7pvczirkBktWpBt1c7AV7TI4RIldqh+3FH NnpOxGQ4VAHL4sfPaLkrNj/johUhyRSHNJmzXZohCvqe62vqyr6ViNgcdVF1qBPdNG90 p5L+b1kwXcNnJouwZs1wGvUFpNpgb0FkRCvG0i/XG/2UWYDuXnWqtG9IUNxLZ/+t1x+J fFHA== X-Gm-Message-State: AOJu0YzaS6p9j7ViAMuh0sMMEZqSKfWg6RTZyl3cChYBNNeVZX0Grsw8 R6ezmHXrVboeEWeJ0RksPrXQTuBuObu9mQCSCiFSAw4k3bYqbqy2GwEVKvpjFOs= X-Google-Smtp-Source: AGHT+IG/LXcBSjrbZYNRYYuDADQb6gSzZZ398Ccu5VLB4Y64SupFhTxkURcTRAGLcLjvTFdJCemGxw== X-Received: by 2002:ac2:5bcd:0:b0:515:9c73:e29a with SMTP id u13-20020ac25bcd000000b005159c73e29amr1020551lfn.66.1713514669741; Fri, 19 Apr 2024 01:17:49 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:49 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 03/53] clk: renesas: rzg2l: Trust value returned by hardware Date: Fri, 19 Apr 2024 11:16:52 +0300 Message-Id: <20240419081742.3496709-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:17:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15590 From: Claudiu Beznea commit bf51d3b2d048c312764a55d91d67a85ee5535e31 upstream. The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. The hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that setting 0 is prohibited. Hence rzg2l_cpg_sd_clk_mux_get_parent() should just read CPG_PL2SDHI_DSEL, trust the value, and return the proper clock parent index based on the value read. Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-5-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index fcbb0e2d2123..330aa67fdab2 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -242,14 +242,8 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) val >>= GET_SHIFT(hwdata->conf); val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0); - if (val) { - val--; - } else { - /* Prohibited clk source, change it to 533 MHz(reset value) */ - rzg2l_cpg_sd_clk_mux_set_parent(hw, 0); - } - return val; + return val ? val - 1 : 0; } static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = { From patchwork Fri Apr 19 08:16:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FC26C41513 for ; Fri, 19 Apr 2024 08:17:57 +0000 (UTC) Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) by mx.groups.io with SMTP id smtpd.web10.15282.1713514672691968675 for ; Fri, 19 Apr 2024 01:17:53 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=KoIrbsr8; spf=pass (domain: tuxon.dev, ip: 209.85.218.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a5252e5aa01so215413966b.1 for ; Fri, 19 Apr 2024 01:17:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514671; x=1714119471; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qzUnqoqllAeG5Q4s0FFdN3G4tgjxxEE0jZzDkFXGTm0=; b=KoIrbsr8i3HyV5dUZytVX65phk7qeqHFpunwPqs2S2XFPBwlTx/uy1PCtxX/NT8pkL G7QT3JLdZhRW6Hs5cKvz0Aolw/WNlF9vpaM1IyeyFGUwT9M8zCKBr7o/CvGfuXD+0CNK mcCfSKD6Dw6XEsgH8lRaUlmTa7nORrI4oLtBEZDTBvAgrIqyN8vldJiDsIjY955CDg87 /6qYjRLD2xPia5SyiJzDG99ZFDmS7sazek7IQpkdq95lQHye9JBTe3VrMGxPwQvLMw1W u54jCBdhofOv6tVMtGSCf2feKg/jiz/nVLCV+7FOIyoGg0Qeh+IQVj19XCu2dVCfDX17 yprg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514671; x=1714119471; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qzUnqoqllAeG5Q4s0FFdN3G4tgjxxEE0jZzDkFXGTm0=; b=bGaSJ9MbJtcmAGH/bvzRSrbAy/GjNp0DWv0E+TVVhz/xmVYPhsXTgXh4ch01mz7Y2f AVH5bhHNSF0AunhF6LjpxzxxXN6jBP1xpQ9zNEr/3HiU2Sgx7HP3avVk5SuS56WMoGdK L8FFzda8nW6JjKVayYUFbDORaCqz/y8MLsb7KEamApsAYE2//1EL2KvGKipedFLKOU61 GwnXPDB0qMI4I/oSemF/LUAFQnZ9lDpV/6jvdc5kFX6Wh0CqCYUWOCvAIBwCQqlwfZ9F VsxTgKQTSdcYwWFM00jrERVhfqY1u3B6I9LnmjFwadXPoUMIej0MFjMuaGCiceFDwbtw m4TA== X-Gm-Message-State: AOJu0YwjmEFCOTVm7JolsBUy9gbxaODwhg0FO4S3cpaL/227z3/mBKMT woofr7AFC41niFwzwkFdqpmEjor8h/CnT4GgUh56YryUYN4FQyL6UejNVpAXi6o= X-Google-Smtp-Source: AGHT+IHL8fVjhZxyWCIizny+y61ohQhQi7z8yqIlHQ0U/SRQRCePjHJyr8yU2+unHG5XmNkClgGpXg== X-Received: by 2002:a17:906:4806:b0:a52:5df2:ab4c with SMTP id w6-20020a170906480600b00a525df2ab4cmr965608ejq.16.1713514671108; Fri, 19 Apr 2024 01:17:51 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 04/53] clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields Date: Fri, 19 Apr 2024 11:16:53 +0300 Message-Id: <20240419081742.3496709-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:17:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15591 From: Claudiu Beznea commit 72977f07b035e488c3f1928832a1616c6cae7278 upstream. Use FIELD_GET() for PLL register fields. This is its purpose. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912045157.177966-14-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 330aa67fdab2..3035b1535344 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -11,6 +11,7 @@ * Copyright (C) 2015 Renesas Electronics Corp. */ +#include #include #include #include @@ -39,14 +40,13 @@ #define WARN_DEBUG(x) do { } while (0) #endif -#define DIV_RSMASK(v, s, m) ((v >> s) & m) #define GET_SHIFT(val) ((val >> 12) & 0xff) #define GET_WIDTH(val) ((val >> 8) & 0xf) -#define KDIV(val) DIV_RSMASK(val, 16, 0xffff) -#define MDIV(val) DIV_RSMASK(val, 6, 0x3ff) -#define PDIV(val) DIV_RSMASK(val, 0, 0x3f) -#define SDIV(val) DIV_RSMASK(val, 0, 0x7) +#define KDIV(val) FIELD_GET(GENMASK(31, 16), val) +#define MDIV(val) FIELD_GET(GENMASK(15, 6), val) +#define PDIV(val) FIELD_GET(GENMASK(5, 0), val) +#define SDIV(val) FIELD_GET(GENMASK(2, 0), val) #define CLK_ON_R(reg) (reg) #define CLK_MON_R(reg) (0x180 + (reg)) From patchwork Fri Apr 19 08:16:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E060C05052 for ; Fri, 19 Apr 2024 08:17:57 +0000 (UTC) Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) by mx.groups.io with SMTP id smtpd.web11.15253.1713514673721295800 for ; Fri, 19 Apr 2024 01:17:54 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Lh2V234Z; spf=pass (domain: tuxon.dev, ip: 209.85.218.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a5269c3f9c7so192612966b.2 for ; Fri, 19 Apr 2024 01:17:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514672; x=1714119472; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DsdCjrlZL0HXe4FRq418Kin+ww19GRS1XMhADQ8Q0x0=; b=Lh2V234ZrGx1Meid46ALyB1ji+YGHSihgA0dhbUEjKUhnQMygwStyRAfqL7YyQVy19 lIelbRINY1EblSW0M+pwV1wIlLv48+bmDZSEH9CinvVPgqeKnN6QWMQExRRTtB+nFbp9 g+5YqL837pQTBN7wOYLFZAKYYbZVlUHdROZaQO3rgQSn4q6Z2XcD+9CufFKIdNXz2YzA tPgdrpCKgqcTT7IErwHTfIxm7PVa01cAqAQGE5fjRabNsjrwc1taVCAlzCNI80SL/vXw PPduvT1r2c9Ku3PGRlk3M3rku/G6Am675GMqGyUHAu6qM74gPdvV1CywAbVRcSjY8zkm hOaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514672; x=1714119472; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DsdCjrlZL0HXe4FRq418Kin+ww19GRS1XMhADQ8Q0x0=; b=n2KajmuSv7zfy76Q7gH5s6DN80A6T38FddFVbGD6zpkLFh502Oy/icveegMfbAJ44r +KYuG1u5xzhtcxXGLnnIkJuBFi1HsN3WSpnSuLmoP7vqZXZS7ZlH6QXmetySd6mZU2V4 IseSOqo983SlfD+cuTFZqk/pkjbkUgbgwCU/C8yIEeUvPVLWPm6s7bXJndq+GaRrGL0V r2ctDOVzTxaXfBRTB7OTwVExhbDLQeDlvv2romIS4jwX9wH//VhqPPPegVdRNZA5dEcy r5mbGWJLJnnmJQegKXdX+Ney3C7nT9STA69dXtdozEbG/pyxW3urbNmvYkipaXIHME+q bgnw== X-Gm-Message-State: AOJu0YxliqERh6kCiRtdAC5HrBLldHskoVRTYAQcYd803NlzfqhbsY2f ibCKc6aoBlFKOi0P0rCZA/KgWAyg9CYui+9QuG6Xllvy/zynQ3W+zFgdXm29QHU= X-Google-Smtp-Source: AGHT+IFW53gBPwrxIMSCT5Epo/S0oypiwc/Hds1p9JkykHNDWZjswZPmdLTxDfz9QX67OOp6bCxduw== X-Received: by 2002:a17:907:7215:b0:a55:8609:1c34 with SMTP id dr21-20020a170907721500b00a5586091c34mr938182ejc.28.1713514672196; Fri, 19 Apr 2024 01:17:52 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:51 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 05/53] clk: renesas: rzg2l: Fix computation formula Date: Fri, 19 Apr 2024 11:16:54 +0300 Message-Id: <20240419081742.3496709-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:17:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15592 From: Claudiu Beznea commit a2b23159499efd36b2d63b3c4534075d12ddc97a upstream. According to the hardware manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf), the computation formula for PLL rate is as follows: Fout = ((m + k/65536) * Fin) / (p * 2^s) and k has values in the range [-32768, 32767]. Dividing k by 65536 with integer arithmetic gives zero all the time, causing slight differences b/w what has been set vs. what is displayed. Thus, get rid of this and decompose the formula before dividing k by 65536. Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-6-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3035b1535344..2260741433b2 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -43,7 +43,7 @@ #define GET_SHIFT(val) ((val >> 12) & 0xff) #define GET_WIDTH(val) ((val >> 8) & 0xf) -#define KDIV(val) FIELD_GET(GENMASK(31, 16), val) +#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), val)) #define MDIV(val) FIELD_GET(GENMASK(15, 6), val) #define PDIV(val) FIELD_GET(GENMASK(5, 0), val) #define SDIV(val) FIELD_GET(GENMASK(2, 0), val) @@ -699,18 +699,18 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw, struct pll_clk *pll_clk = to_pll(hw); struct rzg2l_cpg_priv *priv = pll_clk->priv; unsigned int val1, val2; - unsigned int mult = 1; - unsigned int div = 1; + u64 rate; if (pll_clk->type != CLK_TYPE_SAM_PLL) return parent_rate; val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); - mult = MDIV(val1) + KDIV(val1) / 65536; - div = PDIV(val1) << SDIV(val2); - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div); + rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + KDIV(val1), + 16 + SDIV(val2)); + + return DIV_ROUND_CLOSEST_ULL(rate, PDIV(val1)); } static const struct clk_ops rzg2l_cpg_pll_ops = { From patchwork Fri Apr 19 08:16:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6ECAC0650F for ; Fri, 19 Apr 2024 08:17:57 +0000 (UTC) Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) by mx.groups.io with SMTP id smtpd.web10.15285.1713514675565484437 for ; Fri, 19 Apr 2024 01:17:55 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=GQIVrdSv; spf=pass (domain: tuxon.dev, ip: 209.85.167.52, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-516d1ecaf25so2194778e87.2 for ; Fri, 19 Apr 2024 01:17:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514674; x=1714119474; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VyCTJKLuss+FBt172vSFTgxvb5QYNSzGQefT8db14PU=; b=GQIVrdSve85MuiUC3po1n22AORYzb4wIBUZjDNoAPjS0Yij3jfseW5tY7Va36hpPYJ 7lFFOkcUEEh1yheoSQ34iniUPJUiiN/1fceLOBQrdbkE0HmKhn+M3kS+jXJpgUmkPPHu C9Z5H1YC5e+LVu5HSUQMeA2alTcwIo5uDvsbyTifmDhaescokzU7e1jovb/OkQ49To71 cevYElu5pqDzrtE8B5xDbv0Z/FZi+iQc0SaRlwOBObrU3QBxJm0M3xt7JBLs9R2D8d8s nbNoYwrjuuF7Idmx9Xbjft7Fk24/ZmE/TWzae1zIQ25KW6fidexg5gdSwnr/mq0qhUhv 3Cbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514674; x=1714119474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VyCTJKLuss+FBt172vSFTgxvb5QYNSzGQefT8db14PU=; b=bvFHheDCPm4YvxuRSJIYFfCLZaXNfqgWMDLqI08cRX1jdoxerg12/iPyFi2eXOIAm+ UnOsOnDmn/arYGt6X9OWRgtLUIbbaxB86bP5gEA40anZyo3rL0KABpqkGnxgJDuNX+UM SwHiFkBXVSnUCPJwsuCO1GADtmxMmyTKnwiDCK5tzDTpiaZQTWKxjvHzdBa2JVTe2K0b ABgiVTsHEBxtmMLShiE/mXnojTuEhMcDGTcpl/DGcRlyTEJRTRc0EMOKQI6L1JkvcITt YKo5yhoSsw6g6OJALOzmDIQvmQhNx2gOApXb7TuqTACof+8F5j1a1FUgLvEYPzopbq5f jfAg== X-Gm-Message-State: AOJu0YwHV7Eq1eJ0KSuUotjBHzoX6bOcA43fp8dWUy5XifxlpB6ez0Cb KMKP1ZjukGhNbBA23OjhQyWd7aWqnX54sAfUJu/Q0IvuLqG3jjcAIhbH8EzXOB0= X-Google-Smtp-Source: AGHT+IEV2ejGgdVGiXFNma1qV+O4+SH2hvE8AR52PgJjQFHjwq+ee9Bc0DU+TQpxb+Cn/GLHKFWPgw== X-Received: by 2002:a05:6512:445:b0:519:1bcd:87cf with SMTP id y5-20020a056512044500b005191bcd87cfmr776183lfk.27.1713514673708; Fri, 19 Apr 2024 01:17:53 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:52 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 06/53] clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset() Date: Fri, 19 Apr 2024 11:16:55 +0300 Message-Id: <20240419081742.3496709-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:17:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15593 From: Claudiu Beznea commit 5f9e29b9159a41fcf6733c3b59fa46a90ce3ae20 upstream. Code in rzg2l_cpg_reset() is equivalent with the combined code of rzg2l_cpg_assert() and rzg2l_cpg_deassert(). There is no need to have different versions thus re-use rzg2l_cpg_assert() and rzg2l_cpg_deassert(). Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120070024.4079344-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 38 +++++++++++++-------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 2260741433b2..fee4d3d5c265 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1115,29 +1115,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, #define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev) -static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); - const struct rzg2l_cpg_info *info = priv->info; - unsigned int reg = info->resets[id].off; - u32 dis = BIT(info->resets[id].bit); - u32 we = dis << 16; - - dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); - - /* Reset module */ - writel(we, priv->base + CLK_RST_R(reg)); - - /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ - udelay(35); - - /* Release module from reset state */ - writel(we | dis, priv->base + CLK_RST_R(reg)); - - return 0; -} - static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, unsigned long id) { @@ -1168,6 +1145,21 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, return 0; } +static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = rzg2l_cpg_assert(rcdev, id); + if (ret) + return ret; + + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ + udelay(35); + + return rzg2l_cpg_deassert(rcdev, id); +} + static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, unsigned long id) { From patchwork Fri Apr 19 08:16:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B80D3C071FD for ; Fri, 19 Apr 2024 08:17:57 +0000 (UTC) Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) by mx.groups.io with SMTP id smtpd.web11.15255.1713514676887593126 for ; Fri, 19 Apr 2024 01:17:57 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=D+ViPVsg; spf=pass (domain: tuxon.dev, ip: 209.85.167.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-51abd9fcbf6so638218e87.1 for ; Fri, 19 Apr 2024 01:17:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514675; x=1714119475; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p2hlPxOFybFH23T/YECy3SSN4xpZfD7q3OR4joXitpc=; b=D+ViPVsgnR4BDWg6aoAH1Sbk3gleegEaG43eoqGTVFHELlc6rHYCEVsrrBGzgyo012 ZoY9VgURmllpG5rG9wo+EdC5Ylp2lk90+C12kvMAzMFmBTZA5RX507R4iftJmFLxhDRB pd7aoiVNaoSAv0Vhfemn0ZeWtuCji4ggjchY6zy6cuGY8BBR/lKTf/Xiq9hzBfsJqkNJ +uc18EKt3hQfDla8CEcv7GIPZkQmLGymm8q3rBfB5s6t7Vkup6nZ9zawUtOhH8Z8MpG4 lqS4OtBqP4OTm853SPKvhD0R6ioJ/Y5TVF9NDLplN6wwSAYh+hoIqiesqIsEvvsLM7ce g/fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514675; x=1714119475; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p2hlPxOFybFH23T/YECy3SSN4xpZfD7q3OR4joXitpc=; b=cM2BtgTgHhoYtP2NoDWx8qBEzHNJitVdo3QzIEv5DDf4YrpmM3jrwNXXzhZFuN6WfH WGjbesKdtsDub/uRtsSSFoZ3I5CgutMvI8zhoEQ++R8RtDk2oCCX6PAG0cf7CZ6znFB9 csTCSfXvJVdCnXSKpCXlcUN6k/pWH6vmddvRg87kQInAxp3pToKB5XQT2/wSVKVS9EB9 Boxy2FaC5B8piGiH2OulaxhInO5M7v2907/ELpSAVvTaXEcGfZWOZWL5m0k2sSlHezh5 nts8xUqueHclfKaumXqdAGyy/Ql7fzCD4Zcc/J8/xit78Ee2f+J1C9T6hfJyWvcDxli1 QnFw== X-Gm-Message-State: AOJu0Yzjdpg+ze/Z5BsLaavqCiFzyODk6wPjn12xbwvlW3jsgU6aik8d tB6GyOzsg+wIqSxCszb/7l0hvvVNODfg130e2ZEMbJjTI8svfEhv0JuOa6JZPoc= X-Google-Smtp-Source: AGHT+IE3fkVXUt+XC40H/mU4lCev1UrsuBhrzDKvXLvhRo51SQ4KK7Rj031/y9mdYT+pd51r3QbLbw== X-Received: by 2002:a05:6512:3b11:b0:515:cd23:7090 with SMTP id f17-20020a0565123b1100b00515cd237090mr1488218lfv.8.1713514675129; Fri, 19 Apr 2024 01:17:55 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:54 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 07/53] clk: renesas: rzg2l: Check reset monitor registers Date: Fri, 19 Apr 2024 11:16:56 +0300 Message-Id: <20240419081742.3496709-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:17:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15594 From: Claudiu Beznea commit da235d2fac212d0add570e755feb1167a830bc99 upstream. The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset monitor registers need to be interrogated when the reset signals are toggled (chapters "Procedures for Supplying and Stopping Reset Signals" and "Procedure for Activating Modules"). Without this, there is a chance that different modules (e.g. Ethernet) are not ready after their reset signal is toggled, leading to failures (on probe or resume from deep sleep states). The same indications are available for RZ/V2M for TYPE-B reset controls. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Fixes: 8090bea32484 ("clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 59 ++++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 15 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index fee4d3d5c265..491fb64b1a3c 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1121,12 +1121,27 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev, struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); const struct rzg2l_cpg_info *info = priv->info; unsigned int reg = info->resets[id].off; - u32 value = BIT(info->resets[id].bit) << 16; + u32 mask = BIT(info->resets[id].bit); + s8 monbit = info->resets[id].monbit; + u32 value = mask << 16; dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); writel(value, priv->base + CLK_RST_R(reg)); - return 0; + + if (info->has_clk_mon_regs) { + reg = CLK_MRST_R(reg); + } else if (monbit >= 0) { + reg = CPG_RST_MON; + mask = BIT(monbit); + } else { + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ + udelay(35); + return 0; + } + + return readl_poll_timeout_atomic(priv->base + reg, value, + value & mask, 10, 200); } static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, @@ -1135,14 +1150,28 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev, struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); const struct rzg2l_cpg_info *info = priv->info; unsigned int reg = info->resets[id].off; - u32 dis = BIT(info->resets[id].bit); - u32 value = (dis << 16) | dis; + u32 mask = BIT(info->resets[id].bit); + s8 monbit = info->resets[id].monbit; + u32 value = (mask << 16) | mask; dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, CLK_RST_R(reg)); writel(value, priv->base + CLK_RST_R(reg)); - return 0; + + if (info->has_clk_mon_regs) { + reg = CLK_MRST_R(reg); + } else if (monbit >= 0) { + reg = CPG_RST_MON; + mask = BIT(monbit); + } else { + /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ + udelay(35); + return 0; + } + + return readl_poll_timeout_atomic(priv->base + reg, value, + !(value & mask), 10, 200); } static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, @@ -1154,9 +1183,6 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, if (ret) return ret; - /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ - udelay(35); - return rzg2l_cpg_deassert(rcdev, id); } @@ -1165,18 +1191,21 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, { struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev); const struct rzg2l_cpg_info *info = priv->info; - unsigned int reg = info->resets[id].off; - u32 bitmask = BIT(info->resets[id].bit); s8 monbit = info->resets[id].monbit; + unsigned int reg; + u32 bitmask; if (info->has_clk_mon_regs) { - return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask); + reg = CLK_MRST_R(info->resets[id].off); + bitmask = BIT(info->resets[id].bit); } else if (monbit >= 0) { - u32 monbitmask = BIT(monbit); - - return !!(readl(priv->base + CPG_RST_MON) & monbitmask); + reg = CPG_RST_MON; + bitmask = BIT(monbit); + } else { + return -ENOTSUPP; } - return -ENOTSUPP; + + return !!(readl(priv->base + reg) & bitmask); } static const struct reset_control_ops rzg2l_cpg_reset_ops = { From patchwork Fri Apr 19 08:16:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A78DEC4345F for ; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:55 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 08/53] dt-bindings: soc: renesas: Document Renesas RZ/G3S SoC variants Date: Fri, 19 Apr 2024 11:16:57 +0300 Message-Id: <20240419081742.3496709-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15595 From: Claudiu Beznea commit 9c57c4a9a45c04c19f38986c73847b756ceae237 upstream. Document RZ/G3S (R9A08G045) SoC variants. Signed-off-by: Claudiu Beznea Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912045157.177966-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/renesas.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 9f62712d3237..830121d7dd25 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -334,6 +334,12 @@ properties: - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 - const: renesas,r9a09g011 + - description: RZ/G3S (R9A08G045) + items: + - enum: + - renesas,r9a08g045s33 # PCIe support + - const: renesas,r9a08g045 + additionalProperties: true ... From patchwork Fri Apr 19 08:16:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8FCDC04FFF for ; Fri, 19 Apr 2024 08:18:07 +0000 (UTC) Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) by mx.groups.io with SMTP id smtpd.web11.15257.1713514679806825419 for ; Fri, 19 Apr 2024 01:18:00 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=NRY6Kee8; spf=pass (domain: tuxon.dev, ip: 209.85.218.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-a51a7d4466bso184738966b.2 for ; Fri, 19 Apr 2024 01:17:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514678; x=1714119478; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yewcQmmxC8Th8ZVMjI2OZlthzTp28WUdygEyExZdDwI=; b=NRY6Kee8DffklThO8UQglYS9PZZA1oNWnRmQHEr4nZvtOG5pLxYAzbazSPveXTO3gF m9Vu97W3gkU84P/v4g7UiNNwzNT8C7z9vjXNFy54AUOdYMS9x3WMNRd28XxqXR+m+wQZ q4ZRaYv3JRFMg8Y/9VsXu8HKJpdXO3fGyCkmAv8epbiCIIuHY0O7xwFhi5wekRI25sA6 TIk7lz6fBg4es4nTtK629lHd9TdGwjYjS1v6XnshAD4T6RV9lfESLkZ6XDtyaRxYh70H V22Fxy3qf8J8/H95n9P1oaOiLPH2r/bgakkLgqXGZyGFwgw3TILjcQUxwBq7tYkjruvf n35w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514678; x=1714119478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yewcQmmxC8Th8ZVMjI2OZlthzTp28WUdygEyExZdDwI=; b=As7/X6fysP/fsY4UCn+CQMbu9Fx1PVM82qiMf9zsZs0FCOIZAh7tgAVs3aWQDFbEq+ NrS6oWOLoi88cX8Rrkd2gfJA9FfGOeBv4QGG6ALN+1sKzTJT4SHbKAFsOvXZACRlH7Kx coaB07oR6o5Ur7Tb1P/PlIjFiU0+59ZxN6EUdbAhd4ta7zLRRemXYlCBFlT9CYT/ePe7 r/yeBWgeql2ucgHF/jhO4iRe0qENLeN1wC5sZ5gOSriHQkRX3o5I0Jgr5IYbZ21G8GTM WdWd6JZDmxChjZPo/1yUBHk6CrxRNKjR/ntqw5zJFSIZyzSD7jcOPl7OicWua04vU8MD 4ghA== X-Gm-Message-State: AOJu0YxBjCtlQzEovyAjTRawRdTelRdsYavwcLHFsKa7VvxBggVY0wu5 iZCkqyReBB4cbLkr96QuVWT+7H3cdI5LF5TV8berHpf9c0qG6iAsUE/TMaT7ARE= X-Google-Smtp-Source: AGHT+IEqNDHMyoNssoMWRw0GxtcHMn3yHMdrOYi/wdP6NYcgs8R1neXpxDi3NRIYVaYiBHeVPPwuGw== X-Received: by 2002:a17:906:7949:b0:a47:20c3:7c51 with SMTP id l9-20020a170906794900b00a4720c37c51mr1177634ejo.71.1713514678281; Fri, 19 Apr 2024 01:17:58 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 09/53] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3S SoC Date: Fri, 19 Apr 2024 11:16:58 +0300 Message-Id: <20240419081742.3496709-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15596 From: Claudiu Beznea commit 111287aa60004e1a58320048c89391056288c455 upstream. Document RZ/G3S (R9A08G045) SYSC bindings. The SYSC block found on the RZ/G3S SoC is similar to the one found on the RZ/G2UL. Signed-off-by: Claudiu Beznea Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912045157.177966-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml index ce2875c89329..3c2ede52d9af 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml @@ -23,6 +23,7 @@ properties: - renesas,r9a07g043-sysc # RZ/G2UL - renesas,r9a07g044-sysc # RZ/G2{L,LC} - renesas,r9a07g054-sysc # RZ/V2L + - renesas,r9a08g045-sysc # RZ/G3S reg: maxItems: 1 From patchwork Fri Apr 19 08:16:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4141C04FF6 for ; Fri, 19 Apr 2024 08:18:07 +0000 (UTC) Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mx.groups.io with SMTP id smtpd.web10.15290.1713514681672847244 for ; Fri, 19 Apr 2024 01:18:02 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=lvoReHVh; spf=pass (domain: tuxon.dev, ip: 209.85.167.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-51ac9c6599bso228898e87.1 for ; Fri, 19 Apr 2024 01:18:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514680; x=1714119480; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7LfpRKe3/TAeWMaDuaWyTBgLyfTaQW/LF/lmg///XDU=; b=lvoReHVh7dBtZheXf1cqhOIxw8BYkiu8W3ftx21bowt1nHG18pvdxPCs18JSdocXRn 3q/QVvLKmehGxPYeAABmrp6TAADbWCrUdQghrJeO0n6Ag38WmeEas1i1n/XewMdWeZWo 9rS8qtXL1Wht5PRf6ZA9u80jF4U97+J8p/T4vpoL6ootKpdtpLjzSOPjbtJse1Z0ycgW efeMPmIp1BBkqzyRta/LlasiiGLSLovV2IbeS2ne2jwp2TOEK+5Q0A7a7HHHhiLwxZj3 Vsw4a/lZYCiPKuEewDXzUbZ2xb6cJ8IFQc6otYcoooikvukvd20Ir568mMP9CWcR9Fj5 JkVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514680; x=1714119480; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7LfpRKe3/TAeWMaDuaWyTBgLyfTaQW/LF/lmg///XDU=; b=gVWQy6VSG9szXuOl+15wRQT/SNIbTCyP7dLPpeX8grnBW/sA7KxRmQbLs3He64NVqE V1LM7sBrzCVntLE8n5qEm8GflSX73P1mFrE05kT9rNlj47DgrekvVwLYDT6Zdky22fcM yoVlOODDzp89/R5/3gZIianN3Vri07lNbj6TKhNl+M4NnHDnWuG84MAXlSbA+vcU4b+z Q3ncvEJRbmsWkh857dfCZtcYtBZF/2Xpev2DT3Hlr/nAqS8+tTF2aDrC8JNrhY5Vo10x 3kQQwDDY36Ik4d80y/lmjjmG24KvEYUNatPQpiQI/sO5tmF3KJZhTuLfq3e1QRzVYoAo mEqA== X-Gm-Message-State: AOJu0Yx+qbS3T66Wn+Gq2+1CZo1drLvdELBc3asr7PdPOop2MBONUG5D FQWH6+U07TQbfhvde+UQG2VWrG3bFB7Pzlmv5gWJknVfvT/FvUx5xFk08rxaplvy8/ZvrE82k4b R X-Google-Smtp-Source: AGHT+IFzny8u4UYsJ3kij3ga5jF2HkhxklgG0USjEOXl3qsPhTmNXeDL27tGKDp8I1CGvPvjem6rsQ== X-Received: by 2002:a05:6512:49c:b0:515:d038:5548 with SMTP id v28-20020a056512049c00b00515d0385548mr923243lfq.31.1713514679752; Fri, 19 Apr 2024 01:17:59 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:17:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 10/53] clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM Date: Fri, 19 Apr 2024 11:16:59 +0300 Message-Id: <20240419081742.3496709-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15597 From: Lad Prabhakar commit 3702cff6d9385565b1ea2670a5623f9695412019 upstream. There are cases where not all CPG_MOD clocks should be assumed to support PM. For example on the CRU block there is a particular sequence that needs to be followed to initialize the CSI-2 D-PHY in which individual clocks need to be turned ON/OFF, due to which Runtime PM support wasn't used by the CRU CSI-2 driver. This patch adds support to allow indicating if PM is not supported by the CPG_MOD clocks. Two new members no_pm_mod_clks and num_no_pm_mod_clks are added to struct rzg2l_cpg_info so that MOD clocks which do not support PM can be passed by no_pm_mod_clks[] array and when the driver uses Runtime PM support the clk ID is matched against the no_pm_mod_clks[] array to see if the clk is needed to be included as part of Runtime PM. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20221026014227.162121-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: fixed conflict in the documentation of struct rzg2l_cpg_priv] Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 41 ++++++++++++++++++++------------- drivers/clk/renesas/rzg2l-cpg.h | 4 ++++ 2 files changed, 29 insertions(+), 16 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 491fb64b1a3c..2262c70fb383 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -95,7 +95,8 @@ struct rzg2l_pll5_mux_dsi_div_param { * @num_resets: Number of Module Resets in info->resets[] * @last_dt_core_clk: ID of the last Core Clock exported to DT * @info: Pointer to platform data - * @pll5_mux_dsi_div_params: pll5 mux and dsi div parameters + * @genpd: PM domain + * @mux_dsi_div_params: pll5 mux and dsi div parameters */ struct rzg2l_cpg_priv { struct reset_controller_dev rcdev; @@ -111,6 +112,8 @@ struct rzg2l_cpg_priv { const struct rzg2l_cpg_info *info; + struct generic_pm_domain genpd; + struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; }; @@ -1242,22 +1245,31 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv) return devm_reset_controller_register(priv->dev, &priv->rcdev); } -static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec) +static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv, + const struct of_phandle_args *clkspec) { + const struct rzg2l_cpg_info *info = priv->info; + unsigned int id; + unsigned int i; + if (clkspec->args_count != 2) return false; - switch (clkspec->args[0]) { - case CPG_MOD: - return true; - - default: + if (clkspec->args[0] != CPG_MOD) return false; + + id = clkspec->args[1] + info->num_total_core_clks; + for (i = 0; i < info->num_no_pm_mod_clks; i++) { + if (info->no_pm_mod_clks[i] == id) + return false; } + + return true; } -static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev) +static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev) { + struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd); struct device_node *np = dev->of_node; struct of_phandle_args clkspec; bool once = true; @@ -1267,7 +1279,7 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec)) { - if (rzg2l_cpg_is_pm_clk(&clkspec)) { + if (rzg2l_cpg_is_pm_clk(priv, &clkspec)) { if (once) { once = false; error = pm_clk_create(dev); @@ -1317,16 +1329,13 @@ static void rzg2l_cpg_genpd_remove(void *data) pm_genpd_remove(data); } -static int __init rzg2l_cpg_add_clk_domain(struct device *dev) +static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) { + struct device *dev = priv->dev; struct device_node *np = dev->of_node; - struct generic_pm_domain *genpd; + struct generic_pm_domain *genpd = &priv->genpd; int ret; - genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL); - if (!genpd) - return -ENOMEM; - genpd->name = np->name; genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_ACTIVE_WAKEUP; @@ -1396,7 +1405,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) if (error) return error; - error = rzg2l_cpg_add_clk_domain(dev); + error = rzg2l_cpg_add_clk_domain(priv); if (error) return error; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index aefa53a90059..91e9c2569f80 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -253,6 +253,10 @@ struct rzg2l_cpg_info { unsigned int num_mod_clks; unsigned int num_hw_mod_clks; + /* No PM Module Clocks */ + const unsigned int *no_pm_mod_clks; + unsigned int num_no_pm_mod_clks; + /* Resets */ const struct rzg2l_reset *resets; unsigned int num_resets; From patchwork Fri Apr 19 08:17:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2123C41513 for ; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:00 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 11/53] clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic() Date: Fri, 19 Apr 2024 11:17:00 +0300 Message-Id: <20240419081742.3496709-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15598 From: Geert Uytterhoeven commit 7df8eea64a417f1db6777cddc1d7eda3634b7175 upstream. Use readl_poll_timeout_atomic() instead of open-coding the same operation. As typically no retries are needed, 10 µs is a suitable timeout value. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/900543d4b9abc1004e6aecdb676f23e5508ae96f.1685692810.git.geert+renesas@glider.be Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 2262c70fb383..cf6337fa5e7a 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -903,9 +903,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) unsigned int reg = clock->off; struct device *dev = priv->dev; unsigned long flags; - unsigned int i; u32 bitmask = BIT(clock->bit); u32 value; + int error; if (!clock->off) { dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk); @@ -930,19 +930,13 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) if (!priv->info->has_clk_mon_regs) return 0; - for (i = 1000; i > 0; --i) { - if (((readl(priv->base + CLK_MON_R(reg))) & bitmask)) - break; - cpu_relax(); - } - - if (!i) { + error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value, + value & bitmask, 0, 10); + if (error) dev_err(dev, "Failed to enable CLK_ON %p\n", priv->base + CLK_ON_R(reg)); - return -ETIMEDOUT; - } - return 0; + return error; } static int rzg2l_mod_clock_enable(struct clk_hw *hw) From patchwork Fri Apr 19 08:17:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D84DAC05052 for ; Fri, 19 Apr 2024 08:18:07 +0000 (UTC) Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) by mx.groups.io with SMTP id smtpd.web11.15260.1713514684759223922 for ; Fri, 19 Apr 2024 01:18:05 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=XX76nLv9; spf=pass (domain: tuxon.dev, ip: 209.85.208.171, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f171.google.com with SMTP id 38308e7fff4ca-2d715638540so22160191fa.3 for ; Fri, 19 Apr 2024 01:18:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514683; x=1714119483; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fj437jskGkSLGzlrRwaD8VVZiwYXk8zUEwBscyRDn4o=; b=XX76nLv9Pzw9KW0/pG6Nk8kSD13vu8vvRIACYVgJAxPrFXn5vfy9f1ztRXWIH/wy1/ hRzd1ogTgT5UzoGVJbE2k1iI93ErIdRP6gwAThmjiH3r+w+kyyCUZoKFklIZEJaM0Vs9 2XADP6F1vGEyHi76WBEP0bxrYyziazZbg8/IuvFKC0tXlLsvIman0THl2QxbwEuHDRzR aXobCYMKCz3/1N5NGoCyPo5ah0COlb3Lk4/kEfLohtWrL2AIS0x1/8eGIlYzBdCsHipO lKQaDmLrOsdaz/5WerfalHVs5cRNd5+4ypryCcBaZRemM9skslBlt4apCZ1x4oEBZjF+ I0sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514683; x=1714119483; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fj437jskGkSLGzlrRwaD8VVZiwYXk8zUEwBscyRDn4o=; b=uhONjKX87RmAgLUm89piN6ZEpNACRU38Dc7KqrF0PbhhVJKTGwd6lvHG19cwQH5Cj9 lYN4jhvPuzyFY+K3tb9pcTJ9CtAMrXf9579qsxGkrDDCqt7Sp3wMBGl/CvBfhpAUIyBT UOHUFAjEA5bmSPCwnP/g0qsL/PjOwM4L1b6zPjMP9seqwbeKdoC/WJUWhpIAGJC2tbYd wMy0do9h63loEzThtcp78gCxbb6awx/TrasCMurwpB0cQSU4Q76MYZQ5s8NnFhNs9cOr dKJ3ZHuxZv1aM5VTdKQ5zzEe4/maD2M0TAQc704v7Ur+0Gs9/1LwuBhchSaMj0VRtDXc H+xg== X-Gm-Message-State: AOJu0YyoIC8iPyuy2Nzoh78UWNqO6Jjetxv7TBeVnFaGpS3VqD/9sIaR TsIdNEklPDDZahtGze46zzFP0OUVuEq+xl9rgCY15pB/O62OdRZM/j0D2bA0ddM= X-Google-Smtp-Source: AGHT+IHMXR6GRJei6LySh7X9KPzBxGeS4XSvIOqpX8mBNje/lRAe5WMmOORwNI1VadnFkZKehLc3eA== X-Received: by 2002:a05:6512:220c:b0:519:3243:3083 with SMTP id h12-20020a056512220c00b0051932433083mr970604lfu.14.1713514682744; Fri, 19 Apr 2024 01:18:02 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:02 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 12/53] clk: renesas: rzg2l: Use u32 for flag and mux_flags Date: Fri, 19 Apr 2024 11:17:01 +0300 Message-Id: <20240419081742.3496709-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15599 From: Claudiu Beznea commit 897a3e34d6e73d2386715d5c44c57992f2c0eada upstream. flag and mux_flags are intended to keep bit masks. Use u32 type for it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912045157.177966-15-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 91e9c2569f80..097fd8f61680 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -92,8 +92,8 @@ struct cpg_core_clk { unsigned int conf; const struct clk_div_table *dtable; const char * const *parent_names; - int flag; - int mux_flags; + u32 flag; + u32 mux_flags; int num_parents; }; From patchwork Fri Apr 19 08:17:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D93E8C071DB for ; Fri, 19 Apr 2024 08:18:07 +0000 (UTC) Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) by mx.groups.io with SMTP id smtpd.web10.15295.1713514685724273183 for ; Fri, 19 Apr 2024 01:18:06 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=R3GI+NDC; spf=pass (domain: tuxon.dev, ip: 209.85.208.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-571c22d9de4so1689078a12.3 for ; Fri, 19 Apr 2024 01:18:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514684; x=1714119484; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OXqYr5ZuKUQXxTAfuTtg9D0Uff2e9IEyxaEHNRITfj4=; b=R3GI+NDCgmBiimS06wVi/9Q9khxaUiXcPVNItHdvAv03MXsl0YF/oMAtwEleIjfRZT VRii2N1tR1wIg5AY3zr943JC3GDel5qZ/NrmtjXfXAkGLHTyFVRm4dT6WOKvRRmXVI6x M2Om3HUMSrr186g6Etf9hhXQAEUcU00Mx3/b1FR9ZzKgu9XhMfAodso5wLCD852efsge R9QvPwR7zeVLhlPpgImbnp0c/1bgTj9Bn5V7ReFFH1aIaqr1DSzT47mr2KeVFXU+c/1o 7L++CETiSLhCbzc72pQaFbger0PULbsYo3KYfC1/2w3mDYBPi6crshBiDXPjyz5rP9/d NCTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514684; x=1714119484; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OXqYr5ZuKUQXxTAfuTtg9D0Uff2e9IEyxaEHNRITfj4=; b=m76Jyz1/wydEbT1ckzbKz6ziM3tQxjMB0hXMA49GDrkJfpHNvbGy8J7IDVmKNTap/h yWBT2njnqpHmepWuiQ4tSLGPyOEo/YIUVJYT9KBVDiK0H7m5C9v4dz2ECGhqf5+RBUkz aUBAPQ0uEnfCh51wO5QX4Gy0AL2AiM/AFMQedMUSmmph8eszi+b7JlzwPbA3mFv1AS/S nuGX2o1TdX0tBxNKrO3GqM0zYjbjFpS43CHadmvZE36fceHJy8tVDCLesecki967X4e0 5s8CJcRG97qBuRodyutFl/1hGYANRHZJhJckZjnKvqwYPtMXEVt7KT8oTzToWg1s8UrM ZsFQ== X-Gm-Message-State: AOJu0YyQMciNY7q9T9jEJZJ/SSUVzoOnGk/Ku88XMfDdbWqk5sjoi4qF 7yfG303+rXIilm5vtcsXU6jqQ/1Q4tGGmm6OOnGaR17J2RsY69pq26aUYEV1k8EWsqTUhmacx9d M X-Google-Smtp-Source: AGHT+IHzDklpuS989L+SO6suE9CcC8qHA4UUBd+RHVEJHnxD+btNAR7yjlf8mlP2lO2y6oiB7bnibg== X-Received: by 2002:a17:906:f90d:b0:a4e:6f0d:c53b with SMTP id lc13-20020a170906f90d00b00a4e6f0dc53bmr1034331ejb.35.1713514684062; Fri, 19 Apr 2024 01:18:04 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:03 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 13/53] clk: renesas: rzg2l: Simplify .determine_rate() Date: Fri, 19 Apr 2024 11:17:02 +0300 Message-Id: <20240419081742.3496709-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15600 From: Christophe JAILLET commit bbceb13ce2c7b084bbbf2463ac8ac2b1f2bd2949 upstream. rzg2l_cpg_sd_clk_mux_determine_rate() is the same as __clk_mux_determine_rate_closest(), so use the latter to save some LoC. Signed-off-by: Christophe JAILLET Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/fed02e0325275df84e2d76f8c481e40e7023cbd9.1688760372.git.christophe.jaillet@wanadoo.fr Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index cf6337fa5e7a..43dcea9f7ed1 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -182,12 +182,6 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, return clk_hw->clk; } -static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST); -} - static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct sd_hw_data *hwdata = to_sd_hw_data(hw); @@ -250,7 +244,7 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) } static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = { - .determine_rate = rzg2l_cpg_sd_clk_mux_determine_rate, + .determine_rate = __clk_mux_determine_rate_closest, .set_parent = rzg2l_cpg_sd_clk_mux_set_parent, .get_parent = rzg2l_cpg_sd_clk_mux_get_parent, }; From patchwork Fri Apr 19 08:17:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAF70C04FF6 for ; Fri, 19 Apr 2024 08:18:17 +0000 (UTC) Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) by mx.groups.io with SMTP id smtpd.web11.15261.1713514687605176663 for ; Fri, 19 Apr 2024 01:18:07 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=bxSTpXg5; spf=pass (domain: tuxon.dev, ip: 209.85.218.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-a555b203587so191880366b.3 for ; Fri, 19 Apr 2024 01:18:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514686; x=1714119486; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=anhU6WmbSlVAmRNaOZQ3hY89T8ADhEDCuFtkLjSkO8Y=; b=bxSTpXg5r8DN6DcMU7X3EaV6CNEHkxBe6SuD6y8ddL63XjTX4dsbYBg+annj5MCFc1 JuFBnugJf3ubYQfNtRXgO/kE7q3jpWRNESfqeM+bnw33gBJKXxv+zce/RKNqlrvpP46M IhgTtYvm9trpSdhJAqk4OkHWkrwOB07dIQ60VvPekwxDuPfjy6p5Gn7cYvwcdIc+5Dpo BmFDC2lFfx6Hv1RAepg8QCk8QdhXQfN2fddKMoJUd1hBDdm8Wg6KFOlhxlOnDB5yJ6/Q hmH4L0rHJP1e6Vh04uo7u4EKft64a5/tFF0Sq5bsRODLYRncQ+w22AFFgycOeIr6cr5R tfQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514686; x=1714119486; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=anhU6WmbSlVAmRNaOZQ3hY89T8ADhEDCuFtkLjSkO8Y=; b=IAn6I4QOTD1+gLehQXoyu07z0kP4mBqrSLnDTAJVplYTEFMyWJ98m3Cm6nB1q3FbLe yYQHroOGcBe+vbJ52OHKRUwWHOQ4LQ/ZVsAsqnDkOK7EVIJO0XpmEQtnYH4vCD3wP9en 1OXWaWuyYXN9LGDVj9hvm4/he8k9T0eLo0VgyiH2kvuleP2VpQTQp3gAR2E0czLFjkkd uFTF55m45ijik2eihy2iI85tl1iGGf6juyBg9WqzeC86++MORjSBfvVPwW896D/AXy0M 3KG22XNFYDpcgUo0PmIzNezwNYHIbnzBHcpLPMYDgjCVFaO+2PRyt86JVs+HmV3Alssa DdLA== X-Gm-Message-State: AOJu0YxoSLk8Jv22sXTczRd6KMhbb5VC84l6xr+V2xTGn0vy4kVtHprQ 1R9gMZL8nwkSh0zrgl+BvC+XEoTkFNW5PCyCBS/8BeTBBlXp0uo2mTrBZ8F+iyw= X-Google-Smtp-Source: AGHT+IGRFdByEjPb+vTFgs++LHfsZqU3a0ShL5JHDK38BVF/vueD48EAox5itEy4aN3G8NwBQtK+IQ== X-Received: by 2002:a17:906:1c5b:b0:a51:d204:d69e with SMTP id l27-20020a1709061c5b00b00a51d204d69emr1232304ejg.7.1713514686123; Fri, 19 Apr 2024 01:18:06 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:05 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 14/53] clk: renesas: rzg2l: Use core->name for clock name Date: Fri, 19 Apr 2024 11:17:03 +0300 Message-Id: <20240419081742.3496709-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:17 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15601 From: Claudiu Beznea commit 17939df3c9acd26e4dac1c5943dd8e58e1bcb4e7 upstream. core->name already contains the clock name thus, there is no need to check the GET_SHIFT(core->conf) to decide on it. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912045157.177966-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 43dcea9f7ed1..cb31efab2cce 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -266,7 +266,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, clk_hw_data->priv = priv; clk_hw_data->conf = core->conf; - init.name = GET_SHIFT(core->conf) ? "sd1" : "sd0"; + init.name = core->name; init.ops = &rzg2l_cpg_sd_clk_mux_ops; init.flags = 0; init.num_parents = core->num_parents; From patchwork Fri Apr 19 08:17:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CABA6C4345F for ; Fri, 19 Apr 2024 08:18:17 +0000 (UTC) Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) by mx.groups.io with SMTP id smtpd.web11.15263.1713514688743516672 for ; Fri, 19 Apr 2024 01:18:09 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=gdIvThNI; spf=pass (domain: tuxon.dev, ip: 209.85.218.53, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-a53f131d9deso197458166b.3 for ; Fri, 19 Apr 2024 01:18:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514687; x=1714119487; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FDuQ98tfmN2EWJiGV2dZFGuLoSvlTK5HZ9tG0EzvMFw=; b=gdIvThNISx8/BS5xJ1mNkiVyS+ts3IzuHHUgx2/sc4Ver0NVMTUo18n5EfK3VrldM9 KXI8oawi12yLFooepnV/EnRjKwA8O2Ty3OaAIkBn7V+3dU5F37NtQx0XaddERaeAdQuT UrS5/X5azVx1mE5TkD82kl9YNCI+F7mpJDrIsZB1Rp+4TdCq9snHp5ekeY+JoMo7Cl+H 7jiyq5Sn0jDJwHnN5auBaSvnakyPU5SulxR9YWT6IluIAd29MJcLogfapCWtRhWK+fOZ HNhq1qhvZmNN3w0tURP7YUP3LBfLCpBtkvtuv+8mFFyYpL379LOzZqyCQykBWJWDZ3DT 0SOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514687; x=1714119487; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FDuQ98tfmN2EWJiGV2dZFGuLoSvlTK5HZ9tG0EzvMFw=; b=ddjgaUmi1PrrnK7ZHv3TP/DcrtuUlANZVeZUqxr4S0kBSMQeB37O0w975rvTP0SCSW CJzQq5rEsEi7nSH2HpY1LLEhYb7S+3RUFT42XBuyk4DL17L6/4891DN+vqJXOZRBgCad hXz+WK5y7MY/OS8psOUOQSHbwI3A1WHAgVXSYfdP4ZPSE/hsNrQgXCjJXm4VTU9T2YTY 0ln2BrfIAMC4TjqfqlG8p/G/PFQx7NSWOM2pVJRdFBAKL8PZ7MOx1LYWGfR6Nyl0J10g BH8Tu/szEt/pLLzh9fIIkzmEA15e2YqzyNXVcs8L1FTSgmxGll7icTZcPnPDwaioh0Dt Z3Cw== X-Gm-Message-State: AOJu0Yw7Rv1eCS39xhKQLU3gm4x+rchMcqbzw8Yc+uqXmQ+xbY9fqSKS VzAj7Uj5pKMbvp7XTCeZkuj2eCICQyQAcU8oZ4E/afBUj3gLdVmLd9SfzxgGFeo7a4JywfUOEil T X-Google-Smtp-Source: AGHT+IGxAYWtKQe1XpnIAUBCV1FfBTveInH5wwO1S1TQfp0W+1hHYzguBejcA4iQp4LFiaXI3j3d7w== X-Received: by 2002:a17:906:164f:b0:a51:d522:13d5 with SMTP id n15-20020a170906164f00b00a51d52213d5mr879711ejd.40.1713514687219; Fri, 19 Apr 2024 01:18:07 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:06 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 15/53] clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable() Date: Fri, 19 Apr 2024 11:17:04 +0300 Message-Id: <20240419081742.3496709-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:17 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15602 From: Claudiu Beznea commit becf4a771a12b52dc5b3d2b089598d5603f3bbec upstream. The bitmask << 16 is anyway set on both branches of if thus move it before the if and set the lower bits of registers only in case clock is enabled. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912045157.177966-12-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index cb31efab2cce..572a7e86ef44 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -910,10 +910,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) enable ? "ON" : "OFF"); spin_lock_irqsave(&priv->rmw_lock, flags); + value = bitmask << 16; if (enable) - value = (bitmask << 16) | bitmask; - else - value = bitmask << 16; + value |= bitmask; writel(value, priv->base + CLK_ON_R(reg)); spin_unlock_irqrestore(&priv->rmw_lock, flags); From patchwork Fri Apr 19 08:17:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0E0BC41513 for ; Fri, 19 Apr 2024 08:18:17 +0000 (UTC) Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) by mx.groups.io with SMTP id smtpd.web10.15298.1713514690662157340 for ; Fri, 19 Apr 2024 01:18:10 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=ZSdvQyh0; spf=pass (domain: tuxon.dev, ip: 209.85.208.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-56c5d05128dso1582854a12.0 for ; Fri, 19 Apr 2024 01:18:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514689; x=1714119489; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2jcjlWpfMaOSzcHVY4DDGDPiSAq/wIEEWtp+0+XY2Bg=; b=ZSdvQyh0h3ACXEvRW7zdgTHcf74uqC8XdMm0bQrcLo1aWREhJrD4UzU0YVuPaKzFSH KKHEX4ZAQV6hLxBUMFxpT9+nnGS1/SEyeNicT4/vO7n/BFs1YLqxyFl7AADCGmo/gqHe ziBSvZSWlIM7iF+qzO4exxZOWx8CzXBJWVKTy6cdvHj5kSxXiT7vvfEeO1h3weiRjpx5 RBvJfbX1TD79UhgnEN6zx6BLRhncfmq6mYlGtY4exPbi0pYlrv6/+SvJXdAiL/wiww3g TpO/NithA+hXFjcdq00YzzAiUFJjPOi1y/y/L6iBcFc2MGxdiITLaADOvXCwYCsK2Sp+ q2+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514689; x=1714119489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2jcjlWpfMaOSzcHVY4DDGDPiSAq/wIEEWtp+0+XY2Bg=; b=N0hnu3v22EPz+RfQuetmTvZoJg4nEL3JvKKqas4/ZHNm/THDoqzr0VYnFGVxznYcMU U/7348aQ0L5I8Y7Ts/BbcwCY8B8z5CH+RiGyQCyHPb/VDh6Neb9AGMpMfw5Epq5i9bcB UEzq1ufLUxYIkCvO33KmfTZTKOtjeQE6u3pOEqOKYuJAyT03RCBZXdqCiyTJ5y9FFsFl EpyMyFBRnOO6R4ByuToxfGrxsjr6HlX6qChA8oVuQjsQm3/giETiwHN+xhAK+EadB7/+ l5KwEo+2AEmD6kslUGlmcvsmR/pQoXAsj5qPdOd29xknz3nFH40iLUCe9sZKzGEzYdJT XHZg== X-Gm-Message-State: AOJu0YyXZwEmYyu9aZx2z4MumO9PZdctO93f+UI9/FVTRi5M4A4YC1rJ 883YNloxFqKjzP4Ieqxty2EjMm6r8RnfIxKoFhYysrxq+hwyLsWwFwjOGz65lk1b3huxlUjsfMv y X-Google-Smtp-Source: AGHT+IEWqQiRJpwcP5kqa+fJUx8pCeXQ4Jdym0WO3epCDuvyLmsBk1rylF25fmWGpr/PUNEak2AjJA== X-Received: by 2002:a17:906:2bd7:b0:a52:c873:a66 with SMTP id n23-20020a1709062bd700b00a52c8730a66mr943280ejg.34.1713514689087; Fri, 19 Apr 2024 01:18:09 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:08 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 16/53] clk: renesas: rzg2l: Remove critical area Date: Fri, 19 Apr 2024 11:17:05 +0300 Message-Id: <20240419081742.3496709-17-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:17 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15603 From: Claudiu Beznea commit 5f710e3bc5987373737470f98798bbd49134a2e0 upstream. The spinlock in rzg2l_mod_clock_endisable() is intended to protect RMW-accesses to the hardware register. There is no need to protect instructions that set temporary variables which will be written afterwards to a hardware register. With this only one write to one clock register is executed thus locking/unlocking rmw_lock is removed. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-7-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 572a7e86ef44..b280a468c4a8 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -896,7 +896,6 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) struct rzg2l_cpg_priv *priv = clock->priv; unsigned int reg = clock->off; struct device *dev = priv->dev; - unsigned long flags; u32 bitmask = BIT(clock->bit); u32 value; int error; @@ -908,14 +907,12 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk, enable ? "ON" : "OFF"); - spin_lock_irqsave(&priv->rmw_lock, flags); value = bitmask << 16; if (enable) value |= bitmask; - writel(value, priv->base + CLK_ON_R(reg)); - spin_unlock_irqrestore(&priv->rmw_lock, flags); + writel(value, priv->base + CLK_ON_R(reg)); if (!enable) return 0; From patchwork Fri Apr 19 08:17:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0DCCC05052 for ; Fri, 19 Apr 2024 08:18:17 +0000 (UTC) Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mx.groups.io with SMTP id smtpd.web10.15300.1713514692438391827 for ; Fri, 19 Apr 2024 01:18:12 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=eCivuULx; spf=pass (domain: tuxon.dev, ip: 209.85.208.181, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f181.google.com with SMTP id 38308e7fff4ca-2db17e8767cso25094471fa.3 for ; Fri, 19 Apr 2024 01:18:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514690; x=1714119490; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=crWfIaVyz2slnAzlQast5vbjAXs1OwXJA6IeTLjBbc0=; b=eCivuULxkfui42TMfW0w/NYH6d9VBvbn8oP0h2hZU2o98G7+94Rqpoio7p0dZFumd7 Z62nf3Czasng34eBOlEuLO2ikjNdyUID6L59+Xn0EprhwCb4khhR5/XXJnSZ5xk6y9fc qYXR5ufX1hjH9ax4Uc6VrUrZXHm4+9p/ugWoeEGdeRGRZ0tA3xbbMvH/Nn3HWnOOW5BI 34P0wFabJPrq8M5+q/5Dg4dyEXyDJLEx0Qqi2kA3pdkbLItfyM8QDH2MbyHWf2DeA4D+ OMNATMaxJ9kD4zmAmr6AhT5KMafKmnbG7cL7/T5bNpPf8dJVNDPLvYwDUvH2L3T2a4+g IHsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514690; x=1714119490; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=crWfIaVyz2slnAzlQast5vbjAXs1OwXJA6IeTLjBbc0=; b=iAxCUT5GdcIrDty6MzF5zZZ8gbuFxh+utB6yMKntnDCPGZOc5jCbGV+xNaR8a13JA8 VuL7zLIXUeiXdcA4oIedYjlWDtA45JbXXZhFVJ/qta7jB56h4+PBwHktrAxmJhEjy6Lz VOdAm/2gA1wHGhV+EwqsQKiuXWZjZrRNjP7Ef+kvOXepDp3Gs3VBXwtWD3jd7z7iKkZi puG6qI8t/8RioL6BQ6js70vlgXAj01Nc8WC2fZ4yR2HVV4R+4rBI50s/V2r9AMmfaMdt aLuXTs8Xx6qWIeJSTQtu1wgsiEyWnDElNRJVdmarTPYkhVnUorcMLt4r0sFspeJ7a1a8 uBCw== X-Gm-Message-State: AOJu0Yw6uQ/u2OGor4jEd7JYF8aEWT9svYLfi0x90SzMPpjW+Wz+mfWY YXFXJiQYxkfnCxw94acjaXasHbLT/j6iIZtg5ZIXnwBKUz+lBa0JUytenkfNnj51mv3C8HU0itA C X-Google-Smtp-Source: AGHT+IHs6zSCSyHnnA4dGZWTvnaDLuL2J0K4lyVw3fNZt5EW3gV6VBkhYNtxOOlcCOtXPwmhkvYFnQ== X-Received: by 2002:a19:5e11:0:b0:519:7b00:d371 with SMTP id s17-20020a195e11000000b005197b00d371mr805421lfb.7.1713514690633; Fri, 19 Apr 2024 01:18:10 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:10 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 17/53] clk: renesas: rzg2l: Add support for RZ/G3S PLL Date: Fri, 19 Apr 2024 11:17:06 +0300 Message-Id: <20240419081742.3496709-18-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:17 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15604 From: Claudiu Beznea commit 01eabef547e63d80086acd3f247d36c5f9f92456 upstream. Add support for reading the frequency of PLL1/4/6 as available on RZ/G3S. The computation formula for the PLL frequency is as follows: Fout = (nir + nfr / 4096) * Fin / (mr * pr) Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-8-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 49 ++++++++++++++++++++++++++++++--- drivers/clk/renesas/rzg2l-cpg.h | 3 ++ 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index b280a468c4a8..1a928828baac 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -48,6 +48,11 @@ #define PDIV(val) FIELD_GET(GENMASK(5, 0), val) #define SDIV(val) FIELD_GET(GENMASK(2, 0), val) +#define RZG3S_DIV_P GENMASK(28, 26) +#define RZG3S_DIV_M GENMASK(25, 22) +#define RZG3S_DIV_NI GENMASK(21, 13) +#define RZG3S_DIV_NF GENMASK(12, 1) + #define CLK_ON_R(reg) (reg) #define CLK_MON_R(reg) (0x180 + (reg)) #define CLK_RST_R(reg) (reg) @@ -714,11 +719,43 @@ static const struct clk_ops rzg2l_cpg_pll_ops = { .recalc_rate = rzg2l_cpg_pll_clk_recalc_rate, }; +static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk = to_pll(hw); + struct rzg2l_cpg_priv *priv = pll_clk->priv; + u32 nir, nfr, mr, pr, val; + u64 rate; + + if (pll_clk->type != CLK_TYPE_G3S_PLL) + return parent_rate; + + val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); + + pr = 1 << FIELD_GET(RZG3S_DIV_P, val); + /* Hardware interprets values higher than 8 as p = 16. */ + if (pr > 8) + pr = 16; + + mr = FIELD_GET(RZG3S_DIV_M, val) + 1; + nir = FIELD_GET(RZG3S_DIV_NI, val) + 1; + nfr = FIELD_GET(RZG3S_DIV_NF, val); + + rate = mul_u64_u32_shr(parent_rate, 4096 * nir + nfr, 12); + + return DIV_ROUND_CLOSEST_ULL(rate, (mr * pr)); +} + +static const struct clk_ops rzg3s_cpg_pll_ops = { + .recalc_rate = rzg3s_cpg_pll_clk_recalc_rate, +}; + static struct clk * __init rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, struct clk **clks, void __iomem *base, - struct rzg2l_cpg_priv *priv) + struct rzg2l_cpg_priv *priv, + const struct clk_ops *ops) { struct device *dev = priv->dev; const struct clk *parent; @@ -736,7 +773,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, parent_name = __clk_get_name(parent); init.name = core->name; - init.ops = &rzg2l_cpg_pll_ops; + init.ops = ops; init.flags = 0; init.parent_names = &parent_name; init.num_parents = 1; @@ -831,8 +868,12 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, core->mult, div); break; case CLK_TYPE_SAM_PLL: - clk = rzg2l_cpg_pll_clk_register(core, priv->clks, - priv->base, priv); + clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv, + &rzg2l_cpg_pll_ops); + break; + case CLK_TYPE_G3S_PLL: + clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv, + &rzg3s_cpg_pll_ops); break; case CLK_TYPE_SIPLL5: clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv); diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 097fd8f61680..20da0c620b90 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -102,6 +102,7 @@ enum clk_types { CLK_TYPE_IN, /* External Clock Input */ CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_SAM_PLL, + CLK_TYPE_G3S_PLL, /* Clock with divider */ CLK_TYPE_DIV, @@ -129,6 +130,8 @@ enum clk_types { DEF_TYPE(_name, _id, _type, .parent = _parent) #define DEF_SAMPLL(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) +#define DEF_G3S_PLL(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf) #define DEF_INPUT(_name, _id) \ DEF_TYPE(_name, _id, CLK_TYPE_IN) #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ From patchwork Fri Apr 19 08:17:07 2024 Content-Type: text/plain; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:11 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 18/53] clk: renesas: rzg2l: Add struct clk_hw_data Date: Fri, 19 Apr 2024 11:17:07 +0300 Message-Id: <20240419081742.3496709-19-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:17 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15605 From: Claudiu Beznea commit 97c1c4ccda76d2919775d748cf223637cf0e82ae upstream. Add clk_hw_data struct that keeps the core part of the clock data. sd_hw_data embeds a member of type struct clk_hw_data along with other members (in the next commits). This commit prepares the field for refactoring the SD MUX clock driver. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-9-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 52 +++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 1a928828baac..fa492813f127 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -64,13 +64,29 @@ #define MAX_VCLK_FREQ (148500000) -struct sd_hw_data { +/** + * struct clk_hw_data - clock hardware data + * @hw: clock hw + * @conf: clock configuration (register offset, shift, width) + * @priv: CPG private data structure + */ +struct clk_hw_data { struct clk_hw hw; u32 conf; struct rzg2l_cpg_priv *priv; }; -#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw) +#define to_clk_hw_data(_hw) container_of(_hw, struct clk_hw_data, hw) + +/** + * struct sd_hw_data - SD clock hardware data + * @hw_data: clock hw data + */ +struct sd_hw_data { + struct clk_hw_data hw_data; +}; + +#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw_data) struct rzg2l_pll5_param { u32 pl5_fracin; @@ -189,10 +205,10 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) { - struct sd_hw_data *hwdata = to_sd_hw_data(hw); - struct rzg2l_cpg_priv *priv = hwdata->priv; - u32 off = GET_REG_OFFSET(hwdata->conf); - u32 shift = GET_SHIFT(hwdata->conf); + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 off = GET_REG_OFFSET(clk_hw_data->conf); + u32 shift = GET_SHIFT(clk_hw_data->conf); const u32 clk_src_266 = 2; u32 msk, val, bitmask; unsigned long flags; @@ -209,7 +225,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and * the index to value mapping is done by adding 1 to the index. */ - bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16; + bitmask = (GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0) << shift) << 16; msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; spin_lock_irqsave(&priv->rmw_lock, flags); if (index != clk_src_266) { @@ -238,12 +254,12 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) { - struct sd_hw_data *hwdata = to_sd_hw_data(hw); - struct rzg2l_cpg_priv *priv = hwdata->priv; - u32 val = readl(priv->base + GET_REG_OFFSET(hwdata->conf)); + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); - val >>= GET_SHIFT(hwdata->conf); - val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0); + val >>= GET_SHIFT(clk_hw_data->conf); + val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); return val ? val - 1 : 0; } @@ -259,17 +275,17 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, void __iomem *base, struct rzg2l_cpg_priv *priv) { - struct sd_hw_data *clk_hw_data; + struct sd_hw_data *sd_hw_data; struct clk_init_data init; struct clk_hw *clk_hw; int ret; - clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); - if (!clk_hw_data) + sd_hw_data = devm_kzalloc(priv->dev, sizeof(*sd_hw_data), GFP_KERNEL); + if (!sd_hw_data) return ERR_PTR(-ENOMEM); - clk_hw_data->priv = priv; - clk_hw_data->conf = core->conf; + sd_hw_data->hw_data.priv = priv; + sd_hw_data->hw_data.conf = core->conf; init.name = core->name; init.ops = &rzg2l_cpg_sd_clk_mux_ops; @@ -277,7 +293,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, init.num_parents = core->num_parents; init.parent_names = core->parent_names; - clk_hw = &clk_hw_data->hw; + clk_hw = &sd_hw_data->hw_data.hw; clk_hw->init = &init; ret = devm_clk_hw_register(priv->dev, clk_hw); From patchwork Fri Apr 19 08:17:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DF4EC0650F for ; Fri, 19 Apr 2024 08:18:18 +0000 (UTC) Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) by mx.groups.io with SMTP id smtpd.web10.15303.1713514695904212531 for ; Fri, 19 Apr 2024 01:18:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=RsnS7Dm9; spf=pass (domain: tuxon.dev, ip: 209.85.208.169, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f169.google.com with SMTP id 38308e7fff4ca-2da01cb187cso30327891fa.0 for ; Fri, 19 Apr 2024 01:18:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514694; x=1714119494; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P2AdxgEaiwmkPsUIrm4YNxqGj7QuZwVINKjTX1zNVMw=; b=RsnS7Dm9fCRecG4uh+fQbBfsIiO484hey6XCokAiNq5NhtMQpYdmn7tfGGuQmWrAsJ xjzV7YcHIZUU06YLj0hflrvsAranCp7zw2oQxS5sMHHBl5STRfamDVHJfjX45ezKmUu2 0ZQ5k7ZTgiihBhb8DuKmiLhrbRovLmhtF/elfLph1dHQXYZpOI7nkphQbfenDA7OPT7m qheBPll4Pg/vaUVJ3IvxpNHDS5yjscJGSZuLg5JME9LvQLFFHJRDy6o2MYWSU7nHHk47 4uauveQfJEtRV+vO0io8X51Oc4Dk3SQwFEIqbkjiBSySiRndE0g7nvB7TtALkYaiOhJo QaTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514694; x=1714119494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P2AdxgEaiwmkPsUIrm4YNxqGj7QuZwVINKjTX1zNVMw=; b=p5UNDUXIkcFO+U1aSTLtVVeapagLRM5kAEfW4EatTLzXex+kS1G8aeO4LPOVgfIxwi mmiPQg4qrMCJ4Mnv4m5c0Hc8RIE5dzlqcfBwUgzii4Kdzng6ySCiknqD/Z02bo7vvJmH UvSI9RE27k88OFtbHVhakhfXdppXj+GzEZwtSfp9QAbzLzXK8NzaWVUdJQcyBZhUdSQb wMhuyjJVgadT3lwxpynlQEwjUjrCMlrQ/eL50cCuFZowjBzPqjlD//yB2Gl9SKZ/CjO6 /KBwCfVeLw+rmCNNl7pp9q3cSMR3hcuKbMb/dGksnfmx0VTFSLQXaj0KuYw5pNe/S+Pw g8PA== X-Gm-Message-State: AOJu0YzWQ2f8op0h6KfTQO5Vv80XKrCs60nxRpTHyglAtbDnvhryJbg8 eiDhZBzcCuuIW9Vqolg/Wssn+01ZASpuSlc8mMo5lR+dxr4RhUhrtLxkvR28UNc= X-Google-Smtp-Source: AGHT+IGxXhyEQZ1hjtERAtYg3JMGLt4v0FnuklgW5qo+ORYRY5qx/U18JWRGWRmfezJfT1IxXerekg== X-Received: by 2002:a2e:9c0e:0:b0:2d8:5fe6:820d with SMTP id s14-20020a2e9c0e000000b002d85fe6820dmr978390lji.11.1713514693979; Fri, 19 Apr 2024 01:18:13 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:13 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 19/53] clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header Date: Fri, 19 Apr 2024 11:17:08 +0300 Message-Id: <20240419081742.3496709-20-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:18 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15606 From: Claudiu Beznea commit 3e8008fcf6b7f7c65ad2718c18fb79f37007f1a5 upstream. Remove CPG_SDHI_DSEL and its bits from the generic header as RZ/G3S has different offset registers and bits for this, thus avoid mixing them. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-10-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a07g043-cpg.c | 7 +++++++ drivers/clk/renesas/r9a07g044-cpg.c | 7 +++++++ drivers/clk/renesas/rzg2l-cpg.h | 4 ---- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 1a7a6d60aca4..e0ae25644e1a 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -14,6 +14,13 @@ #include "rzg2l-cpg.h" +/* Specific registers. */ +#define CPG_PL2SDHI_DSEL (0x218) + +/* Clock select configuration. */ +#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) +#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index f5550fccb029..c1c94c58983a 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -15,6 +15,13 @@ #include "rzg2l-cpg.h" +/* Specific registers. */ +#define CPG_PL2SDHI_DSEL (0x218) + +/* Clock select configuration. */ +#define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) +#define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 20da0c620b90..f5382333d327 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -19,7 +19,6 @@ #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) #define CPG_PL6_DDIV (0x210) -#define CPG_PL2SDHI_DSEL (0x218) #define CPG_CLKSTATUS (0x280) #define CPG_PL3_SSEL (0x408) #define CPG_PL6_SSEL (0x414) @@ -69,9 +68,6 @@ #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) -#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) -#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) - #define EXTAL_FREQ_IN_MEGA_HZ (24) /** From patchwork Fri Apr 19 08:17:09 2024 Content-Type: text/plain; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 20/53] clk: renesas: rzg2l: Refactor SD mux driver Date: Fri, 19 Apr 2024 11:17:09 +0300 Message-Id: <20240419081742.3496709-21-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15607 From: Claudiu Beznea commit 16b86e5c03c5b3ef35bf5126b35384faa97428f0 upstream. Refactor SD MUX driver to be able to reuse the same code on RZ/G3S. RZ/G2{L,UL} has a limitation with regards to switching the clock source for SD MUX (MUX clock source has to be switched to 266MHz before switching b/w 533MHz and 400MHz). Rework the handling of this limitation to use a clock notifier that is registered according to platform based initialization data, so the SD MUX code can be reused on RZ/G3S. As RZ/G2{L,UL} and RZ/G3S use different bits in different registers to check if the clock switching has been done, this configuration (register offset, register bits and bitfield width) is now passed through struct cpg_core_clk::sconf (status configuration) from platform specific initialization code. Along with struct cpg_core_clk::sconf the mux table indices are also passed from platform specific initialization code. Also, mux flags are now passed to DEF_SD_MUX() as they will be used later by RZ/G3S. CPG_WEN_BIT macro has been introduced to select properly the WEN bit of various registers. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231006103959.197485-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a07g043-cpg.c | 12 ++- drivers/clk/renesas/r9a07g044-cpg.c | 12 ++- drivers/clk/renesas/rzg2l-cpg.c | 150 ++++++++++++++++++++-------- drivers/clk/renesas/rzg2l-cpg.h | 16 ++- 4 files changed, 139 insertions(+), 51 deletions(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index e0ae25644e1a..b70bb378ab46 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -21,6 +21,10 @@ #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) #define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) +/* Clock status configuration. */ +#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1) +#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, @@ -85,6 +89,8 @@ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; +static const u32 mtable_sdhi[] = { 1, 2, 3 }; + static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -130,8 +136,10 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), - DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi), - DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi), + DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi, + mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), + DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi, + mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), }; diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index c1c94c58983a..7b18b9be76c7 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -22,6 +22,10 @@ #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) #define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) +/* Clock status configuration. */ +#define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1) +#define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, @@ -105,6 +109,8 @@ static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; +static const u32 mtable_sdhi[] = { 1, 2, 3 }; + static const struct { struct cpg_core_clk common[56]; #ifdef CONFIG_CLK_R9A07G054 @@ -170,8 +176,10 @@ static const struct { DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2), DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), - DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi), - DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi), + DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi, + mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), + DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi, + mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8), diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index fa492813f127..9054ad40063f 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -62,31 +62,37 @@ #define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff) #define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff) +#define CPG_WEN_BIT BIT(16) + #define MAX_VCLK_FREQ (148500000) /** * struct clk_hw_data - clock hardware data * @hw: clock hw * @conf: clock configuration (register offset, shift, width) + * @sconf: clock status configuration (register offset, shift, width) * @priv: CPG private data structure */ struct clk_hw_data { struct clk_hw hw; u32 conf; + u32 sconf; struct rzg2l_cpg_priv *priv; }; #define to_clk_hw_data(_hw) container_of(_hw, struct clk_hw_data, hw) /** - * struct sd_hw_data - SD clock hardware data + * struct sd_mux_hw_data - SD MUX clock hardware data * @hw_data: clock hw data + * @mtable: clock mux table */ -struct sd_hw_data { +struct sd_mux_hw_data { struct clk_hw_data hw_data; + const u32 *mtable; }; -#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw_data) +#define to_sd_mux_hw_data(_hw) container_of(_hw, struct sd_mux_hw_data, hw_data) struct rzg2l_pll5_param { u32 pl5_fracin; @@ -143,6 +149,76 @@ static void rzg2l_cpg_del_clk_provider(void *data) of_clk_del_provider(data); } +/* Must be called in atomic context. */ +static int rzg2l_cpg_wait_clk_update_done(void __iomem *base, u32 conf) +{ + u32 bitmask = GENMASK(GET_WIDTH(conf) - 1, 0) << GET_SHIFT(conf); + u32 off = GET_REG_OFFSET(conf); + u32 val; + + return readl_poll_timeout_atomic(base + off, val, !(val & bitmask), 10, 200); +} + +int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, + void *data) +{ + struct clk_notifier_data *cnd = data; + struct clk_hw *hw = __clk_get_hw(cnd->clk); + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 off = GET_REG_OFFSET(clk_hw_data->conf); + u32 shift = GET_SHIFT(clk_hw_data->conf); + const u32 clk_src_266 = 3; + unsigned long flags; + int ret; + + if (event != PRE_RATE_CHANGE || (cnd->new_rate / MEGA == 266)) + return NOTIFY_DONE; + + spin_lock_irqsave(&priv->rmw_lock, flags); + + /* + * As per the HW manual, we should not directly switch from 533 MHz to + * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz) + * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first, + * and then switch to the target setting (2’b01 (533 MHz) or 2’b10 + * (400 MHz)). + * Setting a value of '0' to the SEL_SDHI0_SET or SEL_SDHI1_SET clock + * switching register is prohibited. + * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and + * the index to value mapping is done by adding 1 to the index. + */ + + writel((CPG_WEN_BIT | clk_src_266) << shift, priv->base + off); + + /* Wait for the update done. */ + ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf); + + spin_unlock_irqrestore(&priv->rmw_lock, flags); + + if (ret) + dev_err(priv->dev, "failed to switch to safe clk source\n"); + + return notifier_from_errno(ret); +} + +static int rzg2l_register_notifier(struct clk_hw *hw, const struct cpg_core_clk *core, + struct rzg2l_cpg_priv *priv) +{ + struct notifier_block *nb; + + if (!core->notifier) + return 0; + + nb = devm_kzalloc(priv->dev, sizeof(*nb), GFP_KERNEL); + if (!nb) + return -ENOMEM; + + nb->notifier_call = core->notifier; + + return clk_notifier_register(hw->clk, nb); +} + static struct clk * __init rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks, @@ -206,48 +282,27 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data); struct rzg2l_cpg_priv *priv = clk_hw_data->priv; u32 off = GET_REG_OFFSET(clk_hw_data->conf); u32 shift = GET_SHIFT(clk_hw_data->conf); - const u32 clk_src_266 = 2; - u32 msk, val, bitmask; unsigned long flags; + u32 val; int ret; - /* - * As per the HW manual, we should not directly switch from 533 MHz to - * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz) - * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first, - * and then switch to the target setting (2’b01 (533 MHz) or 2’b10 - * (400 MHz)). - * Setting a value of '0' to the SEL_SDHI0_SET or SEL_SDHI1_SET clock - * switching register is prohibited. - * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and - * the index to value mapping is done by adding 1 to the index. - */ - bitmask = (GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0) << shift) << 16; - msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; + val = clk_mux_index_to_val(sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, index); + spin_lock_irqsave(&priv->rmw_lock, flags); - if (index != clk_src_266) { - writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off); - - ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val, - !(val & msk), 10, - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); - if (ret) - goto unlock; - } - writel(bitmask | ((index + 1) << shift), priv->base + off); + writel((CPG_WEN_BIT | val) << shift, priv->base + off); + + /* Wait for the update done. */ + ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf); - ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val, - !(val & msk), 10, - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US); -unlock: spin_unlock_irqrestore(&priv->rmw_lock, flags); if (ret) - dev_err(priv->dev, "failed to switch clk source\n"); + dev_err(priv->dev, "Failed to switch parent\n"); return ret; } @@ -255,13 +310,15 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) { struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data); struct rzg2l_cpg_priv *priv = clk_hw_data->priv; - u32 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); + u32 val; + val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); val >>= GET_SHIFT(clk_hw_data->conf); val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); - return val ? val - 1 : 0; + return clk_mux_val_to_index(hw, sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, val); } static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = { @@ -275,31 +332,40 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core, void __iomem *base, struct rzg2l_cpg_priv *priv) { - struct sd_hw_data *sd_hw_data; + struct sd_mux_hw_data *sd_mux_hw_data; struct clk_init_data init; struct clk_hw *clk_hw; int ret; - sd_hw_data = devm_kzalloc(priv->dev, sizeof(*sd_hw_data), GFP_KERNEL); - if (!sd_hw_data) + sd_mux_hw_data = devm_kzalloc(priv->dev, sizeof(*sd_mux_hw_data), GFP_KERNEL); + if (!sd_mux_hw_data) return ERR_PTR(-ENOMEM); - sd_hw_data->hw_data.priv = priv; - sd_hw_data->hw_data.conf = core->conf; + sd_mux_hw_data->hw_data.priv = priv; + sd_mux_hw_data->hw_data.conf = core->conf; + sd_mux_hw_data->hw_data.sconf = core->sconf; + sd_mux_hw_data->mtable = core->mtable; init.name = core->name; init.ops = &rzg2l_cpg_sd_clk_mux_ops; - init.flags = 0; + init.flags = core->flag; init.num_parents = core->num_parents; init.parent_names = core->parent_names; - clk_hw = &sd_hw_data->hw_data.hw; + clk_hw = &sd_mux_hw_data->hw_data.hw; clk_hw->init = &init; ret = devm_clk_hw_register(priv->dev, clk_hw); if (ret) return ERR_PTR(ret); + ret = rzg2l_register_notifier(clk_hw, core, priv); + if (ret) { + dev_err(priv->dev, "Failed to register notifier for %s\n", + core->name); + return ERR_PTR(ret); + } + return clk_hw->clk; } diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index f5382333d327..f1910913b29a 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -9,6 +9,8 @@ #ifndef __RENESAS_RZG2L_CPG_H__ #define __RENESAS_RZG2L_CPG_H__ +#include + #define CPG_SIPLL5_STBY (0x140) #define CPG_SIPLL5_CLK1 (0x144) #define CPG_SIPLL5_CLK3 (0x14C) @@ -42,8 +44,6 @@ #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) -#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 200 - /* n = 0/1/2 for PLL1/4/6 */ #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) @@ -86,8 +86,11 @@ struct cpg_core_clk { unsigned int mult; unsigned int type; unsigned int conf; + unsigned int sconf; const struct clk_div_table *dtable; + const u32 *mtable; const char * const *parent_names; + notifier_fn_t notifier; u32 flag; u32 mux_flags; int num_parents; @@ -150,10 +153,11 @@ enum clk_types { .parent_names = _parent_names, \ .num_parents = ARRAY_SIZE(_parent_names), \ .mux_flags = CLK_MUX_READ_ONLY) -#define DEF_SD_MUX(_name, _id, _conf, _parent_names) \ - DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ +#define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \ + DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \ .parent_names = _parent_names, \ - .num_parents = ARRAY_SIZE(_parent_names)) + .num_parents = ARRAY_SIZE(_parent_names), \ + .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier) #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ @@ -272,4 +276,6 @@ extern const struct rzg2l_cpg_info r9a07g044_cpg_info; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:16 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 21/53] clk: divider: Add re-usable determine_rate implementations Date: Fri, 19 Apr 2024 11:17:10 +0300 Message-Id: <20240419081742.3496709-22-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15608 From: Martin Blumenstingl commit bbd7a6cc382f4317b08ba71151b23abf76fc4c34 upstream. These are useful when running on 32-bit systems to increase the upper supported frequency limit. clk_ops.round_rate returns a signed long which limits the maximum rate on 32-bit systems to 2^31 (or approx. 2.14GHz). clk_ops.determine_rate internally uses an unsigned long so the maximum rate on 32-bit systems is 2^32 or approx. 4.29GHz. To avoid code-duplication switch over divider_{ro_,}round_rate_parent to use the new divider_{ro_,}determine_rate functions. Reviewed-by: Jerome Brunet Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210627223959.188139-2-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd [claudiu.beznea: keep unchanged the divider_{ro_,}round_rate_parent() functions] Signed-off-by: Claudiu Beznea --- drivers/clk/clk-divider.c | 38 ++++++++++++++++++++++++++++++++++++ include/linux/clk-provider.h | 6 ++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index f32157cb4013..24dd9897128f 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -342,6 +342,44 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent, return bestdiv; } +int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags) +{ + int div; + + div = clk_divider_bestdiv(hw, req->best_parent_hw, req->rate, + &req->best_parent_rate, table, width, flags); + + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); + + return 0; +} +EXPORT_SYMBOL_GPL(divider_determine_rate); + +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags, unsigned int val) +{ + int div; + + div = _get_div(table, val, flags, width); + + /* Even a read-only clock can propagate a rate change */ + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!req->best_parent_hw) + return -EINVAL; + + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, + req->rate * div); + } + + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); + + return 0; +} +EXPORT_SYMBOL_GPL(divider_ro_determine_rate); + long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 54e19005e78d..75cdef73e751 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -656,6 +656,12 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val); +int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags); +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags, unsigned int val); int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags); From patchwork Fri Apr 19 08:17:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10E5FC05052 for ; Fri, 19 Apr 2024 08:18:28 +0000 (UTC) Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) by mx.groups.io with SMTP id smtpd.web10.15304.1713514699782911652 for ; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:17 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 22/53] clk: renesas: rzg2l: Add divider clock for RZ/G3S Date: Fri, 19 Apr 2024 11:17:11 +0300 Message-Id: <20240419081742.3496709-23-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15609 From: Claudiu Beznea commit 62b1feac485866494f111e3a6aa4a9ae03a7a2b9 upstream. Add a divider clock driver for RZ/G3S. This will be used on RZ/G3S for the SDHI, SPI, OCTA, I, I2, I3, P0, P1, P2, and P3 core clocks. The divider has some limitation for SDHI, OCTA and SPI clocks: - SDHI div cannot be 1 if parent rate is 800MHz, - OCTA, SPI div cannot be 1 if parent rate is 400MHz. To handle these limitations, a notifier is registered from platform specific clock driver, which makes sure proper actions are taken before the clock rate is changed, when needed. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231006103959.197485-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 186 ++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 11 ++ 2 files changed, 197 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 9054ad40063f..3b691445bf52 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -94,6 +94,24 @@ struct sd_mux_hw_data { #define to_sd_mux_hw_data(_hw) container_of(_hw, struct sd_mux_hw_data, hw_data) +/** + * struct div_hw_data - divider clock hardware data + * @hw_data: clock hw data + * @dtable: pointer to divider table + * @invalid_rate: invalid rate for divider + * @max_rate: maximum rate for divider + * @width: divider width + */ +struct div_hw_data { + struct clk_hw_data hw_data; + const struct clk_div_table *dtable; + unsigned long invalid_rate; + unsigned long max_rate; + u32 width; +}; + +#define to_div_hw_data(_hw) container_of(_hw, struct div_hw_data, hw_data) + struct rzg2l_pll5_param { u32 pl5_fracin; u8 pl5_refdiv; @@ -202,6 +220,53 @@ int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event return notifier_from_errno(ret); } +int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, + void *data) +{ + struct clk_notifier_data *cnd = data; + struct clk_hw *hw = __clk_get_hw(cnd->clk); + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 off = GET_REG_OFFSET(clk_hw_data->conf); + u32 shift = GET_SHIFT(clk_hw_data->conf); + unsigned long flags; + int ret = 0; + u32 val; + + if (event != PRE_RATE_CHANGE || !div_hw_data->invalid_rate || + div_hw_data->invalid_rate % cnd->new_rate) + return NOTIFY_DONE; + + spin_lock_irqsave(&priv->rmw_lock, flags); + + val = readl(priv->base + off); + val >>= shift; + val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); + + /* + * There are different constraints for the user of this notifiers as follows: + * 1/ SD div cannot be 1 (val == 0) if parent rate is 800MHz + * 2/ OCTA / SPI div cannot be 1 (val == 0) if parent rate is 400MHz + * As SD can have only one parent having 800MHz and OCTA div can have + * only one parent having 400MHz we took into account the parent rate + * at the beginning of function (by checking invalid_rate % new_rate). + * Now it is time to check the hardware divider and update it accordingly. + */ + if (!val) { + writel((CPG_WEN_BIT | 1) << shift, priv->base + off); + /* Wait for the update done. */ + ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf); + } + + spin_unlock_irqrestore(&priv->rmw_lock, flags); + + if (ret) + dev_err(priv->dev, "Failed to downgrade the div\n"); + + return notifier_from_errno(ret); +} + static int rzg2l_register_notifier(struct clk_hw *hw, const struct cpg_core_clk *core, struct rzg2l_cpg_priv *priv) { @@ -219,6 +284,124 @@ static int rzg2l_register_notifier(struct clk_hw *hw, const struct cpg_core_clk return clk_notifier_register(hw->clk, nb); } +static unsigned long rzg3s_div_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 val; + + val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); + val >>= GET_SHIFT(clk_hw_data->conf); + val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); + + return divider_recalc_rate(hw, parent_rate, val, div_hw_data->dtable, + CLK_DIVIDER_ROUND_CLOSEST, div_hw_data->width); +} + +static int rzg3s_div_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) +{ + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data); + + if (div_hw_data->max_rate && req->rate > div_hw_data->max_rate) + req->rate = div_hw_data->max_rate; + + return divider_determine_rate(hw, req, div_hw_data->dtable, div_hw_data->width, + CLK_DIVIDER_ROUND_CLOSEST); +} + +static int rzg3s_div_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw); + struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data); + struct rzg2l_cpg_priv *priv = clk_hw_data->priv; + u32 off = GET_REG_OFFSET(clk_hw_data->conf); + u32 shift = GET_SHIFT(clk_hw_data->conf); + unsigned long flags; + u32 val; + int ret; + + val = divider_get_val(rate, parent_rate, div_hw_data->dtable, div_hw_data->width, + CLK_DIVIDER_ROUND_CLOSEST); + + spin_lock_irqsave(&priv->rmw_lock, flags); + writel((CPG_WEN_BIT | val) << shift, priv->base + off); + /* Wait for the update done. */ + ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf); + spin_unlock_irqrestore(&priv->rmw_lock, flags); + + return ret; +} + +static const struct clk_ops rzg3s_div_clk_ops = { + .recalc_rate = rzg3s_div_clk_recalc_rate, + .determine_rate = rzg3s_div_clk_determine_rate, + .set_rate = rzg3s_div_clk_set_rate, +}; + +static struct clk * __init +rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks, + void __iomem *base, struct rzg2l_cpg_priv *priv) +{ + struct div_hw_data *div_hw_data; + struct clk_init_data init = {}; + const struct clk_div_table *clkt; + struct clk_hw *clk_hw; + const struct clk *parent; + const char *parent_name; + u32 max = 0; + int ret; + + parent = clks[core->parent & 0xffff]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + parent_name = __clk_get_name(parent); + + div_hw_data = devm_kzalloc(priv->dev, sizeof(*div_hw_data), GFP_KERNEL); + if (!div_hw_data) + return ERR_PTR(-ENOMEM); + + init.name = core->name; + init.flags = core->flag; + init.ops = &rzg3s_div_clk_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + /* Get the maximum divider to retrieve div width. */ + for (clkt = core->dtable; clkt->div; clkt++) { + if (max < clkt->div) + max = clkt->div; + } + + div_hw_data->hw_data.priv = priv; + div_hw_data->hw_data.conf = core->conf; + div_hw_data->hw_data.sconf = core->sconf; + div_hw_data->dtable = core->dtable; + div_hw_data->invalid_rate = core->invalid_rate; + div_hw_data->max_rate = core->max_rate; + div_hw_data->width = fls(max) - 1; + + clk_hw = &div_hw_data->hw_data.hw; + clk_hw->init = &init; + + ret = devm_clk_hw_register(priv->dev, clk_hw); + if (ret) + return ERR_PTR(ret); + + ret = rzg2l_register_notifier(clk_hw, core, priv); + if (ret) { + dev_err(priv->dev, "Failed to register notifier for %s\n", + core->name); + return ERR_PTR(ret); + } + + return clk_hw->clk; +} + static struct clk * __init rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks, @@ -964,6 +1147,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, clk = rzg2l_cpg_div_clk_register(core, priv->clks, priv->base, priv); break; + case CLK_TYPE_G3S_DIV: + clk = rzg3s_cpg_div_clk_register(core, priv->clks, priv->base, priv); + break; case CLK_TYPE_MUX: clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv); break; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index f1910913b29a..4755befaf38e 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -89,6 +89,8 @@ struct cpg_core_clk { unsigned int sconf; const struct clk_div_table *dtable; const u32 *mtable; + const unsigned long invalid_rate; + const unsigned long max_rate; const char * const *parent_names; notifier_fn_t notifier; u32 flag; @@ -105,6 +107,7 @@ enum clk_types { /* Clock with divider */ CLK_TYPE_DIV, + CLK_TYPE_G3S_DIV, /* Clock with clock source selector */ CLK_TYPE_MUX, @@ -143,6 +146,13 @@ enum clk_types { DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ .parent = _parent, .dtable = _dtable, \ .flag = CLK_DIVIDER_READ_ONLY) +#define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \ + _max_rate, _clk_flags, _notif) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \ + .parent = _parent, .dtable = _dtable, \ + .invalid_rate = _invalid_rate, \ + .max_rate = _max_rate, .flag = (_clk_flags), \ + .notifier = _notif) #define DEF_MUX(_name, _id, _conf, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ .parent_names = _parent_names, \ @@ -277,5 +287,6 @@ extern const struct rzg2l_cpg_info r9a07g054_cpg_info; extern const struct rzg2l_cpg_info r9a09g011_cpg_info; int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data); +int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); #endif From patchwork Fri Apr 19 08:17:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AF17C04FFF for ; Fri, 19 Apr 2024 08:18:28 +0000 (UTC) Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) by mx.groups.io with SMTP id smtpd.web10.15306.1713514701106389637 for ; Fri, 19 Apr 2024 01:18:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=K7OZ4SZ7; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:19 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 23/53] dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC Date: Fri, 19 Apr 2024 11:17:12 +0300 Message-Id: <20240419081742.3496709-24-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15610 From: Claudiu Beznea commit e372aee8c24957cbcb55d93b14ba386096497bca upstream. Add documentation for the RZ/G3S CPG. The RZ/G3S CPG module is almost identical to the one available in RZ/G2{L,UL}, the exception being some core clocks as follows: - The SD clock is composed of a mux and a divider, and the divider has some limitations (div = 1 cannot be set if mux rate is 800MHz), - There are 3 SD clocks, - The OCTA and TSU clocks are specific to RZ/G3S, - PLL1/4/6 are specific to RZ/G3S with its own computation formula. Even with this RZ/G3S could use the same bindings as RZ/G2L. Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse Generator (CPG) core clocks, module clocks and resets were added. Signed-off-by: Claudiu Beznea Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-13-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../bindings/clock/renesas,rzg2l-cpg.yaml | 1 + include/dt-bindings/clock/r9a08g045-cpg.h | 242 ++++++++++++++++++ 2 files changed, 243 insertions(+) create mode 100644 include/dt-bindings/clock/r9a08g045-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 8880b834f264..614a3f82b55f 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -27,6 +27,7 @@ properties: - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a08g045-cpg # RZ/G3S - renesas,r9a09g011-cpg # RZ/V2M reg: diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h new file mode 100644 index 000000000000..410725b778a8 --- /dev/null +++ b/include/dt-bindings/clock/r9a08g045-cpg.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ + +#include + +/* R9A08G045 CPG Core Clocks */ +#define R9A08G045_CLK_I 0 +#define R9A08G045_CLK_I2 1 +#define R9A08G045_CLK_I3 2 +#define R9A08G045_CLK_S0 3 +#define R9A08G045_CLK_SPI0 4 +#define R9A08G045_CLK_SPI1 5 +#define R9A08G045_CLK_SD0 6 +#define R9A08G045_CLK_SD1 7 +#define R9A08G045_CLK_SD2 8 +#define R9A08G045_CLK_M0 9 +#define R9A08G045_CLK_HP 10 +#define R9A08G045_CLK_TSU 11 +#define R9A08G045_CLK_ZT 12 +#define R9A08G045_CLK_P0 13 +#define R9A08G045_CLK_P1 14 +#define R9A08G045_CLK_P2 15 +#define R9A08G045_CLK_P3 16 +#define R9A08G045_CLK_P4 17 +#define R9A08G045_CLK_P5 18 +#define R9A08G045_CLK_AT 19 +#define R9A08G045_CLK_OC0 20 +#define R9A08G045_CLK_OC1 21 +#define R9A08G045_OSCCLK 22 +#define R9A08G045_OSCCLK2 23 +#define R9A08G045_SWD 24 + +/* R9A08G045 Module Clocks */ +#define R9A08G045_OCTA_ACLK 0 +#define R9A08G045_OCTA_MCLK 1 +#define R9A08G045_CA55_SCLK 2 +#define R9A08G045_CA55_PCLK 3 +#define R9A08G045_CA55_ATCLK 4 +#define R9A08G045_CA55_GICCLK 5 +#define R9A08G045_CA55_PERICLK 6 +#define R9A08G045_CA55_ACLK 7 +#define R9A08G045_CA55_TSCLK 8 +#define R9A08G045_SRAM_ACPU_ACLK0 9 +#define R9A08G045_SRAM_ACPU_ACLK1 10 +#define R9A08G045_SRAM_ACPU_ACLK2 11 +#define R9A08G045_GIC600_GICCLK 12 +#define R9A08G045_IA55_CLK 13 +#define R9A08G045_IA55_PCLK 14 +#define R9A08G045_MHU_PCLK 15 +#define R9A08G045_SYC_CNT_CLK 16 +#define R9A08G045_DMAC_ACLK 17 +#define R9A08G045_DMAC_PCLK 18 +#define R9A08G045_OSTM0_PCLK 19 +#define R9A08G045_OSTM1_PCLK 20 +#define R9A08G045_OSTM2_PCLK 21 +#define R9A08G045_OSTM3_PCLK 22 +#define R9A08G045_OSTM4_PCLK 23 +#define R9A08G045_OSTM5_PCLK 24 +#define R9A08G045_OSTM6_PCLK 25 +#define R9A08G045_OSTM7_PCLK 26 +#define R9A08G045_MTU_X_MCK_MTU3 27 +#define R9A08G045_POE3_CLKM_POE 28 +#define R9A08G045_GPT_PCLK 29 +#define R9A08G045_POEG_A_CLKP 30 +#define R9A08G045_POEG_B_CLKP 31 +#define R9A08G045_POEG_C_CLKP 32 +#define R9A08G045_POEG_D_CLKP 33 +#define R9A08G045_WDT0_PCLK 34 +#define R9A08G045_WDT0_CLK 35 +#define R9A08G045_WDT1_PCLK 36 +#define R9A08G045_WDT1_CLK 37 +#define R9A08G045_WDT2_PCLK 38 +#define R9A08G045_WDT2_CLK 39 +#define R9A08G045_SPI_HCLK 40 +#define R9A08G045_SPI_ACLK 41 +#define R9A08G045_SPI_CLK 42 +#define R9A08G045_SPI_CLKX2 43 +#define R9A08G045_SDHI0_IMCLK 44 +#define R9A08G045_SDHI0_IMCLK2 45 +#define R9A08G045_SDHI0_CLK_HS 46 +#define R9A08G045_SDHI0_ACLK 47 +#define R9A08G045_SDHI1_IMCLK 48 +#define R9A08G045_SDHI1_IMCLK2 49 +#define R9A08G045_SDHI1_CLK_HS 50 +#define R9A08G045_SDHI1_ACLK 51 +#define R9A08G045_SDHI2_IMCLK 52 +#define R9A08G045_SDHI2_IMCLK2 53 +#define R9A08G045_SDHI2_CLK_HS 54 +#define R9A08G045_SDHI2_ACLK 55 +#define R9A08G045_SSI0_PCLK2 56 +#define R9A08G045_SSI0_PCLK_SFR 57 +#define R9A08G045_SSI1_PCLK2 58 +#define R9A08G045_SSI1_PCLK_SFR 59 +#define R9A08G045_SSI2_PCLK2 60 +#define R9A08G045_SSI2_PCLK_SFR 61 +#define R9A08G045_SSI3_PCLK2 62 +#define R9A08G045_SSI3_PCLK_SFR 63 +#define R9A08G045_SRC_CLKP 64 +#define R9A08G045_USB_U2H0_HCLK 65 +#define R9A08G045_USB_U2H1_HCLK 66 +#define R9A08G045_USB_U2P_EXR_CPUCLK 67 +#define R9A08G045_USB_PCLK 68 +#define R9A08G045_ETH0_CLK_AXI 69 +#define R9A08G045_ETH0_CLK_CHI 70 +#define R9A08G045_ETH0_REFCLK 71 +#define R9A08G045_ETH1_CLK_AXI 72 +#define R9A08G045_ETH1_CLK_CHI 73 +#define R9A08G045_ETH1_REFCLK 74 +#define R9A08G045_I2C0_PCLK 75 +#define R9A08G045_I2C1_PCLK 76 +#define R9A08G045_I2C2_PCLK 77 +#define R9A08G045_I2C3_PCLK 78 +#define R9A08G045_SCIF0_CLK_PCK 79 +#define R9A08G045_SCIF1_CLK_PCK 80 +#define R9A08G045_SCIF2_CLK_PCK 81 +#define R9A08G045_SCIF3_CLK_PCK 82 +#define R9A08G045_SCIF4_CLK_PCK 83 +#define R9A08G045_SCIF5_CLK_PCK 84 +#define R9A08G045_SCI0_CLKP 85 +#define R9A08G045_SCI1_CLKP 86 +#define R9A08G045_IRDA_CLKP 87 +#define R9A08G045_RSPI0_CLKB 88 +#define R9A08G045_RSPI1_CLKB 89 +#define R9A08G045_RSPI2_CLKB 90 +#define R9A08G045_RSPI3_CLKB 91 +#define R9A08G045_RSPI4_CLKB 92 +#define R9A08G045_CANFD_PCLK 93 +#define R9A08G045_CANFD_CLK_RAM 94 +#define R9A08G045_GPIO_HCLK 95 +#define R9A08G045_ADC_ADCLK 96 +#define R9A08G045_ADC_PCLK 97 +#define R9A08G045_TSU_PCLK 98 +#define R9A08G045_PDM_PCLK 99 +#define R9A08G045_PDM_CCLK 100 +#define R9A08G045_PCI_ACLK 101 +#define R9A08G045_PCI_CLKL1PM 102 +#define R9A08G045_SPDIF_PCLK 103 +#define R9A08G045_I3C_PCLK 104 +#define R9A08G045_I3C_TCLK 105 +#define R9A08G045_VBAT_BCLK 106 + +/* R9A08G045 Resets */ +#define R9A08G045_CA55_RST_1_0 0 +#define R9A08G045_CA55_RST_3_0 1 +#define R9A08G045_CA55_RST_4 2 +#define R9A08G045_CA55_RST_5 3 +#define R9A08G045_CA55_RST_6 4 +#define R9A08G045_CA55_RST_7 5 +#define R9A08G045_CA55_RST_8 6 +#define R9A08G045_CA55_RST_9 7 +#define R9A08G045_CA55_RST_10 8 +#define R9A08G045_CA55_RST_11 9 +#define R9A08G045_CA55_RST_12 10 +#define R9A08G045_SRAM_ACPU_ARESETN0 11 +#define R9A08G045_SRAM_ACPU_ARESETN1 12 +#define R9A08G045_SRAM_ACPU_ARESETN2 13 +#define R9A08G045_GIC600_GICRESET_N 14 +#define R9A08G045_GIC600_DBG_GICRESET_N 15 +#define R9A08G045_IA55_RESETN 16 +#define R9A08G045_MHU_RESETN 17 +#define R9A08G045_DMAC_ARESETN 18 +#define R9A08G045_DMAC_RST_ASYNC 19 +#define R9A08G045_SYC_RESETN 20 +#define R9A08G045_OSTM0_PRESETZ 21 +#define R9A08G045_OSTM1_PRESETZ 22 +#define R9A08G045_OSTM2_PRESETZ 23 +#define R9A08G045_OSTM3_PRESETZ 24 +#define R9A08G045_OSTM4_PRESETZ 25 +#define R9A08G045_OSTM5_PRESETZ 26 +#define R9A08G045_OSTM6_PRESETZ 27 +#define R9A08G045_OSTM7_PRESETZ 28 +#define R9A08G045_MTU_X_PRESET_MTU3 29 +#define R9A08G045_POE3_RST_M_REG 30 +#define R9A08G045_GPT_RST_C 31 +#define R9A08G045_POEG_A_RST 32 +#define R9A08G045_POEG_B_RST 33 +#define R9A08G045_POEG_C_RST 34 +#define R9A08G045_POEG_D_RST 35 +#define R9A08G045_WDT0_PRESETN 36 +#define R9A08G045_WDT1_PRESETN 37 +#define R9A08G045_WDT2_PRESETN 38 +#define R9A08G045_SPI_HRESETN 39 +#define R9A08G045_SPI_ARESETN 40 +#define R9A08G045_SDHI0_IXRST 41 +#define R9A08G045_SDHI1_IXRST 42 +#define R9A08G045_SDHI2_IXRST 43 +#define R9A08G045_SSI0_RST_M2_REG 44 +#define R9A08G045_SSI1_RST_M2_REG 45 +#define R9A08G045_SSI2_RST_M2_REG 46 +#define R9A08G045_SSI3_RST_M2_REG 47 +#define R9A08G045_SRC_RST 48 +#define R9A08G045_USB_U2H0_HRESETN 49 +#define R9A08G045_USB_U2H1_HRESETN 50 +#define R9A08G045_USB_U2P_EXL_SYSRST 51 +#define R9A08G045_USB_PRESETN 52 +#define R9A08G045_ETH0_RST_HW_N 53 +#define R9A08G045_ETH1_RST_HW_N 54 +#define R9A08G045_I2C0_MRST 55 +#define R9A08G045_I2C1_MRST 56 +#define R9A08G045_I2C2_MRST 57 +#define R9A08G045_I2C3_MRST 58 +#define R9A08G045_SCIF0_RST_SYSTEM_N 59 +#define R9A08G045_SCIF1_RST_SYSTEM_N 60 +#define R9A08G045_SCIF2_RST_SYSTEM_N 61 +#define R9A08G045_SCIF3_RST_SYSTEM_N 62 +#define R9A08G045_SCIF4_RST_SYSTEM_N 63 +#define R9A08G045_SCIF5_RST_SYSTEM_N 64 +#define R9A08G045_SCI0_RST 65 +#define R9A08G045_SCI1_RST 66 +#define R9A08G045_IRDA_RST 67 +#define R9A08G045_RSPI0_RST 68 +#define R9A08G045_RSPI1_RST 69 +#define R9A08G045_RSPI2_RST 70 +#define R9A08G045_RSPI3_RST 71 +#define R9A08G045_RSPI4_RST 72 +#define R9A08G045_CANFD_RSTP_N 73 +#define R9A08G045_CANFD_RSTC_N 74 +#define R9A08G045_GPIO_RSTN 75 +#define R9A08G045_GPIO_PORT_RESETN 76 +#define R9A08G045_GPIO_SPARE_RESETN 77 +#define R9A08G045_ADC_PRESETN 78 +#define R9A08G045_ADC_ADRST_N 79 +#define R9A08G045_TSU_PRESETN 80 +#define R9A08G045_OCTA_ARESETN 81 +#define R9A08G045_PDM0_PRESETNT 82 +#define R9A08G045_PCI_ARESETN 83 +#define R9A08G045_PCI_RST_B 84 +#define R9A08G045_PCI_RST_GP_B 85 +#define R9A08G045_PCI_RST_PS_B 86 +#define R9A08G045_PCI_RST_RSM_B 87 +#define R9A08G045_PCI_RST_CFG_B 88 +#define R9A08G045_PCI_RST_LOAD_B 89 +#define R9A08G045_SPDIF_RST 90 +#define R9A08G045_I3C_TRESETN 91 +#define R9A08G045_I3C_PRESETN 92 +#define R9A08G045_VBAT_BRESETN 93 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */ From patchwork Fri Apr 19 08:17:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24841C41513 for ; Fri, 19 Apr 2024 08:18:28 +0000 (UTC) Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) by mx.groups.io with SMTP id smtpd.web10.15307.1713514702551836934 for ; Fri, 19 Apr 2024 01:18:22 -0700 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:20 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 24/53] clk: renesas: Add minimal boot support for RZ/G3S SoC Date: Fri, 19 Apr 2024 11:17:13 +0300 Message-Id: <20240419081742.3496709-25-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15611 From: Claudiu Beznea commit de60a3ebe410670ffdbbc95faa25a820da44ab11 upstream. Add minimal clock and reset support for the RZ/G3S SoC to be able to boot Linux from SD Card/eMMC. This includes necessary core clocks for booting and GIC, SCIF, GPIO, and SD0 module clocks and resets. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231006103959.197485-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a08g045-cpg.c | 214 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 6 + drivers/clk/renesas/rzg2l-cpg.h | 1 + 5 files changed, 228 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/renesas/r9a08g045-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 591c961979eb..8e03eab59115 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -35,6 +35,7 @@ config CLK_RENESAS select CLK_R9A07G043 if ARCH_R9A07G043 select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_R9A07G054 if ARCH_R9A07G054 + select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_SH73A0 if ARCH_SH73A0 @@ -171,6 +172,10 @@ config CLK_R9A07G054 bool "RZ/V2L clock support" if COMPILE_TEST select CLK_RZG2L +config CLK_R9A08G045 + bool "RZ/G3S clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_R9A09G011 bool "RZ/V2M clock support" if COMPILE_TEST select CLK_RZG2L @@ -198,7 +203,7 @@ config CLK_RCAR_USB2_CLOCK_SEL This is a driver for R-Car USB2 clock selector config CLK_RZG2L - bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST + bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER # Generic diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 2e57c7047dc3..34815dd77f58 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o +obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c new file mode 100644 index 000000000000..389d32b32168 --- /dev/null +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3S CPG driver + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzg2l-cpg.h" + +/* RZ/G3S Specific registers. */ +#define G3S_CPG_PL2_DDIV (0x204) +#define G3S_CPG_SDHI_DDIV (0x218) +#define G3S_CPG_PLL_DSEL (0x240) +#define G3S_CPG_SDHI_DSEL (0x244) +#define G3S_CLKDIVSTATUS (0x280) +#define G3S_CLKSELSTATUS (0x284) + +/* RZ/G3S Specific division configuration. */ +#define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3) +#define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1) + +/* RZ/G3S Clock status configuration. */ +#define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1) +#define G3S_DIVPL2B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 5, 1) +#define G3S_DIVPL3A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 8, 1) +#define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1) +#define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1) +#define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1) + +#define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1) +#define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1) + +/* RZ/G3S Specific clocks select. */ +#define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1) +#define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2) + +/* PLL 1/4/6 configuration registers macro. */ +#define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12) + +#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \ + .parent_names = (_parent_names), \ + .num_parents = ARRAY_SIZE((_parent_names)), \ + .mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \ + .flag = (_clk_flags)) + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A08G045_SWD, + + /* External Input Clocks */ + CLK_EXTAL, + + /* Internal Core Clocks */ + CLK_OSC_DIV1000, + CLK_PLL1, + CLK_PLL2, + CLK_PLL2_DIV2, + CLK_PLL2_DIV2_8, + CLK_PLL2_DIV6, + CLK_PLL3, + CLK_PLL3_DIV2, + CLK_PLL3_DIV2_4, + CLK_PLL3_DIV2_8, + CLK_PLL3_DIV6, + CLK_PLL4, + CLK_PLL6, + CLK_PLL6_DIV2, + CLK_SEL_SDHI0, + CLK_SEL_PLL4, + CLK_P1_DIV2, + CLK_P3_DIV2, + CLK_SD0_DIV4, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +/* Divider tables */ +static const struct clk_div_table dtable_1_2[] = { + { 0, 1 }, + { 1, 2 }, + { 0, 0 }, +}; + +static const struct clk_div_table dtable_1_8[] = { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 0, 0 }, +}; + +static const struct clk_div_table dtable_1_32[] = { + { 0, 1 }, + { 1, 2 }, + { 2, 4 }, + { 3, 8 }, + { 4, 32 }, + { 0, 0 }, +}; + +/* Mux clock names tables. */ +static const char * const sel_sdhi[] = { ".pll2_div2", ".pll6", ".pll2_div6" }; +static const char * const sel_pll4[] = { ".osc_div1000", ".pll4" }; + +/* Mux clock indices tables. */ +static const u32 mtable_sd[] = { 0, 2, 3 }; +static const u32 mtable_pll4[] = { 0, 1 }; + +static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + + /* Internal Core Clocks */ + DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), + DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3), + DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), + DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), + DEF_FIXED(".pll3_div2_8", CLK_PLL3_DIV2_8, CLK_PLL3_DIV2, 1, 8), + DEF_FIXED(".pll3_div6", CLK_PLL3_DIV6, CLK_PLL3, 1, 6), + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2), + DEF_SD_MUX(".sel_sd0", CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi, + mtable_sd, 0, NULL), + DEF_SD_MUX(".sel_pll4", CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4, + mtable_pll4, CLK_SET_PARENT_GATE, NULL), + + /* Core output clk */ + DEF_G3S_DIV("I", R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8, + 0, 0, 0, NULL), + DEF_G3S_DIV("P0", R9A08G045_CLK_P0, CLK_PLL2_DIV2_8, G3S_DIVPL2B, G3S_DIVPL2B_STS, + dtable_1_32, 0, 0, 0, NULL), + DEF_G3S_DIV("SD0", R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS, + dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, + rzg3s_cpg_div_clk_notifier), + DEF_FIXED(".sd0_div4", CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4), + DEF_FIXED("M0", R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), + DEF_G3S_DIV("P1", R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS, + dtable_1_32, 0, 0, 0, NULL), + DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A08G045_CLK_P1, 1, 2), + DEF_G3S_DIV("P2", R9A08G045_CLK_P2, CLK_PLL3_DIV2_8, DIVPL3B, G3S_DIVPL3B_STS, + dtable_1_32, 0, 0, 0, NULL), + DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS, + dtable_1_32, 0, 0, 0, NULL), + DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2), + DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2), + DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1), + DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3), +}; + +static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { + DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), + DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), + DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), + DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), + DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), + DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2), + DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3), + DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), + DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), +}; + +static const struct rzg2l_reset r9a08g045_resets[] = { + DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), + DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), + DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), + DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), +}; + +static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { + MOD_CLK_BASE + R9A08G045_GIC600_GICCLK, + MOD_CLK_BASE + R9A08G045_IA55_CLK, + MOD_CLK_BASE + R9A08G045_DMAC_ACLK, +}; + +const struct rzg2l_cpg_info r9a08g045_cpg_info = { + /* Core Clocks */ + .core_clks = r9a08g045_core_clks, + .num_core_clks = ARRAY_SIZE(r9a08g045_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks = r9a08g045_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r9a08g045_crit_mod_clks), + + /* Module Clocks */ + .mod_clks = r9a08g045_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks), + .num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1, + + /* Resets */ + .resets = r9a08g045_resets, + .num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs = true, +}; diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3b691445bf52..e05471a6ca8d 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1728,6 +1728,12 @@ static const struct of_device_id rzg2l_cpg_match[] = { .data = &r9a07g054_cpg_info, }, #endif +#ifdef CONFIG_CLK_R9A08G045 + { + .compatible = "renesas,r9a08g045-cpg", + .data = &r9a08g045_cpg_info, + }, +#endif #ifdef CONFIG_CLK_R9A09G011 { .compatible = "renesas,r9a09g011-cpg", diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 4755befaf38e..6e38c8fc888c 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -284,6 +284,7 @@ struct rzg2l_cpg_info { extern const struct rzg2l_cpg_info r9a07g043_cpg_info; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; extern const struct rzg2l_cpg_info r9a07g054_cpg_info; +extern const struct rzg2l_cpg_info r9a08g045_cpg_info; extern const struct rzg2l_cpg_info r9a09g011_cpg_info; int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data); From patchwork Fri Apr 19 08:17:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33622C0650F for ; Fri, 19 Apr 2024 08:18:28 +0000 (UTC) Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) by mx.groups.io with SMTP id smtpd.web11.15270.1713514703418985405 for ; Fri, 19 Apr 2024 01:18:23 -0700 Authentication-Results: mx.groups.io; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 25/53] clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 Date: Fri, 19 Apr 2024 11:17:14 +0300 Message-Id: <20240419081742.3496709-26-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15612 From: Claudiu Beznea commit 4bce4bedbe6daa54cf701184601f913a0c00bb1c upstream. Add clock and reset support for the SDHI1 and SDHI2 blocks on the RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231010132701.1658737-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 34 +++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 389d32b32168..4394cb241d99 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -25,6 +25,8 @@ /* RZ/G3S Specific division configuration. */ #define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3) #define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1) +#define G3S_DIV_SDHI1 DDIV_PACK(G3S_CPG_SDHI_DDIV, 4, 1) +#define G3S_DIV_SDHI2 DDIV_PACK(G3S_CPG_SDHI_DDIV, 8, 1) /* RZ/G3S Clock status configuration. */ #define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1) @@ -33,13 +35,19 @@ #define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1) #define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1) #define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1) +#define G3S_DIV_SDHI1_STS DDIV_PACK(G3S_CLKDIVSTATUS, 25, 1) +#define G3S_DIV_SDHI2_STS DDIV_PACK(G3S_CLKDIVSTATUS, 26, 1) #define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1) #define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1) +#define G3S_SEL_SDHI1_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 17, 1) +#define G3S_SEL_SDHI2_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 18, 1) /* RZ/G3S Specific clocks select. */ #define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1) #define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2) +#define G3S_SEL_SDHI1 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2) +#define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2) /* PLL 1/4/6 configuration registers macro. */ #define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12) @@ -74,10 +82,14 @@ enum clk_ids { CLK_PLL6, CLK_PLL6_DIV2, CLK_SEL_SDHI0, + CLK_SEL_SDHI1, + CLK_SEL_SDHI2, CLK_SEL_PLL4, CLK_P1_DIV2, CLK_P3_DIV2, CLK_SD0_DIV4, + CLK_SD1_DIV4, + CLK_SD2_DIV4, /* Module Clocks */ MOD_CLK_BASE, @@ -136,6 +148,10 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2), DEF_SD_MUX(".sel_sd0", CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi, mtable_sd, 0, NULL), + DEF_SD_MUX(".sel_sd1", CLK_SEL_SDHI1, G3S_SEL_SDHI1, G3S_SEL_SDHI1_STS, sel_sdhi, + mtable_sd, 0, NULL), + DEF_SD_MUX(".sel_sd2", CLK_SEL_SDHI2, G3S_SEL_SDHI2, G3S_SEL_SDHI2_STS, sel_sdhi, + mtable_sd, 0, NULL), DEF_SD_MUX(".sel_pll4", CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4, mtable_pll4, CLK_SET_PARENT_GATE, NULL), @@ -147,7 +163,15 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { DEF_G3S_DIV("SD0", R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS, dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, rzg3s_cpg_div_clk_notifier), + DEF_G3S_DIV("SD1", R9A08G045_CLK_SD1, CLK_SEL_SDHI1, G3S_DIV_SDHI1, G3S_DIV_SDHI1_STS, + dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, + rzg3s_cpg_div_clk_notifier), + DEF_G3S_DIV("SD2", R9A08G045_CLK_SD2, CLK_SEL_SDHI2, G3S_DIV_SDHI2, G3S_DIV_SDHI2_STS, + dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, + rzg3s_cpg_div_clk_notifier), DEF_FIXED(".sd0_div4", CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4), + DEF_FIXED(".sd1_div4", CLK_SD1_DIV4, R9A08G045_CLK_SD1, 1, 4), + DEF_FIXED(".sd2_div4", CLK_SD2_DIV4, R9A08G045_CLK_SD2, 1, 4), DEF_FIXED("M0", R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), DEF_G3S_DIV("P1", R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS, dtable_1_32, 0, 0, 0, NULL), @@ -170,6 +194,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2), DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3), + DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4), + DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5), + DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6), + DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7), + DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8), + DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), + DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), + DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), }; @@ -178,6 +210,8 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), + DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), + DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), From patchwork Fri Apr 19 08:17:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33E7FC071FD for ; Fri, 19 Apr 2024 08:18:28 +0000 (UTC) Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) by mx.groups.io with SMTP id smtpd.web10.15309.1713514705131899848 for ; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:22 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 26/53] clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux Date: Fri, 19 Apr 2024 11:17:15 +0300 Message-Id: <20240419081742.3496709-27-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15613 From: Claudiu Beznea commit 9b2a11c83859c06233049b134bd8ee974b284559 upstream. The status configuration for SD1 mux clock is SEL_SDHI1_STS. Fix it. Fixes: 16b86e5c03c5 ("clk: renesas: rzg2l: Refactor SD mux driver") Reported-by: Hien Huynh Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240131102930.1841901-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a07g043-cpg.c | 2 +- drivers/clk/renesas/r9a07g044-cpg.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index b70bb378ab46..075ade0925d4 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -138,7 +138,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi, mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), - DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi, + DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_shdi, mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 7b18b9be76c7..22c03c8d4636 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -178,7 +178,7 @@ static const struct { DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi, mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), - DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi, + DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_shdi, mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), From patchwork Fri Apr 19 08:17:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B6A0C071DB for ; Fri, 19 Apr 2024 08:18:28 +0000 (UTC) Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) by mx.groups.io with SMTP id smtpd.web11.15271.1713514706463093491 for ; Fri, 19 Apr 2024 01:18:26 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=c6xfFG8f; spf=pass (domain: tuxon.dev, ip: 209.85.208.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-5708d8beec6so2167583a12.0 for ; Fri, 19 Apr 2024 01:18:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514705; x=1714119505; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a2u77/UNyhFBmoWyr1vZ7Mi5m07t/tZTJIfrMiV2dew=; b=c6xfFG8f6B4kspz+Qh2nbGc+IL3TAoqj+Uv1NURG3QE6r7XF8hPrUnRJ498Bxf8drT fBRuCzVGOxV1XitrgkZDFZGlmllQUIbg+VZbQGLCwjKQ65P/WIEZnr2TeUorcxxiDjBK 8gFlmdmyoiAmhTSIcGYkCKKBt2aoRiGlfqzLdh6AZJXpBgqKYuoBUYfU2QNDCB1L5xnR 1BjJUjAwfTUnbjoO/ABlb5iTg96ll3iH4Ia71Y6NIf0eJ2kRMU0PsbMmTQeI40q/495t xQlcC5pLI1QuwVnXFb+kxK8icVrN5CO6LszU2y5b1yVoS+Fy/eYrvIHUuPAzd71UQCLI jRuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514705; x=1714119505; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a2u77/UNyhFBmoWyr1vZ7Mi5m07t/tZTJIfrMiV2dew=; b=pTN1I0G8LhEfowzbEAOAGbYAewxRWfSIsLt7wEyDwlPFarKMOZqaRAK0trIs8tLGj4 GwPot5FP77X67LwKA98bcmP4trI2cNOY09p2RVTZyphoPrGJXTgFi5Fx7gi3lucVwN4f h6fdnzan9vQtI9cSn/b29XmcTAAxBxWxt8PY2YLE94JYAnzarl4IhsdPIN7XA6oJ718C VFxb6Xiw0R1O8r3wpVnEBTeeskETqWKqLMRGf4yhohGh2x5RPPAaJy+ll6TOg5eC4O8k 8rFyU8ZfUY9jJw3tFv2mHyA6HvM4ukiTTVNMYsSPwul1nsP9Xk/7I4uzLsHcmlPIQVz3 wcoA== X-Gm-Message-State: AOJu0Yz4gBupJaKT2IUnES/q05n4tDCziRwPjI36MZ8JPL210STEwyw2 zjYe2nlHgxkKPpEKLRMmvs1lCVq7mFv7VwDI6WlKhxcDH4X9Vv8enFqcoLq0pGc= X-Google-Smtp-Source: AGHT+IGwuD2hfGAI5Ery4nrdoVHeMKed+7wKbydjLcBfhxTcafJMPiz9GKkcTlOprsGeYqv0elYepw== X-Received: by 2002:a17:907:94ca:b0:a55:8a04:d729 with SMTP id dn10-20020a17090794ca00b00a558a04d729mr751754ejc.72.1713514704925; Fri, 19 Apr 2024 01:18:24 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:24 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 27/53] soc: renesas: Use "#ifdef" for single-symbol definition checks Date: Fri, 19 Apr 2024 11:17:16 +0300 Message-Id: <20240419081742.3496709-28-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15614 From: Geert Uytterhoeven commit 2653d5bf1c9d123c0d8b8c1634cf54dacfcfdb52 upstream. Replace "#if defined(CONFIG_)" by "#ifdef CONFIG_" for brevity. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/6026a3fe36735f0e6a0ecb037bf7c45f42aa3daf.1678705241.git.geert+renesas@glider.be [claudiu.beznea: adapt to v5.10] Signed-off-by: Claudiu Beznea --- drivers/soc/renesas/renesas-soc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 92584f5ab967..ba3dcdf8ddac 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -343,20 +343,20 @@ static const struct of_device_id renesas_socs[] __initconst = { #ifdef CONFIG_ARCH_R8A779A0 { .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u }, #endif -#if defined(CONFIG_ARCH_R9A07G043) +#ifdef CONFIG_ARCH_R9A07G043 #ifdef CONFIG_RISCV { .compatible = "renesas,r9a07g043", .data = &soc_rz_five }, #else { .compatible = "renesas,r9a07g043", .data = &soc_rz_g2ul }, #endif #endif -#if defined(CONFIG_ARCH_R9A07G044) +#ifdef CONFIG_ARCH_R9A07G044 { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l }, #endif -#if defined(CONFIG_ARCH_R9A07G054) +#ifdef CONFIG_ARCH_R9A07G054 { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, #endif -#if defined(CONFIG_ARCH_R9A09G011) +#ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif #ifdef CONFIG_ARCH_SH73A0 From patchwork Fri Apr 19 08:17:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 478DCC07C79 for ; Fri, 19 Apr 2024 08:18:28 +0000 (UTC) Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) by mx.groups.io with SMTP id smtpd.web11.15273.1713514707583403875 for ; Fri, 19 Apr 2024 01:18:27 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=ITVvoYY9; spf=pass (domain: tuxon.dev, ip: 209.85.218.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-a4715991c32so186186266b.1 for ; Fri, 19 Apr 2024 01:18:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514706; x=1714119506; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wGe8OhrNd5ExkofOMiSpKCzmNy8+dJX0t3+6P2ZkxLk=; b=ITVvoYY91bYm+zwenxHgEIK5/Ccf/sHdwN42EMB+GruMLofT3vl0qTJFEYVt01KB0u qtfHAW21vuTgeRmtwxq4WKDI44kuD/mvbiswkgTMTzyf8IYDlKZdsnbHqDgCVPm36V2e DzHbH7zOJMNGFwRTY5OlM6AZ/icpB7zK0Og6rPEMRYswl/oUr0OwYeb9NGzzvU6/590j cuJHK5KZryrl7Z2wydJS/97EFlstCOKbh8j0zsmM3TO2xn/pUvxdtBGmr8j5/6q0pc9C IzVpKgy91YUaVlwE3/rr3tnd0aaF9p64eK98Sq6HMMiLCOlQ1ktJuqqDFEoezacb/sXG kwyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514706; x=1714119506; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wGe8OhrNd5ExkofOMiSpKCzmNy8+dJX0t3+6P2ZkxLk=; b=SXdisyJ9sFcZbqXqQm4Fs50pFM4olighkK3eoS3jAsF1bj+1LNq8m4VVlvNsGR5gmX XgWXSZLMa6liGgdGTPYFYrJcLlJUVbTuhgK5QcYggaiq4d3aH0tpLNTO7uJVXcS81ZCn x39pInm59mAUdzB3d2w4nmcCE9S+D5/mpOU/x7IvbK3OSaBsjbkFc0kBNqBYrTqC2SeU eChjAEV38k98HAAXO4mveRMm3YGefTVjK678wCP4vcC8zlfzMo8t/pQHljWNoSVIn389 E6ch/s2GJvWC943dw72HoJpAIzNhXtcbzMKz9sO8ARVujeCzr1AHep7qYfyaNjI+ngY3 RkyA== X-Gm-Message-State: AOJu0YzqqUtmVRvwGYxGNNsDqFiD3Ef3KfXvbnRLn2DbfIQxnD8somrD drP3SwgZq8MO9eb6UYdRx0hk1OYNsIobtjY3Bja4X16jcH6WKKc3jWqQn2wCj/c= X-Google-Smtp-Source: AGHT+IGSbkk+7KNdX8YNNJdyNcBQqSG5Bzcaz+1Z/JtsYyK6VYkHkdkeBcbI8v+0EGYAtilTCxzy/A== X-Received: by 2002:a17:906:7708:b0:a51:969e:ba0 with SMTP id q8-20020a170906770800b00a51969e0ba0mr829204ejm.44.1713514706086; Fri, 19 Apr 2024 01:18:26 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:25 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 28/53] soc: renesas: Identify RZ/G3S SoC Date: Fri, 19 Apr 2024 11:17:17 +0300 Message-Id: <20240419081742.3496709-29-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15615 From: Claudiu Beznea commit 0b9729cdb895a477ba3551cd2102baee2e697cbb upstream. Add support to identify the RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912045157.177966-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/soc/renesas/Kconfig | 6 ++++++ drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 6256fd3b6efd..f9aed9eb9f43 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -303,6 +303,12 @@ config ARCH_R9A07G054 help This enables support for the Renesas RZ/V2L SoC variants. +config ARCH_R9A08G045 + bool "ARM64 Platform support for RZ/G3S" + select ARCH_RZG2L + help + This enables support for the Renesas RZ/G3S SoC variants. + config ARCH_R9A09G011 bool "ARM64 Platform support for RZ/V2M" select PM diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index ba3dcdf8ddac..854020afd1ab 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -68,6 +68,10 @@ static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = { .name = "RZ/G2UL", }; +static const struct renesas_family fam_rzg3s __initconst __maybe_unused = { + .name = "RZ/G3S", +}; + static const struct renesas_family fam_rzv2l __initconst __maybe_unused = { .name = "RZ/V2L", }; @@ -166,6 +170,11 @@ static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = { .id = 0x8450447, }; +static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = { + .family = &fam_rzg3s, + .id = 0x85e0447, +}; + static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = { .family = &fam_rzv2l, .id = 0x8447447, @@ -356,6 +365,9 @@ static const struct of_device_id renesas_socs[] __initconst = { #ifdef CONFIG_ARCH_R9A07G054 { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, #endif +#ifdef CONFIG_ARCH_R9A08G045 + { .compatible = "renesas,r9a08g045", .data = &soc_rz_g3s }, +#endif #ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif @@ -399,6 +411,7 @@ static const struct of_device_id renesas_ids[] __initconst = { { .compatible = "renesas,r9a07g043-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l }, + { .compatible = "renesas,r9a08g045-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m }, { .compatible = "renesas,prr", .data = &id_prr }, { /* sentinel */ } From patchwork Fri Apr 19 08:17:18 2024 Content-Type: text/plain; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:27 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 29/53] pinctrl: renesas: rzg2l: Make struct rzg2l_pinctrl_data::dedicated_pins constant Date: Fri, 19 Apr 2024 11:17:18 +0300 Message-Id: <20240419081742.3496709-30-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15616 From: Claudiu Beznea commit 84c580e9695084d688904a18bfdc129aeca78144 upstream. struct rzg2l_pinctrl_data::dedicated_pins is constant thus mark it so. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912045157.177966-29-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 2965c67d8ad0..e1d1142637ae 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -129,7 +129,7 @@ struct rzg2l_pinctrl_data { const char * const *port_pins; const u32 *port_pin_configs; unsigned int n_ports; - struct rzg2l_dedicated_configs *dedicated_pins; + const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; }; @@ -1055,7 +1055,7 @@ static const u32 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; -static struct { +static const struct { struct rzg2l_dedicated_configs common[35]; struct rzg2l_dedicated_configs rzg2l_pins[7]; } rzg2l_dedicated_pins = { From patchwork Fri Apr 19 08:17:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 435AFC4345F for ; Fri, 19 Apr 2024 08:18:38 +0000 (UTC) Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) by mx.groups.io with SMTP id smtpd.web10.15314.1713514711147304953 for ; Fri, 19 Apr 2024 01:18:31 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=OCC+G5Ck; spf=pass (domain: tuxon.dev, ip: 209.85.218.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-a5568bef315so312470866b.1 for ; Fri, 19 Apr 2024 01:18:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514709; x=1714119509; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PHVzgjXbfTrCSny9eYfxnklDdEKzyWdujMDMUKZpe4k=; b=OCC+G5CkjpB+ey2EzjEcfz54hSV4NBrdR2ADsTmBTJ8Ieyfx2zwc3e6wAgpjrVqNcp OTr2uKIOgFtwAMKRSrJcC9yXHyqEtBELvSXbMkn6l+MJhhKoN8LfG/jdUTL8WSZTuTxl prwKlXMbHALsHTYGeTtxJyPaUuC0EKVLcmSNwWm4/n5Wm38RTdbAEZp35RfSARUIZ60s 31ku0ZIlkMMvEGp3OyEHEuZNioL/XRfjTW9H3PNrIPqd/ZNYIqGHVXRgG7asLC9x8Eyf z96jKzYk10GkCdrE0EiewRG8IKmAcxAJjGWGxgcb8rPPYkptEEH03q0/FD2GmXu9qoUY SVtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514709; x=1714119509; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PHVzgjXbfTrCSny9eYfxnklDdEKzyWdujMDMUKZpe4k=; b=hRWGwI2b5XFgGNgPQn2PZchfTQjt1Yr797cO9fYso8plz5nKrONYKcGNKLBkrYsZeR PKir5Rci5nULCLeJfXkSZsemB63mB++lnJAfST808eJEC9om0RP/cKxvM+WRQZIJ/MVd TjFlxJP9UQx4z2/VP2YHFLXKwo4ldvAp/1FAoi7qgquPtEs6j69+4Lv0Kvg6rIg0CO3m 21Y51nGf5UheyZX/IYKqp8c+aa7IfeWLkVFYnwL/vftsMEiP6pQG5Qz7KS1Id0MXq6lz bebspon2jaVzjbEJ2gtFbUNATbd/XuZzG59Kyj/ClQ74TG+ovUCQzITFjF3Y3/cnSxZv wD7w== X-Gm-Message-State: AOJu0Yxu4JgyWOdqhsDZzh2FzPVjym+Gzb80BVn+GAvhYr9crzZSnavw j/9R6P1WQY0QMWm9gxNbTronK81nLuIcRQNBfESn0qEWigecXJ0g7JIc/Bf7gAA= X-Google-Smtp-Source: AGHT+IH2Euux8EDy52EQsQVMyKmlwc24OrVxraFsuIlh8+Jb0JQ9qPpNUPSpNkIMuOe1dmCn98dnxg== X-Received: by 2002:a17:906:b041:b0:a55:5520:f43f with SMTP id bj1-20020a170906b04100b00a555520f43fmr3548636ejb.10.1713514709482; Fri, 19 Apr 2024 01:18:29 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:28 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 30/53] pinctrl: renesas: rzg2l: Make reverse order of enable() for disable() Date: Fri, 19 Apr 2024 11:17:19 +0300 Message-Id: <20240419081742.3496709-31-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15617 From: Biju Das commit dd462cf53e4dff0f4eba5e6650e31ceddec74c6f upstream. We usually do reverse order of enable() for disable(). Currently, the ordering of irq_chip_disable_parent() is not correct in rzg2l_gpio_irq_disable(). Fix the incorrect order. Fixes: db2e5f21a48e ("pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt") Signed-off-by: Biju Das Tested-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230918123355.262115-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index e1d1142637ae..4802c6b1302a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1171,6 +1171,8 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) u32 port; u8 bit; + irq_chip_disable_parent(d); + port = RZG2L_PIN_ID_TO_PORT(hwirq); bit = RZG2L_PIN_ID_TO_PIN(hwirq); @@ -1185,7 +1187,6 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) spin_unlock_irqrestore(&pctrl->lock, flags); gpiochip_disable_irq(gc, hwirq); - irq_chip_disable_parent(d); } static void rzg2l_gpio_irq_enable(struct irq_data *d) From patchwork Fri Apr 19 08:17:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53149C04FFF for ; Fri, 19 Apr 2024 08:18:38 +0000 (UTC) Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) by mx.groups.io with SMTP id smtpd.web10.15315.1713514712796690959 for ; Fri, 19 Apr 2024 01:18:33 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=pcDUWRuv; spf=pass (domain: tuxon.dev, ip: 209.85.218.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-a5557e3ebcaso290874766b.1 for ; Fri, 19 Apr 2024 01:18:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514711; x=1714119511; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dbAYJfSHyWAa/RaHAACeJhexN6Yn1A33rLMrdz9biAY=; b=pcDUWRuv99awzZDd9V6Qwh9b/XRX1jkxgBxpuneY8ytG5XTG+giFwiQa81fO5+P563 drOmIT9LxNVe5/DD1a+yNMERNs5yoV9nhlDU4s8CUV6QjhVMMDEHBQq4CF+kpvYBiGAC eGCC4z1ALJ6AwZKSb4hu/Q6YPtxsnH0Rsg9+xYeGJPPW8YeSbCNfungVayd6OPeDBk/p 1EiLVW95RRLH3d4Jfhk5sWVHBracc44TpFwYwRVJ1jJftYQOREBSEUsyyf649wxoidxN i+5VZQCzXq1v3QOTPAVNBo8pah+PvCjppe6ETbAbz1LE0498DerRq+nPWr0HcIVKbZkk fLow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514711; x=1714119511; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dbAYJfSHyWAa/RaHAACeJhexN6Yn1A33rLMrdz9biAY=; b=GEK6LMMyYgyvJCYlJWbzzoFk9gqD7SLU6aaWnFelR3e9rJpShKdozuwwaaW5PLO1nf JFqJchoxpMaVDzCaFbh5wMHIIA+lgf6ctoVoLFUvLuYyAEYbkmsCGzZbcGLmP3U2aVsj AetuYpraq3gHWy1RCHLeTxV+YDu+UKu1X6D7oYu9q2uzKrK/NpjcqWcV9CZhc1AFVaK8 R/sx3dgYdazpoHutcZhZv0BpiPV/T8ipqM69br6UoONrCcI4lRN3xwthiR3b529Fucsp EMsSJNMmA235QyE2F0H587Z3mM4T/mP83i8Knv/qQNyUyzTM6jP49iArvp8YWbYgJbSs QjhQ== X-Gm-Message-State: AOJu0YzfVXwR7h44hiDWSxqHdDZ3ETx4WRxIc2TuYwnLYczGQPdwXL+j EAsmFU80awuTBKiZb02yBHrI4AAHe7/kIJbFfpYqfKKVq2A7QM/mgNEix4UP92Y= X-Google-Smtp-Source: AGHT+IFG8a2UixQX8uR72NZQZMa8BdO9vOr/FuEBdSe8VFdcekkywFBv+937K4BeanaqN/M9mjbgMw== X-Received: by 2002:a17:906:28d1:b0:a55:6c07:1569 with SMTP id p17-20020a17090628d100b00a556c071569mr1408934ejd.0.1713514711269; Fri, 19 Apr 2024 01:18:31 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:30 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 31/53] pinctrl: renesas: rzg2l: Rename rzg2l_gpio_configs[] Date: Fri, 19 Apr 2024 11:17:20 +0300 Message-Id: <20240419081742.3496709-32-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15618 From: Geert Uytterhoeven commit c385256611b1af79d180e35c07992b43e1be5067 upstream. The rzg2l_gpio_configs array is really related to the RZ/G2L (R9A07G044) Soc only. Hence rename it to r9a07g044_gpio_configs[]. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/19958e63a2b793be5182640c4301ec5a77a507f6.1695369116.git.geert+renesas@glider.be Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 4802c6b1302a..beb6fd73c3fa 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -981,7 +981,7 @@ static const char * const rzg2l_gpio_names[] = { "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", }; -static const u32 rzg2l_gpio_configs[] = { +static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), @@ -1483,7 +1483,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) struct clk *clk; int ret; - BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > + BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > @@ -1533,10 +1533,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pins = rzg2l_gpio_names, - .port_pin_configs = rzg2l_gpio_configs, - .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), + .port_pin_configs = r9a07g044_gpio_configs, + .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, - .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), }; From patchwork Fri Apr 19 08:17:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635800 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F731C05052 for ; Fri, 19 Apr 2024 08:18:38 +0000 (UTC) Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) by mx.groups.io with SMTP id smtpd.web10.15316.1713514714014936181 for ; Fri, 19 Apr 2024 01:18:34 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=nP6DSzUJ; spf=pass (domain: tuxon.dev, ip: 209.85.218.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-a5269c3f9c7so192702466b.2 for ; Fri, 19 Apr 2024 01:18:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514712; x=1714119512; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RoUlEaYptIxHAAha0kI3E2qQMB1I0667JVuMWCK9CEs=; b=nP6DSzUJBB1pCS5VTT+m2jPPaJxyyZe3+o9LT10+QatrNSIpzGKVNWXb3ueenzSwnt hszTm0IB6td1VS6DoZanE3UzruH5T6re/pHHrsI72OUPyyTvXB8ISmW8WeGHGLLAXDN7 pfzNYNa9txNA+EgV5vCdChtmy7yi2WW7rLcCBsPHSb9GvGp5jFdJPKNW0ihY+viuLsJj fTiYELOMt2bCcsDa6Yy/rBgPIq6QwYmSA7GONjrF3Gqp1K0NMIJl75IkeGelFxXIwUaB VIaHD4asBNZFPGX7Tpe1K5I8tSc4GXOsLpA3xKpTZHvvmyBXtM3HGcfqGz0w3IlrHqbH nJ2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514712; x=1714119512; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RoUlEaYptIxHAAha0kI3E2qQMB1I0667JVuMWCK9CEs=; b=GR+Y/SLVc2fZkfvabO2Cicffr1ggDFBHRw2xvIpW9+h+cP9T5bRwgpybgIZLUgjfSF QNyQ/bBX/ygZ6W0ALN1z8SsTwHbNNKBHQ7Nf/K+bYpPeiN6DmLARr25bQrpGsVL45agz r63EWajmHVrEglv6deYaiGWaO+UMSByfBCX2eOtHdkAS9DzrASHokv94wqUg0kCYGoJm e6ugo7/0wWGm09dZ6vckM3dbNFlYIVvf5s4J1WCV1muyTi7YwPM0A4/z851JUHumx/TB oj+RkZun+RAduHUW+4quUBwUhFe7si1YCQRobFS94oRP74K21IPD+J0L5X3J3ZI/VgN7 WcNA== X-Gm-Message-State: AOJu0YyWoxTGiS85ygfJRiYf1IgM3P0XFUvvlErC//nnm7eLe2p+UmbT hAxcc1MrvOCLJeVM33uBJKSWk0uvBtK9N9u0Zr5SKlOImuH/V9FGljDY81l0zhw= X-Google-Smtp-Source: AGHT+IHMRCijOOlv6zrh0OpXalajVhqnfr5nnvUVx6QL0ojtHYJwYbM5HT+m420UUfjzNJYpAUhXrg== X-Received: by 2002:a17:907:2daa:b0:a51:deec:483c with SMTP id gt42-20020a1709072daa00b00a51deec483cmr1236842ejc.6.1713514712499; Fri, 19 Apr 2024 01:18:32 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:32 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 32/53] pinctrl: renesas: rzg2l: Add validation of GPIO pin in rzg2l_gpio_request() Date: Fri, 19 Apr 2024 11:17:21 +0300 Message-Id: <20240419081742.3496709-33-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15619 From: Lad Prabhakar commit c944d9dea75e453d18bc8c100022e990c2eac3cb upstream. Validate the GPIO pin request in the rzg2l_gpio_request() callback using the rzg2l_validate_gpio_pin() function. This stops any accidental usage of GPIO pins which are not supported by the SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230925154548.27048-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index beb6fd73c3fa..85d9d2895fc3 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -791,12 +791,18 @@ static const struct pinconf_ops rzg2l_pinctrl_confops = { static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; u32 port = RZG2L_PIN_ID_TO_PORT(offset); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + u32 *pin_data = pin_desc->drv_data; unsigned long flags; u8 reg8; int ret; + ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); + if (ret) + return ret; + ret = pinctrl_gpio_request(chip->base + offset); if (ret) return ret; From patchwork Fri Apr 19 08:17:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6749BC071DB for ; Fri, 19 Apr 2024 08:18:38 +0000 (UTC) Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) by mx.groups.io with SMTP id smtpd.web11.15278.1713514715839922493 for ; Fri, 19 Apr 2024 01:18:36 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=MKzN1m14; spf=pass (domain: tuxon.dev, ip: 209.85.208.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-571d8606f40so137139a12.2 for ; Fri, 19 Apr 2024 01:18:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514714; x=1714119514; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X82k7BqJfzzgb+MIBLJCPJD4rVxRCpJxx2olbchS56c=; b=MKzN1m14o30Gij9DtMShAXl9Pvvusu7ZuYZgrTFdTg/bLsNsQ1FLbFj5DqglmL31a/ h1AP4BYyj/wXUunsbftC8QX3LuzxSQCEYZ50r5BXDgRnYW3L4CNghEUWKq6gdPu+9OPh 6h76ayDtvOr12LTS+NwHgM1OvbUuRBWIUahpNO1Gd3WXrK2emkrzdgDjqOO0Cp8ABgv9 Xi40UeLMuKs6jycMEWUfNyRW6WYOVIISdLJQpnfp4HCAZfiLdDbVMublggG5Utf1Eatu MFgxvufGHQVmCV4XrbtJC/AyoLuq3OCNe30K8jr3h31yn6ljdAUpUCeHCYYVBHmjvPbP IySA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514714; x=1714119514; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X82k7BqJfzzgb+MIBLJCPJD4rVxRCpJxx2olbchS56c=; b=jts7yFUPJ/eShXOPPhimmscFeo247RR6fet75fYMQ6C9vsSzzVEvBR3LPU5xqGLfGj VZcAF9PTM0rrfYgZfVt19Q+YJWT7SNSSUN4Qg7Ehtzgx+NXiIINVG9vH7fMCNpqK9jQY bplfrIsD36gdrD5Q5OM7f9n5UoQSDaPAKMop/u3TlhE/nfsLfiF+jeFYEvnr6MIhKxro oxTIovCWJ1UYNEsBa/a+JwAcN2WPfss73zFLMly94PPBm3nKjOqs/PnJXY11aXEoqehu atnCuuaTg9deb/FTwGV834Zd/aj+ZCa3Y076XR0DxYuSUoq2XUjWl+G/jjjwXvyk63uT UBRw== X-Gm-Message-State: AOJu0YwE2DWgGOEnXieNjCsb4TAXoqLJ81IWKs+i/tfq2hqBYkFzjdvF SfiPnpwFWRgJvatROPJgk/i4pBLODG6fa6CMH2YMPSIBvPS+H3sfqGUT5/qBiik= X-Google-Smtp-Source: AGHT+IEio1RmcR06EybV+Aw5ZBqtZCIQVa3AlhnzpsAxbtajqkj4kmu9e0HIyJfy5DGpKBl++soCxg== X-Received: by 2002:a17:906:754:b0:a51:d1f6:3938 with SMTP id z20-20020a170906075400b00a51d1f63938mr976657ejb.42.1713514714149; Fri, 19 Apr 2024 01:18:34 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:33 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 33/53] pinctrl: renesas: rzg2l: Index all registers based on port offset Date: Fri, 19 Apr 2024 11:17:22 +0300 Message-Id: <20240419081742.3496709-34-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15620 From: Claudiu Beznea commit 77e18969da3a5a0ed5f7c3b80869c0acf25377ab upstream. To get the address that needs to be read/written for specific port functionalities, the P(), PM(), PMC(), PFC(), PIN(), IOLH() IEN(), ISEL() macros are used. Some of these macros receive as argument the hardware port identifier, some the hardware port offset address (e.g. ISEL() received port identifier, IOLH() received port offset address). This makes it hard to extend the current driver for SoCs where port identifiers are not contiguous in the memory map of the pin controller. This is the case for the RZ/G3S pin controller where ports are mapped as follows: port offset port identifier ----------- --------------- 0x20 P0 0x21 P5 0x22 P6 0x23 P11 0x24 P12 0x25 P13 0x26 P14 0x27 P15 0x28 P16 0x29 P17 0x2a P18 0x30 P1 0x31 P2 0x32 P3 0x33 P4 0x34 P7 0x35 P8 0x36 P8 0x37 P10 To make this achievable, change all the above macros used to get the address of a port register for a specific port functionality based on the port hardware address. Summarized, all the above macros will get as argument the port offset address listed in the above table. With this RZG2L_SINGLE_PIN_GET_PORT_OFFSET(), RZG2L_PIN_ID_TO_PORT_OFFSET() and RZG2L_GPIO_PORT_GET_INDEX() were replaced by RZG2L_PIN_CFG_TO_PORT_OFFSET(); RZG2L_SINGLE_PIN_GET_CFGS() and RZG2L_GPIO_PORT_GET_CFGS() were replaced by RZG2L_PIN_CFG_TO_CAPS(). Also rzg2l_pinctrl_set_pfc_mode() does not need the port argument anymore. Also rzg2l_gpio_direction_input() and rzg2l_gpio_direction_output() do not need to translate port and bit locally as this can be done by rzg2l_gpio_set_direction(). To use the same naming for port, bit/pin, and register offset, replace the port_offset variable names in different places by variables named off. There is no longer a need to initialize cfg and bit in different code places. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Link: https://lore.kernel.org/r/20230929053915.1530607-15-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 174 ++++++++++++------------ 1 file changed, 88 insertions(+), 86 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 85d9d2895fc3..4ebdb74ba7c6 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -70,8 +70,6 @@ */ #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) -#define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) -#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) /* * BIT(31) indicates dedicated pin, p is the register index while @@ -81,18 +79,21 @@ #define RZG2L_SINGLE_PIN BIT(31) #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ ((p) << 24) | ((b) << 20) | (f)) -#define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) -#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) - -#define P(n) (0x0000 + 0x10 + (n)) -#define PM(n) (0x0100 + 0x20 + (n) * 2) -#define PMC(n) (0x0200 + 0x10 + (n)) -#define PFC(n) (0x0400 + 0x40 + (n) * 4) -#define PIN(n) (0x0800 + 0x10 + (n)) -#define IOLH(n) (0x1000 + (n) * 8) -#define IEN(n) (0x1800 + (n) * 8) -#define ISEL(n) (0x2c80 + (n) * 8) + +#define RZG2L_PIN_CFG_TO_CAPS(cfg) ((cfg) & GENMASK(19, 0)) +#define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ + (((cfg) & GENMASK(30, 24)) >> 24) : \ + (((cfg) & GENMASK(26, 20)) >> 20)) + +#define P(off) (0x0000 + (off)) +#define PM(off) (0x0100 + (off) * 2) +#define PMC(off) (0x0200 + (off)) +#define PFC(off) (0x0400 + (off) * 4) +#define PIN(off) (0x0800 + (off)) +#define IOLH(off) (0x1000 + (off) * 8) +#define IEN(off) (0x1800 + (off) * 8) +#define ISEL(off) (0x2C00 + (off) * 8) #define PWPR (0x3014) #define SD_CH(n) (0x3000 + (n) * 4) #define QSPI (0x3008) @@ -113,7 +114,6 @@ #define PM_OUTPUT 0x2 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) -#define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) #define RZG2L_TINT_MAX_INTERRUPT 32 @@ -157,7 +157,7 @@ static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, - u8 port, u8 pin, u8 func) + u8 pin, u8 off, u8 func) { unsigned long flags; u32 reg; @@ -165,30 +165,30 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, spin_lock_irqsave(&pctrl->lock, flags); /* Set pin to 'Non-use (Hi-Z input protection)' */ - reg = readw(pctrl->base + PM(port)); + reg = readw(pctrl->base + PM(off)); reg &= ~(PM_MASK << (pin * 2)); - writew(reg, pctrl->base + PM(port)); + writew(reg, pctrl->base + PM(off)); /* Temporarily switch to GPIO mode with PMC register */ - reg = readb(pctrl->base + PMC(port)); - writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); + reg = readb(pctrl->base + PMC(off)); + writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); /* Set the PWPR register to allow PFC register to write */ writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ /* Select Pin function mode with PFC register */ - reg = readl(pctrl->base + PFC(port)); + reg = readl(pctrl->base + PFC(off)); reg &= ~(PFC_MASK << (pin * 4)); - writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); + writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); /* Set the PWPR register to be write-protected */ writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ /* Switch to Peripheral pin function with PMC register */ - reg = readb(pctrl->base + PMC(port)); - writeb(reg | BIT(pin), pctrl->base + PMC(port)); + reg = readb(pctrl->base + PMC(off)); + writeb(reg | BIT(pin), pctrl->base + PMC(off)); spin_unlock_irqrestore(&pctrl->lock, flags); }; @@ -214,11 +214,14 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, pins = group->pins; for (i = 0; i < group->num_pins; i++) { - dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", - RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), - psel_val[i]); - rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), - RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); + unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); + + dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", + RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i]); + + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i]); } return 0; @@ -464,14 +467,14 @@ static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, u32 cfg, u32 port, u8 bit) { u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); - u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); u32 data; if (bit >= pincount || port >= pctrl->data->n_port_pins) return -EINVAL; data = pctrl->data->port_pin_configs[port]; - if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data)) + if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) return -EINVAL; return 0; @@ -521,20 +524,17 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int arg = 0; unsigned long flags; void __iomem *addr; - u32 port_offset; - u32 cfg = 0; - u8 bit = 0; + u32 off, cfg; + u8 bit; if (!pin_data) return -EINVAL; + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); - cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); } else { - cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); - port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); bit = RZG2L_PIN_ID_TO_PIN(_pin); if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) @@ -545,7 +545,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_ENABLE: if (!(cfg & PIN_CFG_IEN)) return -EINVAL; - arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); + arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); if (!arg) return -EINVAL; break; @@ -575,7 +575,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IOLH_A)) return -EINVAL; - index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); + index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); arg = iolh_groupa_mA[index]; break; } @@ -586,7 +586,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IOLH_B)) return -EINVAL; - index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); + index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); arg = iolh_groupb_oi[index]; break; } @@ -611,21 +611,18 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, enum pin_config_param param; unsigned long flags; void __iomem *addr; - u32 port_offset; unsigned int i; - u32 cfg = 0; - u8 bit = 0; + u32 cfg, off; + u8 bit; if (!pin_data) return -EINVAL; + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); - cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); } else { - cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); - port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); bit = RZG2L_PIN_ID_TO_PIN(_pin); if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) @@ -642,7 +639,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IEN)) return -EINVAL; - rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); + rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); break; } @@ -683,7 +680,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (index >= ARRAY_SIZE(iolh_groupa_mA)) return -EINVAL; - rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); + rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; } @@ -701,7 +698,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (index >= ARRAY_SIZE(iolh_groupb_oi)) return -EINVAL; - rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); + rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; } @@ -792,9 +789,10 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + u32 *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 port = RZG2L_PIN_ID_TO_PORT(offset); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); - u32 *pin_data = pin_desc->drv_data; unsigned long flags; u8 reg8; int ret; @@ -810,28 +808,32 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) spin_lock_irqsave(&pctrl->lock, flags); /* Select GPIO mode in PMC Register */ - reg8 = readb(pctrl->base + PMC(port)); + reg8 = readb(pctrl->base + PMC(off)); reg8 &= ~BIT(bit); - writeb(reg8, pctrl->base + PMC(port)); + writeb(reg8, pctrl->base + PMC(off)); spin_unlock_irqrestore(&pctrl->lock, flags); return 0; } -static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, - u8 bit, bool output) +static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, + bool output) { + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; u16 reg16; spin_lock_irqsave(&pctrl->lock, flags); - reg16 = readw(pctrl->base + PM(port)); + reg16 = readw(pctrl->base + PM(off)); reg16 &= ~(PM_MASK << (bit * 2)); reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); - writew(reg16, pctrl->base + PM(port)); + writew(reg16, pctrl->base + PM(off)); spin_unlock_irqrestore(&pctrl->lock, flags); } @@ -839,13 +841,15 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); - if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { + if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { u16 reg16; - reg16 = readw(pctrl->base + PM(port)); + reg16 = readw(pctrl->base + PM(off)); reg16 = (reg16 >> (bit * 2)) & PM_MASK; if (reg16 == PM_OUTPUT) return GPIO_LINE_DIRECTION_OUT; @@ -858,10 +862,8 @@ static int rzg2l_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); - u8 bit = RZG2L_PIN_ID_TO_PIN(offset); - rzg2l_gpio_set_direction(pctrl, port, bit, false); + rzg2l_gpio_set_direction(pctrl, offset, false); return 0; } @@ -870,19 +872,21 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; u8 reg8; spin_lock_irqsave(&pctrl->lock, flags); - reg8 = readb(pctrl->base + P(port)); + reg8 = readb(pctrl->base + P(off)); if (value) - writeb(reg8 | BIT(bit), pctrl->base + P(port)); + writeb(reg8 | BIT(bit), pctrl->base + P(off)); else - writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); + writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); spin_unlock_irqrestore(&pctrl->lock, flags); } @@ -891,11 +895,9 @@ static int rzg2l_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); - u8 bit = RZG2L_PIN_ID_TO_PIN(offset); rzg2l_gpio_set(chip, offset, value); - rzg2l_gpio_set_direction(pctrl, port, bit, true); + rzg2l_gpio_set_direction(pctrl, offset, true); return 0; } @@ -903,17 +905,19 @@ static int rzg2l_gpio_direction_output(struct gpio_chip *chip, static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); - u32 port = RZG2L_PIN_ID_TO_PORT(offset); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); u16 reg16; - reg16 = readw(pctrl->base + PM(port)); + reg16 = readw(pctrl->base + PM(off)); reg16 = (reg16 >> (bit * 2)) & PM_MASK; if (reg16 == PM_INPUT) - return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); + return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); else if (reg16 == PM_OUTPUT) - return !!(readb(pctrl->base + P(port)) & BIT(bit)); + return !!(readb(pctrl->base + P(off)) & BIT(bit)); else return -EINVAL; } @@ -1172,17 +1176,16 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; void __iomem *addr; - u32 port; - u8 bit; irq_chip_disable_parent(d); - port = RZG2L_PIN_ID_TO_PORT(hwirq); - bit = RZG2L_PIN_ID_TO_PIN(hwirq); - - addr = pctrl->base + ISEL(port); + addr = pctrl->base + ISEL(off); if (bit >= 4) { bit -= 4; addr += 4; @@ -1200,17 +1203,16 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; + unsigned int *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; void __iomem *addr; - u32 port; - u8 bit; gpiochip_enable_irq(gc, hwirq); - port = RZG2L_PIN_ID_TO_PORT(hwirq); - bit = RZG2L_PIN_ID_TO_PIN(hwirq); - - addr = pctrl->base + ISEL(port); + addr = pctrl->base + ISEL(off); if (bit >= 4) { bit -= 4; addr += 4; From patchwork Fri Apr 19 08:17:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 774D0C0650F for ; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:35 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 34/53] pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets Date: Fri, 19 Apr 2024 11:17:23 +0300 Message-Id: <20240419081742.3496709-35-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15621 From: Claudiu Beznea commit 1f89aa906fac1d569ecf8f427b1edca6e26fa472 upstream. SD, PWPR power registers have different offsets b/w RZ/G2L and RZ/G3S. Add a per SoC configuration data structure that is initialized with the proper register offsets for individual SoCs. The rzg2l_hwcfg structure will be extended further in later commits. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-16-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 52 ++++++++++++++++++++----- 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 4ebdb74ba7c6..f6a7041028b6 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -94,8 +94,7 @@ #define IOLH(off) (0x1000 + (off) * 8) #define IEN(off) (0x1800 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) -#define PWPR (0x3014) -#define SD_CH(n) (0x3000 + (n) * 4) +#define SD_CH(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ @@ -120,6 +119,24 @@ #define RZG2L_TINT_IRQ_START_INDEX 9 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) +/** + * struct rzg2l_register_offsets - specific register offsets + * @pwpr: PWPR register offset + * @sd_ch: SD_CH register offset + */ +struct rzg2l_register_offsets { + u16 pwpr; + u16 sd_ch; +}; + +/** + * struct rzg2l_hwcfg - hardware configuration data structure + * @regs: hardware specific register offsets + */ +struct rzg2l_hwcfg { + const struct rzg2l_register_offsets regs; +}; + struct rzg2l_dedicated_configs { const char *name; u32 config; @@ -132,6 +149,7 @@ struct rzg2l_pinctrl_data { const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; + const struct rzg2l_hwcfg *hwcfg; }; struct rzg2l_pinctrl { @@ -159,6 +177,7 @@ static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { + const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; unsigned long flags; u32 reg; @@ -174,8 +193,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); /* Set the PWPR register to allow PFC register to write */ - writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ - writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ + writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ /* Select Pin function mode with PFC register */ reg = readl(pctrl->base + PFC(off)); @@ -183,8 +202,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); /* Set the PWPR register to be write-protected */ - writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ - writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ + writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ /* Switch to Peripheral pin function with PMC register */ reg = readb(pctrl->base + PMC(off)); @@ -519,6 +538,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; unsigned int arg = 0; @@ -554,9 +575,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, u32 pwr_reg = 0x0; if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg = SD_CH(0); + pwr_reg = SD_CH(regs->sd_ch, 0); else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg = SD_CH(1); + pwr_reg = SD_CH(regs->sd_ch, 1); else if (cfg & PIN_CFG_IO_VMC_QSPI) pwr_reg = QSPI; else @@ -608,6 +629,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; enum pin_config_param param; unsigned long flags; void __iomem *addr; @@ -651,9 +674,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, return -EINVAL; if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg = SD_CH(0); + pwr_reg = SD_CH(regs->sd_ch, 0); else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg = SD_CH(1); + pwr_reg = SD_CH(regs->sd_ch, 1); else if (cfg & PIN_CFG_IO_VMC_QSPI) pwr_reg = QSPI; else @@ -1530,6 +1553,13 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) return 0; } +static const struct rzg2l_hwcfg rzg2l_hwcfg = { + .regs = { + .pwpr = 0x3014, + .sd_ch = 0x3000, + }, +}; + static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, @@ -1537,6 +1567,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), + .hwcfg = &rzg2l_hwcfg, }; static struct rzg2l_pinctrl_data r9a07g044_data = { @@ -1547,6 +1578,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), + .hwcfg = &rzg2l_hwcfg, }; static const struct of_device_id rzg2l_pinctrl_of_table[] = { From patchwork Fri Apr 19 08:17:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66EA2C4345F for ; Fri, 19 Apr 2024 08:18:48 +0000 (UTC) Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) by mx.groups.io with SMTP id smtpd.web11.15280.1713514718860523571 for ; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:36 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 35/53] pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S Date: Fri, 19 Apr 2024 11:17:24 +0300 Message-Id: <20240419081742.3496709-36-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15622 From: Claudiu Beznea commit 35a3610e5a2407913dd6505de06975ba5056af9e upstream. On RZ/G3S PFC register allow setting 8 functions for individual ports (function1 to function8). For function1 the register need to be configured with 0, for function8 the register need to be configured with 7. We cannot use zero based addressing when requesting functions from different code places as the documentation (RZG3S_pinfunction_List_r1.0.xlsx) states explicitly that function0 is GPIO. Add a new member to struct rzg2l_hwcfg that will keep the offset that needs to be substracted before applying a value to a PFC register. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-17-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index f6a7041028b6..e924bd19ecfb 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -132,9 +132,11 @@ struct rzg2l_register_offsets { /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @func_base: base number for port function (see register PFC) */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + u8 func_base; }; struct rzg2l_dedicated_configs { @@ -217,6 +219,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int group_selector) { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct function_desc *func; unsigned int i, *psel_val; struct group_desc *group; @@ -238,9 +241,9 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", - RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i]); + RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i]); + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); } return 0; From patchwork Fri Apr 19 08:17:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6821AC04FF6 for ; Fri, 19 Apr 2024 08:18:48 +0000 (UTC) Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) by mx.groups.io with SMTP id smtpd.web11.15282.1713514720313720819 for ; Fri, 19 Apr 2024 01:18:40 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=kkMtumQF; spf=pass (domain: tuxon.dev, ip: 209.85.218.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a5561b88bb3so187516966b.0 for ; Fri, 19 Apr 2024 01:18:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514719; x=1714119519; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iV7kggneN0m0q162OOT+99CLLUIKLoK2ZdGhsP7+6Lg=; b=kkMtumQF/6TD01Wt7xU84bIrOYjPVfyDwEbEpiDnNuwqvdF4Webl8u18jFWavfoxWA SzVjoPtncv+2OsfX3rGRTHG0TATGqw2vwBxt4sertmIgx3B/w6Jqjja+xzC0iQxtnX3J MD1xXvgJ/dp+KrmyiF9g8Vcxm/Xxn8jCsbAxaon1KoKq7wC8zJ4GDup5TTbC08igAWgq u0IFSoQKt9m4Zn5sQJyhPYN3a+saFYX54+wEUVWploKtnaTPD3mAYu7B0bGhfJ4nEw6W PNvl0j+Ixx5ak5x5KehMJHTFgsRWyV1WvjL4HUwiCfrAs5QVW93atk5edTiHuK05rogz 530w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514719; x=1714119519; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iV7kggneN0m0q162OOT+99CLLUIKLoK2ZdGhsP7+6Lg=; b=nMPKsavsLaG/YvoMczbW2n3VolUU4q20tRV8im+l54GLDldl0Juli2iocraKBtDZEY DgHLZJTWAsdVLBZeyHjB+8kJjmGAQ7DKtDM8vl1I36codX7E6sRCNfNo9MPOtErfbXLw JsYrQ7e73jcvlB097+ajVjCSI51N/0b8BpAg/GsSTZmNw3AACmI/m9N4XzW6pAFH4kdT zfp0wYgAPLvW3Hc3poYnCJNWeSeTqxC/X8mv3zZ9Yjx2oSibwfNq2yPITKne70J4vDFD lDhPP+vBb3VqVgKYVeM7vpy7lPCBbm77/Fz4sIFhCbPJv6Ern+Fllez8R077Oy4SnHE6 qxzQ== X-Gm-Message-State: AOJu0YxW/OU2AcpZs4X7LDkY/tWuReIAHgCnKZMNw42VTs9Hc0qvCGGF zShKcOwDPqd8UaKOf32bYeiiFj+lBwSMkUxiOq7NCfiG48Nc2lKkWwYm1EhcP94= X-Google-Smtp-Source: AGHT+IF4RoXiQLRXRqnQq/9i3gfUo06cb+EiAXY9PXmvYhthNyxK7Loaats2RF9x6BOn0gzS3Sx0RQ== X-Received: by 2002:a17:906:1b4b:b0:a52:5383:c22 with SMTP id p11-20020a1709061b4b00b00a5253830c22mr1186046ejg.69.1713514718785; Fri, 19 Apr 2024 01:18:38 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:38 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 36/53] pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration Date: Fri, 19 Apr 2024 11:17:25 +0300 Message-Id: <20240419081742.3496709-37-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15623 From: Claudiu Beznea commit cca38201b492305dd1fbd3d28df398b5595f4836 upstream. Move drive strength and output impedance values to the SoC-specific configuration data structure (struct rzg2l_hwcfg). This allows extending the drive strength support for RZ/G3S. Along with this the DS values were converted to uA for simple integration with RZ/G3S support. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-18-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 42 ++++++++++++++++++------- 1 file changed, 31 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index e924bd19ecfb..9791df26e149 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -129,13 +129,30 @@ struct rzg2l_register_offsets { u16 sd_ch; }; +/** + * enum rzg2l_iolh_index - starting indices in IOLH specific arrays + * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source + * @RZG2L_IOLH_IDX_MAX: maximum index + */ +enum rzg2l_iolh_index { + RZG2L_IOLH_IDX_3V3 = 0, + RZG2L_IOLH_IDX_MAX = 4, +}; + +/* Maximum number of driver strength entries per power source. */ +#define RZG2L_IOLH_MAX_DS_ENTRIES (4) + /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @iolh_groupa_ua: IOLH group A uA specific values + * @iolh_groupb_oi: IOLH group B output impedance specific values * @func_base: base number for port function (see register PFC) */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; + u16 iolh_groupb_oi[4]; u8 func_base; }; @@ -173,9 +190,6 @@ struct rzg2l_pinctrl { struct mutex mutex; /* serialize adding groups and functions */ }; -static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; -static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; - static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -600,7 +614,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); - arg = iolh_groupa_mA[index]; + arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; break; } @@ -611,7 +625,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); - arg = iolh_groupb_oi[index]; + arg = hwcfg->iolh_groupb_oi[index]; break; } @@ -699,11 +713,12 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IOLH_A)) return -EINVAL; - for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { - if (arg == iolh_groupa_mA[index]) + for (index = RZG2L_IOLH_IDX_3V3; + index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { + if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) break; } - if (index >= ARRAY_SIZE(iolh_groupa_mA)) + if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) return -EINVAL; rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); @@ -717,11 +732,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, if (!(cfg & PIN_CFG_IOLH_B)) return -EINVAL; - for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) { - if (arg == iolh_groupb_oi[index]) + for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { + if (arg == hwcfg->iolh_groupb_oi[index]) break; } - if (index >= ARRAY_SIZE(iolh_groupb_oi)) + if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) return -EINVAL; rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); @@ -1561,6 +1576,11 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .pwpr = 0x3014, .sd_ch = 0x3000, }, + .iolh_groupa_ua = { + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, + }, + .iolh_groupb_oi = { 100, 66, 50, 33, }, }; static struct rzg2l_pinctrl_data r9a07g043_data = { From patchwork Fri Apr 19 08:17:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73983C05052 for ; Fri, 19 Apr 2024 08:18:48 +0000 (UTC) Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) by mx.groups.io with SMTP id smtpd.web11.15283.1713514721672585289 for ; Fri, 19 Apr 2024 01:18:42 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=QnUtImla; spf=pass (domain: tuxon.dev, ip: 209.85.218.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a5269c3f9c7so192718066b.2 for ; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:39 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 37/53] pinctrl: renesas: rzg2l: Add support for different DS values on different groups Date: Fri, 19 Apr 2024 11:17:26 +0300 Message-Id: <20240419081742.3496709-38-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15624 From: Claudiu Beznea commit ae5b425faf1074a757fad093085f6be654b7db99 upstream. RZ/G3S supports different drive strength values for different power sources and pin groups (A, B, C). On each group there could be up to 4 drive strength values per power source. Available power sources are 1v8, 2v5, 3v3. Drive strength values are more fine tuned than what was previously available on the driver thus the necessity of having micro-amp support. As drive strength and power source values are linked together the hardware setup for these was moved at the end of rzg2l_pinctrl_pinconf_set() to ensure proper validation of the new values. The drive strength values are expected to be initialized though the SoC-specific hardware configuration data structure. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-19-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 323 ++++++++++++++++++++---- 1 file changed, 272 insertions(+), 51 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 9791df26e149..a3f6f2507e7c 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -51,6 +51,8 @@ #define PIN_CFG_FILONOFF BIT(10) #define PIN_CFG_FILNUM BIT(11) #define PIN_CFG_FILCLKSEL BIT(12) +#define PIN_CFG_IOLH_C BIT(13) +#define PIN_CFG_SOFT_PS BIT(14) #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ PIN_CFG_SR | \ @@ -131,12 +133,16 @@ struct rzg2l_register_offsets { /** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays + * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source + * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source * @RZG2L_IOLH_IDX_MAX: maximum index */ enum rzg2l_iolh_index { - RZG2L_IOLH_IDX_3V3 = 0, - RZG2L_IOLH_IDX_MAX = 4, + RZG2L_IOLH_IDX_1V8 = 0, + RZG2L_IOLH_IDX_2V5 = 4, + RZG2L_IOLH_IDX_3V3 = 8, + RZG2L_IOLH_IDX_MAX = 12, }; /* Maximum number of driver strength entries per power source. */ @@ -146,13 +152,19 @@ enum rzg2l_iolh_index { * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets * @iolh_groupa_ua: IOLH group A uA specific values + * @iolh_groupb_ua: IOLH group B uA specific values + * @iolh_groupc_ua: IOLH group C uA specific values * @iolh_groupb_oi: IOLH group B output impedance specific values + * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) * @func_base: base number for port function (see register PFC) */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; + u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; + u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; u16 iolh_groupb_oi[4]; + bool drive_strength_ua; u8 func_base; }; @@ -171,6 +183,16 @@ struct rzg2l_pinctrl_data { const struct rzg2l_hwcfg *hwcfg; }; +/** + * struct rzg2l_pinctrl_pin_settings - pin data + * @power_source: power source + * @drive_strength_ua: drive strength (in micro amps) + */ +struct rzg2l_pinctrl_pin_settings { + u16 power_source; + u16 drive_strength_ua; +}; + struct rzg2l_pinctrl { struct pinctrl_dev *pctl; struct pinctrl_desc desc; @@ -188,8 +210,12 @@ struct rzg2l_pinctrl { spinlock_t lock; /* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ + + struct rzg2l_pinctrl_pin_settings *settings; }; +static const u16 available_ps[] = { 1800, 2500, 3300 }; + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -549,6 +575,156 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, spin_unlock_irqrestore(&pctrl->lock, flags); } +static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) +{ + if (caps & PIN_CFG_IO_VMC_SD0) + return SD_CH(regs->sd_ch, 0); + if (caps & PIN_CFG_IO_VMC_SD1) + return SD_CH(regs->sd_ch, 1); + if (caps & PIN_CFG_IO_VMC_QSPI) + return QSPI; + + return -EINVAL; +} + +static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) +{ + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; + int pwr_reg; + + if (caps & PIN_CFG_SOFT_PS) + return pctrl->settings[pin].power_source; + + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); + if (pwr_reg < 0) + return pwr_reg; + + return (readl(pctrl->base + pwr_reg) & PVDD_MASK) ? 1800 : 3300; +} + +static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) +{ + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; + int pwr_reg; + + if (caps & PIN_CFG_SOFT_PS) { + pctrl->settings[pin].power_source = ps; + return 0; + } + + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); + if (pwr_reg < 0) + return pwr_reg; + + writel((ps == 1800) ? PVDD_1800 : PVDD_3300, pctrl->base + pwr_reg); + pctrl->settings[pin].power_source = ps; + + return 0; +} + +static bool rzg2l_ps_is_supported(u16 ps) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(available_ps); i++) { + if (available_ps[i] == ps) + return true; + } + + return false; +} + +static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(available_ps); i++) { + if (available_ps[i] == ps) + break; + } + + /* + * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have + * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source + */ + return i * RZG2L_IOLH_MAX_DS_ENTRIES; +} + +static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) +{ + if (caps & PIN_CFG_IOLH_A) + return hwcfg->iolh_groupa_ua[val]; + + if (caps & PIN_CFG_IOLH_B) + return hwcfg->iolh_groupb_ua[val]; + + if (caps & PIN_CFG_IOLH_C) + return hwcfg->iolh_groupc_ua[val]; + + /* Should not happen. */ + return 0; +} + +static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, + enum rzg2l_iolh_index ps_index, u16 ua) +{ + const u16 *array = NULL; + unsigned int i; + + if (caps & PIN_CFG_IOLH_A) + array = &hwcfg->iolh_groupa_ua[ps_index]; + + if (caps & PIN_CFG_IOLH_B) + array = &hwcfg->iolh_groupb_ua[ps_index]; + + if (caps & PIN_CFG_IOLH_C) + array = &hwcfg->iolh_groupc_ua[ps_index]; + + if (!array) + return -EINVAL; + + for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { + if (array[i] == ua) + return i; + } + + return -EINVAL; +} + +static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, + enum rzg2l_iolh_index iolh_idx, + u16 ds) +{ + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const u16 *array = NULL; + unsigned int i; + + if (caps & PIN_CFG_IOLH_A) + array = hwcfg->iolh_groupa_ua; + + if (caps & PIN_CFG_IOLH_B) + array = hwcfg->iolh_groupb_ua; + + if (caps & PIN_CFG_IOLH_C) + array = hwcfg->iolh_groupc_ua; + + /* Should not happen. */ + if (!array) + return false; + + if (!array[iolh_idx]) + return false; + + for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { + if (array[iolh_idx + i] == ds) + return true; + } + + return false; +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) @@ -556,13 +732,11 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; - const struct rzg2l_register_offsets *regs = &hwcfg->regs; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; unsigned int *pin_data = pin->drv_data; unsigned int arg = 0; - unsigned long flags; - void __iomem *addr; u32 off, cfg; + int ret; u8 bit; if (!pin_data) @@ -588,40 +762,49 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; break; - case PIN_CONFIG_POWER_SOURCE: { - u32 pwr_reg = 0x0; - - if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg = SD_CH(regs->sd_ch, 0); - else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg = SD_CH(regs->sd_ch, 1); - else if (cfg & PIN_CFG_IO_VMC_QSPI) - pwr_reg = QSPI; - else - return -EINVAL; - - spin_lock_irqsave(&pctrl->lock, flags); - addr = pctrl->base + pwr_reg; - arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300; - spin_unlock_irqrestore(&pctrl->lock, flags); + case PIN_CONFIG_POWER_SOURCE: + ret = rzg2l_get_power_source(pctrl, _pin, cfg); + if (ret < 0) + return ret; + arg = ret; break; - } case PIN_CONFIG_DRIVE_STRENGTH: { unsigned int index; - if (!(cfg & PIN_CFG_IOLH_A)) + if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); + /* + * Drive strenght mA is supported only by group A and only + * for 3V3 port source. + */ arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; break; } + case PIN_CONFIG_DRIVE_STRENGTH_UA: { + enum rzg2l_iolh_index iolh_idx; + u8 val; + + if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || + !hwcfg->drive_strength_ua) + return -EINVAL; + + ret = rzg2l_get_power_source(pctrl, _pin, cfg); + if (ret < 0) + return ret; + iolh_idx = rzg2l_ps_to_iolh_idx(ret); + val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); + arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); + break; + } + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { unsigned int index; - if (!(cfg & PIN_CFG_IOLH_B)) + if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) return -EINVAL; index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); @@ -645,14 +828,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; - unsigned int *pin_data = pin->drv_data; const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; - const struct rzg2l_register_offsets *regs = &hwcfg->regs; + struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; + unsigned int *pin_data = pin->drv_data; enum pin_config_param param; - unsigned long flags; - void __iomem *addr; unsigned int i; u32 cfg, off; + int ret; u8 bit; if (!pin_data) @@ -683,34 +865,15 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, break; } - case PIN_CONFIG_POWER_SOURCE: { - unsigned int mV = pinconf_to_config_argument(_configs[i]); - u32 pwr_reg = 0x0; - - if (mV != 1800 && mV != 3300) - return -EINVAL; - - if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg = SD_CH(regs->sd_ch, 0); - else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg = SD_CH(regs->sd_ch, 1); - else if (cfg & PIN_CFG_IO_VMC_QSPI) - pwr_reg = QSPI; - else - return -EINVAL; - - addr = pctrl->base + pwr_reg; - spin_lock_irqsave(&pctrl->lock, flags); - writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr); - spin_unlock_irqrestore(&pctrl->lock, flags); + case PIN_CONFIG_POWER_SOURCE: + settings.power_source = pinconf_to_config_argument(_configs[i]); break; - } case PIN_CONFIG_DRIVE_STRENGTH: { unsigned int arg = pinconf_to_config_argument(_configs[i]); unsigned int index; - if (!(cfg & PIN_CFG_IOLH_A)) + if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) return -EINVAL; for (index = RZG2L_IOLH_IDX_3V3; @@ -725,11 +888,19 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, break; } + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || + !hwcfg->drive_strength_ua) + return -EINVAL; + + settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]); + break; + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { unsigned int arg = pinconf_to_config_argument(_configs[i]); unsigned int index; - if (!(cfg & PIN_CFG_IOLH_B)) + if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) return -EINVAL; for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { @@ -748,6 +919,39 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, } } + /* Apply power source. */ + if (settings.power_source != pctrl->settings[_pin].power_source) { + ret = rzg2l_ps_is_supported(settings.power_source); + if (!ret) + return -EINVAL; + + /* Apply power source. */ + ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); + if (ret) + return ret; + } + + /* Apply drive strength. */ + if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { + enum rzg2l_iolh_index iolh_idx; + int val; + + iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); + ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, + settings.drive_strength_ua); + if (!ret) + return -EINVAL; + + /* Get register value for this PS/DS tuple. */ + val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); + if (val < 0) + return val; + + /* Apply drive strength. */ + rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); + pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; + } + return 0; } @@ -1462,6 +1666,7 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) { + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct pinctrl_pin_desc *pins; unsigned int i, j; u32 *pin_data; @@ -1504,6 +1709,22 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) pins[index].drv_data = &pin_data[index]; } + pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), + GFP_KERNEL); + if (!pctrl->settings) + return -ENOMEM; + + for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { + if (pin_data[i] & PIN_CFG_SOFT_PS) { + pctrl->settings[i].power_source = 3300; + } else { + ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); + if (ret < 0) + continue; + pctrl->settings[i].power_source = ret; + } + } + ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, &pctrl->pctl); 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:41 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 38/53] dt-bindings: pinctrl: renesas: Document RZ/G3S SoC Date: Fri, 19 Apr 2024 11:17:27 +0300 Message-Id: <20240419081742.3496709-39-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15625 From: Claudiu Beznea commit 60e4dc192ce2ebabcdd7c3487387a802110dc1a5 upstream. Add documentation for the pin controller found on the Renesas RZ/G3S (R9A08G045) SoC. Compared to RZ/G2{L,UL}, RZ/G3S has 82 general-purpose IOs, no slew rate and output impedance support, and more values for drive strength which needs to be expressed in microamp. Signed-off-by: Claudiu Beznea Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-21-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index b1cbb8a4b0c0..692d87356f7d 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -25,6 +25,7 @@ properties: - enum: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + - renesas,r9a08g045-pinctrl # RZ/G3S - items: - enum: @@ -77,6 +78,21 @@ additionalProperties: - $ref: pincfg-node.yaml# - $ref: pinmux-node.yaml# + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a08g045-pinctrl + then: + properties: + drive-strength: false + output-impedance-ohms: false + slew-rate: false + else: + properties: + drive-strength-microamp: false + description: Pin controller client devices use pin configuration subnodes (children and grandchildren) for desired pin configuration. @@ -92,6 +108,10 @@ additionalProperties: pins: true drive-strength: enum: [ 2, 4, 8, 12 ] + drive-strength-microamp: + enum: [ 1900, 2200, 4000, 4400, 4500, 4700, 5200, 5300, 5700, + 5800, 6000, 6050, 6100, 6550, 6800, 7000, 8000, 9000, + 10000 ] output-impedance-ohms: enum: [ 33, 50, 66, 100 ] power-source: From patchwork Fri Apr 19 08:17:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82C87C41513 for ; Fri, 19 Apr 2024 08:18:48 +0000 (UTC) Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) by mx.groups.io with SMTP id smtpd.web10.15317.1713514724887666043 for ; Fri, 19 Apr 2024 01:18:45 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=fiCdOBn/; spf=pass (domain: tuxon.dev, ip: 209.85.218.53, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-a5568bef315so312505766b.1 for ; Fri, 19 Apr 2024 01:18:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514723; x=1714119523; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xsk2O0phvjbEZspd3XQuGgqDn9SdeqDV3GczTLp/M1g=; b=fiCdOBn/+JVGdanqBcCym4ktmhpS5FUJ66bJVDqu13uf6yQOtbcN2SxxdK23mRLUpm 5VQBONzmMFrZfL984JO5tgCoOab1LL8LTNk6xdj+Mi2gulehPsxOlSAfcWmA6GHxN4L4 YfjIbuCPpfRcIg3uI1vIZ3i53TECPrY5gJ0x9vbLLfpeb7Oe2FsyCosEGgS+gXclibA6 F5PhxCYiFEVTJsBK8j1V1cKGGu9nKuL2XwRRVFXqQmPS51IFFX0/wOGdhw5NCsXBQh+i Hnm8KW6qhc0ACLtalrQVj8aILlMa1WxruJfv61ncUsgMsXW6UVaf4MoXytu6BpHGUWpp PFpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514723; x=1714119523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xsk2O0phvjbEZspd3XQuGgqDn9SdeqDV3GczTLp/M1g=; b=vTFZPie1G/qBWcgPRXcnkg2iB1jqo6cOextnMwes7XdPxVDDf55/0Ojr2++1TVRabX +cf6Pc2T83GWmlA9HcKvDvm51gjKW9asjQVysvIdkeHv6ZjhB9dxAtw37HoojSMVCr19 y7fHVIZeW/MB2In48dQQiCpuKdwJW4xgGJcUCnXZdOdKeciCnOe/ZYoEgCb5YKPNyM9w R7BlmEcQ+QoDjWxKF3nl71Mn+VQNjmFLThiYDKEAc45QMkslKbYkwlCm71jJXt1u2EBu BraGDrhRzTtymZfX4d13c8WIYmuHkPhTGIFR+d3x0IxHj0iSrb3aNrITnPkDzABHCF6E 0Kgw== X-Gm-Message-State: AOJu0YwbgbfkFY/obPixQyZJxpGg6q99dwg/V3c5BGj+Ktpi5ggIz/z+ ZFISmNO72+z0xIXaTHgJfv110ML9nbFsf504442Tl061klkxfrPO/atjNDWZUEI= X-Google-Smtp-Source: AGHT+IHn9+KGOurjv7EpHbWV9yNCm6GB78kMrLwoOLzqVnGKaC6PeZgZNlKkYrtl1uTDQImD4Ukxrw== X-Received: by 2002:a17:906:46d6:b0:a52:613d:b5 with SMTP id k22-20020a17090646d600b00a52613d00b5mr1603670ejs.13.1713514723207; Fri, 19 Apr 2024 01:18:43 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:42 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 39/53] pinctrl: renesas: rzg2l: Add RZ/G3S support Date: Fri, 19 Apr 2024 11:17:28 +0300 Message-Id: <20240419081742.3496709-40-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15626 From: Claudiu Beznea commit c6a088e5a03b37a1ee646986b4ef44121715b46e upstream. Add basic support for RZ/G3S to be able to boot from SD card, have a running console port, and use GPIOs. RZ/G3S has 82 general-purpose IO ports. Support for the remaining pin functions (e.g. Ethernet, XSPI) will be added along with controller-specific support. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-22-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 126 +++++++++++++++++++++++- 1 file changed, 124 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a3f6f2507e7c..a3f31065c4bc 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -54,13 +54,19 @@ #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) -#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ - PIN_CFG_SR | \ +#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ + (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ PIN_CFG_FILONOFF | \ PIN_CFG_FILNUM | \ PIN_CFG_FILCLKSEL) +#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ + PIN_CFG_SR) + +#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ + PIN_CFG_SOFT_PS) + #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ PIN_CFG_FILONOFF | \ PIN_CFG_FILNUM | \ @@ -1310,6 +1316,36 @@ static const u32 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; +static const u32 r9a08g045_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ + RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH0)), /* P1 */ + RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH0)), /* P2 */ + RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH0)), /* P3 */ + RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH0)), /* P4 */ + RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ + RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ + RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH1)), /* P7 */ + RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH1)), /* P8 */ + RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH1)), /* P9 */ + RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | + PIN_CFG_IO_VMC_ETH1)), /* P10 */ + RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ + RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ + RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ + RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ + RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ + RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ + RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ + RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ +}; + static const struct { struct rzg2l_dedicated_configs common[35]; struct rzg2l_dedicated_configs rzg2l_pins[7]; @@ -1396,6 +1432,46 @@ static const struct { } }; +static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { + { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | + PIN_CFG_FILCLKSEL)) }, + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | + PIN_CFG_SOFT_PS)) }, + { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD0)) }, + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, + { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1)) }, +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) { unsigned int gpioint; @@ -1759,6 +1835,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -1804,6 +1883,35 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .iolh_groupb_oi = { 100, 66, 50, 33, }, }; +static const struct rzg2l_hwcfg rzg3s_hwcfg = { + .regs = { + .pwpr = 0x3000, + .sd_ch = 0x3004, + }, + .iolh_groupa_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, + }, + .iolh_groupb_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, + }, + .iolh_groupc_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, + /* 2v5 source */ + [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, + }, + .drive_strength_ua = true, + .func_base = 1, +}; + static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, @@ -1825,6 +1933,16 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .hwcfg = &rzg2l_hwcfg, }; +static struct rzg2l_pinctrl_data r9a08g045_data = { + .port_pins = rzg2l_gpio_names, + .port_pin_configs = r9a08g045_gpio_configs, + .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), + .dedicated_pins = rzg3s_dedicated_pins, + .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), + .hwcfg = &rzg3s_hwcfg, +}; + static const struct of_device_id rzg2l_pinctrl_of_table[] = { { .compatible = "renesas,r9a07g043-pinctrl", @@ -1834,6 +1952,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { .compatible = "renesas,r9a07g044-pinctrl", .data = &r9a07g044_data, }, + { + .compatible = "renesas,r9a08g045-pinctrl", + .data = &r9a08g045_data, + }, { /* sentinel */ } }; From patchwork Fri Apr 19 08:17:29 2024 Content-Type: text/plain; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:44 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 40/53] dt-bindings: mmc: renesas,sdhi: Document RZ/G3S support Date: Fri, 19 Apr 2024 11:17:29 +0300 Message-Id: <20240419081742.3496709-41-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:48 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15627 From: Claudiu Beznea commit 3b7eee6aae0b3212183fa63a4ae7887924218987 upstream. Document support for the SD Card/MMC interface on the Renesas RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230912045157.177966-32-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Ulf Hansson [claudiu.beznea: fixed conflict in allOf section] Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 91aa9b84d23f..6588b5d0f2ac 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -59,6 +59,7 @@ properties: - renesas,sdhi-r9a07g043 # RZ/G2UL - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} - renesas,sdhi-r9a07g054 # RZ/V2L + - renesas,sdhi-r9a08g045 # RZ/G3S - renesas,sdhi-r9a09g011 # RZ/V2M - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 @@ -113,6 +114,7 @@ allOf: - renesas,sdhi-r9a07g043 - renesas,sdhi-r9a07g044 - renesas,sdhi-r9a07g054 + - renesas,sdhi-r9a08g045 then: properties: clocks: From patchwork Fri Apr 19 08:17:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B7EBC4345F for ; Fri, 19 Apr 2024 08:18:58 +0000 (UTC) Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mx.groups.io with SMTP id smtpd.web10.15319.1713514728356662913 for ; Fri, 19 Apr 2024 01:18:48 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=KX0FlGjy; spf=pass (domain: tuxon.dev, ip: 209.85.167.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-518a3e0d2ecso2715260e87.3 for ; Fri, 19 Apr 2024 01:18:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514726; x=1714119526; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0yjeEQQU5UbcsKcDF/bM7rzYtDeLoSfFhMg8PpgTF60=; b=KX0FlGjytRzZaefriOd/+sqBVgEQIUh2d+Vyq34u8EA2EWt86Zi0DNJY27u3yssjYF /ePHxuWGrwizvezGBme+OF7zgt2n/PXQ93drubrYLnoI2OTmJgeWDlZI9Q3j059qXQrz kAcL4+yhTGLlZd35D6YJOxsMyD2nmaAauXAlGuo3yMleklRJ4nHMG1sfPh0NDq39fokO txoJyPolewm0YJGVv0xFx7MBrJ/1pPdJpAU8MfL+oHtpV2bSpu/eABwYuEup0HzNYI2Y mp46spmzJJBO2vMVW5AwPyA6/oN7KqMlr4J3rGI3hSqy7EI7N8R47FuFmJrnoMxoR1Z/ kKEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514726; x=1714119526; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0yjeEQQU5UbcsKcDF/bM7rzYtDeLoSfFhMg8PpgTF60=; b=Rthm1GYChBxTc2X183StM4PK5iztzaYrXAnkBERQsKXfuBmQteL5VBSemszBn3+iVl 6nJ9Jw35u6EC7DPjNeigXsyypR1wrCwiipf6bceCFS97gPph0kzMZGa80/u3eFc8h2z6 giH48FMxfsZazUZu42ZG+1b92y6XEqnLoEqDv5uzzJW8hq8F6xCThxhjokHdIG7vFTXX MwsOUqo2ywlnDlL9f3VXWqIi3hnb0IBwBUO5I6z5ja6gDnswVy4iYF9Q6SSnSybxxGwR sOTrtV15Uav83dWHbcCZprJ51JZBFwpVhwVZUcyMl2cjSP3/DwjZzkVlrJdU1AqZULqR RuLQ== X-Gm-Message-State: AOJu0YxdRnWerWAmdTcvoaSy9pWMa3719HtI/6Dn02exz5YW4S5vqRmP VoQL+wHCfDnzMb4Y4WT360IEKfXD3ov/ZmNC8NWihR55qUh53aYLkjD6djmOFtA= X-Google-Smtp-Source: AGHT+IEvoSLMxLtsMoVmcgLtYvFEg0lp4pAym1SoTKoYIUD1VxY9ezGjohy/NXcME9mvJ/XnGQYc4A== X-Received: by 2002:a05:6512:32a7:b0:516:cbca:5c9a with SMTP id q7-20020a05651232a700b00516cbca5c9amr1067485lfe.9.1713514726519; Fri, 19 Apr 2024 01:18:46 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 41/53] dt-bindings: serial: renesas,scif: document r9a08g045 support Date: Fri, 19 Apr 2024 11:17:30 +0300 Message-Id: <20240419081742.3496709-42-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:58 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15628 From: Claudiu Beznea commit 8e3c825288c6a091e3e80edcebe746b927dd1f73 upstream. Document support for the Serial Communication Interface with FIFO (SCIF) available in the Renesas RZ/G3S (R9A08G045) SoC. SCIF interface in Renesas RZ/G3S is similar to the one available in RZ/G2L. Signed-off-by: Claudiu Beznea Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231006103959.197485-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index cd2ea22b0d07..1b1a9e586361 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -72,6 +72,7 @@ properties: - enum: - renesas,scif-r9a07g043 # RZ/G2UL - renesas,scif-r9a07g054 # RZ/V2L + - renesas,scif-r9a08g045 # RZ/G3S - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback reg: From patchwork Fri Apr 19 08:17:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C2F3C04FF6 for ; Fri, 19 Apr 2024 08:18:58 +0000 (UTC) Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) by mx.groups.io with SMTP id smtpd.web10.15321.1713514730265626140 for ; Fri, 19 Apr 2024 01:18:50 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=CpS83Fhj; spf=pass (domain: tuxon.dev, ip: 209.85.167.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-518f8a69f82so2114092e87.2 for ; Fri, 19 Apr 2024 01:18:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514728; x=1714119528; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0k0JqLCTm5YJ9uCkGHJ+BOxGiI9vPdO/4XaCNz5/Z0g=; b=CpS83FhjLC5Ab/cceF9U92liFzqn7WOIQ8jAysK3qEa5IJIuAn7t3PJtNQhOk4w5K9 ZW5EG3G9DMdMCt89fCocwJ9kOarSm2tnqD+3t66+HyoDH/mKZdrLOtsHaibjAL2s8cgs 01hLfPOETxpc5j4tufsQT1cecgaIpd6IGtBgdWJPXow5WRXfxx7fQ5gFagA5RUsv2BPs 2NaBtNL4WDniYFD7qegMOEqWZ8qEhAiR53AfRTVXme/3spxQDRSlFeYrVMQavapt7VX7 wZJaJtIWfmtLrIpTf8hvaj2peRsxgxcVeDaL/QvDfXXN1CmOuiGf2VcFzWsOPHROiBZd X7Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514728; x=1714119528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0k0JqLCTm5YJ9uCkGHJ+BOxGiI9vPdO/4XaCNz5/Z0g=; b=tmHnAIo3U95845cRM3wG5BrIPmyGBTLum93CluWe5TUlfVL1LgOEv/sGzNBCygkW3q 9VlOntvmuZbWz1aVVIfCsu3OvBJi++CDq5ZKDSo1xvCbg/FWdr+0PxFHiZStlDjR1Q0L 2mGzKdty5YZZQeFf6iSj53S9l3AevaikNE2u33xODPCgnGiOSBbS7Yrv4DwMxZWjEJdE k5Q06ecHPbJMBLE+eTM9BcsSR2Qu4OS2xT0M5lSX1C+W7Yc7vNPJaF8AjeB3SAybZ+tQ qFgxVgS/vvEkomiin9sp3m5pahaSF7IyODeszVyP2rDGZ4eBFJGOOouLJi0ga1FHI5t8 ZUXw== X-Gm-Message-State: AOJu0YzZNl3JePaiTw6aOi5jQVj2+7X4+mDUED/F6Xf20PaP8kKHYztI KuKj9RqJhGGy2Q5IKKhikYKJU8a6A7PZCQlcR567MZNDtiokTrUnooRKBP3AU6o= X-Google-Smtp-Source: AGHT+IHyyGS6+Q76rhHZgauCxZfPPOaBpgiw1kFwEgHPFPxdP83QIkhZ/Q413UMmuWVtZSKs4nGBsg== X-Received: by 2002:a05:6512:608:b0:519:7698:e9d9 with SMTP id b8-20020a056512060800b005197698e9d9mr1059403lfe.35.1713514728345; Fri, 19 Apr 2024 01:18:48 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 42/53] dt-bindings: soc: renesas: Document RZ/G3S SMARC SoM Date: Fri, 19 Apr 2024 11:17:31 +0300 Message-Id: <20240419081742.3496709-43-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:58 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15629 From: Claudiu Beznea commit 1c3be6ca72293723e009a29fbe90385fa047e5ee upstream. Document the Renesas RZ/G3S SMARC SoM board which is based on the Renesas RZ/G3S (R9A08G045S33) SoC. Suggested-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-24-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/renesas.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 830121d7dd25..ea995b9c77e8 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -340,6 +340,12 @@ properties: - renesas,r9a08g045s33 # PCIe support - const: renesas,r9a08g045 + - description: RZ/G3S SMARC Module (SoM) + items: + - const: renesas,rzg3s-smarcm # RZ/G3S SMARC Module (SoM) + - const: renesas,r9a08g045s33 # PCIe support + - const: renesas,r9a08g045 + additionalProperties: true ... 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:49 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 43/53] dt-bindings: soc: renesas: Document SMARC Carrier-II EVK Date: Fri, 19 Apr 2024 11:17:32 +0300 Message-Id: <20240419081742.3496709-44-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:58 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15630 From: Claudiu Beznea commit 6042f5365bee167ac27d02454f5cba403747277a upstream. Document the Renesas SMARC Carrier-II EVK board which is based on the Renesas RZ/G3S SMARC SoM. The SMARC Carrier-II EVK consists of an RZ/G3S SoM module and a SMARC Carrier-II carrier board; the SoM module sits on top of the carrier board. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-27-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/renesas.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index ea995b9c77e8..76be05de1788 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -346,6 +346,13 @@ properties: - const: renesas,r9a08g045s33 # PCIe support - const: renesas,r9a08g045 + - description: RZ SMARC Carrier-II Evaluation Kit + items: + - const: renesas,smarc2-evk # RZ SMARC Carrier-II EVK + - const: renesas,rzg3s-smarcm # RZ/G3S SMARC SoM + - const: renesas,r9a08g045s33 # PCIe support + - const: renesas,r9a08g045 + additionalProperties: true ... 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 44/53] arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC Date: Fri, 19 Apr 2024 11:17:33 +0300 Message-Id: <20240419081742.3496709-45-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:58 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15631 From: Claudiu Beznea commit e20396d65b959a65be84e0eda3c106360114b7ae upstream. Add the initial DTSI for the RZ/G3S SoC. The files in this commit have the following meaning: - r9a08g045.dtsi: RZ/G3S family SoC common parts - r9a08g045s33.dtsi: RZ/G3S R0A08G045S33 SoC specific parts Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-23-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 139 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi | 14 ++ 2 files changed, 153 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi new file mode 100644 index 000000000000..7971e44a5a0a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a08g045"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a08g045-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a08g045-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a08g045-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_GPIO_RSTN>, + <&cpg R9A08G045_GPIO_PORT_RESETN>, + <&cpg R9A08G045_GPIO_SPARE_RESETN>; + }; + + sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c00000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + gic: interrupt-controller@12400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x12400000 0 0x40000>, + <0x0 0x12440000 0 0x60000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi new file mode 100644 index 000000000000..3351f26c7a2a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S R9A08G045S33 SoC specific part + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a08g045.dtsi" + +/ { + compatible = "renesas,r9a08g045s33", "renesas,r9a08g045"; +}; From patchwork Fri Apr 19 08:17:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635813 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9702C0650F for ; Fri, 19 Apr 2024 08:18:58 +0000 (UTC) Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) by mx.groups.io with SMTP id smtpd.web10.15324.1713514734443534846 for ; Fri, 19 Apr 2024 01:18:54 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=C74+xV+3; spf=pass (domain: tuxon.dev, ip: 209.85.208.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-56e1baf0380so2217843a12.3 for ; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:52 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 45/53] arm64: dts: renesas: Add initial support for RZ/G3S SMARC SoM Date: Fri, 19 Apr 2024 11:17:34 +0300 Message-Id: <20240419081742.3496709-46-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:58 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15632 From: Claudiu Beznea commit adb4f0c5699c45d0034abde786e748250705a3b6 upstream. Add initial support for the RZ/G3S SMARC SoM. The following devices available on the SoM are added to this initial device tree: - RZ/G3S SoC: Renesas R9A08G045S33GBG - Clock Generator (only 24MHz output): Renesas 5L35023B - 1GiB LPDDR4 SDRAM: Micron MT53D512M16D1DS-046 - 64GB eMMC Flash (though SD ch0): Micron MTFC64GBCAQTC SD channel 0 of RZ/G3S is connected to an uSD card interface and an eMMC. The selection b/w them is done through a hardware switch. The DT will select b/w uSD and eMMC through the SW_SD0_DEV_SEL build flag. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-25-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi new file mode 100644 index 000000000000..185ca8289a35 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include + +/* + * Signals of SW_CONFIG switches: + * @SW_SD0_DEV_SEL: + * 0 - SD0 is connected to eMMC + * 1 - SD0 is connected to uSD0 card + */ +#define SW_SD0_DEV_SEL 1 + +/ { + compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; + + aliases { + mmc0 = &sdhi0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device-type = "memory"; + /* First 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + vcc_sdhi0: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + +#if SW_SD0_DEV_SEL + vccq_sdhi0: regulator1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +#else + reg_1p8v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; +#endif +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +#if SW_SD0_DEV_SEL +/* SD0 slot */ +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_uhs_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <125000000>; + status = "okay"; +}; +#else +/* eMMC */ +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + max-frequency = <125000000>; + status = "okay"; +}; +#endif + +&pinctrl { + sdhi0_pins: sd0 { + data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + cd { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_uhs_pins: sd0-uhs { + data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + cd { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_emmc_pins: sd0-emmc { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7", + "SD0_CLK", "SD0_CMD", "SD0_RST#"; + power-source = <1800>; + }; +}; From patchwork Fri Apr 19 08:17:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE39DC41513 for ; Fri, 19 Apr 2024 08:18:58 +0000 (UTC) Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) by mx.groups.io with SMTP id smtpd.web11.15290.1713514735618631007 for ; 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([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:53 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 46/53] arm64: dts: renesas: Add initial device tree for RZ SMARC Carrier-II Board Date: Fri, 19 Apr 2024 11:17:35 +0300 Message-Id: <20240419081742.3496709-47-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:58 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15633 From: Claudiu Beznea commit d1ae4200bb268fda8cf885e053306c2bd7deb62a upstream. Add the initial device tree for the RZ SMARC Carrier-II. At the moment it contains only the serial interface. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-26-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi new file mode 100644 index 000000000000..e7073a09ed2e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ SMARC Carrier-II Board. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include + +/ { + aliases { + serial0 = &scif0; + }; +}; + +&pinctrl { + scif0_pins: scif0 { + pinmux = , /* RXD */ + ; /* TXD */ + }; +}; + +&scif0 { + pinctrl-names = "default"; + pinctrl-0 = <&scif0_pins>; + status = "okay"; +}; From patchwork Fri Apr 19 08:17:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D053EC071DB for ; Fri, 19 Apr 2024 08:18:58 +0000 (UTC) Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) by mx.groups.io with SMTP id smtpd.web11.15292.1713514736913619579 for ; Fri, 19 Apr 2024 01:18:57 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=P2xJQC0u; spf=pass (domain: tuxon.dev, ip: 209.85.218.52, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-a526a200879so214604466b.1 for ; Fri, 19 Apr 2024 01:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514735; x=1714119535; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G5oyNifRdRvSRNh5qaJ2VWlKtPeDHcZUJmI1cVYbRHk=; b=P2xJQC0uFnrSUyp1sS91bAteuUtV/ecBF0eF7pUGkD0RkC2FDr9xjFbOAmnED0A3j/ zz184lxTG3C5I6VuyXPgEg21YOBdO0+G9DNkvCiQFk7n+hWe4hYufZWEeD5e3Wr4gbDu B5/vRD9OpBcSozE8u1ZOkuoXTw6pOuWjbwOfbokuEuZgL4t3hdrpI6ywBhDuGmiOXmJs w3/wHOJhpvDhxQGoNEtWUODVwUoXkL6sb/RxlD7ow/kxcI2tZjYLpK0q4Z83TkhgqcSt x5wY3+svC4b9shq+GWNh4sBD6TCwJi1BWmgn2B3jf4fHRPRxKksM3vLjjsTWGcTu9VAS ofHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514735; x=1714119535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G5oyNifRdRvSRNh5qaJ2VWlKtPeDHcZUJmI1cVYbRHk=; b=pycwx6ALXCPHN+PKJU6so7XSeipCo9UlKfDBzV/uTIsSlfddPwNsEeL/bXOx3voclY zgq3g85sMuWZP+Os1qUjgjAIjlUFrKfs9OjAMRnF1b8vz8D5SAipuE8W69ag8QdNgGyI FK6geSdEmzwgEi6WUWaJZq9nOlUd24AXPbPM91/FDRuId8jehu9fc74ZICh+5oRSFGg6 zBayGoaZVPce7qVIA50IudOuKbliPs4AkoRN+aaPGehHJoloYqeybvHxPQqUprHMRK2h kCLjg8T7zUCklruKmM0OlCTH2Sj3qsHAfVS+NjqzsAghxkgy4jmqJ8InMTAmGjiPpgZx bh7A== X-Gm-Message-State: AOJu0YxpG4y+z68EnB7HftO5xasHDEh5zajB7k8SvCb2SX+rPJIJp+id lQUVRyJKlWwLlK8vkCy34Gw84M8x5PSZ3VFMDxSfjM1rExX9kTydRMVhMIvll9Q= X-Google-Smtp-Source: AGHT+IGOHM+DZfDGEIwbg0Jq13z88Ayu+o/nZAHsLM9oksN4zBkSON0m9D++BA7rFaR0Bo2z0GEJYQ== X-Received: by 2002:a17:907:bb97:b0:a55:661d:8ab1 with SMTP id xo23-20020a170907bb9700b00a55661d8ab1mr979029ejc.39.1713514735362; Fri, 19 Apr 2024 01:18:55 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:54 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 47/53] arm64: dts: renesas: Add initial device tree for RZ/G3S SMARC EVK board Date: Fri, 19 Apr 2024 11:17:36 +0300 Message-Id: <20240419081742.3496709-48-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:58 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15634 From: Claudiu Beznea commit 177e2ee9a967d410b6daeff7a5b85f96bb833a2e upstream. Add the initial device tree for the Renesas RZ/G3S SMARC EVK board. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-28-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r9a08g045s33-smarc.dts | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 44eafef2ea0a..1814400549c5 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -64,4 +64,6 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb +dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb + dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts new file mode 100644 index 000000000000..6b57e0e02dbe --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SMARC EVK board + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a08g045s33.dtsi" +#include "rzg3s-smarc-som.dtsi" +#include "rzg3s-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK version 2 based on r9a08g045s33"; + compatible = "renesas,smarc2-evk", "renesas,rzg3s-smarcm", + "renesas,r9a08g045s33", "renesas,r9a08g045"; +}; From patchwork Fri Apr 19 08:17:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5452C07C79 for ; Fri, 19 Apr 2024 08:18:58 +0000 (UTC) Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) by mx.groups.io with SMTP id smtpd.web11.15293.1713514738195747151 for ; Fri, 19 Apr 2024 01:18:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=PbcjRwIY; spf=pass (domain: tuxon.dev, ip: 209.85.218.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-a53f131d9deso197549266b.3 for ; Fri, 19 Apr 2024 01:18:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514736; x=1714119536; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4PFkdWL5MtliNa5vgxvGnxJTfoXqABZtjj6NQYhcNzM=; b=PbcjRwIY9fx6TPfOioNOP7UM+6l5qJPaw2GRNWtAE5L4xB8/8112zGRtES2oqJ0/KI JtT7NwqS+bwORrNsfAdY/CKSbAZPKSW0O2k4pJObK/WpA+kTvSP2o8Blj4m2nXqMVjnS XQ2mBbMqqUgOu8aPxRuZsFFRDoCL2bT2BjGNvbUuseW1t8jmgasuPbCb4L69wSwdDBIw C1mTfXJt9w9hHJ4doWG2qtDe+e8wxETHt5IKQwWqu6CacAkxD2WgPxcgaRi6aZAeH3XQ IzqW+ZfXAr32y6y6TtJYT+JSuYcOur9DCx7ZxhFyOm9kYhVvA4wBKBziypMkcW1hyjOE 5apA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514736; x=1714119536; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4PFkdWL5MtliNa5vgxvGnxJTfoXqABZtjj6NQYhcNzM=; b=QOZNz1JPhtQJaIUKZA7DaN0cP/71b9Cs8J5DekWvEoq+Za/nBFa5uqRc6wbQH+Egm0 joRF0tAye8w4EtLnhoKhMXI02rDG02R7P1SnrfwtN5IuVaFQQabWTfolWdltJKU4NK3l 5AUSu6ITmQzZNzAB7N8P+WiJhEMo84IFERUhJb/rEf37LiBgQakF3Eovd7nhZmcYQpnj vv2byOPDn4PLtnhkz/kxFVXph/o7doIC3vrx8ltDDI014NLI7uJ5vZ3grQm2sGrsSsMo sTZyvRdFJ4O4PnDcWLHxGG5h0G2dyTHsTHN0QHS79PueZZdWqotocfmd/CKdwehnpEHc LSfA== X-Gm-Message-State: AOJu0Yxz0FUtajjKn8Fmh4lWQXKPv/f7kSuIU6v2KP3Mw4AUpxzdUhUH p3nlZgFC1q4maaenD9Rss9PoQQcNzNOzYHXklu2wqdUA5dlI5xNlusk5/PhRF64agFmEJxHxm2j s X-Google-Smtp-Source: AGHT+IF+WgozN/O8ahFO4RlikNkzlFsAnv86Zj5RyPEYwxHaASeWn3u997mdrHkYhf0kGt7LCQMipg== X-Received: by 2002:a17:907:3e1a:b0:a55:8c0b:bc00 with SMTP id hp26-20020a1709073e1a00b00a558c0bbc00mr363726ejc.62.1713514736690; Fri, 19 Apr 2024 01:18:56 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:56 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 48/53] arm64: dts: renesas: r9a08g045: Add nodes for SDHI1 and SDHI2 Date: Fri, 19 Apr 2024 11:17:37 +0300 Message-Id: <20240419081742.3496709-49-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:18:58 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15635 From: Claudiu Beznea commit 6a35583085a70bbf37e8f905e098a1dae5711165 upstream. Add DT nodes for SDHI1 and SDHI2 available on RZ/G3S (R9A08G045). Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231010132701.1658737-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 7971e44a5a0a..534b728a8e14 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -118,6 +118,36 @@ sdhi0: mmc@11c00000 { status = "disabled"; }; + sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c10000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi2: mmc@11c20000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c20000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI2_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Fri Apr 19 08:17:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2B31C04FF6 for ; Fri, 19 Apr 2024 08:19:08 +0000 (UTC) Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) by mx.groups.io with SMTP id smtpd.web11.15294.1713514739682496338 for ; Fri, 19 Apr 2024 01:19:00 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=RDp8HpaA; spf=pass (domain: tuxon.dev, ip: 209.85.218.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-a5561b88bb3so187549366b.0 for ; Fri, 19 Apr 2024 01:18:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514738; x=1714119538; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2R+UmzW4uO4Wz7m+wRKRRHfO4GEbAXwsuAxZn2mclRo=; b=RDp8HpaANXCCrPDIz7OaQpQKSxiLotXMxasmvj+/coShwcgFnVjcfmmcM8UvYZ9Jor RlbYR99tYaXrZaYjli+1Ge5raY2uJbZiZwkTLsEsHo3oDii4mZJleIEFbn/QYG5RslTH KWh5Hi1PSaqNy7qoNzqDL5NkK1IeL6RBv89pDOJnYb51M7f1NzWSMXxYl4Hab7K1FNoc ddwBRvOdmsiy+jshILbEGBsAzC4UBukYOOSTWMiw4hbPlOTgzKwNoaMTgDSBMxLpHweL yiuJTLoPc7YloQocBi5rF1NnaZ8fs5pFtKbxt76Efnu2e7BO2I5U5o4cwfv62E4QFtf2 05Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514738; x=1714119538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2R+UmzW4uO4Wz7m+wRKRRHfO4GEbAXwsuAxZn2mclRo=; b=dxJBPtXqONktLTLJZB0dQnt+UozKR70G0NdkcVY4Q2Vd/h/zD9Pm0pV0DKrxbrU7jN wKNAJ87Pj8SGMBbgba79pGQdVc56hLEgFYBxLNQw21z8C94bzo2+NG1d/baLneJVNySL lHUGHSTUQdv3z3dF+SxgTmtHWg13qDsZK0XaJoNa9jEeBOUf6qSGuWZrLNB9MwiNLa5j JxDzR0PGY7vx3YOVwDVEQ6YpOlvW7Ff6g/sRQmQrc59mVnY8IEAnQEasy7U/ImywSTsc dlKxBMAq2GGWAMk+JXYdNAiMdPEPO5Qi/+Ijbqfrv5ihUx3UyGzVzBAi2Z+C0PgbgDD6 +T3g== X-Gm-Message-State: AOJu0Yw9b1IDUg6H2p3AhIqghfHQzx6UY/f11deohl6sfofG7L92Lkd7 WO544VvftHkaZyLwUJSyZcEkZ9yXQOB1r91WPBwNWRMO+eYxDzQmA96mFihatLw= X-Google-Smtp-Source: AGHT+IFAgMf5HxLLeUfysYWjAa9Fpv9bpHBFK5tsVWz5RIEi2fGydJQXNrF4UzchpCXuz0By3S3b9w== X-Received: by 2002:a17:907:7f22:b0:a52:572e:729f with SMTP id qf34-20020a1709077f2200b00a52572e729fmr1579279ejc.60.1713514738165; Fri, 19 Apr 2024 01:18:58 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 49/53] arm64: dts: renesas: r9a08g045: Add missing cache-level for L3 cache Date: Fri, 19 Apr 2024 11:17:38 +0300 Message-Id: <20240419081742.3496709-50-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:19:08 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15636 From: Claudiu Beznea commit 1d071ea156aaa5942564282d69866596b6de95c9 upstream. Fix the following DTBS check warnings: arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: cache-controller-0: 'cache-level' is a required property from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: cache-controller-0: 'cache-level' is a required property from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: cache-controller-0: Unevaluated properties are not allowed ('cache-size', 'cache-unified' were unexpected) from schema $id: http://devicetree.org/schemas/cache.yaml# Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231010132701.1658737-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 534b728a8e14..6c7b29b69d0e 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -29,6 +29,7 @@ cpu0: cpu@0 { L3_CA55: cache-controller-0 { compatible = "cache"; + cache-level = <3>; cache-unified; cache-size = <0x40000>; }; From patchwork Fri Apr 19 08:17:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2AEFC4345F for ; Fri, 19 Apr 2024 08:19:08 +0000 (UTC) Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) by mx.groups.io with SMTP id smtpd.web11.15295.1713514741380234874 for ; Fri, 19 Apr 2024 01:19:01 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=YwHQ/qm7; spf=pass (domain: tuxon.dev, ip: 209.85.208.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-571d6d1943fso211824a12.2 for ; Fri, 19 Apr 2024 01:19:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514740; x=1714119540; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JA8u4MVHkNzXVIrqfjKWy0CIgT/wq4HGtLUGMza3xqw=; b=YwHQ/qm72OI2hNZsWjXvduNBFdDBtdnl4ID5b9meVBt8JMaQSn1+yyyI4BWY2zC1DP L61headgVlzmp0b5tu96ZUAfc+DfxrObWsigPqSjkJOmSDsoS+RyLyeILAt/EN7SpmUJ FQ9s0XP+xtnAxCDxi+Qx+XX3gfPUuXBDhw82rnG1RJ8za0xunQqeApV9xZjTfJ2wx3oQ MNgWdfwHB42+lk6CiRiAVwb6ICEn1AW3a2FXc60dk0mmPiuRAUQyt+tM2cf0Q6w7NisT BH9QgORedy4CP+fh1fW00Z1szl87p2vSmWWSQ24uTP3I3H3bRUKeJ2MgKCs6kB48x4x+ ZqWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514740; x=1714119540; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JA8u4MVHkNzXVIrqfjKWy0CIgT/wq4HGtLUGMza3xqw=; b=ASzNlwOH1UKL6IvlCbN9bFbudwDjxZp/kuEyiAWYjVoFYAiSEd+j/7L5kxt8tNCw4x alVpGPLz+sAwyMOJo3Dh3T/wPIrknHPCYm3KvbPVet+MwBHEAVyK5cqZZ2sITH8HZEbK OsfnK0K6kdsZJHpwNhRMRCvXmyg8AZCr4j/6cd0ccWDrvGTB87YP5BltXHmYQXAOH7ZE bjfRZGoYIi/ic2H7DLl11QZQDS9RoW/2xfdjzwfUvYi8H5E0o7Mpn0IZfBaKIjxyHjQu D/Gnq5vhvaYUCe4hjn9p18CIh0WboZumem0AWQsghVNr9Rqy7jiCbhDFPL2v/UhIAqUP r+5w== X-Gm-Message-State: AOJu0YwI2AgcamxHpf87hkttp0HERFda/S/kvQa8aBbyBoLlBjUWbBR4 szOCEKprVFp3iApZO4hGICW1Do7bSK5v+X2VtVGzOHHai1uTU4qjOj6TRgmw+sQ= X-Google-Smtp-Source: AGHT+IGrAihfRWtEHwPwXMsWEMni6VCO7GglM79lQjK5ZFLSLREzCmkUV8AzGKxADHq3Xh2n9cD+2A== X-Received: by 2002:a17:906:1c5a:b0:a52:3d07:de62 with SMTP id l26-20020a1709061c5a00b00a523d07de62mr974491ejg.58.1713514739826; Fri, 19 Apr 2024 01:18:59 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:18:58 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 50/53] arm64: dts: renesas: rzg3s-smarc-som: Spelling s/device-type/device_type/ Date: Fri, 19 Apr 2024 11:17:39 +0300 Message-Id: <20240419081742.3496709-51-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:19:08 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15637 From: Claudiu Beznea commit aca0f89bad145c4f1c4d4d60a957de1e4f4522a4 upstream. Fix the following DTBS check warnings: arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dt: /: memory@48000000: 'device-type' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/memory.yaml# arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: /: memory@48000000: 'device_type' is a required property from schema $id: http://devicetree.org/schemas/memory.yaml# Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231010132701.1658737-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 185ca8289a35..a199de8f8b02 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -29,7 +29,7 @@ chosen { }; memory@48000000 { - device-type = "memory"; + device_type = "memory"; /* First 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; From patchwork Fri Apr 19 08:17:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2BFFC05052 for ; Fri, 19 Apr 2024 08:19:08 +0000 (UTC) Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) by mx.groups.io with SMTP id smtpd.web10.15328.1713514742955740319 for ; Fri, 19 Apr 2024 01:19:03 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=O43N6V8U; spf=pass (domain: tuxon.dev, ip: 209.85.218.52, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-a5557e3ebcaso290943666b.1 for ; Fri, 19 Apr 2024 01:19:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514741; x=1714119541; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u0nlrfxotDpFG/L+MwE4rqUWNkO4KHNQlNXxnwoPv7o=; b=O43N6V8UY1LlEuL+bC0Sxa/JXIkl1W4WTqxhE3ARusOW5qM5wpa1Lj/HDu76yYiFbw OWLA+SL7uSKnO6DyMY4bmThzkJgg8IeBhE4pbeEHf5PAyLmv/y1+gmyt6o+/bWm8BXPx hb51F3jDCg6QY/Lxe3Mc196W8up8UtEN0sgTJEcWePjhXdfI+3dF1TFXaA+m51tb8QXh jR1IwHKrizA78V2V/YTwx2+t3Etp+bPheHl3jJhkSqTqBBGF4CT0h0REs6/zMiB0k58x 4eXcvxL3VMJo9DTUPbEyolkQAq6kJTXSphE6Mcy6U397Zx0gO6dUCNUg55nDsU3VkbuP B+Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514741; x=1714119541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u0nlrfxotDpFG/L+MwE4rqUWNkO4KHNQlNXxnwoPv7o=; b=TbHvth9OR1GZI1F+1y8zKpV2w3QchZgc0+sMiUPxuD3r5WWiSOanzHXzsQzGJmYXhx ofbGsh2si17SqXmqwxeX932G3Dj/V4VHkxAqJqmZkRA0GAyslNPLWJF1ce/Wsxo/1KMv 25BIGuu/obX5Y6PPwFk1R0khFMPylPUZva0UhqoNH5rL7llcLZNZAvtRP+VIvGPdyTWl HQSGXSyK1znFn4J3OuDaz2C1tCwzlz1TiUhoOfd7c2PM84AGjBtB06gsBsJ3bhyQWGMq mldv9hyzm7VlXo6EHZ9IW+SwxTqNMPPfJ7+C+Tt6LZJdW3iwfG07curm4BTOBqQkEMnT gZsw== X-Gm-Message-State: AOJu0Yx/sdWmHjOwf00JRKdjVfr7skVVjiOVxx5k3shjcG4KIBlBfuzi /U8iYj1BDPFv2vrPXY7ezQvm76NtOEK/UtAPAHAJ+Ah1Ypbl44hbowLBX6PeZL4= X-Google-Smtp-Source: AGHT+IFibLJ8wLF/F/dyAumZ6T0MnHcCt8MDe1+K3h9muiuDln/KXwHFICJcow0IgUHHsE2JpTEbbw== X-Received: by 2002:a17:906:c141:b0:a55:7614:fa44 with SMTP id dp1-20020a170906c14100b00a557614fa44mr4142616ejc.3.1713514741383; Fri, 19 Apr 2024 01:19:01 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.18.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:19:00 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 51/53] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Date: Fri, 19 Apr 2024 11:17:40 +0300 Message-Id: <20240419081742.3496709-52-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:19:08 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15638 From: Claudiu Beznea commit 00cbba479142a3c962a44b127db4ab6cdc2b2b70 upstream. Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI0, IRQ0, IRQ1. The selection b/w SDHI2 and SCIF1, SSI0, IRQ0, IRQ1 is done with a switch button. To be able to select b/w these a compilation flag has been added (SW_SD2_EN) at the moment being instantiated to select SDHI2. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231016105344.294096-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index a199de8f8b02..01a4a9da7afc 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -13,14 +13,21 @@ * @SW_SD0_DEV_SEL: * 0 - SD0 is connected to eMMC * 1 - SD0 is connected to uSD0 card + * @SW_SD2_EN: + * 0 - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + * 1 - SD2 is connected to SoC */ #define SW_SD0_DEV_SEL 1 +#define SW_SD2_EN 1 / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { mmc0 = &sdhi0; +#if SW_SD2_EN + mmc2 = &sdhi2; +#endif }; chosen { @@ -63,6 +70,15 @@ reg_1p8v: regulator1 { regulator-always-on; }; #endif + + vcc_sdhi2: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &extal_clk { @@ -100,6 +116,17 @@ &sdhi0 { }; #endif +#if SW_SD2_EN +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_sdhi2>; + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; +#endif + &pinctrl { sdhi0_pins: sd0 { data { @@ -139,4 +166,26 @@ sdhi0_emmc_pins: sd0-emmc { "SD0_CLK", "SD0_CMD", "SD0_RST#"; power-source = <1800>; }; + + sdhi2_pins: sd2 { + data { + pins = "P11_2", "P11_3", "P12_0", "P12_1"; + input-enable; + }; + + ctrl { + pins = "P11_1"; + input-enable; + }; + + mux { + pinmux = , /* SD2_CLK */ + , /* SD2_CMD */ + , /* SD2_DATA0 */ + , /* SD2_DATA1 */ + , /* SD2_DATA2 */ + , /* SD2_DATA3 */ + ; /* SD2_CD# */ + }; + }; }; From patchwork Fri Apr 19 08:17:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6BF2C04FFF for ; Fri, 19 Apr 2024 08:19:08 +0000 (UTC) Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) by mx.groups.io with SMTP id smtpd.web11.15297.1713514744528017561 for ; Fri, 19 Apr 2024 01:19:04 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=NslQCmZq; spf=pass (domain: tuxon.dev, ip: 209.85.167.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-51ac9c6599bso230280e87.1 for ; Fri, 19 Apr 2024 01:19:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514743; x=1714119543; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JhGnexjjrSUz4tSsD3nUG33MJNdufwhBsCqIhPflCFw=; b=NslQCmZqhSmz/TqLGX9Dser6AIzykDzS6+GHKCRnap5JP0FFuFOFw0mjJ27FnQLM2J eV7XT8lUUcJVZLWznwc2a8f+avJFvV/VkdmsXze3BlmnGVe+a0ycQtwSogSZmmWZRimi 1tkAYqCHG4Yu/RxvxOiQo0biHgrE0MTqBCjq7xi5sUtWnF6T9IThct2+kGaf0MuAgCHj 24iRHk9pcmJU9NzPGXqaP53JKBi5lLFxHvhfpFD5qaaXoR3BxeqsikjJKOdZ7ldhCZGN gtdZPYV37Yy/lx0r0ZfdJSz9/BMjyfhgxb7EiB6pCJI8jHzHOU+ujjCcBPbwKD1jXlFo PA/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514743; x=1714119543; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JhGnexjjrSUz4tSsD3nUG33MJNdufwhBsCqIhPflCFw=; b=kX05YH8ufm1pfU7xpLOjXrunTVijEzKwY1WgHqnPLFAxmmxqU6C3fi60ftuEoQiQFD WQzjEmFrO+uXRxp4REnFWfuPNHWFh2L4CuXSBD7ETRkEOAyUuQLn6QhA9ym+qyeR9pC0 mIY9aIv2vC5dBvlQ5XpUM20pgsl04Kjf6pNAn8l9kZRg32tD70wVFcP8NQVI2MfykmWv ww1bRiQdZ1mNSuXE+ttM9bG0ZhiZqQYmq28e0Xk4kNIWF63CQ0blPN1e9D0P+wcJT8x2 ajJwC1z6iGsoD3smbJx7q23cBOcfNV3mLD4xFw/C4WCchyKD5o0ncPgDnzD63AQGP2d7 yQlQ== X-Gm-Message-State: AOJu0Yz9yP1wTsRGqfYaI/9xN7dxe0DlRsVkDfbR+kt+xicUShtsxrVn YA4zz4QideuFmginCgqY7UpmEpZOQOAc2Dzs3UXk4s5HAuSxe4hW+nB1Bk+rono= X-Google-Smtp-Source: AGHT+IEJ4S20cWWjccob34CfQ4rLIycZ+J955NV7T8pNBjcvUt9dCPzkx4cyrbAsGM2PtYPvZz7LbA== X-Received: by 2002:a05:6512:10c6:b0:51a:c44d:b95f with SMTP id k6-20020a05651210c600b0051ac44db95fmr634567lfg.28.1713514742687; Fri, 19 Apr 2024 01:19:02 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.19.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:19:02 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 52/53] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Date: Fri, 19 Apr 2024 11:17:41 +0300 Message-Id: <20240419081742.3496709-53-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:19:08 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15639 From: Claudiu Beznea commit 993a207c114e137159c8d255576badfcd9defba8 upstream. Add SDHI1 to RZ/G3S Smarc Carrier-II board. This is connected to a uSD interface. Although Vccq doesn't cross the boundary of SoM it has been added to RZ/G3S Smarc Carrier-II dtsi to have all the bits related to SDHI1 in a single place. At the moment SoM is used only with RZ/G3S Smarc Carrier-II board. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231016105344.294096-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 65 ++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index e7073a09ed2e..214520137230 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -11,6 +11,26 @@ / { aliases { serial0 = &scif0; + mmc1 = &sdhi1; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; }; }; @@ -19,6 +39,38 @@ scif0_pins: scif0 { pinmux = , /* RXD */ ; /* TXD */ }; + + sdhi1_pins: sd1 { + data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + cd { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1-uhs { + data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + cd { + pinmux = ; /* SD1_CD */ + }; + }; }; &scif0 { @@ -26,3 +78,16 @@ &scif0 { pinctrl-0 = <&scif0_pins>; status = "okay"; }; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <125000000>; + status = "okay"; +}; From patchwork Fri Apr 19 08:17:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13635820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0874BC41513 for ; Fri, 19 Apr 2024 08:19:09 +0000 (UTC) Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) by mx.groups.io with SMTP id smtpd.web11.15298.1713514746182768529 for ; Fri, 19 Apr 2024 01:19:06 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=g+HN4tM9; spf=pass (domain: tuxon.dev, ip: 209.85.218.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-a5544fd07easo194092566b.0 for ; Fri, 19 Apr 2024 01:19:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1713514744; x=1714119544; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vsWLMdxYbNB+m5l4uv+6VkVys5+4SAj+aoAfRsQ0K34=; b=g+HN4tM99eGz89/2WXpjSz8s9E/nwgawGf+EjXGeDlX0sadm8q8BBT9BTckRsZhK4h AqxAauDME6unxmqLvbyTRYiPPVYhtr0bS9TqKcQ6rmE/t7fgaRrPZrXeXtthepYnFtWc VmaqbuF+Blgc+UHOHzo4XYWyLkfkmVnnjltQnmr6aw+oASH9l2X5d3j04hfQ8xwU7gJf L70DodMFwR7bV7Cnn6xDWfbYq3eIEX1iwnkVOILMnoLdXAVsTclU9VgJ/XmbVxl/5tGT hs67ScAmnjfS22Qcu14M+vuo4dwhjQQzfDuzm4+qdzdYdGrl8vwKOl2GR9jw/3H0gSQo xAvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713514744; x=1714119544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vsWLMdxYbNB+m5l4uv+6VkVys5+4SAj+aoAfRsQ0K34=; b=Q23sVpIV4dgTaKqylMH2HxfiLTWKFOXRKziYTbxS7+vRAemTyo+nn3+T1bSWeOfThp eDz0Jak5UwKizgJeD5E8Xuxqfzz4Z2mRRLjf6IAyten9n7KduMW8Mjf5BLk3oRVVED1L ZhuX1h5vcV9dQXZxWJY+4Y6YVi5CCAewJf5j9X1M0DtVPMHhz8TN18F3whzKg/q8fRFU GHWbR/GWnkFBeKhnldrraOMcXoCguNXBfWaDe5zBb/wKoGxHtMQQiIx/Q19HzbBu6rai oe+qMNFNJYBBtTfHFcZMJZ8PCUqQPP1p5QjwWo4urzI/5K8dlacNo36a0yK9RlEXLWsU UIvQ== X-Gm-Message-State: AOJu0YzTJi0uesmbN5iKtO9rZnYtctOafibkAoPEJ4i6Q8bt0O+/PCeR VJVeoeEoXygm+3rrM+SdBiPLIIWH4G20qztnk1Z3cvlD2qOKVGh5Wvfhkb+6Cq0= X-Google-Smtp-Source: AGHT+IHNGpK4YhABRHKetjaDoUpAjuHA/iOqvJbyTRHan/KAem6QESUEomHlDPg6N6uBUptAqyZW4Q== X-Received: by 2002:a17:906:a290:b0:a52:6832:1ae0 with SMTP id i16-20020a170906a29000b00a5268321ae0mr968393ejz.59.1713514744635; Fri, 19 Apr 2024 01:19:04 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.185]) by smtp.gmail.com with ESMTPSA id w23-20020a170907271700b00a556f2f18d6sm1816243ejk.57.2024.04.19.01.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 01:19:03 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 53/53] arm64: defconfig: Enable RZ/G3S (R9A08G045) SoC Date: Fri, 19 Apr 2024 11:17:42 +0300 Message-Id: <20240419081742.3496709-54-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> References: <20240419081742.3496709-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 19 Apr 2024 08:19:09 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15640 From: Claudiu Beznea commit 09cfdb5a97b53d117682211a4d32a39af2e819e4 upstream. Enable the config flag for the Renesas RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230929053915.1530607-29-claudiu.beznea@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index bd22f23b551c..25228f0a5c7b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -974,6 +974,7 @@ CONFIG_ARCH_R8A77995=y CONFIG_ARCH_R9A07G043=y CONFIG_ARCH_R9A07G044=y CONFIG_ARCH_R9A07G054=y +CONFIG_ARCH_R9A08G045=y CONFIG_ARCH_R9A09G011=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y