From patchwork Tue Apr 23 08:48:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13639626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB7E4C4345F for ; Tue, 23 Apr 2024 08:48:24 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.710428.1109648 (Exim 4.92) (envelope-from ) id 1rzBp1-0001s5-Lj; Tue, 23 Apr 2024 08:48:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 710428.1109648; Tue, 23 Apr 2024 08:48:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzBp1-0001ry-Ij; Tue, 23 Apr 2024 08:48:15 +0000 Received: by outflank-mailman (input) for mailman id 710428; Tue, 23 Apr 2024 08:48:14 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzBp0-0001rq-E9 for xen-devel@lists.xenproject.org; Tue, 23 Apr 2024 08:48:14 +0000 Received: from pb-smtp20.pobox.com (pb-smtp20.pobox.com [173.228.157.52]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 368071bd-014e-11ef-b4bb-af5377834399; Tue, 23 Apr 2024 10:48:12 +0200 (CEST) Received: from pb-smtp20.pobox.com (unknown [127.0.0.1]) by pb-smtp20.pobox.com (Postfix) with ESMTP id 343F52F507; Tue, 23 Apr 2024 04:48:10 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp20.sea.icgroup.com (unknown [127.0.0.1]) by pb-smtp20.pobox.com (Postfix) with ESMTP id 2CACE2F506; Tue, 23 Apr 2024 04:48:10 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp20.pobox.com (Postfix) with ESMTPSA id 816562F505; Tue, 23 Apr 2024 04:48:06 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 368071bd-014e-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=tBZw+tTNRdaf6qGurFVkABj1A orbI3wQr6+AHMyDkRk=; b=vPB+e6UJ4L4kKdEv5sFHA4N/zd8WEk9dIy53m6zGk TEfftH13Tik//ZTlNZGbM47qd4/pdaEYvdH/p8hxyGzbdP8O1ytT88JXWgWW60KC GWwlt7u3pX+PVjyQNZ9KEoq5OOEsROptDU6Til96dbcI7wa5exL5iaPI1HIQjGHD Pg= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Andrew Cooper , Stefano Stabellini Subject: [XEN PATCH v1 1/7] x86/vpmu: separate amd/intel vPMU code Date: Tue, 23 Apr 2024 11:48:03 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 3421AB46-014E-11EF-8BF4-F515D2CDFF5E-90055647!pb-smtp20.pobox.com Build AMD vPMU when CONFIG_AMD is on, and Intel vPMU when CONFIG_INTEL is on respectively, allowing for a plaftorm-specific build. Also separate arch_vpmu_ops initializers using these options and static inline stubs. No functional change intended. Signed-off-by: Sergiy Kibrik CC: Andrew Cooper CC: Jan Beulich Reviewed-by: Stefano Stabellini --- changes in v1: - switch to CONFIG_{AMD,INTEL} instead of CONFIG_{SVM,VMX} xen/arch/x86/cpu/Makefile | 4 +++- xen/arch/x86/include/asm/vpmu.h | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index 35561fe51d..eafce5f204 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -10,4 +10,6 @@ obj-y += intel.o obj-y += intel_cacheinfo.o obj-y += mwait-idle.o obj-y += shanghai.o -obj-y += vpmu.o vpmu_amd.o vpmu_intel.o +obj-y += vpmu.o +obj-$(CONFIG_AMD) += vpmu_amd.o +obj-$(CONFIG_INTEL) += vpmu_intel.o diff --git a/xen/arch/x86/include/asm/vpmu.h b/xen/arch/x86/include/asm/vpmu.h index dae9b43dac..e7a8f211f8 100644 --- a/xen/arch/x86/include/asm/vpmu.h +++ b/xen/arch/x86/include/asm/vpmu.h @@ -11,6 +11,7 @@ #define __ASM_X86_HVM_VPMU_H_ #include +#include #define vcpu_vpmu(vcpu) (&(vcpu)->arch.vpmu) #define vpmu_vcpu(vpmu) container_of((vpmu), struct vcpu, arch.vpmu) @@ -42,9 +43,27 @@ struct arch_vpmu_ops { #endif }; +#ifdef CONFIG_INTEL const struct arch_vpmu_ops *core2_vpmu_init(void); +#else +static inline const struct arch_vpmu_ops *core2_vpmu_init(void) +{ + return ERR_PTR(-ENODEV); +} +#endif +#ifdef CONFIG_AMD const struct arch_vpmu_ops *amd_vpmu_init(void); const struct arch_vpmu_ops *hygon_vpmu_init(void); +#else +static inline const struct arch_vpmu_ops *amd_vpmu_init(void) +{ + return ERR_PTR(-ENODEV); +} +static inline const struct arch_vpmu_ops *hygon_vpmu_init(void) +{ + return ERR_PTR(-ENODEV); +} +#endif struct vpmu_struct { u32 flags; From patchwork Tue Apr 23 08:50:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13639627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54455C4345F for ; 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a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=aYD43tk+gWcyJQX2GE5PLFjHO p7VB7dWZgOWsQGq9gU=; b=b9bWZqrJCuMB6yFz66DOS65k9dAox6+zmq11HPZRZ xuTsr9VtncYPmCJBBV0uvWTaYpw2L31N+2cEkEM3l0MLSzFkiy1dQBkKDO/CEx0L EDFKF/YH39t5bxaQtEwMcRakeb4H1UqO7tHyjQdpI0+j6Z+YAmH42XlqiKDlRgYi MQ= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v1 2/7] x86/intel: guard vmce_has_lmce() with INTEL option Date: Tue, 23 Apr 2024 11:50:09 +0300 Message-Id: <5e26895d84f8b7750799740ac2324b2cb92fa97e.1713860310.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 7F821B2A-014E-11EF-9A68-F515D2CDFF5E-90055647!pb-smtp20.pobox.com Since MCG_LMCE_P bit is specific to Intel CPUs the code to check it can possibly be excluded from build if !CONFIG_INTEL. With these guards calls to vmce_has_lmce() are eliminated and mce_intel.c can end up not being built. Also replace boilerplate code that checks for MCG_LMCE_P flag with vmce_has_lmce(), which might contribute to readability a bit. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini --- xen/arch/x86/cpu/mcheck/vmce.c | 4 ++-- xen/arch/x86/msr.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 353d4f19b2..c437f62c0a 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -199,7 +199,7 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val) * bits are always set in guest MSR_IA32_FEATURE_CONTROL by Xen, so it * does not need to check them here. */ - if ( cur->arch.vmce.mcg_cap & MCG_LMCE_P ) + if ( IS_ENABLED(CONFIG_INTEL) && vmce_has_lmce(cur) ) { *val = cur->arch.vmce.mcg_ext_ctl; mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL %#"PRIx64"\n", @@ -324,7 +324,7 @@ int vmce_wrmsr(uint32_t msr, uint64_t val) break; case MSR_IA32_MCG_EXT_CTL: - if ( (cur->arch.vmce.mcg_cap & MCG_LMCE_P) && + if ( IS_ENABLED(CONFIG_INTEL) && vmce_has_lmce(cur) && !(val & ~MCG_EXT_CTL_LMCE_EN) ) cur->arch.vmce.mcg_ext_ctl = val; else diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 9babd441f9..4010c87d93 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -86,7 +86,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) goto gp_fault; *val = IA32_FEATURE_CONTROL_LOCK; - if ( vmce_has_lmce(v) ) + if ( IS_ENABLED(CONFIG_INTEL) && vmce_has_lmce(v) ) *val |= IA32_FEATURE_CONTROL_LMCE_ON; if ( cp->basic.vmx ) *val |= IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX; From patchwork Tue Apr 23 08:52:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13639631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2FDC7C04FF8 for ; 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a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=S1rwCtNYMTM6b7pGJJ8grguoV 77WucEJ1NnbYDjwq30=; b=x+nWwy8vZGgQ662bifcMeCFlB6UAPDjpKka1g8OqA LzvCuebQ7lPmAdyZMRSTJIjV/DEGLqb551EPsp1iCsbZZ+cCPWwPEZM6/njNJ4l0 RUdW1lpG4sT9PdwOoEscAKZdXLZ9T3EZ76VcuadNSXDEgbY0DMtSL+ylPRhej8aN UI= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v1 3/7] x86/MCE: guard access to Intel/AMD-specific MCA MSRs Date: Tue, 23 Apr 2024 11:52:17 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: CB7F013C-014E-11EF-A908-F515D2CDFF5E-90055647!pb-smtp20.pobox.com Add build-time checks for newly introduced INTEL/AMD config options when calling vmce_{intel/amd}_{rdmsr/wrmsr}() routines. This way a platform-specific code can be omitted in vmce code, if this platform is disabled in config. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini --- xen/arch/x86/cpu/mcheck/vmce.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index c437f62c0a..be229684a4 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -141,12 +141,14 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) case X86_VENDOR_CENTAUR: case X86_VENDOR_SHANGHAI: case X86_VENDOR_INTEL: - ret = vmce_intel_rdmsr(v, msr, val); + ret = IS_ENABLED(CONFIG_INTEL) ? + vmce_intel_rdmsr(v, msr, val) : -ENODEV; break; case X86_VENDOR_AMD: case X86_VENDOR_HYGON: - ret = vmce_amd_rdmsr(v, msr, val); + ret = IS_ENABLED(CONFIG_AMD) ? + vmce_amd_rdmsr(v, msr, val) : -ENODEV; break; default: @@ -272,12 +274,14 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) switch ( boot_cpu_data.x86_vendor ) { case X86_VENDOR_INTEL: - ret = vmce_intel_wrmsr(v, msr, val); + ret = IS_ENABLED(CONFIG_INTEL) ? + vmce_intel_wrmsr(v, msr, val) : -ENODEV; break; case X86_VENDOR_AMD: case X86_VENDOR_HYGON: - ret = vmce_amd_wrmsr(v, msr, val); + ret = IS_ENABLED(CONFIG_AMD) ? + vmce_amd_wrmsr(v, msr, val) : -ENODEV; break; default: From patchwork Tue Apr 23 08:54:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13639632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E95DAC4345F for ; Tue, 23 Apr 2024 08:54:44 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.710440.1109678 (Exim 4.92) (envelope-from ) id 1rzBv8-0004nh-NZ; Tue, 23 Apr 2024 08:54:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 710440.1109678; Tue, 23 Apr 2024 08:54:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzBv8-0004na-Kk; Tue, 23 Apr 2024 08:54:34 +0000 Received: by outflank-mailman (input) for mailman id 710440; Tue, 23 Apr 2024 08:54:33 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzBv7-0004kK-F3 for xen-devel@lists.xenproject.org; Tue, 23 Apr 2024 08:54:33 +0000 Received: from pb-smtp20.pobox.com (pb-smtp20.pobox.com [173.228.157.52]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 1925f680-014f-11ef-909a-e314d9c70b13; Tue, 23 Apr 2024 10:54:32 +0200 (CEST) Received: from pb-smtp20.pobox.com (unknown [127.0.0.1]) by pb-smtp20.pobox.com (Postfix) with ESMTP id 76ED42F58C; Tue, 23 Apr 2024 04:54:30 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp20.sea.icgroup.com (unknown [127.0.0.1]) by pb-smtp20.pobox.com (Postfix) with ESMTP id 6F3552F58B; Tue, 23 Apr 2024 04:54:30 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp20.pobox.com (Postfix) with ESMTPSA id E65F52F588; Tue, 23 Apr 2024 04:54:26 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1925f680-014f-11ef-909a-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=qBdCaQo8xXPRL9koiygD4Doyw FZCckSSqeafkQGDihU=; b=WCbm9Gvv8A5FY/iF7cCg5LLERujQJjvAcQ7N4+Dt3 vqIta6Fh56FnKa8UtNPKzhLjZANpOdRqMvbn+C8YgYVkN6UpTLWfPuth1CEP8kvn trXWAn04JfsQlWO2FNsN3Mo7QvrUcAaTe+xQgo6yojDA4nh0UfMpP8+nOcsw2X8n pc= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v1 4/7] x86/MCE: guard lmce_support/cmci_support Date: Tue, 23 Apr 2024 11:54:23 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 16E01ED6-014F-11EF-9FC5-F515D2CDFF5E-90055647!pb-smtp20.pobox.com Guard access to Intel-specific lmce_support & cmci_support variables in common MCE/VMCE code. These are set in Intel-specific parts of mcheck code and can potentially be skipped if building for non-intel platform by disabling CONFIG_INTEL option. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini --- xen/arch/x86/cpu/mcheck/mce.c | 4 ++-- xen/arch/x86/cpu/mcheck/vmce.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 2844685983..72dfaf28cb 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -611,7 +611,7 @@ static void set_poll_bankmask(struct cpuinfo_x86 *c) mb = per_cpu(poll_bankmask, cpu); BUG_ON(!mb); - if ( cmci_support && opt_mce ) + if ( IS_ENABLED(CONFIG_INTEL) && cmci_support && opt_mce ) { const struct mca_banks *cmci = per_cpu(no_cmci_banks, cpu); @@ -1607,7 +1607,7 @@ long do_mca(XEN_GUEST_HANDLE_PARAM(xen_mc_t) u_xen_mc) break; case XEN_MC_INJECT_TYPE_LMCE: - if ( !lmce_support ) + if ( IS_ENABLED(CONFIG_INTEL) && !lmce_support ) { ret = x86_mcerr("No LMCE support", -EINVAL); break; diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index be229684a4..6051ab2b2e 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -546,7 +546,7 @@ int vmce_enable_mca_cap(struct domain *d, uint64_t cap) if ( cap & XEN_HVM_MCA_CAP_LMCE ) { - if ( !lmce_support ) + if ( IS_ENABLED(CONFIG_INTEL) && !lmce_support ) return -EINVAL; for_each_vcpu(d, v) v->arch.vmce.mcg_cap |= MCG_LMCE_P; From patchwork Tue Apr 23 08:56:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13639633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9BB4C4345F for ; Tue, 23 Apr 2024 08:56:48 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.710450.1109688 (Exim 4.92) (envelope-from ) id 1rzBx7-0005Za-5m; Tue, 23 Apr 2024 08:56:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 710450.1109688; Tue, 23 Apr 2024 08:56:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzBx7-0005ZT-2z; Tue, 23 Apr 2024 08:56:37 +0000 Received: by outflank-mailman (input) for mailman id 710450; Tue, 23 Apr 2024 08:56:36 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzBx6-0005Yn-5q for xen-devel@lists.xenproject.org; Tue, 23 Apr 2024 08:56:36 +0000 Received: from pb-smtp1.pobox.com (pb-smtp1.pobox.com [64.147.108.70]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 62e34d29-014f-11ef-909a-e314d9c70b13; Tue, 23 Apr 2024 10:56:35 +0200 (CEST) Received: from pb-smtp1.pobox.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 0A5961FD769; Tue, 23 Apr 2024 04:56:34 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp1.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 022721FD768; Tue, 23 Apr 2024 04:56:34 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp1.pobox.com (Postfix) with ESMTPSA id C113D1FD767; Tue, 23 Apr 2024 04:56:32 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 62e34d29-014f-11ef-909a-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=cIUMk06Iz/UdL/eIZeqDIguEs WgJvKn0D2mTsky2q7Q=; b=UJX65VpyP4bUaX3rMU8JvyDG0duxJcb+i221/pWHC ZzUvnR2fFIVtwH7MGW1XnnkgW4mEET+PNZbsmC1mjXxbegkxkQsW14GYpdGcbqJr FIr7+Uuzsa94RluQFqjlkFYNO4ek7zzSPXvHtzqk09v3wfHC6m94HFUfAwFP9MEg yA= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v1 5/7] x86/MCE: guard {intel/amd}_mcheck_init() calls Date: Tue, 23 Apr 2024 11:56:30 +0300 Message-Id: <0c7d28740db4d6581ebc81a158c970258e547959.1713860310.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 61E2A1EC-014F-11EF-8E73-78DCEB2EC81B-90055647!pb-smtp1.pobox.com Guard calls to CPU-specific mcheck init routines in common MCE code using new INTEL/AMD config options. The purpose is not to build platform-specific mcheck code and calls to it, if this platform is disabled in config. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini --- xen/arch/x86/cpu/mcheck/mce.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 72dfaf28cb..42e84e76b7 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -761,7 +761,8 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) { case X86_VENDOR_AMD: case X86_VENDOR_HYGON: - inited = amd_mcheck_init(c, bsp); + inited = IS_ENABLED(CONFIG_AMD) ? amd_mcheck_init(c, bsp) : + mcheck_unset; break; case X86_VENDOR_INTEL: @@ -769,7 +770,8 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) { case 6: case 15: - inited = intel_mcheck_init(c, bsp); + inited = IS_ENABLED(CONFIG_INTEL) ? intel_mcheck_init(c, bsp) : + mcheck_unset; break; } break; From patchwork Tue Apr 23 08:58:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13639634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1C84C4345F for ; Tue, 23 Apr 2024 08:58:53 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.710455.1109697 (Exim 4.92) (envelope-from ) id 1rzBz7-00069r-H3; Tue, 23 Apr 2024 08:58:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 710455.1109697; Tue, 23 Apr 2024 08:58:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzBz7-00069k-EK; Tue, 23 Apr 2024 08:58:41 +0000 Received: by outflank-mailman (input) for mailman id 710455; Tue, 23 Apr 2024 08:58:40 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzBz6-00069X-0C for xen-devel@lists.xenproject.org; Tue, 23 Apr 2024 08:58:40 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id ac6e209e-014f-11ef-909a-e314d9c70b13; Tue, 23 Apr 2024 10:58:39 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 442431F0845; Tue, 23 Apr 2024 04:58:37 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 3B3301F0844; Tue, 23 Apr 2024 04:58:37 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id 1F5E91F0843; Tue, 23 Apr 2024 04:58:36 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ac6e209e-014f-11ef-909a-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=VFOZ78GE83950bFvFp1D2oIQO K0G5qlHi1q6MPGjNmw=; b=qgY84Vw7CGByYaErRK9vOYRyCeOp7oDOCm8TJ7RUN ua78MvChW9tdaQKm+cXTRPK7wIdTeM0SEtnmmQE0ZypGZLyRJJc31o8ylRZP+Z3S UtYDRdQCGETU4s1WRPmKb9ubwQzVWdD4TU1OpaUzWiMxYZYd1aKbunRQZluTl0Qr Wo= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v1 6/7] x86/MCE: guard call to Intel-specific intel_get_extended_msrs() Date: Tue, 23 Apr 2024 11:58:34 +0300 Message-Id: <6769d564725912245cb83aaf7543933b4b5fb80d.1713860310.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: AB669ED6-014F-11EF-BB0C-25B3960A682E-90055647!pb-smtp2.pobox.com Add check for CONFIG_INTEL build option to conditional call of this routine, so that if Intel support is disabled the call would be eliminated. No functional change intended. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- xen/arch/x86/cpu/mcheck/mce.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 42e84e76b7..de2e16a6e2 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -328,7 +328,8 @@ mcheck_mca_logout(enum mca_source who, struct mca_banks *bankmask, ASSERT(mig); mca_init_global(mc_flags, mig); /* A hook here to get global extended msrs */ - if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) + if ( IS_ENABLED(CONFIG_INTEL) && + boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) intel_get_extended_msrs(mig, mci); } } From patchwork Tue Apr 23 09:00:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13639635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9AD5C4345F for ; Tue, 23 Apr 2024 09:00:55 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.710467.1109708 (Exim 4.92) (envelope-from ) id 1rzC19-0007bF-1g; Tue, 23 Apr 2024 09:00:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 710467.1109708; Tue, 23 Apr 2024 09:00:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzC18-0007b8-VE; Tue, 23 Apr 2024 09:00:46 +0000 Received: by outflank-mailman (input) for mailman id 710467; Tue, 23 Apr 2024 09:00:45 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rzC16-0007b0-Ub for xen-devel@lists.xenproject.org; Tue, 23 Apr 2024 09:00:44 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id f628cbc8-014f-11ef-b4bb-af5377834399; Tue, 23 Apr 2024 11:00:42 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 445F11F087C; Tue, 23 Apr 2024 05:00:41 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 3B5F91F087B; Tue, 23 Apr 2024 05:00:41 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id 3B7741F087A; Tue, 23 Apr 2024 05:00:40 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f628cbc8-014f-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=9+9XMXvzGyolHzNNE3bL+S4CK XGZAy5Za91IKnXnLa8=; b=ydVPJ0EmcaP/WyWi01IUt/358xO8U1M33CZGr1egP eMYUcoMJB00N6Rje8h2AbIZkkj+SisqEpXGO85qV1k/Qa9rXAIoy0zBksMy5Np7h SUrEBiNWM6WfIf+qiQmwqOMF/L5H9eiVcQQQCYa9tZd5ZdQUbCfD9bPQ8iqs0dCs 5w= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v1 7/7] x86/MCE: optional build of AMD/Intel MCE code Date: Tue, 23 Apr 2024 12:00:37 +0300 Message-Id: <82df6ef350a2b4f42ec7adf12a90ebeae1d133f6.1713860310.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: F5617A42-014F-11EF-8DD6-25B3960A682E-90055647!pb-smtp2.pobox.com Separate Intel/AMD-specific MCE code using CONFIG_{INTEL,AMD} config options. Now we can avoid build of mcheck code if support for specific platform is intentionally disabled by configuration. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini --- xen/arch/x86/cpu/mcheck/Makefile | 6 ++---- xen/arch/x86/cpu/mcheck/non-fatal.c | 6 ++++++ xen/arch/x86/cpu/mcheck/vmce.h | 1 + 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/Makefile b/xen/arch/x86/cpu/mcheck/Makefile index f927f10b4d..5b3f6d875c 100644 --- a/xen/arch/x86/cpu/mcheck/Makefile +++ b/xen/arch/x86/cpu/mcheck/Makefile @@ -1,12 +1,10 @@ -obj-y += amd_nonfatal.o -obj-y += mce_amd.o obj-y += mcaction.o obj-y += barrier.o -obj-y += intel-nonfatal.o obj-y += mctelem.o obj-y += mce.o obj-y += mce-apei.o -obj-y += mce_intel.o +obj-$(CONFIG_AMD) += mce_amd.o amd_nonfatal.o +obj-$(CONFIG_INTEL) += mce_intel.o intel-nonfatal.o obj-y += non-fatal.o obj-y += util.o obj-y += vmce.o diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c index 33cacd15c2..2d91a3b1e0 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -24,14 +24,20 @@ static int __init cf_check init_nonfatal_mce_checker(void) * Check for non-fatal errors every MCE_RATE s */ switch (c->x86_vendor) { +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: /* Assume we are on K8 or newer AMD or Hygon CPU here */ amd_nonfatal_mcheck_init(c); break; +#endif +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: intel_nonfatal_mcheck_init(c); break; +#endif + default: + return -ENODEV; } printk(KERN_INFO "mcheck_poll: Machine check polling timer started.\n"); return 0;