From patchwork Tue Apr 23 10:01:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13639685 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A817A5EE8D; Tue, 23 Apr 2024 10:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713866515; cv=none; b=CINCsopKf5XJYentvX8su8Xj4+zEgegultUsUgU8o+q2LwJ8SgC2Px651V4JcN8oUyWA0s43NuaeKewsKj5KL/En1kIkpyJp1H5XT+s2iTT0t8UzsSKxGojyi1zQYZB0z4CJ2fy94juUxrZ605k4pM0GxBpVd2wTwkAACrBRvt8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713866515; c=relaxed/simple; bh=HK7nTIHxj4vRn1zLzL4Ml297uns17UJ5VfHqPQW4dAA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rfPDemz5XyfH2GYJiTDddvY9+pk70W2IuIx8vmHE3PIDQbIxB9lhXfYNhKmH9vdCUmNpoubJJhf53ogoBfXjfgXTzWm8jVBfXEjY43xmX1H33JFspdO489ClCt+QNGn1x4qxG3w+VNWtQLIegXeiCoA/6gpRzG6q6qM+cJEyh6I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=np8hB3aR; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="np8hB3aR" Received: by mail.gandi.net (Postfix) with ESMTPSA id 269F41C000C; Tue, 23 Apr 2024 10:01:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1713866508; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+jkSaR8RN3FHUyVZmT8l3Mp5fnnAxigkjdQtpVmnrtI=; b=np8hB3aRqLPP/YVkDs5g4oOgvcmkH8S/H24b1cwNg4ihYKUhKBbpH8qtwvSPc7LQafk7pv +7MVQtuzACXnZWNEfb6jMduRm5IuCL7yLuTyJxApsw6n2sgnAjXtAIg8yUFpuncozYoM/I 3pne5mfZFjZt4D0pZtjprMGYBMyw2rQhU7J1QdSj4uUPaqAQA769NrjpRMnVpd7EABn1ok ObUYB5QKoBupMY2QH2IQB8aDXb9P3zSzFNCBagtVRGfYFvJHFlnE8/WYOGAaRxa2/k2MvO rD6nD7fXI4nn9xCghIgMea5yO+k+YmAM1AKWbRXEaMKojACj6pjhKJGvbQ43Bw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Apr 2024 12:01:40 +0200 Subject: [PATCH v4 1/6] spi: cadence-qspi: allow FIFO depth detection Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240423-cdns-qspi-mbly-v4-1-3d2a7b535ad0@bootlin.com> References: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> In-Reply-To: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com If FIFO depth DT property is provided, check it matches what hardware reports and warn otherwise. Else, use hardware provided value. Hardware exposes FIFO depth indirectly because CQSPI_REG_SRAMPARTITION is partially read-only. Move probe cqspi->ddata assignment prior to cqspi_of_get_pdata() call. Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 9896e9fe7ffb..5a83940220a9 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1510,8 +1510,8 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { - dev_err(dev, "couldn't determine fifo-depth\n"); - return -ENXIO; + /* Zero signals FIFO depth should be runtime detected. */ + cqspi->fifo_depth = 0; } if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { @@ -1541,8 +1541,6 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) { u32 reg; - cqspi_controller_enable(cqspi, 0); - /* Configure the remap address register, no remap */ writel(0, cqspi->iobase + CQSPI_REG_REMAP); @@ -1576,8 +1574,29 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) reg |= CQSPI_REG_CONFIG_DMA_MASK; writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); } +} - cqspi_controller_enable(cqspi, 1); +static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi) +{ + struct device *dev = &cqspi->pdev->dev; + u32 reg, fifo_depth; + + /* + * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N + * the FIFO depth. + */ + writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION); + reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION); + fifo_depth = reg + 1; + + /* FIFO depth of zero means no value from devicetree was provided. */ + if (cqspi->fifo_depth == 0) { + cqspi->fifo_depth = fifo_depth; + dev_dbg(dev, "using FIFO depth of %u\n", fifo_depth); + } else if (fifo_depth != cqspi->fifo_depth) { + dev_warn(dev, "detected FIFO depth (%u) different from config (%u)\n", + fifo_depth, cqspi->fifo_depth); + } } static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) @@ -1730,6 +1749,7 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->pdev = pdev; cqspi->host = host; cqspi->is_jh7110 = false; + cqspi->ddata = ddata = of_device_get_match_data(dev); platform_set_drvdata(pdev, cqspi); /* Obtain configuration from OF. */ @@ -1821,8 +1841,6 @@ static int cqspi_probe(struct platform_device *pdev) /* write completion is supported by default */ cqspi->wr_completion = true; - ddata = of_device_get_match_data(dev); - cqspi->ddata = ddata; if (ddata) { if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, @@ -1864,7 +1882,10 @@ static int cqspi_probe(struct platform_device *pdev) } cqspi_wait_idle(cqspi); + cqspi_controller_enable(cqspi, 0); + cqspi_controller_detect_fifo_depth(cqspi); cqspi_controller_init(cqspi); + cqspi_controller_enable(cqspi, 1); cqspi->current_cs = -1; cqspi->sclk = 0; @@ -1947,7 +1968,9 @@ static int cqspi_runtime_resume(struct device *dev) clk_prepare_enable(cqspi->clk); cqspi_wait_idle(cqspi); + cqspi_controller_enable(cqspi, 0); cqspi_controller_init(cqspi); + cqspi_controller_enable(cqspi, 1); cqspi->current_cs = -1; cqspi->sclk = 0; From patchwork Tue Apr 23 10:01:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13639684 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A82895FDA6; Tue, 23 Apr 2024 10:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713866515; cv=none; b=F10Xb5KtKGIIr9VHorzN6vnShb2ax+OMJnxCa99A/5QmuEdENO5sttM3RQCHWOe87JZGhWN+cZJAtIjPANLOAy5DQy2OWs4d/g7hUrCBgUvtes+Ulwto+/XoiOxIp5DxsKf1Mlm8rgJtNY6MIf0WGP34qX2h52Ek/lr1UphrE9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713866515; c=relaxed/simple; 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a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1713866509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kGNLEQi4vjLPM4/+K8lcB+bqcRv9SUQX2PQJaBnW2l0=; b=GhHVZ5ZA4maacHUrY5LlPBRHRa83rkSGLklZkRpZM6NF8c634ZZY8qVk5/DmO5oSNpre8k Ufazmo1CO5N5inq10XLSDMBWMz7p8yRPa8uduyLqWzNeq8hSw1Ks7ra/Cytui6i2njQh5Z SfAb5arq1yAzO2hytaNQHQ7L+9YK3bIsRLIUNHl+d+sPz9QXqfjEDFblYTN/eTfT/vrAWC dd2Et2R9dhdbDl0YLRpDBDV1u3GrgLHXc2j/yYoSoadqsHHmePs7BsJ8EU7/t6UPnG8+ap SvQTHjnbanBtnJwtsUMXHZO0+NktIy3CdS+VM3JUZLphPfGkWQxD3Tt/VYzG6g== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Apr 2024 12:01:41 +0200 Subject: [PATCH v4 2/6] spi: cadence-qspi: add no-IRQ mode to indirect reads Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240423-cdns-qspi-mbly-v4-2-3d2a7b535ad0@bootlin.com> References: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> In-Reply-To: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Support reads through polling, without any IRQ. The main reason is performance; profiling shows that the first IRQ comes quickly on our specific hardware. Once this IRQ arrives, we poll until all data is retrieved. Avoid initial sleep to reduce IRQ count. Hide this behavior behind a quirk flag. This is confirmed through micro-benchmarks, but also end-to-end performance tests. Mobileye EyeQ5, octal flash, reading 235M on a UBIFS filesystem: - No optimizations, ~10.34s, ~22.7 MB/s, 199230 IRQs - CQSPI_SLOW_SRAM, ~10.34s, ~22.7 MB/s, 70284 IRQs - CQSPI_RD_NO_IRQ, ~9.37s, ~25.1 MB/s, 521 IRQs Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 5a83940220a9..a82e23526a6f 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -42,6 +42,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX); #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) +#define CQSPI_RD_NO_IRQ BIT(6) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -702,6 +703,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, const size_t n_rx) { struct cqspi_st *cqspi = f_pdata->cqspi; + bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ); struct device *dev = &cqspi->pdev->dev; void __iomem *reg_base = cqspi->iobase; void __iomem *ahb_base = cqspi->ahb_base; @@ -725,17 +727,20 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, * all the read interrupts disabled for max performance. */ - if (!cqspi->slow_sram) + if (use_irq && cqspi->slow_sram) + writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); + else if (use_irq) writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); else - writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); + writel(0, reg_base + CQSPI_REG_IRQMASK); reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTRD_START_MASK, reg_base + CQSPI_REG_INDIRECTRD); while (remaining > 0) { - if (!wait_for_completion_timeout(&cqspi->transfer_complete, + if (use_irq && + !wait_for_completion_timeout(&cqspi->transfer_complete, msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) ret = -ETIMEDOUT; @@ -777,7 +782,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, bytes_to_read = cqspi_get_rd_sram_level(cqspi); } - if (remaining > 0) { + if (use_irq && remaining > 0) { reinit_completion(&cqspi->transfer_complete); if (cqspi->slow_sram) writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); From patchwork Tue Apr 23 10:01:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13639686 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A820E5FBA6; Tue, 23 Apr 2024 10:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713866515; cv=none; b=IWL+mcUE1xg+nkXATJivQ24mMvBFUCGewZS7Dsn2Sxq1RTbu0A08ptNgK9p6BSkjTBp9ztk7lbV5fAnQFiP1aqFes7o6aG0UQhGMeua0OzSQXsO85UVqXkVFQxbeMHVB05Ro8MGdpHyhVVwGH+BMVQo49WyE+24KkjUpuO5qeAs= ARC-Message-Signature: i=1; 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Tue, 23 Apr 2024 10:01:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1713866510; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=69cnUQUcGYJmLIaC0THyrs7sb2kh2LjvS2li/WRvhmg=; b=IWB+ViNjDlwEDhQ0mU6ufOVJejzzXLai/lEyNOE7G/lilUbSF+mSHCkCfrsekEHbnM6Q4M k42SHhMZINUZJi4/55djZmTBgvXCmqf7IL2GLm1a50Zy/VE3kqhcIp3fhiAJM807Cq+YvN qQksQiVEc2Lwp0vQa0v2uueqeFxeeyRXqg2/2T3+9tjb+Hdn76+NjlLQ1nbeh9nOtCcWvp YY5TqkOBgeMd41f8fSJw9w5080f1fFl/SagcXgKxboEeuCn2K7KKFYFlzvIawod6r+JB6F 0cLbYlQ8mNvac75PwQRZLA0mva4mhSbKyOJMFNK9tIClzXqE7b7dJMaW42nIAw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Apr 2024 12:01:42 +0200 Subject: [PATCH v4 3/6] spi: cadence-qspi: add early busywait to cqspi_wait_for_bit() Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240423-cdns-qspi-mbly-v4-3-3d2a7b535ad0@bootlin.com> References: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> In-Reply-To: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Call readl_relaxed_poll_timeout() with no sleep at the start of cqspi_wait_for_bit(). If its short timeout expires, a sleeping readl_relaxed_poll_timeout() call takes the relay. The reason is to avoid hrtimer interrupts on the system. All read operations are expected to take less than 100µs. Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index a82e23526a6f..87c88ee708e4 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -120,6 +120,7 @@ struct cqspi_driver_platdata { /* Operation timeout value */ #define CQSPI_TIMEOUT_MS 500 #define CQSPI_READ_TIMEOUT_MS 10 +#define CQSPI_BUSYWAIT_TIMEOUT_US 500 /* Runtime_pm autosuspend delay */ #define CQSPI_AUTOSUSPEND_TIMEOUT 2000 @@ -298,13 +299,27 @@ struct cqspi_driver_platdata { #define CQSPI_REG_VERSAL_DMA_VAL 0x602 -static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) +static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata, + void __iomem *reg, const u32 mask, bool clr, + bool busywait) { + u64 timeout_us = CQSPI_TIMEOUT_MS * USEC_PER_MSEC; u32 val; + if (busywait) { + int ret = readl_relaxed_poll_timeout(reg, val, + (((clr ? ~val : val) & mask) == mask), + 0, CQSPI_BUSYWAIT_TIMEOUT_US); + + if (ret != -ETIMEDOUT) + return ret; + + timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US; + } + return readl_relaxed_poll_timeout(reg, val, (((clr ? ~val : val) & mask) == mask), - 10, CQSPI_TIMEOUT_MS * 1000); + 10, timeout_us); } static bool cqspi_is_idle(struct cqspi_st *cqspi) @@ -434,8 +449,8 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) writel(reg, reg_base + CQSPI_REG_CMDCTRL); /* Polling for completion. */ - ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, - CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); + ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL, + CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true); if (ret) { dev_err(&cqspi->pdev->dev, "Flash command execution timed out.\n"); @@ -790,8 +805,8 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, } /* Check indirect done status */ - ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, - CQSPI_REG_INDIRECTRD_DONE_MASK, 0); + ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD, + CQSPI_REG_INDIRECTRD_DONE_MASK, 0, true); if (ret) { dev_err(dev, "Indirect read completion error (%i)\n", ret); goto failrd; @@ -1091,8 +1106,8 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, } /* Check indirect done status */ - ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, - CQSPI_REG_INDIRECTWR_DONE_MASK, 0); + ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR, + CQSPI_REG_INDIRECTWR_DONE_MASK, 0, false); if (ret) { dev_err(dev, "Indirect write completion error (%i)\n", ret); goto failwr; From patchwork Tue Apr 23 10:01:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13639683 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A82405FBAA; Tue, 23 Apr 2024 10:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="p51pCjr/" Received: by mail.gandi.net (Postfix) with ESMTPSA id 8189D1C001C; Tue, 23 Apr 2024 10:01:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1713866511; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9d1LWBS78fz/noWt+gqf119+B397lC3IF2943t1mJfE=; b=p51pCjr/a5r4zzZu1njCWQXO3/yoPufH9zRqZh84JLpWmBtq3mWr26sDFzZ+PTatF/fC8g NSUJmWPx/gMi53afkoTr4Z5ZlcmG/o5zBdmzcuDRPDDf9OXJ30v74dqB925vcGq2RBvw4o tFt8hjnSzNcVdJk2vfKAmb7n8uQASlk7rmjvA/k+cdji2Qk3UvmBfhwlLe4TjAihVYdgll u5thehFVolGgeg1Xg35wdrls78JW7HcgHvdAtQjVzWrISyTDSkuuu4JAd/qtDghltq2c69 nKRcGwdrLcTMp6Bg57uG40ChpxrXU3ptJpVFTzB3WQDw7Os4dW3UxIo9GnhPeg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Apr 2024 12:01:43 +0200 Subject: [PATCH v4 4/6] spi: cadence-qspi: add mobileye,eyeq5-ospi compatible Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240423-cdns-qspi-mbly-v4-4-3d2a7b535ad0@bootlin.com> References: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> In-Reply-To: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Declare a new mobileye,eyeq5-ospi compatible. Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 87c88ee708e4..05ebb03d319f 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -2055,6 +2055,12 @@ static const struct cqspi_driver_platdata pensando_cdns_qspi = { .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, }; +static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = { + .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, + .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | + CQSPI_RD_NO_IRQ, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -2088,6 +2094,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "amd,pensando-elba-qspi", .data = &pensando_cdns_qspi, }, + { + .compatible = "mobileye,eyeq5-ospi", + .data = &mobileye_eyeq5_ospi, + }, { /* end of table */ } }; From patchwork Tue Apr 23 10:01:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13639687 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EF8F5FDB5; Tue, 23 Apr 2024 10:01:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713866515; cv=none; b=cIoBS3Umg/UdMcQj0xJXiETGaOOIG7HAvj9vV9oHIvhhvmmKKp59+zTiYZx9rRXvzbxnmHD1KGkwKuuC9iiAq3vce7PrZVXFtn+dj1imVF26mW6i6WJUdbfwtphGOtxjHe3Qjfusez+iiMdOkyp6uapi73gjr9pehabH8coM5os= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713866515; c=relaxed/simple; bh=vuFml2Tbieyo6tIWPbphQoCJOz5E27f346lkQPXpqDA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BBMU6/oh1j1N43IeK6o7gBvgmsrJjGxPxQCGcpMIk5KCDQC/puhcoomy/fP+Iy1O/u9KYNFb7HcBQOAVAn65/Gi6XekS3Uo6cQVU/69ckOkFFBWRZrxXQuyd/iW+bolyr6/7msydM2/dGKi3QRKnmQXlg6YhNMynl+msM3yvMo8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=YuTbLg8u; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="YuTbLg8u" Received: by mail.gandi.net (Postfix) with ESMTPSA id 4543D1C000D; Tue, 23 Apr 2024 10:01:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1713866511; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/Ysm4DbzpqSZj84XzesirmTyGQsD5pPgqx8ZXriQXW0=; b=YuTbLg8utCHFpsX8uzPncIZO3UoXEJ6hPAhIx9QypocJwztMd4Wvkh1lzBBdIXXLUD797z QLoZNrmiL89sYRd5BmaTrT3fsZI0Sx+SIAsZ9CADbFzQQDmnRFW64w7KO+8lLz8arDqtjq aH62QIia9RLUZPjd5i7f5IFxnf/wRq1e4cxCxKGJDzVbLfclHwxCcO1FQlfopij/JxNmx6 6Z0lRATv5nZ/fkrTUutfwekh4b2vbxP0vEh/NAXNs34SVS9PRfEm0udQX6i06jUalbFzCv geM/2HajDCXmsUMqFDcxv/WjSo2IyM7TM9dhCwnMqQwKIOrWBdflhpQviRE1dA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Apr 2024 12:01:44 +0200 Subject: [PATCH v4 5/6] MIPS: mobileye: eyeq5: Add SPI-NOR controller node Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240423-cdns-qspi-mbly-v4-5-3d2a7b535ad0@bootlin.com> References: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> In-Reply-To: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Add Cadence Quad SPI controller node to EyeQ5 SoC devicetree. Octal is supported. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 8d4f65ec912d..1543c2b9bcb6 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -158,6 +158,21 @@ timer { clocks = <&core0_clk>; }; }; + + ospi: spi@2100000 { + compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor"; + reg = <0 0x2100000 0x0 0x1000>, + <0 0x10000000 0x0 0x8000000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&clocks EQ5C_DIV_OSPI>; + assigned-clocks = <&clocks EQ5C_DIV_OSPI>; + assigned-clock-rates = <167000000>; + #address-cells = <1>; + #size-cells = <0>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + }; }; }; From patchwork Tue Apr 23 10:01:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13639689 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 320185FDDC; Tue, 23 Apr 2024 10:01:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713866519; cv=none; b=orS8+AbQ0rSyJmyf7a5tg68jmor8qqM7FjWuaiuOSgiwtrGrmownrNSH4WoeAV+ATVfqjaUl4wVnoRqvh+IU+xXZ3K/Et5ynPyzZ43wuX/DkLDWUqY+KSBKucGcWbL20y7xZ1Etiw/aVrFG1BTrsOcyFKcstYZxvX9Ux+ypWEC4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713866519; c=relaxed/simple; bh=F/9Yanst1hBH0HDc3LX9DP2jVFZb4lsc+NgoZKuU+jU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oNA803iXWQxwCb5k6Jl7Ve2SlM004+AYviTFsP0fMi35eGo3yu1CI2BnZ4FN78fxxWZ97/abQhZ7DX+SmLEP3fEHkuRg3BVuRPRSxAddCkWJrhDV4mRD9W2Ku8v0pAvBeVPSRB0DMF1XjRe1q/+knf1l294RVOvQSA3Zc2s1ulQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=eYViJkpo; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="eYViJkpo" Received: by mail.gandi.net (Postfix) with ESMTPSA id F07E41C0018; Tue, 23 Apr 2024 10:01:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1713866512; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0sXwCu/pnKjPhnbG0qZ+rGnft7Ztmr1z9mGamghTqGc=; b=eYViJkpo23dM3LsyVoZzOXw7uklJUF2oG+ntLMI9K7aDcOg5zfsfgqRsPbbfKvxGM0TQYr 6vbOyPXRAfC8Dj0I87/AKP6SK8V9HyBcvfITU3Fo4LNis7BTwLSu9qf3oCfM95W7PjzgQE xOVlZ4FVcRr5sx2f9QoFiMjMWTsxg1KIJUrUGaU+mc30F8/fJERj2+jnFUxa/EIIYNuF7b YzRH8UWmZzYeZZPBr19rzPTHeRiQ1bWDxG4/Kk52FMZ3EaL0UXKdLeSaadMad2+gQEc7Nn 6D5/M5lP1T+1MUYRZd3gLLMLUkHN9aQdT/G1Lzp+aIFJwVwjaFPk+JzO6nbRVw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Apr 2024 12:01:45 +0200 Subject: [PATCH v4 6/6] MIPS: mobileye: eyeq5: add octal flash node to eval board DTS Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240423-cdns-qspi-mbly-v4-6-3d2a7b535ad0@bootlin.com> References: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> In-Reply-To: <20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Add SPI-NOR octal flash node to evaluation board devicetree. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts index 6898b2d8267d..0e5fee7b680c 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts +++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts @@ -21,3 +21,18 @@ memory@0 { <0x8 0x02000000 0x0 0x7E000000>; }; }; + +&ospi { + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; /* chip select */ + + spi-max-frequency = <40000000>; + spi-rx-bus-width = <8>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <400>; + cdns,tsd2d-ns = <400>; + cdns,tchsh-ns = <125>; + cdns,tslch-ns = <50>; + }; +};