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Tue, 23 Apr 2024 19:13:35 +0300 From: George Stark To: , , , , , , , CC: , , , , , George Stark , Dmitry Rokosov Subject: [PATCH 1/1] arm64: dts: meson: a1: add definitions for meson pwm Date: Tue, 23 Apr 2024 19:13:27 +0300 Message-ID: <20240423161327.2522556-1-gnstark@salutedevices.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [100.64.160.123] X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 184882 [Apr 23 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: gnstark@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 18 0.3.18 b9d6ada76958f07c6a68617a7ac8df800bc4166c, {Tracking_uf_ne_domains}, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;100.64.160.123:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1;127.0.0.199:7.1.2;lore.kernel.org:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean, bases: 2024/04/23 15:16:00 X-KSMG-LinksScanning: Clean, bases: 2024/04/23 15:16:00 X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/04/23 04:11:00 #24934400 X-KSMG-AntiVirus-Status: Clean, skipped X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240423_091339_492502_9D69F435 X-CRM114-Status: GOOD ( 11.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: George Stark The chip has 3 dual channel PWM modules AB, CD, EF those can be connected to various digital I/O pins. Each of 6 PWM is driven by individually selected clock parent and 8-bit divider. The PWM signal is generated using two 16-bit counters. Signed-off-by: George Stark Signed-off-by: Dmitry Rokosov --- This patch depends on [1]. Links: [1] https://lore.kernel.org/linux-pwm/20240423161006.2522351-1-gnstark@salutedevices.com/T/#t arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 212 ++++++++++++++++++++++ 1 file changed, 212 insertions(+) -- 2.25.1 diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 6caeb97d6d3e..641180514bce 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -307,6 +307,188 @@ mux { }; }; + pwm_a_pins1: pwm-a-pins1 { + mux { + groups = "pwm_a_x6"; + function = "pwm_a"; + }; + }; + + pwm_a_pins2: pwm-a-pins2 { + mux { + groups = "pwm_a_x7"; + function = "pwm_a"; + }; + }; + + pwm_a_pins3: pwm-a-pins3 { + mux { + groups = "pwm_a_f10"; + function = "pwm_a"; + }; + }; + + pwm_a_pins4: pwm-a-pins4 { + mux { + groups = "pwm_a_f6"; + function = "pwm_a"; + }; + }; + + pwm_a_pins5: pwm-a-pins5 { + mux { + groups = "pwm_a_a"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm-b-pins1 { + mux { + groups = "pwm_b_x"; + function = "pwm_b"; + }; + }; + + pwm_b_pins2: pwm-b-pins2 { + mux { + groups = "pwm_b_f"; + function = "pwm_b"; + }; + }; + + pwm_b_pins3: pwm-b-pins3 { + mux { + groups = "pwm_b_a"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm-c-pins1 { + mux { + groups = "pwm_c_x"; + function = "pwm_c"; + }; + }; + + pwm_c_pins2: pwm-c-pins2 { + mux { + groups = "pwm_c_f3"; + function = "pwm_c"; + }; + }; + + pwm_c_pins3: pwm-c-pins3 { + mux { + groups = "pwm_c_f8"; + function = "pwm_c"; + }; + }; + + pwm_c_pins4: pwm-c-pins4 { + mux { + groups = "pwm_c_a"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm-d-pins1 { + mux { + groups = "pwm_d_x15"; + function = "pwm_d"; + }; + }; + + pwm_d_pins2: pwm-d-pins2 { + mux { + groups = "pwm_d_x13"; + function = "pwm_d"; + }; + }; + + pwm_d_pins3: pwm-d-pins3 { + mux { + groups = "pwm_d_x10"; + function = "pwm_d"; + }; + }; + + pwm_d_pins4: pwm-d-pins4 { + mux { + groups = "pwm_d_f"; + function = "pwm_d"; + }; + }; + + pwm_e_pins1: pwm-e-pins1 { + mux { + groups = "pwm_e_p"; + function = "pwm_e"; + }; + }; + + pwm_e_pins2: pwm-e-pins2 { + mux { + groups = "pwm_e_x16"; + function = "pwm_e"; + }; + }; + + pwm_e_pins3: pwm-e-pins3 { + mux { + groups = "pwm_e_x14"; + function = "pwm_e"; + }; + }; + + pwm_e_pins4: pwm-e-pins4 { + mux { + groups = "pwm_e_x2"; + function = "pwm_e"; + }; + }; + + pwm_e_pins5: pwm-e-pins5 { + mux { + groups = "pwm_e_f"; + function = "pwm_e"; + }; + }; + + pwm_e_pins6: pwm-e-pins6 { + mux { + groups = "pwm_e_a"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm-f-pins1 { + mux { + groups = "pwm_f_b"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm-f-pins2 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_f_pins3: pwm-f-pins3 { + mux { + groups = "pwm_f_f4"; + function = "pwm_f"; + }; + }; + + pwm_f_pins4: pwm-f-pins4 { + mux { + groups = "pwm_f_f12"; + function = "pwm_f"; + }; + }; + sdio_pins: sdio { mux0 { groups = "sdcard_d0_x", @@ -648,6 +830,26 @@ uart_AO_B: serial@2000 { status = "disabled"; }; + pwm_ab: pwm@2400 { + compatible = "amlogic,meson-a1-pwm"; + reg = <0x0 0x2400 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&clkc_periphs CLKID_PWM_A>, + <&clkc_periphs CLKID_PWM_B>; + power-domains = <&pwrc PWRC_I2C_ID>; + status = "disabled"; + }; + + pwm_cd: pwm@2800 { + compatible = "amlogic,meson-a1-pwm"; + reg = <0x0 0x2800 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&clkc_periphs CLKID_PWM_C>, + <&clkc_periphs CLKID_PWM_D>; + power-domains = <&pwrc PWRC_I2C_ID>; + status = "disabled"; + }; + saradc: adc@2c00 { compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; @@ -732,6 +934,16 @@ sec_AO: ao-secure@5a20 { amlogic,has-chip-id; }; + pwm_ef: pwm@5400 { + compatible = "amlogic,meson-a1-pwm"; + reg = <0x0 0x5400 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&clkc_periphs CLKID_PWM_E>, + <&clkc_periphs CLKID_PWM_F>; + power-domains = <&pwrc PWRC_I2C_ID>; + status = "disabled"; + }; + clkc_pll: pll-clock-controller@7c80 { compatible = "amlogic,a1-pll-clkc"; reg = <0 0x7c80 0 0x18c>;