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Miller" , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 16/71] crypto: x86/poly1305 - Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:58 -0700 Message-ID: <20240424181458.41462-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck --- arch/x86/crypto/poly1305_glue.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/crypto/poly1305_glue.c b/arch/x86/crypto/poly1305_glue.c index 1dfb8af48a3c..08ff4b489f7e 100644 --- a/arch/x86/crypto/poly1305_glue.c +++ b/arch/x86/crypto/poly1305_glue.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include asmlinkage void poly1305_init_x86_64(void *ctx, @@ -269,7 +269,7 @@ static int __init poly1305_simd_mod_init(void) boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_AVX512F) && cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM | XFEATURE_MASK_AVX512, NULL) && /* Skylake downclocks unacceptably much when using zmm, but later generations are fast. */ - boot_cpu_data.x86_model != INTEL_FAM6_SKYLAKE_X) + boot_cpu_data.x86_vfm != INTEL_SKYLAKE_X) static_branch_enable(&poly1305_use_avx512); return IS_REACHABLE(CONFIG_CRYPTO_HASH) ? crypto_register_shash(&alg) : 0; } From patchwork Wed Apr 24 18:14:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Luck X-Patchwork-Id: 13642303 X-Patchwork-Delegate: herbert@gondor.apana.org.au Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A92D3178CF1; Wed, 24 Apr 2024 18:15:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982513; cv=none; b=kbUi8Ltz8BhWdB+lpoVkxbJ0UDdbTnyLCPggx2KRJuTW5MhwokLCWbbkN1XgzedesL8D5DMjqR2AlgqWCclhwp6R8Xr6t9yB+AozmduJdMHApsbNshKAA6Jbu0YkaYACIVS71nAJCLf0fhIqn6jtt1IGPeMa4v7UBotbNvbuwuE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982513; c=relaxed/simple; bh=CwybUVe8crx1l4CZK03c9vCx8DvC8Bgt8uPcKdw9g+E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EVzH1jitA5Sh2gx09/HvH3daPjAfI7gBk/Ilpss1IwsFGWJoG6NEd2mDWmv8XS+O2AOZC0dX3Kt+xp1lji1pJbHrtAMpeEYIr5o6xztmwAzMoh4GugFzZWrP1cIgcv2xhKolnZitRUNY+vLJYQKSh7cMzMloqQ2jRoPTAClaKf8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bAAcl3uF; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bAAcl3uF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982511; x=1745518511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CwybUVe8crx1l4CZK03c9vCx8DvC8Bgt8uPcKdw9g+E=; b=bAAcl3uFqRB9u8Gf3IwmVVdlEML24vDkIZ2J+EnIUeNIIq7e3dq7Ssnp 9vXumMjUDrBdGa/HQIBK8QGs+DZ6R4lcnF+Zvtn61Jkr0ACKiyYChRNHJ WmGCHjXe0RHGaGqxfx61OuKJ5aOsUO6wImFJqOe/JOHcMw87vYu3eCzuN fFkMWL1X8euGoplAqtDb+ccVBoe/rkasHlcW6mlbpoBkpqtjdSMtPNKpK GiKyypZfilfBXyFK2/p/FvSEcZ3MQ1Dfo2iScVOVxGBinIdod3Qxw1qSL POPrseuLRSm+DB9nMfDsdweAP0ikM4WMhtQ67a8JCod4/K6wRzpFJG27n w==; X-CSE-ConnectionGUID: uHGqBQJ0SkOyduGKD8eHjA== X-CSE-MsgGUID: RZ+vYtXeQyKgftJTZUb8xA== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9481843" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9481843" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:59 -0700 X-CSE-ConnectionGUID: fIvJjhdlSqKYHN3AWZyHZg== X-CSE-MsgGUID: jJio6ahnToe8mAdZagIthw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262631" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:14:59 -0700 From: Tony Luck To: Borislav Petkov , Herbert Xu , "David S. Miller" , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: "H. Peter Anvin" , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 17/71] crypto: x86/twofish - Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:14:58 -0700 Message-ID: <20240424181458.41481-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck --- arch/x86/crypto/twofish_glue_3way.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/crypto/twofish_glue_3way.c b/arch/x86/crypto/twofish_glue_3way.c index 90454cf18e0d..82311249048f 100644 --- a/arch/x86/crypto/twofish_glue_3way.c +++ b/arch/x86/crypto/twofish_glue_3way.c @@ -12,6 +12,8 @@ #include #include +#include + #include "twofish.h" #include "ecb_cbc_helpers.h" @@ -107,10 +109,10 @@ static bool is_blacklisted_cpu(void) if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return false; - if (boot_cpu_data.x86 == 0x06 && - (boot_cpu_data.x86_model == 0x1c || - boot_cpu_data.x86_model == 0x26 || - boot_cpu_data.x86_model == 0x36)) { + switch (boot_cpu_data.x86_vfm) { + case INTEL_ATOM_BONNELL: + case INTEL_ATOM_BONNELL_MID: + case INTEL_ATOM_SALTWELL: /* * On Atom, twofish-3way is slower than original assembler * implementation. Twofish-3way trades off some performance in