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Thu, 25 Apr 2024 09:15:03 +0000 From: Niko Pasaloukos To: "robh@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "arnd@arndb.de" , "olof@lixom.net" , Niko Pasaloukos , Neil Jones , Matt Redfearn , James Cowgill , "heiko.stuebner@cherry.de" , "shawnguo@kernel.org" , "macromorgan@hotmail.com" , "sre@kernel.org" , "hvilleneuve@dimonoff.com" , "andre.przywara@arm.com" , "rafal@milecki.pl" , "linus.walleij@linaro.org" , "andersson@kernel.org" , "konrad.dybcio@linaro.org" , "geert+renesas@glider.be" , "neil.armstrong@linaro.org" , "m.szyprowski@samsung.com" , "nfraprado@collabora.com" , "u-kumar1@ti.com" CC: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH v3 1/5] dt-bindings: Add Blaize vendor prefix Thread-Topic: [PATCH v3 1/5] dt-bindings: Add Blaize vendor prefix Thread-Index: AQHalvEOV588QeieAEiOPEbJljZFTQ== Date: Thu, 25 Apr 2024 09:15:03 +0000 Message-ID: <20240425091403.17483-2-nikolaos.pasaloukos@blaize.com> References: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com> In-Reply-To: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MA0PR01MB10184:EE_|PN0PR01MB9905:EE_ x-ms-office365-filtering-correlation-id: 8c54136a-f5e9-46f3-e917-08dc650830e3 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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(www.blaize.com) is a SoC manufacturer with integrated programmable Graph-Streaming-Processors for AI and ML. Signed-off-by: Nikolaos Pasaloukos Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b97d298b3eb6..746ff14028d1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -214,6 +214,8 @@ patternProperties: description: Shenzhen BigTree Tech Co., LTD "^bitmain,.*": description: Bitmain Technologies + "^blaize,.*": + description: Blaize, Inc. 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Thu, 25 Apr 2024 09:15:04 +0000 From: Niko Pasaloukos To: "robh@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "arnd@arndb.de" , "olof@lixom.net" , Niko Pasaloukos , Neil Jones , Matt Redfearn , James Cowgill , "heiko.stuebner@cherry.de" , "shawnguo@kernel.org" , "macromorgan@hotmail.com" , "sre@kernel.org" , "hvilleneuve@dimonoff.com" , "andre.przywara@arm.com" , "rafal@milecki.pl" , "linus.walleij@linaro.org" , "andersson@kernel.org" , "konrad.dybcio@linaro.org" , "geert+renesas@glider.be" , "neil.armstrong@linaro.org" , "m.szyprowski@samsung.com" , "nfraprado@collabora.com" , "u-kumar1@ti.com" CC: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH v3 2/5] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC Thread-Topic: [PATCH v3 2/5] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC Thread-Index: AQHalvEO42bqaUXUz0uYtplzKtu8VA== Date: Thu, 25 Apr 2024 09:15:04 +0000 Message-ID: <20240425091403.17483-3-nikolaos.pasaloukos@blaize.com> References: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com> In-Reply-To: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MA0PR01MB10184:EE_|PN0PR01MB9905:EE_ x-ms-office365-filtering-correlation-id: 75d519ff-1813-4298-d989-08dc6508315f x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Reviewed-by: James Cowgill Reviewed-by: Matt Redfearn Reviewed-by: Neil Jones Signed-off-by: Nikolaos Pasaloukos --- .../devicetree/bindings/arm/blaize.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/blaize.yaml diff --git a/Documentation/devicetree/bindings/arm/blaize.yaml b/Documentation/devicetree/bindings/arm/blaize.yaml new file mode 100644 index 000000000000..8034aeb7a2b4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/blaize.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/blaize.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Blaize Platforms + +maintainers: + - James Cowgill + - Matt Redfearn + - Neil Jones + - Nikolaos Pasaloukos + +description: | + Blaize Platforms using SoCs designed by Blaize Inc. + + The products currently based on the BLZP1600 SoC: + + - BLZP1600-SoM: SoM module + - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM + + The compatible property should follow the format: + + compatible = "blaize,blzp1600-cb2", "blaize,blzp1600"; + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Blaize BLZP1600 based boards + items: + - enum: + - blaize,blzp1600-cb2 + - const: blaize,blzp1600 + +additionalProperties: true + +... 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Thu, 25 Apr 2024 09:15:04 +0000 From: Niko Pasaloukos To: "robh@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "arnd@arndb.de" , "olof@lixom.net" , Niko Pasaloukos , Neil Jones , Matt Redfearn , James Cowgill , "heiko.stuebner@cherry.de" , "shawnguo@kernel.org" , "macromorgan@hotmail.com" , "sre@kernel.org" , "hvilleneuve@dimonoff.com" , "andre.przywara@arm.com" , "rafal@milecki.pl" , "linus.walleij@linaro.org" , "andersson@kernel.org" , "konrad.dybcio@linaro.org" , "geert+renesas@glider.be" , "neil.armstrong@linaro.org" , "m.szyprowski@samsung.com" , "nfraprado@collabora.com" , "u-kumar1@ti.com" CC: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH v3 3/5] arm64: Add Blaize BLZP1600 SoC family Thread-Topic: [PATCH v3 3/5] arm64: Add Blaize BLZP1600 SoC family Thread-Index: AQHalvEPfozL11ntbUuuDRV40b2+fw== Date: Thu, 25 Apr 2024 09:15:04 +0000 Message-ID: <20240425091403.17483-4-nikolaos.pasaloukos@blaize.com> References: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com> In-Reply-To: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MA0PR01MB10184:EE_|PN0PR01MB9905:EE_ x-ms-office365-filtering-correlation-id: cea17869-9360-421f-ee6c-08dc650831cf x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Reviewed-by: James Cowgill Reviewed-by: Matt Redfearn Reviewed-by: Neil Jones Signed-off-by: Nikolaos Pasaloukos --- arch/arm64/Kconfig.platforms | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 24335565bad5..c2a523637b23 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -94,6 +94,11 @@ config ARCH_BITMAIN help This enables support for the Bitmain SoC Family. +config ARCH_BLAIZE_BLZP1600 + bool "Blaize BLZP1600 SoC Platforms" + help + This enables support for the Blaize BLZP1600 SoC family + config ARCH_EXYNOS bool "Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG From patchwork Thu Apr 25 09:15:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikolaos Pasaloukos X-Patchwork-Id: 13643017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F24EC19F53 for ; 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b=OXg2IbUuNOLOvMnoMX0IQ/OwDgpR13ttDqnGE7FPDXn/jxF3Il9qocwviSzNX8tJApr35wk0aaxz/h+bTjXzSmrz4Vi9ncgmLWxvX+u+kV20oN6mYxZ7gIzl+OGYdptBhYf/fKsGPjvKGuCsUPIZCKmRkJ8ALzX4X3Qx2pM0zQY= Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:12a::5) by PN0PR01MB9905.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:14c::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.46; Thu, 25 Apr 2024 09:15:06 +0000 Received: from MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655]) by MA0PR01MB10184.INDPRD01.PROD.OUTLOOK.COM ([fe80::309a:12cf:74a4:5655%3]) with mapi id 15.20.7472.044; Thu, 25 Apr 2024 09:15:05 +0000 From: Niko Pasaloukos To: "robh@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "arnd@arndb.de" , "olof@lixom.net" , Niko Pasaloukos , Neil Jones , Matt Redfearn , James Cowgill , "heiko.stuebner@cherry.de" , "shawnguo@kernel.org" , "macromorgan@hotmail.com" , "sre@kernel.org" , "hvilleneuve@dimonoff.com" , "andre.przywara@arm.com" , "rafal@milecki.pl" , "linus.walleij@linaro.org" , "andersson@kernel.org" , "konrad.dybcio@linaro.org" , "geert+renesas@glider.be" , "neil.armstrong@linaro.org" , "m.szyprowski@samsung.com" , "nfraprado@collabora.com" , "u-kumar1@ti.com" CC: "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2 Thread-Topic: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2 Thread-Index: AQHalvEPQKrAV9M0NkyhD59YDgTJ5Q== Date: Thu, 25 Apr 2024 09:15:05 +0000 Message-ID: <20240425091403.17483-5-nikolaos.pasaloukos@blaize.com> References: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com> In-Reply-To: <20240425091403.17483-1-nikolaos.pasaloukos@blaize.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MA0PR01MB10184:EE_|PN0PR01MB9905:EE_ x-ms-office365-filtering-correlation-id: 5730f823-d898-4668-7325-08dc65083255 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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This consists of a Carrier-Board-2 and a SoM. The blaize-blzp1600.dtsi is the common part for the SoC, blaize-blzp1600-som.dtsi is the common part for the SoM and blaize-blzp1600-cb2.dts is the board specific file. Co-developed-by: James Cowgill Signed-off-by: James Cowgill Co-developed-by: Matt Redfearn Signed-off-by: Matt Redfearn Co-developed-by: Neil Jones Signed-off-by: Neil Jones Signed-off-by: Nikolaos Pasaloukos --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/blaize/Makefile | 2 + .../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++ .../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++ .../boot/dts/blaize/blaize-blzp1600.dtsi | 209 ++++++++++++++++++ 5 files changed, 319 insertions(+) create mode 100644 arch/arm64/boot/dts/blaize/Makefile create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 30dd6347a929..601b6381ea0c 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y += apm subdir-y += apple subdir-y += arm subdir-y += bitmain +subdir-y += blaize subdir-y += broadcom subdir-y += cavium subdir-y += exynos diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blaize/Makefile new file mode 100644 index 000000000000..595e7a350300 --- /dev/null +++ b/arch/arm64/boot/dts/blaize/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BLAIZE_BLZP1600) += blaize-blzp1600-cb2.dtb diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts new file mode 100644 index 000000000000..0bdec7e81380 --- /dev/null +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Blaize, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "blaize-blzp1600-som.dtsi" +#include + +/ { + model = "Blaize BLZP1600 SoM1600P CB2 Development Board"; + + compatible = "blaize,blzp1600-cb2", "blaize,blzp1600"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200"; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + status = "okay"; + + gpio_expander: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "RSP_PIN_7", /* GPIO_0 */ + "RSP_PIN_11", /* GPIO_1 */ + "RSP_PIN_13", /* GPIO_2 */ + "RSP_PIN_15", /* GPIO_3 */ + "RSP_PIN_27", /* GPIO_4 */ + "RSP_PIN_29", /* GPIO_5 */ + "RSP_PIN_31", /* GPIO_6 */ + "RSP_PIN_33", /* GPIO_7 */ + "RSP_PIN_37", /* GPIO_8 */ + "RSP_PIN_16", /* GPIO_9 */ + "RSP_PIN_18", /* GPIO_10 */ + "RSP_PIN_22", /* GPIO_11 */ + "RSP_PIN_28", /* GPIO_12 */ + "RSP_PIN_32", /* GPIO_13 */ + "RSP_PIN_36", /* GPIO_14 */ + "TP31"; /* GPIO_15 */ + }; + + gpio_expander_m2: gpio@75 { + compatible = "ti,tca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */ + "M2_W_DIS2_N", /* GPIO_1 */ + "M2_UART_WAKE_N", /* GPIO_2 */ + "M2_COEX3", /* GPIO_3 */ + "M2_COEX_RXD", /* GPIO_4 */ + "M2_COEX_TXD", /* GPIO_5 */ + "M2_VENDOR_PIN40", /* GPIO_6 */ + "M2_VENDOR_PIN42", /* GPIO_7 */ + "M2_VENDOR_PIN38", /* GPIO_8 */ + "M2_SDIO_RST_N", /* GPIO_9 */ + "M2_SDIO_WAKE_N", /* GPIO_10 */ + "M2_PETN1", /* GPIO_11 */ + "M2_PERP1", /* GPIO_12 */ + "M2_PERN1", /* GPIO_13 */ + "UIM_SWP", /* GPIO_14 */ + "UART1_TO_RSP"; /* GPIO_15 */ + }; +}; diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi new file mode 100644 index 000000000000..efac0d6b3d60 --- /dev/null +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Blaize, Inc. All rights reserved. + */ + +#include "blaize-blzp1600.dtsi" + +/ { + memory@1000 { + device_type = "memory"; + reg = <0x0 0x00001000 0xfffff000>; + }; +}; + +/* i2c4 bus is available only on the SoM, not on the board */ +&i2c4 { + clock-frequency = <100000>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi new file mode 100644 index 000000000000..26d8943d60ab --- /dev/null +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Blaize, Inc. All rights reserved. + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = /* Physical Secure PPI */ + , + /* Physical Non-Secure PPI */ + , + /* Hypervisor PPI */ + , + /* Virtual PPI */ + ; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + sram@0 { + /* + * On BLZP1600 there is no general purpose (non-secure) SRAM. + * A small DDR memory space has been reserved for general use. + */ + compatible = "mmio-sram"; + reg = <0x0 0x00000000 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x00000000 0x1000>; + + /* SCMI reserved buffer space on DDR space */ + scmi0_shm: scmi-sram@800 { + compatible = "arm,scmi-shmem"; + reg = <0x800 0x80>; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82002000>; + #address-cells = <1>; + #size-cells = <0>; + + shmem = <&scmi0_shm>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@200410000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x2 0x00410000 0x20000>, + <0x2 0x00420000 0x20000>, + <0x2 0x00440000 0x20000>, + <0x2 0x00460000 0x20000>; + interrupts = ; + }; + + uart0: serial@2004d0000 { + compatible = "ns16550a"; + reg = <0x2 0x004d0000 0x1000>; + clocks = <&scmi_clk 59>; + resets = <&scmi_rst 59>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + uart1: serial@2004e0000 { + compatible = "ns16550a"; + reg = <0x2 0x004e0000 0x1000>; + clocks = <&scmi_clk 60>; + resets = <&scmi_rst 60>; + reg-shift = <2>; + interrupts = ; + status = "disabled"; + }; + + i2c0: i2c@2004f0000 { + compatible = "snps,designware-i2c"; + reg = <0x2 0x004f0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk 54>; + resets = <&scmi_rst 54>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@200500000 { + compatible = "snps,designware-i2c"; + reg = <0x2 0x00500000 0x1000>; + interrupts = ; + clocks = <&scmi_clk 55>; + resets = <&scmi_rst 55>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@200510000 { + compatible = "snps,designware-i2c"; + reg = <0x2 0x00510000 0x1000>; + interrupts = ; + clocks = <&scmi_clk 56>; + resets = <&scmi_rst 56>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@200520000 { + compatible = "snps,designware-i2c"; + reg = <0x2 0x00520000 0x1000>; + interrupts = ; + clocks = <&scmi_clk 57>; + resets = <&scmi_rst 57>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@200530000 { + compatible = "snps,designware-i2c"; + reg = <0x2 0x00530000 0x1000>; + interrupts = ; + clocks = <&scmi_clk 58>; + resets = <&scmi_rst 58>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + arm_cc712: crypto@200550000 { + compatible = "arm,cryptocell-712-ree"; + reg = <0x2 0x00550000 0x1000>; + interrupts = ; + clocks = <&scmi_clk 7>; + }; + }; +}; From patchwork Thu Apr 25 09:15:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikolaos Pasaloukos X-Patchwork-Id: 13643015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A530C4345F for ; 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Signed-off-by: Nikolaos Pasaloukos --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..7d368a8911bf 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -43,6 +43,7 @@ CONFIG_ARCH_BCM_IPROC=y CONFIG_ARCH_BCMBCA=y CONFIG_ARCH_BRCMSTB=y CONFIG_ARCH_BERLIN=y +CONFIG_ARCH_BLAIZE_BLZP1600=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_SPARX5=y CONFIG_ARCH_K3=y