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Fri, 26 Apr 2024 05:27:40 -0700 From: Jon Hunter To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Thierry Reding CC: Vidya Sagar , , , Jon Hunter , "Manikanta Maddireddy" Subject: [PATCH] PCI: tegra194: Set address alignment for endpoint mode Date: Fri, 26 Apr 2024 13:27:31 +0100 Message-ID: <20240426122731.42499-1-jonathanh@nvidia.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C9:EE_|SA1PR12MB7038:EE_ X-MS-Office365-Filtering-Correlation-Id: 543f33ab-b157-423f-a332-08dc65ec537b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|82310400014|36860700004|1800799015; X-Microsoft-Antispam-Message-Info: w/dGcr5wktF1BKfLq+vV76j0Lv2iOn0xEOOi7Ln+CWSpM3Dxuutq6tqz0tsvn6gKzJ8mmC2yHavF5QqenIcgo1blsFqrhNmrcWK3DO52nJwd+oiKOkJ+BhzfZo5w+PhXramogSIFjPxFnmhvNgQNKffXfXWzO6hWXXdCq6bcyDuIvW5ZzqvRhXRBgcZSzET0aWNx5bLbO9TKOP51LHN14ZfbA2c690+eSJ/Dxy070NwAjMRA1DYL0nsaQwAnZfhsljjgKeGZ3mzTp+ZP+VV80z6jDNd0hMHECjZ64r2EL5uqWDPzRZ3sTAvk5E6dURZ/2f+TICxqlzx0hZcwQ4dDngJ6GhYJx4JwfuASxlpx2l6xMPxGl1r0uivOPoo+Rcx1uARD+wnjXeNOZvvwO/8WOqt2T9ikmkY+xQ85nS2cmGlGWtqW0rCH3g5Zls2YdH4Jn6ERMAoEnaq3poVAPjE1QrZjbTf6IvrSEJJooxS3dJxuSEHh6Xuy9fkgvt0bX2n6XDndh/UcnS+kTHj8HQyjEt1hwzIHaXzS7wiz4RB9kcFUUBW/earnqy1T/s3uc5SRb8zAFfaRO+D8Qz79BsrcnATCXlcjFio/Xh9bzU8vowhCLpSmASn+BobGyC1htIsWwvZy0xg54c7tFfn+jCgf2eGoH5LdLoS1Jrgu1kozMaPlwzdSLvZgR7gRQ7AsV9B1WrFnKc7MXQHv1CrbaMWd9X4Xfq81ntTgDWWbZ0BKQ4nSW0dmhDgbm5k9bGqyBPF8NDM2R04hzx+wosyg8NXi22/XLdjJWE0z+XT8WZZBKjqQnmybbGOfMz3E7aQgZNdb7DcocG97/ppiyj0MHaHFe7wJnRq/pZVB+f5K6YAZ60s/0UXP3it8BDW7xBlXb7pUv8f0nFxDoAGLRjdUcs8qiYzwTDjfoisbie9LMvQrUpe1RmEBIHyBrdchWYfqjWcbiuBBTSLfSOnHFA59HE59B2T9iDkkelTirs2JiMEGhAshaQllnpiT3tSBNtjxwpkA0vpVrr64++sDMNXV+E3p2jaaXTWesWWyK3MYAIvEGaZaKpp2HqmR5pFWW8LvEsT20tsc/TFzKq2RQVRpL3oaKzcG+kxzh/IS7P7bWAqB1Ai9bmHg0x+LHVI8rtDkeIwdBOxflJyks3TIf7K2l2lQnjIZafmAZ7Ypgzliedch1gGBhoYz0tDeU3Nf9kyHnF0hKTZHlp3H/JoYcep+tyAo958mxI6w+Ft68jXuWfUmn/kXUF4plzyuXKL7dnqPpa6VeuoqPPoLjAgfa5vOsKtA/hVc1/uYV01jgQXM8GqH8zK2qRKYlTwD3wHCnbQ3cC6kUZ6kUI5u5n1UtCQyY5g59xL7Ex+YKquV0zxlF+60XYF+hukHDdF3sCd4UiYHno2p X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(82310400014)(36860700004)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2024 12:28:06.5504 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 543f33ab-b157-423f-a332-08dc65ec537b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7038 Tegra194 and Tegra234 devices require that the endpoint address is aligned on a 64kB boundary and therefore, set the endpoint address alignment to 64kB in the Tegra194 PCIe driver. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Suggested-by: Manikanta Maddireddy Signed-off-by: Jon Hunter --- drivers/pci/controller/dwc/pcie-tegra194.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 93f5433c5c55..4537313ef37a 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2015,6 +2015,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = { .bar[BAR_3] = { .type = BAR_RESERVED, }, .bar[BAR_4] = { .type = BAR_RESERVED, }, .bar[BAR_5] = { .type = BAR_RESERVED, }, + .align = SZ_64K, }; static const struct pci_epc_features*