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Similarly to other ADIS1650X devices, ADIS16501 supports sync-mode values [0,2]. Signed-off-by: Ramona Gradinariu Acked-by: Conor Dooley --- Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml index 9b7ad609f7db..db52e7063116 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml @@ -30,6 +30,7 @@ properties: - adi,adis16467-2 - adi,adis16467-3 - adi,adis16500 + - adi,adis16501 - adi,adis16505-1 - adi,adis16505-2 - adi,adis16505-3 @@ -90,6 +91,7 @@ allOf: contains: enum: - adi,adis16500 + - adi,adis16501 - adi,adis16505-1 - adi,adis16505-2 - adi,adis16505-3 From patchwork Fri Apr 26 13:53:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramona Gradinariu X-Patchwork-Id: 13644827 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 980EF148315; Fri, 26 Apr 2024 13:53:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714139631; cv=none; b=VS4S5IgxNLDeb/brDJWTwiC+GfltOVZguW2CSWsOtJ6/OpUiJXmDlPnKS/a6yvpn9HZzpkOSlvqWKPRpQIEx1claGIoUmvr21Pq116vzhKlpVmCWotjOvPyE5q5nCxsoxxOiKg9H9h/wPFS3qjJcguWJR3tjzPfdwnf62MEOZv0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714139631; c=relaxed/simple; bh=1QGay2Hfl/jmLzw9AMlc080b/HzXD5PzQDCQZR5eI9Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OpRVBvjRPnbSQ07mEGcwjASCdqVhInPABOmwTZ/P9HQ9m+DXTjzNX8OSoBoR97W8fh0PFrL7fHtfcqLP2E0WZY65XwncPcMhMoB7/juMmvJCLH6epZJHPoKLABFktvytXF5lnFK61qll5+8/boTov3Xo5MvdNumJ3Ic4YqogY7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=i0iGB8wx; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="i0iGB8wx" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-41b9dff6be8so2908585e9.3; Fri, 26 Apr 2024 06:53:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714139628; x=1714744428; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XNj7uanEHO11oDZAHjwfACtzLhB1XMhzYg/IGylKoL4=; b=i0iGB8wxATsCokO+JpuYwp2ixFnQT82eCZyrRwPufWW0tyWp6h2RBGi7yr6ZouCQKt u2c4X+HVKjypV8YVzXByAHrha3U/BKkT8tiJwNnFiX2CYPjMsnIYAdsLnS9F3VzjZiYr BoUdr/1a1GurXuJpRvAG40Fik1VC2vN6YDxpUEBP6h2RKJ9ilA96Hj0KmfEazIi4Ytzw 972lFgzPTR4AZICNzUNIgc5//LG5huHf4cEqE26RDyf0nbeOR/qD/EOENvhvOZecxGQb w1bY1xGWLMIX+Ifo2zRvtnOFxfracfZ8LaG7L021xiFpTt+ZZ1+RvmXs5PZoiMlHpmxn 5+TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714139628; x=1714744428; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XNj7uanEHO11oDZAHjwfACtzLhB1XMhzYg/IGylKoL4=; b=kYxaa6vb7zw+h9eip6Lwuk7APcZU9W63sWK+z+PybitJdPdoCYXHkFD1gOqwlzh9AU yeljG46vuLMWLN8waYsi/TXpU4kbnY3pIR0F3N37Bpr1nMMEwYEh2mY++5LPEmwQfB/e g3dWAFQfgXSWjJpHS+4ixGEtQ3RDM4DMDXWiZWbT3uuQcGA0bVYU4JUqo21F0R6pjPJq JHU4/sHXI4/tbNGzIRjxwBTpsv4qQmyxGu3PvJ/qidlHP9pk16VSFQBo3/BlwAz5Ad81 KTXWrnhKVIfBXC5G5wUqyibx+/fr7vk54smBvjLvJlXneyT4vjUpwZnPFUKy9TEUj6Ys X2/Q== X-Forwarded-Encrypted: i=1; AJvYcCUg/LAS198Q9iOoITCmdarRMfZ/QiiN/nXwTBaFOHF8d+X40t2YiQ8VJu0gFHFNVsuM562dqA1E7bT/dLDjUqfD9tmDcbf7IjK03ygxIP5bQ05LI+w/NRQx6Wes46GeSpQFfzauXQ== X-Gm-Message-State: AOJu0Yx3RI+ZyNKtEN8DcZNhBqZXm7eEuYvm6juZnNER5bQIDufovKXw Coj4jR+0uKprAQAdKsgx6/zx4PO+TeTGqtk1ZzKNnBOeUaGqOp8pbmlOQY6E X-Google-Smtp-Source: AGHT+IHpsfxWro17MY42FzMYbH+MNJFNyyR2QQv3DjBIFhw14wIz1XHnyUsFQX07TDEAjCa3naQVDw== X-Received: by 2002:a05:600c:4587:b0:418:4851:a08a with SMTP id r7-20020a05600c458700b004184851a08amr2229989wmo.37.1714139627792; Fri, 26 Apr 2024 06:53:47 -0700 (PDT) Received: from rbolboac.. ([2a02:2f0e:320d:e800:f4f8:b5e1:d7d4:bf65]) by smtp.gmail.com with ESMTPSA id k6-20020a5d6d46000000b003434f526cb5sm22302919wri.95.2024.04.26.06.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 06:53:47 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH 2/7] drivers: iio: imu: Add support for ADIS16501 Date: Fri, 26 Apr 2024 16:53:34 +0300 Message-Id: <20240426135339.185602-3-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> References: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for ADIS16501 device in already existing ADIS16475 driver. Signed-off-by: Ramona Gradinariu --- drivers/iio/imu/Kconfig | 4 ++-- drivers/iio/imu/adis16475.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/iio/imu/Kconfig b/drivers/iio/imu/Kconfig index 52a155ff3250..782fb80e44c2 100644 --- a/drivers/iio/imu/Kconfig +++ b/drivers/iio/imu/Kconfig @@ -36,8 +36,8 @@ config ADIS16475 select IIO_ADIS_LIB_BUFFER if IIO_BUFFER help Say yes here to build support for Analog Devices ADIS16470, ADIS16475, - ADIS16477, ADIS16465, ADIS16467, ADIS16500, ADIS16505, ADIS16507 inertial - sensors. + ADIS16477, ADIS16465, ADIS16467, ADIS16500, ADIS16501, ADIS16505, + ADIS16507 inertial sensors. To compile this driver as a module, choose M here: the module will be called adis16475. diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index 01f55cc902fa..7fab40daa659 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -661,6 +661,7 @@ enum adis16475_variant { ADIS16467_2, ADIS16467_3, ADIS16500, + ADIS16501, ADIS16505_1, ADIS16505_2, ADIS16505_3, @@ -980,6 +981,25 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts), }, + [ADIS16501] = { + .name = "adis16501", + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 1, + .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), + .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(720), + .deltvel_max_val = 125, + .int_clk = 2000, + .max_dec = 1999, + .sync = adis16475_sync_mode, + /* pulse sync not supported */ + .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, + .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, + .adis_data = ADIS16475_DATA(16501, &adis1650x_timeouts), + }, [ADIS16505_1] = { .name = "adis16505-1", .num_channels = ARRAY_SIZE(adis16477_channels), @@ -1482,6 +1502,8 @@ static const struct of_device_id adis16475_of_match[] = { .data = &adis16475_chip_info[ADIS16467_3] }, { .compatible = "adi,adis16500", .data = &adis16475_chip_info[ADIS16500] }, + { .compatible = "adi,adis16501", + .data = &adis16475_chip_info[ADIS16501] }, { .compatible = "adi,adis16505-1", .data = &adis16475_chip_info[ADIS16505_1] }, { .compatible = "adi,adis16505-2", From patchwork Fri Apr 26 13:53:35 2024 Content-Type: text/plain; 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([2a02:2f0e:320d:e800:f4f8:b5e1:d7d4:bf65]) by smtp.gmail.com with ESMTPSA id k6-20020a5d6d46000000b003434f526cb5sm22302919wri.95.2024.04.26.06.53.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 06:53:48 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH 3/7] iio: imu: adis16475: Re-define ADIS16475_DATA Date: Fri, 26 Apr 2024 16:53:35 +0300 Message-Id: <20240426135339.185602-4-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> References: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Re-define ADIS16475_DATA such that it takes _burst_max_len and _burst_max_speed_hz as parameters. Signed-off-by: Ramona Gradinariu --- drivers/iio/imu/adis16475.c | 136 +++++++++++++++++++++++------------- 1 file changed, 89 insertions(+), 47 deletions(-) diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index 7fab40daa659..52333772fbe0 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -690,32 +690,32 @@ static const char * const adis16475_status_error_msgs[] = { [ADIS16475_DIAG_STAT_CLK] = "Clock error", }; -#define ADIS16475_DATA(_prod_id, _timeouts) \ -{ \ - .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \ - .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \ - .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \ - .prod_id_reg = ADIS16475_REG_PROD_ID, \ - .prod_id = (_prod_id), \ - .self_test_mask = BIT(2), \ - .self_test_reg = ADIS16475_REG_GLOB_CMD, \ - .cs_change_delay = 16, \ - .read_delay = 5, \ - .write_delay = 5, \ - .status_error_msgs = adis16475_status_error_msgs, \ - .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ - BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ - BIT(ADIS16475_DIAG_STAT_SPI) | \ - BIT(ADIS16475_DIAG_STAT_STANDBY) | \ - BIT(ADIS16475_DIAG_STAT_SENSOR) | \ - BIT(ADIS16475_DIAG_STAT_MEMORY) | \ - BIT(ADIS16475_DIAG_STAT_CLK), \ - .unmasked_drdy = true, \ - .timeouts = (_timeouts), \ - .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \ - .burst_len = ADIS16475_BURST_MAX_DATA, \ - .burst_max_len = ADIS16475_BURST32_MAX_DATA, \ - .burst_max_speed_hz = ADIS16475_BURST_MAX_SPEED \ +#define ADIS16475_DATA(_prod_id, _timeouts, _burst_max_len, _burst_max_speed_hz) \ +{ \ + .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \ + .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \ + .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \ + .prod_id_reg = ADIS16475_REG_PROD_ID, \ + .prod_id = (_prod_id), \ + .self_test_mask = BIT(2), \ + .self_test_reg = ADIS16475_REG_GLOB_CMD, \ + .cs_change_delay = 16, \ + .read_delay = 5, \ + .write_delay = 5, \ + .status_error_msgs = adis16475_status_error_msgs, \ + .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ + BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ + BIT(ADIS16475_DIAG_STAT_SPI) | \ + BIT(ADIS16475_DIAG_STAT_STANDBY) | \ + BIT(ADIS16475_DIAG_STAT_SENSOR) | \ + BIT(ADIS16475_DIAG_STAT_MEMORY) | \ + BIT(ADIS16475_DIAG_STAT_CLK), \ + .unmasked_drdy = true, \ + .timeouts = (_timeouts), \ + .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \ + .burst_len = ADIS16475_BURST_MAX_DATA, \ + .burst_max_len = _burst_max_len, \ + .burst_max_speed_hz = _burst_max_speed_hz \ } static const struct adis16475_sync adis16475_sync_mode[] = { @@ -753,7 +753,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16475_1] = { .name = "adis16475-1", @@ -770,7 +772,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16475_2] = { .name = "adis16475-2", @@ -787,7 +791,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16475_3] = { .name = "adis16475-3", @@ -804,7 +810,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16477_1] = { .name = "adis16477-1", @@ -822,7 +830,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16477_2] = { .name = "adis16477-2", @@ -840,7 +850,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16477_3] = { .name = "adis16477-3", @@ -858,7 +870,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16465_1] = { .name = "adis16465-1", @@ -875,7 +889,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16465_2] = { .name = "adis16465-2", @@ -892,7 +908,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16465_3] = { .name = "adis16465-3", @@ -909,7 +927,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16467_1] = { .name = "adis16467-1", @@ -926,7 +946,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16467_2] = { .name = "adis16467-2", @@ -943,7 +965,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16467_3] = { .name = "adis16467-3", @@ -960,7 +984,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), - .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts), + .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16500] = { .name = "adis16500", @@ -979,7 +1005,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts), + .adis_data = ADIS16475_DATA(16500, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16501] = { .name = "adis16501", @@ -998,7 +1026,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16501, &adis1650x_timeouts), + .adis_data = ADIS16475_DATA(16501, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16505_1] = { .name = "adis16505-1", @@ -1017,7 +1047,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), + .adis_data = ADIS16475_DATA(16505, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16505_2] = { .name = "adis16505-2", @@ -1036,7 +1068,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), + .adis_data = ADIS16475_DATA(16505, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16505_3] = { .name = "adis16505-3", @@ -1055,7 +1089,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts), + .adis_data = ADIS16475_DATA(16505, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16507_1] = { .name = "adis16507-1", @@ -1074,7 +1110,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), + .adis_data = ADIS16475_DATA(16507, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16507_2] = { .name = "adis16507-2", @@ -1093,7 +1131,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), + .adis_data = ADIS16475_DATA(16507, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, [ADIS16507_3] = { .name = "adis16507-3", @@ -1112,7 +1152,9 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { /* pulse sync not supported */ .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, - .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts), + .adis_data = ADIS16475_DATA(16507, &adis16475_timeouts, + ADIS16475_BURST32_MAX_DATA, + ADIS16475_BURST_MAX_SPEED), }, }; From patchwork Fri Apr 26 13:53:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramona Gradinariu X-Patchwork-Id: 13644829 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 459E1148850; Fri, 26 Apr 2024 13:53:52 +0000 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([2a02:2f0e:320d:e800:f4f8:b5e1:d7d4:bf65]) by smtp.gmail.com with ESMTPSA id k6-20020a5d6d46000000b003434f526cb5sm22302919wri.95.2024.04.26.06.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 06:53:49 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH 4/7] iio: imu: adis_buffer: Add buffer setup API with buffer attributes Date: Fri, 26 Apr 2024 16:53:36 +0300 Message-Id: <20240426135339.185602-5-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> References: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add new API called devm_adis_setup_buffer_and_trigger_with_attrs() which also takes buffer attributes as a parameter. Rewrite devm_adis_setup_buffer_and_trigger() implementation such that it calls devm_adis_setup_buffer_and_trigger_with_attrs() with buffer attributes parameter NULL Signed-off-by: Ramona Gradinariu --- drivers/iio/imu/adis_buffer.c | 32 ++++++++++++++++++-------------- include/linux/iio/imu/adis.h | 18 ++++++++++++++---- 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/iio/imu/adis_buffer.c b/drivers/iio/imu/adis_buffer.c index 928933027ae3..b6c0d8690070 100644 --- a/drivers/iio/imu/adis_buffer.c +++ b/drivers/iio/imu/adis_buffer.c @@ -175,31 +175,36 @@ static void adis_buffer_cleanup(void *arg) } /** - * devm_adis_setup_buffer_and_trigger() - Sets up buffer and trigger for - * the managed adis device + * devm_adis_setup_buffer_and_trigger_with_attrs() - Sets up buffer and trigger + * for the managed adis device with buffer attributes. * @adis: The adis device * @indio_dev: The IIO device - * @trigger_handler: Optional trigger handler, may be NULL. + * @trigger_handler: Trigger handler: should handle the buffer readings. + * @ops: Optional buffer setup functions, may be NULL. + * @buffer_attrs: Extra buffer attributes. * * Returns 0 on success, a negative error code otherwise. * - * This function sets up the buffer and trigger for a adis devices. If - * 'trigger_handler' is NULL the default trigger handler will be used. The - * default trigger handler will simply read the registers assigned to the - * currently active channels. + * This function sets up the buffer (with buffer setup functions and extra + * buffer attributes) and trigger for a adis devices with buffer attributes. */ int -devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev, - irq_handler_t trigger_handler) +devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis, struct iio_dev *indio_dev, + irq_handler_t trigger_handler, + const struct iio_buffer_setup_ops *ops, + const struct attribute **buffer_attrs) { int ret; if (!trigger_handler) trigger_handler = adis_trigger_handler; - ret = devm_iio_triggered_buffer_setup(&adis->spi->dev, indio_dev, - &iio_pollfunc_store_time, - trigger_handler, NULL); + ret = devm_iio_triggered_buffer_setup_ext(&adis->spi->dev, indio_dev, + &iio_pollfunc_store_time, + trigger_handler, + IIO_BUFFER_DIRECTION_IN, + ops, + buffer_attrs); if (ret) return ret; @@ -212,5 +217,4 @@ devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev, return devm_add_action_or_reset(&adis->spi->dev, adis_buffer_cleanup, adis); } -EXPORT_SYMBOL_NS_GPL(devm_adis_setup_buffer_and_trigger, IIO_ADISLIB); - +EXPORT_SYMBOL_NS_GPL(devm_adis_setup_buffer_and_trigger_with_attrs, IIO_ADISLIB); diff --git a/include/linux/iio/imu/adis.h b/include/linux/iio/imu/adis.h index 8898966bc0f0..20978374527f 100644 --- a/include/linux/iio/imu/adis.h +++ b/include/linux/iio/imu/adis.h @@ -515,11 +515,19 @@ int adis_single_conversion(struct iio_dev *indio_dev, #define ADIS_ROT_CHAN(mod, addr, si, info_sep, info_all, bits) \ ADIS_MOD_CHAN(IIO_ROT, mod, addr, si, info_sep, info_all, bits) +#define devm_adis_setup_buffer_and_trigger(adis, indio_dev, trigger_handler) \ + devm_adis_setup_buffer_and_trigger_with_attrs((adis), (indio_dev), \ + (trigger_handler), NULL, \ + NULL) + #ifdef CONFIG_IIO_ADIS_LIB_BUFFER int -devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev, - irq_handler_t trigger_handler); +devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis, + struct iio_dev *indio_dev, + irq_handler_t trigger_handler, + const struct iio_buffer_setup_ops *ops, + const struct attribute **buffer_attrs); int devm_adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev); @@ -529,8 +537,10 @@ int adis_update_scan_mode(struct iio_dev *indio_dev, #else /* CONFIG_IIO_BUFFER */ static inline int -devm_adis_setup_buffer_and_trigger(struct adis *adis, struct iio_dev *indio_dev, - irq_handler_t trigger_handler) +devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis, struct iio_dev *indio_dev, + irq_handler_t trigger_handler, + const struct iio_buffer_setup_ops *ops, + const struct attribute **buffer_attrs) { return 0; } From patchwork Fri Apr 26 13:53:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramona Gradinariu X-Patchwork-Id: 13644830 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FB22148FF1; Fri, 26 Apr 2024 13:53:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([2a02:2f0e:320d:e800:f4f8:b5e1:d7d4:bf65]) by smtp.gmail.com with ESMTPSA id k6-20020a5d6d46000000b003434f526cb5sm22302919wri.95.2024.04.26.06.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 06:53:50 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH 5/7] iio: imu: adis16475: Create push single sample API Date: Fri, 26 Apr 2024 16:53:37 +0300 Message-Id: <20240426135339.185602-6-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> References: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Create push single sample API reposnsible for pushing a single sample into the buffer. This is a preparation patch for FIFO support where more than one sample has to be pushed in the trigger handler. Signed-off-by: Ramona Gradinariu --- drivers/iio/imu/adis16475.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index 52333772fbe0..7cfef553f298 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -1249,9 +1249,8 @@ static void adis16475_burst32_check(struct adis16475 *st) } } -static irqreturn_t adis16475_trigger_handler(int irq, void *p) +static int adis16475_push_single_sample(struct iio_poll_func *pf) { - struct iio_poll_func *pf = p; struct iio_dev *indio_dev = pf->indio_dev; struct adis16475 *st = iio_priv(indio_dev); struct adis *adis = &st->adis; @@ -1340,6 +1339,15 @@ static irqreturn_t adis16475_trigger_handler(int irq, void *p) * array. */ adis16475_burst32_check(st); + return ret; +} + +static irqreturn_t adis16475_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + + adis16475_push_single_sample(pf); iio_trigger_notify_done(indio_dev->trig); return IRQ_HANDLED; From patchwork Fri Apr 26 13:53:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramona Gradinariu X-Patchwork-Id: 13644831 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CDB1149009; Fri, 26 Apr 2024 13:53:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714139636; cv=none; b=MSXTA/WRNac1wSHaoqIxU2IQYBkmhz/6gM49yGsFEjpb0t4vnWe1p+SXW4uTGf8ctcoZw49eC1N9H+fbFcM4sl/tzOBevXOdCs99GDbKVnNozvTUaT/82jGdNwxnRX449C69KB6ffxaM5F7+Owfl+fKXDFRgKKfgaQd8MhUCmwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714139636; c=relaxed/simple; bh=m2yxV5B405RCZQld4AIwLovxgEUSP5z4fMOhlaEf9yI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lcVCk27ZmhOYDmU6IGplrOlAD7Fkt1jZo+dajTE1TWFWcHvD7gL82RpsuN1WuzhqakxOkOI9heM64RvXSPxrKCIV0+CvX/Gjp6GZES4+vHZoXqJduueNxfFS2JglPYfgOfqybTX90BQ9TvPIXbUpNQsUa2gNURBjm3RjW/UT2iE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jEFbLxFP; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jEFbLxFP" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-34c1fff534fso1271433f8f.1; Fri, 26 Apr 2024 06:53:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714139632; x=1714744432; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bLJ9dsSLK+nY8Hvlsn/3+HI9I2fOpNl7ItjLv5mlK7A=; b=jEFbLxFPPNK9n//JdjmUmawgJ3EzZeK07I1BtlvsTvp9NGZakL678XKzbgZ4HrpA+w T4VrPVzPAM6kLlYqbxMBvgcTh0XxwfISpXu6rFnrJ2vbPuD77iXdMtpiu+lHstftJF1d Sq8nm1Kp7bwHQIpYtCijzHiRvKqAxURq7af55zeg/OPxEpurQe/kxfzdMJXhMjN4fy9Z qcxlZIZKjIrYDurIlYfK0vF55MHaPZj9ZAnmdsbOuwclxzTdmNVyqDm4EB2BeuJFcqfB u5ZJv07NekG4Zj7k9QDcC/qGMMLYei8mnNr6NANOIZxS4UZFH4qjj63AYtWQg/Q3cAZo zpYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714139632; x=1714744432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bLJ9dsSLK+nY8Hvlsn/3+HI9I2fOpNl7ItjLv5mlK7A=; b=Vc8dQPnNHCZCEntGhd8ovJ4ZBlvUfm0QZRKhjamrRKCLNpwGVEDfvZIRHYXJufotVQ rPgNbqICn9TgnzCmbxev1th4FDQ4jYBxDQBf/1kG/2/PmB+DkKfhonNyynQW4BaT7vSD ZG1S7mZi4LrkbikP4Ox6QZufFeXq6NDkbVztC9C51VAaIQZ1JeoEXzLWeV5T+1pBPs7u RbssIFeaUBfNJa0PoDwy25La5XOAj7aLwlF88Ne8pSvBD4IA4fBQKza9wfZmuHH5KsA+ ZXtnS58NNlnW0/PY/QQOgaXcG5v/c3GW6wq4HxYy44fvAVoQZS+Pu3SBJA5WESomlBay 2QnA== X-Forwarded-Encrypted: i=1; AJvYcCVy9LiYpWh54ZYtBKjqsTfFqVLL0ecXXnulVtryWQaVgzkAIsK6ymH13cwTCBhMMDxWvyO3LIQ89GMWF3CoI7JJbLh6FdHErqngrRkzuT4Bb0EUKQKRoQn9c/k5fSuecNm9toMOlg== X-Gm-Message-State: AOJu0Yz/29HBrRASGH2eBQTT/N3UqBooYpDcmbhy6gw2QGNW+chcTIHP S3x2zVWfRcpPtfoVAwA8DJcBllOqiAf6phEF4xdLI/UjKb0wKi9tLnahYuZs X-Google-Smtp-Source: AGHT+IHEms0dC8ezv3c4Amk0JUZhJpSMYgKLuKKM9jXiTHegW2/Lhl7B/LSPhkV3pnb3KFmE0A3q9w== X-Received: by 2002:a5d:4386:0:b0:34b:8bf:6019 with SMTP id i6-20020a5d4386000000b0034b08bf6019mr1733253wrq.70.1714139632252; Fri, 26 Apr 2024 06:53:52 -0700 (PDT) Received: from rbolboac.. ([2a02:2f0e:320d:e800:f4f8:b5e1:d7d4:bf65]) by smtp.gmail.com with ESMTPSA id k6-20020a5d6d46000000b003434f526cb5sm22302919wri.95.2024.04.26.06.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 06:53:51 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH 6/7] dt-bindings: iio: imu: Add ADIS1657X family devices compatibles Date: Fri, 26 Apr 2024 16:53:38 +0300 Message-Id: <20240426135339.185602-7-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> References: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add ADIS1657X family devices compatibles and specify the according maximum SPI baudrate. Similarly to other ADIS1650X devices, ADIS1657X supports sync-mode values [0,2]. Signed-off-by: Ramona Gradinariu --- .../bindings/iio/imu/adi,adis16475.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml index db52e7063116..9d185f7bfdcb 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml @@ -37,6 +37,12 @@ properties: - adi,adis16507-1 - adi,adis16507-2 - adi,adis16507-3 + - adi,adis16575-2 + - adi,adis16575-3 + - adi,adis16576-2 + - adi,adis16576-3 + - adi,adis16577-2 + - adi,adis16577-3 reg: maxItems: 1 @@ -98,6 +104,12 @@ allOf: - adi,adis16507-1 - adi,adis16507-2 - adi,adis16507-3 + - adi,adis16575-2 + - adi,adis16575-3 + - adi,adis16576-2 + - adi,adis16576-3 + - adi,adis16577-2 + - adi,adis16577-3 then: properties: @@ -114,6 +126,23 @@ allOf: dependencies: adi,sync-mode: [ clocks ] + - if: + properties: + compatible: + contains: + enum: + - adi,adis16575-2 + - adi,adis16575-3 + - adi,adis16576-2 + - adi,adis16576-3 + - adi,adis16577-2 + - adi,adis16577-3 + + then: + properties: + spi-max-frequency: + maximum: 15000000 + unevaluatedProperties: false examples: From patchwork Fri Apr 26 13:53:39 2024 Content-Type: text/plain; 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([2a02:2f0e:320d:e800:f4f8:b5e1:d7d4:bf65]) by smtp.gmail.com with ESMTPSA id k6-20020a5d6d46000000b003434f526cb5sm22302919wri.95.2024.04.26.06.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 06:53:53 -0700 (PDT) From: Ramona Gradinariu To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, nuno.sa@analog.com Cc: Ramona Gradinariu Subject: [PATCH 7/7] drivers: iio: imu: Add support for adis1657x family Date: Fri, 26 Apr 2024 16:53:39 +0300 Message-Id: <20240426135339.185602-8-ramona.bolboaca13@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> References: <20240426135339.185602-1-ramona.bolboaca13@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for ADIS1657X family devices in already exiting ADIS16475 driver. Signed-off-by: Ramona Gradinariu --- drivers/iio/imu/adis16475.c | 536 +++++++++++++++++++++++++++++++++--- 1 file changed, 499 insertions(+), 37 deletions(-) diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index 7cfef553f298..c759ec456258 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,8 @@ FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x) #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2) #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x) +#define ADIS16475_SYNC_4KHZ_MASK BIT(11) +#define ADIS16475_SYNC_4KHZ(x) FIELD_PREP(ADIS16475_SYNC_4KHZ_MASK, x) #define ADIS16475_REG_UP_SCALE 0x62 #define ADIS16475_REG_DEC_RATE 0x64 #define ADIS16475_REG_GLOB_CMD 0x68 @@ -66,14 +69,31 @@ #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) /* number of data elements in burst mode */ #define ADIS16475_BURST32_MAX_DATA 32 +#define ADIS16575_BURST32_MAX_DATA 34 #define ADIS16475_BURST_MAX_DATA 20 #define ADIS16475_MAX_SCAN_DATA 20 /* spi max speed in brust mode */ #define ADIS16475_BURST_MAX_SPEED 1000000 +#define ADIS16575_BURST_MAX_SPEED 8000000 #define ADIS16475_LSB_DEC_MASK 0 #define ADIS16475_LSB_FIR_MASK 1 #define ADIS16500_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0) #define ADIS16500_BURST_DATA_SEL_1_CHN_MASK GENMASK(12, 7) +#define ADIS16475_MAX_FIFO_WM 511 +#define ADIS16475_REG_FIFO_CTRL 0x5A +#define ADIS16475_WM_LVL_MASK GENMASK(15, 4) +#define ADIS16475_WM_LVL(x) FIELD_PREP(ADIS16475_WM_LVL_MASK, x) +#define ADIS16475_WM_POL_MASK BIT(3) +#define ADIS16475_WM_POL(x) FIELD_PREP(ADIS16475_WM_POL_MASK, x) +#define ADIS16475_WM_EN_MASK BIT(2) +#define ADIS16475_WM_EN(x) FIELD_PREP(ADIS16475_WM_EN_MASK, x) +#define ADIS16475_OVERFLOW_MASK BIT(1) +#define ADIS16475_STOP_ENQUEUE FIELD_PREP(ADIS16475_OVERFLOW_MASK, 0) +#define ADIS16475_OVERWRITE_OLDEST FIELD_PREP(ADIS16475_OVERFLOW_MASK, 1) +#define ADIS16475_FIFO_EN_MASK BIT(0) +#define ADIS16475_FIFO_EN(x) FIELD_PREP(ADIS16475_FIFO_EN_MASK, x) +#define ADIS16475_FIFO_FLUSH_CMD BIT(5) +#define ADIS16475_REG_FIFO_CNT 0x3C enum { ADIS16475_SYNC_DIRECT = 1, @@ -95,6 +115,9 @@ struct adis16475_chip_info { const char *name; #define ADIS16475_HAS_BURST32 BIT(0) #define ADIS16475_HAS_BURST_DELTA_DATA BIT(1) +#define ADIS16475_HAS_TIMESTAMP32 BIT(2) +#define ADIS16475_NEEDS_BURST_REQUEST BIT(3) +#define ADIS16475_HAS_FIFO BIT(4) const long flags; u32 num_channels; u32 gyro_max_val; @@ -116,6 +139,7 @@ struct adis16475 { bool burst32; unsigned long lsb_flag; u16 sync_mode; + u16 fifo_watermark; /* Alignment needed for the timestamp */ __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8); }; @@ -310,6 +334,9 @@ static int adis16475_set_freq(struct adis16475 *st, const u32 freq) u16 dec; int ret; u32 sample_rate = st->clk_freq; + /* The optimal sample rate for the supported IMUs is between int_clk - 100 and int_clk + 100. */ + u32 max_sample_rate = st->info->int_clk * 1000 + 100000; + u32 min_sample_rate = st->info->int_clk * 1000 - 100000; if (!freq) return -EINVAL; @@ -317,8 +344,9 @@ static int adis16475_set_freq(struct adis16475 *st, const u32 freq) adis_dev_lock(&st->adis); /* * When using sync scaled mode, the input clock needs to be scaled so that we have - * an IMU sample rate between (optimally) 1900 and 2100. After this, we can use the - * decimation filter to lower the sampling rate in order to get what the user wants. + * an IMU sample rate between (optimally) int_clk - 100 and int_clk + 100. + * After this, we can use the decimation filter to lower the sampling rate in order + * to get what the user wants. * Optimally, the user sample rate is a multiple of both the IMU sample rate and * the input clock. Hence, calculating the sync_scale dynamically gives us better * chances of achieving a perfect/integer value for DEC_RATE. The math here is: @@ -336,23 +364,25 @@ static int adis16475_set_freq(struct adis16475 *st, const u32 freq) * solution. In this case, we get the highest multiple of the input clock * lower than the IMU max sample rate. */ - if (scaled_rate > 2100000) - scaled_rate = 2100000 / st->clk_freq * st->clk_freq; + if (scaled_rate > max_sample_rate) + scaled_rate = max_sample_rate / st->clk_freq * st->clk_freq; + else - scaled_rate = 2100000 / scaled_rate * scaled_rate; + scaled_rate = max_sample_rate / scaled_rate * scaled_rate; /* * This is not an hard requirement but it's not advised to run the IMU - * with a sample rate lower than 1900Hz due to possible undersampling - * issues. However, there are users that might really want to take the risk. - * Hence, we provide a module parameter for them. If set, we allow sample - * rates lower than 1.9KHz. By default, we won't allow this and we just roundup - * the rate to the next multiple of the input clock bigger than 1.9KHz. This - * is done like this as in some cases (when DEC_RATE is 0) might give - * us the closest value to the one desired by the user... + * with a sample rate lower than internal clock frequency, due to possible + * undersampling issues. However, there are users that might really want + * to take the risk. Hence, we provide a module parameter for them. If set, + * we allow sample rates lower than internal clock frequency. + * By default, we won't allow this and we just roundup the rate to the next + * multiple of the input clock. This is done like this as in some cases + * (when DEC_RATE is 0) might give us the closest value to the one desired + * by the user... */ - if (scaled_rate < 1900000 && !low_rate_allow) - scaled_rate = roundup(1900000, st->clk_freq); + if (scaled_rate < min_sample_rate && !low_rate_allow) + scaled_rate = roundup(min_sample_rate, st->clk_freq); sync_scale = scaled_rate / st->clk_freq; ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, sync_scale); @@ -437,6 +467,130 @@ static int adis16475_set_filter(struct adis16475 *st, const u32 filter) return 0; } +static ssize_t adis16475_get_fifo_enabled(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct adis16475 *st = iio_priv(indio_dev); + int ret; + u16 val; + + ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val); + if (ret) + return ret; + val = FIELD_GET(ADIS16475_FIFO_EN_MASK, val); + + return sysfs_emit(buf, "%d\n", val); +} + +static ssize_t adis16475_get_fifo_watermark(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct adis16475 *st = iio_priv(indio_dev); + + int ret; + u16 val; + + ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val); + if (ret) + return ret; + val = FIELD_GET(ADIS16475_WM_LVL_MASK, val) + 1; + + return sysfs_emit(buf, "%d\n", val); +} + +static ssize_t hwfifo_watermark_min_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sysfs_emit(buf, "%s\n", "1"); +} + +static ssize_t hwfifo_watermark_max_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sysfs_emit(buf, "%s\n", __stringify(ADIS16475_MAX_FIFO_WM)); +} + +static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); +static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); +static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, + adis16475_get_fifo_watermark, NULL, 0); +static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, + adis16475_get_fifo_enabled, NULL, 0); + +static const struct attribute *adis16475_fifo_attributes[] = { + &iio_dev_attr_hwfifo_watermark_min.dev_attr.attr, + &iio_dev_attr_hwfifo_watermark_max.dev_attr.attr, + &iio_dev_attr_hwfifo_watermark.dev_attr.attr, + &iio_dev_attr_hwfifo_enabled.dev_attr.attr, + NULL, +}; + +static int adis16475_buffer_postenable(struct iio_dev *indio_dev) +{ + struct adis16475 *st = iio_priv(indio_dev); + struct adis *adis = &st->adis; + u16 val; + + val = ADIS16475_FIFO_EN(1); + return adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL, ADIS16475_FIFO_EN_MASK, val); +} + +static int adis16475_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct adis16475 *st = iio_priv(indio_dev); + struct adis *adis = &st->adis; + int ret; + u16 val; + + adis_dev_lock(&st->adis); + + val = ADIS16475_FIFO_EN(0); + ret = __adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL, ADIS16475_FIFO_EN_MASK, val); + if (ret) + goto unlock; + + ret = __adis_write_reg_16(adis, ADIS16475_REG_GLOB_CMD, + ADIS16475_FIFO_FLUSH_CMD); + +unlock: + adis_dev_unlock(&st->adis); + return ret; +} + +static const struct iio_buffer_setup_ops adis16475_buffer_ops = { + .postenable = adis16475_buffer_postenable, + .postdisable = adis16475_buffer_postdisable, +}; + +static int adis16475_set_watermark(struct iio_dev *indio_dev, unsigned int val) +{ + struct adis16475 *st = iio_priv(indio_dev); + int ret; + u16 wm_lvl; + + adis_dev_lock(&st->adis); + + if (val > ADIS16475_MAX_FIFO_WM) + val = ADIS16475_MAX_FIFO_WM; + + wm_lvl = ADIS16475_WM_LVL(val - 1); + ret = __adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, ADIS16475_WM_LVL_MASK, wm_lvl); + if (ret) + goto unlock; + + st->fifo_watermark = val; + +unlock: + adis_dev_unlock(&st->adis); + return ret; +} + static const u32 adis16475_calib_regs[] = { [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L, [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L, @@ -668,6 +822,12 @@ enum adis16475_variant { ADIS16507_1, ADIS16507_2, ADIS16507_3, + ADIS16575_2, + ADIS16575_3, + ADIS16576_2, + ADIS16576_3, + ADIS16577_2, + ADIS16577_3, }; enum { @@ -725,6 +885,12 @@ static const struct adis16475_sync adis16475_sync_mode[] = { { ADIS16475_SYNC_PULSE, 1000, 2100 }, }; +static const struct adis16475_sync adis16575_sync_mode[] = { + { ADIS16475_SYNC_OUTPUT }, + { ADIS16475_SYNC_DIRECT, 1900, 4100 }, + { ADIS16475_SYNC_SCALED, 1, 400 }, +}; + static const struct adis_timeout adis16475_timeouts = { .reset_ms = 200, .sw_reset_ms = 200, @@ -1156,6 +1322,150 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { ADIS16475_BURST32_MAX_DATA, ADIS16475_BURST_MAX_SPEED), }, + [ADIS16575_2] = { + .name = "adis16575-2", + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 8, + .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), + .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(450), + .deltvel_max_val = 100, + .int_clk = 4000, + .max_dec = 3999, + .sync = adis16575_sync_mode, + .num_sync = ARRAY_SIZE(adis16575_sync_mode), + .flags = ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data = ADIS16475_DATA(16575, &adis16475_timeouts, + ADIS16575_BURST32_MAX_DATA, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16575_3] = { + .name = "adis16575-3", + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 8, + .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), + .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2000), + .deltvel_max_val = 100, + .int_clk = 4000, + .max_dec = 3999, + .sync = adis16575_sync_mode, + .num_sync = ARRAY_SIZE(adis16575_sync_mode), + .flags = ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data = ADIS16475_DATA(16575, &adis16475_timeouts, + ADIS16575_BURST32_MAX_DATA, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16576_2] = { + .name = "adis16576-2", + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 40, + .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), + .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(450), + .deltvel_max_val = 125, + .int_clk = 4000, + .max_dec = 3999, + .sync = adis16575_sync_mode, + .num_sync = ARRAY_SIZE(adis16575_sync_mode), + .flags = ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data = ADIS16475_DATA(16576, &adis16475_timeouts, + ADIS16575_BURST32_MAX_DATA, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16576_3] = { + .name = "adis16576-3", + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 40, + .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), + .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2000), + .deltvel_max_val = 125, + .int_clk = 4000, + .max_dec = 3999, + .sync = adis16575_sync_mode, + .num_sync = ARRAY_SIZE(adis16575_sync_mode), + .flags = ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data = ADIS16475_DATA(16576, &adis16475_timeouts, + ADIS16575_BURST32_MAX_DATA, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16577_2] = { + .name = "adis16577-2", + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), + .accel_max_val = 40, + .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), + .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(450), + .deltvel_max_val = 400, + .int_clk = 4000, + .max_dec = 3999, + .sync = adis16575_sync_mode, + .num_sync = ARRAY_SIZE(adis16575_sync_mode), + .flags = ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data = ADIS16475_DATA(16577, &adis16475_timeouts, + ADIS16575_BURST32_MAX_DATA, + ADIS16575_BURST_MAX_SPEED), + }, + [ADIS16577_3] = { + .name = "adis16577-3", + .num_channels = ARRAY_SIZE(adis16477_channels), + .channels = adis16477_channels, + .gyro_max_val = 1, + .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), + .accel_max_val = 40, + .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), + .temp_scale = 100, + .deltang_max_val = IIO_DEGREE_TO_RAD(2000), + .deltvel_max_val = 400, + .int_clk = 4000, + .max_dec = 3999, + .sync = adis16575_sync_mode, + .num_sync = ARRAY_SIZE(adis16575_sync_mode), + .flags = ADIS16475_HAS_BURST32 | + ADIS16475_HAS_BURST_DELTA_DATA | + ADIS16475_NEEDS_BURST_REQUEST | + ADIS16475_HAS_TIMESTAMP32 | + ADIS16475_HAS_FIFO, + .adis_data = ADIS16475_DATA(16577, &adis16475_timeouts, + ADIS16575_BURST32_MAX_DATA, + ADIS16575_BURST_MAX_SPEED), + }, }; static int adis16475_update_scan_mode(struct iio_dev *indio_dev, @@ -1188,17 +1498,14 @@ static const struct iio_info adis16475_info = { .write_raw = &adis16475_write_raw, .update_scan_mode = adis16475_update_scan_mode, .debugfs_reg_access = adis_debugfs_reg_access, + .hwfifo_set_watermark = adis16475_set_watermark, }; static bool adis16475_validate_crc(const u8 *buffer, u16 crc, - const bool burst32) + u16 burst_size, u16 start_idx) { int i; - /* extra 6 elements for low gyro and accel */ - const u16 sz = burst32 ? ADIS16475_BURST32_MAX_DATA : - ADIS16475_BURST_MAX_DATA; - - for (i = 0; i < sz - 2; i++) + for (i = start_idx; i < burst_size - 2; i++) crc -= buffer[i]; return crc == 0; @@ -1226,8 +1533,11 @@ static void adis16475_burst32_check(struct adis16475 *st) * In 32-bit mode we need extra 2 bytes for all gyro * and accel channels. */ - adis->burst_extra_len = 6 * sizeof(u16); - adis->xfer[1].len += 6 * sizeof(u16); + adis->burst_extra_len = (6 + !!(st->info->flags & ADIS16475_HAS_TIMESTAMP32)) * + sizeof(u16); + adis->xfer[1].len += (6 + !!(st->info->flags & ADIS16475_HAS_TIMESTAMP32)) * + sizeof(u16); + dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d", adis->xfer[1].len); @@ -1243,7 +1553,8 @@ static void adis16475_burst32_check(struct adis16475 *st) /* Remove the extra bits */ adis->burst_extra_len = 0; - adis->xfer[1].len -= 6 * sizeof(u16); + adis->xfer[1].len -= (6 + !!(st->info->flags & ADIS16475_HAS_TIMESTAMP32)) * + sizeof(u16); dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n", adis->xfer[1].len); } @@ -1258,20 +1569,31 @@ static int adis16475_push_single_sample(struct iio_poll_func *pf) __be16 *buffer; u16 crc; bool valid; + u8 crc_offset = 9; + u16 burst_size = ADIS16475_BURST_MAX_DATA; + u16 start_idx = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 2 : 0; + /* offset until the first element after gyro and accel */ const u8 offset = st->burst32 ? 13 : 7; + if (st->burst32) { + crc_offset = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 16 : 15; + burst_size = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? + ADIS16575_BURST32_MAX_DATA : ADIS16475_BURST32_MAX_DATA; + } + ret = spi_sync(adis->spi, &adis->msg); if (ret) - goto check_burst32; + return ret; buffer = adis->buffer; - crc = be16_to_cpu(buffer[offset + 2]); - valid = adis16475_validate_crc(adis->buffer, crc, st->burst32); + crc = be16_to_cpu(buffer[crc_offset]); + valid = adis16475_validate_crc(adis->buffer, crc, burst_size, start_idx); + if (!valid) { dev_err(&adis->spi->dev, "Invalid crc\n"); - goto check_burst32; + return ret; } for_each_set_bit(bit, indio_dev->active_scan_mask, @@ -1332,22 +1654,111 @@ static int adis16475_push_single_sample(struct iio_poll_func *pf) } iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); -check_burst32: + + return 0; +} + +static irqreturn_t adis16475_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct adis16475 *st = iio_priv(indio_dev); + + adis16475_push_single_sample(pf); /* * We only check the burst mode at the end of the current capture since * it takes a full data ready cycle for the device to update the burst * array. */ adis16475_burst32_check(st); - return ret; + + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; } -static irqreturn_t adis16475_trigger_handler(int irq, void *p) +static int adis16575_custom_burst_read(struct iio_poll_func *pf, u8 burst_req) +{ + struct iio_dev *indio_dev = pf->indio_dev; + struct adis16475 *st = iio_priv(indio_dev); + struct adis *adis = &st->adis; + unsigned int burst_length, burst_max_length; + u8 *tx; + + burst_length = adis->data->burst_len + adis->burst_extra_len; + + if (adis->data->burst_max_len) + burst_max_length = adis->data->burst_max_len; + else + burst_max_length = burst_length; + + tx = adis->buffer + burst_max_length; + tx[0] = ADIS_READ_REG(burst_req); + + if (burst_req) + return spi_sync(adis->spi, &adis->msg); + + return adis16475_push_single_sample(pf); +} + +/* + * This handler is meant to be used for devices which support burst readings + * from FIFO (namely devices from adis1657x family). + * In order to pop the FIFO the 0x68 0x00 FIFO pop burst request has to be sent. + * If the previous device command was not a FIFO pop burst request, the FIFO pop + * burst request will simply pop the FIFO without returning valid data. + * For the nth consecutive burst request, the + * device will send the data popped with the (n-1)th consecutive burst request. + * In order to read the data which was popped previously, without popping the FIFO, + * the 0x00 0x00 burst request has to be sent. + * If after a 0x68 0x00 FIFO pop burst request, there is any other device access + * different from a 0x68 0x00 or a 0x00 0x00 burst request, the FIFO data popped + * previously will be lost. + */ +static irqreturn_t adis16475_trigger_handler_with_fifo(int irq, void *p) { struct iio_poll_func *pf = p; struct iio_dev *indio_dev = pf->indio_dev; + struct adis16475 *st = iio_priv(indio_dev); + struct adis *adis = &st->adis; + int ret; + u16 fifo_cnt, i; - adis16475_push_single_sample(pf); + adis_dev_lock(&st->adis); + + ret = __adis_read_reg_16(adis, ADIS16475_REG_FIFO_CNT, &fifo_cnt); + if (ret || fifo_cnt < 2) + goto unlock; + + if (fifo_cnt > st->fifo_watermark) + fifo_cnt = st->fifo_watermark; + + /* + * First burst request - FIFO pop: popped data will be returned in the + * next burst request. + */ + ret = adis16575_custom_burst_read(pf, adis->data->burst_reg_cmd); + if (ret) + goto unlock; + + for (i = 0; i < fifo_cnt - 1; i++) { + ret = adis16475_push_single_sample(pf); + if (ret) + goto unlock; + } + + /* FIFO read without popping */ + ret = adis16575_custom_burst_read(pf, 0); + if (ret) + goto unlock; + +unlock: + /* + * We only check the burst mode at the end of the current capture since + * reading data from registers will impact the FIFO reading. + */ + adis16475_burst32_check(st); + adis_dev_unlock(&st->adis); iio_trigger_notify_done(indio_dev->trig); return IRQ_HANDLED; @@ -1359,6 +1770,17 @@ static int adis16475_config_sync_mode(struct adis16475 *st) struct device *dev = &st->adis.spi->dev; const struct adis16475_sync *sync; u32 sync_mode; + u16 max_sample_rate = st->info->int_clk + 100; + u16 val; + + /* if available, enable 4khz internal clock */ + if (st->info->int_clk == 4000) { + val = ADIS16475_SYNC_4KHZ(1); + ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, + ADIS16475_SYNC_4KHZ_MASK, val); + if (ret) + return ret; + } /* default to internal clk */ st->clk_freq = st->info->int_clk * 1000; @@ -1398,10 +1820,9 @@ static int adis16475_config_sync_mode(struct adis16475 *st) /* * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale. * Hence, default the IMU sample rate to the highest multiple of the input - * clock lower than the IMU max sample rate. The optimal range is - * 1900-2100 sps... + * clock lower than the IMU max sample rate. */ - up_scale = 2100 / st->clk_freq; + up_scale = max_sample_rate / st->clk_freq; ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, @@ -1467,7 +1888,23 @@ static int adis16475_config_irq_pin(struct adis16475 *st) */ usleep_range(250, 260); - return 0; + /* + * If the device has FIFO support, configure the watermark polarity + * pin as well. + */ + if (st->info->flags & ADIS16475_HAS_FIFO) { + val = ADIS16475_WM_POL(polarity); + ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, + ADIS16475_WM_POL_MASK, val); + if (ret) + return ret; + + /* Enable watermark interrupt pin. */ + val = ADIS16475_WM_EN(1); + ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, ADIS16475_WM_EN_MASK, val); + } + + return ret; } @@ -1509,8 +1946,21 @@ static int adis16475_probe(struct spi_device *spi) if (ret) return ret; - ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, - adis16475_trigger_handler); + if (st->info->flags & ADIS16475_HAS_FIFO) { + ret = devm_adis_setup_buffer_and_trigger_with_attrs(&st->adis, indio_dev, + adis16475_trigger_handler_with_fifo, + &adis16475_buffer_ops, + adis16475_fifo_attributes); + if (ret) + return ret; + /* Update overflow behavior to always overwrite the oldest sample. */ + u16 val = ADIS16475_OVERWRITE_OLDEST; + + ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, ADIS16475_OVERFLOW_MASK, val); + } else { + ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, + adis16475_trigger_handler); + } if (ret) return ret; @@ -1566,6 +2016,18 @@ static const struct of_device_id adis16475_of_match[] = { .data = &adis16475_chip_info[ADIS16507_2] }, { .compatible = "adi,adis16507-3", .data = &adis16475_chip_info[ADIS16507_3] }, + { .compatible = "adi,adis16575-2", + .data = &adis16475_chip_info[ADIS16575_2] }, + { .compatible = "adi,adis16575-3", + .data = &adis16475_chip_info[ADIS16575_3] }, + { .compatible = "adi,adis16576-2", + .data = &adis16475_chip_info[ADIS16576_2] }, + { .compatible = "adi,adis16576-3", + .data = &adis16475_chip_info[ADIS16576_3] }, + { .compatible = "adi,adis16577-2", + .data = &adis16475_chip_info[ADIS16577_2] }, + { .compatible = "adi,adis16577-3", + .data = &adis16475_chip_info[ADIS16577_3] }, { }, }; MODULE_DEVICE_TABLE(of, adis16475_of_match);