From patchwork Fri Apr 26 19:51:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Schofield X-Patchwork-Id: 13645321 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DCF9BA45 for ; Fri, 26 Apr 2024 19:51:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714161074; cv=none; b=mlkkfNmvPBfI4A+P43QOC9a/urYFMrMd3d88C/pbLeUkLxwjxhKeQV4JIq84cr6japGAJZ/UGQURRiCaAjJiXtoLH6VY7msMH5kWI8Vvwno3uYmjON+PuiqFu/Re1SJtp5p1xsCJavNamK0tKwL22a3ZzXpRnthVUqBO5oBL0mk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714161074; c=relaxed/simple; bh=Z6AozJvzQquOQrKyvNyJ6ejPuesKHeFe4Y2EadNYO2g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=okmo0xgM3eK0Fbi1RuXjxq49XQW10p8vhmthI+C0MIKSzSR7dcOnWl1CyR/x7QasY6gOoe5WV3wmtT+qHyEVscLuvZk36V14ACJNo8me+0HvtbfI7ix4OsRW7MHWthUG0fHu4nQjwcO7T/Wnqt2oRXXc8Z+9GmOicP+d7Alm27I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=m0+eQ7oh; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="m0+eQ7oh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714161072; x=1745697072; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z6AozJvzQquOQrKyvNyJ6ejPuesKHeFe4Y2EadNYO2g=; b=m0+eQ7oh3p9e6VhGViauMTXBUrvGz3WC4jgIKsIEe1W1ltUcscHhG32e aoBUL13bn5R1FauyIaAlLhZApyK2JWpcSDS+ymG/aan/iRGktxc9eLj4E tkKOewRBuJgLN2QJkQIsipKBp2l8O0Q9GQBswWNqBV2uj0f35y9lmDJ4G RNfLqMO99TyAlpzhMC+D0z2J6eptEn6XrCnuOn48A1N5JAU/S7IAnwON5 zLgahEHR0qNzueN8lPfdVeLd85pHLsH9RTctH5aPlavH7c+rbH8hbkCxQ Q+LwFS9Wg344gPK1UANZs6YVsJ51l5TPoxxQC+XvBhbsQkpIVcJG4MQAi w==; X-CSE-ConnectionGUID: O8UDEGi2R1aXuQEQe7x72Q== X-CSE-MsgGUID: 3dJBsplXQwWNkaBoCpNZpA== X-IronPort-AV: E=McAfee;i="6600,9927,11056"; a="10067040" X-IronPort-AV: E=Sophos;i="6.07,233,1708416000"; d="scan'208";a="10067040" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 12:51:11 -0700 X-CSE-ConnectionGUID: 9qUsQKPqT36EGcabf0oMBw== X-CSE-MsgGUID: VBT2SybwS++/HFXlfc4ZOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,233,1708416000"; d="scan'208";a="56432092" Received: from aschofie-mobl2.amr.corp.intel.com (HELO localhost) ([10.212.224.120]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 12:51:11 -0700 From: alison.schofield@intel.com To: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams Cc: linux-cxl@vger.kernel.org Subject: [PATCH 1/3] cxl/acpi: Restore XOR'd position bits during address translation Date: Fri, 26 Apr 2024 12:51:05 -0700 Message-Id: X-Mailer: git-send-email 2.40.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Alison Schofield When a CXL region is created in a CXL Window (CFMWS) that uses XOR interleave arithmetic XOR maps are applied during the HPA->DPA translation. The XOR function changes the interleave selector bit (aka position bit) in the HPA thereby varying which host bridge services an HPA. The purpose is to minimize hot spots thereby improving performance. When a device reports a DPA in events such as poison, general_media, and dram, the driver translates that DPA back to an HPA. Presently, the CXL driver translation only considers the modulo position and will report the wrong HPA for XOR configured CFMWS's. Add a helper function that restores the XOR'd bits during DPA->HPA address translation. Plumb a root decoder callback to the new helper when XOR interleave arithmetic is in use. For MODULO arithmetic, just let the callback be NULL - as in no extra work required. Fixes: 28a3ae4ff66c ("cxl/trace: Add an HPA to cxl_poison trace events") Signed-off-by: Alison Schofield --- drivers/cxl/acpi.c | 49 +++++++++++++++++++++++++++++++++++++--- drivers/cxl/core/port.c | 5 +++- drivers/cxl/core/trace.c | 5 ++++ drivers/cxl/cxl.h | 6 ++++- 4 files changed, 60 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index af5cb818f84d..519e933b5a4b 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -74,6 +74,44 @@ static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos) return cxlrd->cxlsd.target[n]; } +static u64 restore_xor_pos(u64 hpa, u64 map) +{ + int restore_value, restore_pos = 0; + + /* + * Restore the position bit to its value before the + * xormap was applied at HPA->DPA translation. + * + * restore_pos is the lowest set bit in the map + * restore_value is the XORALLBITS in (hpa AND map) + */ + + while ((map & (1ULL << restore_pos)) == 0) + restore_pos++; + + restore_value = (hweight64(hpa & map) & 1); + if (restore_value) + hpa |= (1ULL << restore_pos); + else + hpa &= ~(1ULL << restore_pos); + + return hpa; +} + +static u64 cxl_xor_trans(struct cxl_root_decoder *cxlrd, u64 hpa, int iw) +{ + struct cxl_cxims_data *cximsd = cxlrd->platform_data; + + /* No xormaps for ways of 1 or 3 */ + if (iw == 1 || iw == 3) + return hpa; + + for (int i = 0; i < cximsd->nr_maps; i++) + hpa = restore_xor_pos(hpa, cximsd->xormaps[i]); + + return hpa; +} + struct cxl_cxims_context { struct device *dev; struct cxl_root_decoder *cxlrd; @@ -325,6 +363,7 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws, struct cxl_cxims_context cxims_ctx; struct cxl_root_decoder *cxlrd; struct device *dev = ctx->dev; + cxl_addr_trans_fn addr_trans; cxl_calc_hb_fn cxl_calc_hb; struct cxl_decoder *cxld; unsigned int ways, i, ig; @@ -365,12 +404,16 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws, if (rc) goto err_insert; - if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) + if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { cxl_calc_hb = cxl_hb_modulo; - else + addr_trans = NULL; + + } else { cxl_calc_hb = cxl_hb_xor; + addr_trans = cxl_xor_trans; + } - cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb); + cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb, addr_trans); if (IS_ERR(cxlrd)) return PTR_ERR(cxlrd); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 2b0cab556072..cd4f004f5372 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1808,6 +1808,7 @@ static int cxl_switch_decoder_init(struct cxl_port *port, * @port: owning CXL root of this decoder * @nr_targets: static number of downstream targets * @calc_hb: which host bridge covers the n'th position by granularity + * @addr_trans: address translation helper function * * Return: A new cxl decoder to be registered by cxl_decoder_add(). A * 'CXL root' decoder is one that decodes from a top-level / static platform @@ -1816,7 +1817,8 @@ static int cxl_switch_decoder_init(struct cxl_port *port, */ struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, unsigned int nr_targets, - cxl_calc_hb_fn calc_hb) + cxl_calc_hb_fn calc_hb, + cxl_addr_trans_fn addr_trans) { struct cxl_root_decoder *cxlrd; struct cxl_switch_decoder *cxlsd; @@ -1839,6 +1841,7 @@ struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, } cxlrd->calc_hb = calc_hb; + cxlrd->addr_trans = addr_trans; mutex_init(&cxlrd->range_lock); cxld = &cxlsd->cxld; diff --git a/drivers/cxl/core/trace.c b/drivers/cxl/core/trace.c index d0403dc3c8ab..a7ea4a256036 100644 --- a/drivers/cxl/core/trace.c +++ b/drivers/cxl/core/trace.c @@ -36,6 +36,7 @@ static bool cxl_is_hpa_in_range(u64 hpa, struct cxl_region *cxlr, int pos) static u64 cxl_dpa_to_hpa(u64 dpa, struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled) { + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent); u64 dpa_offset, hpa_offset, bits_upper, mask_upper, hpa; struct cxl_region_params *p = &cxlr->params; int pos = cxled->pos; @@ -75,6 +76,10 @@ static u64 cxl_dpa_to_hpa(u64 dpa, struct cxl_region *cxlr, /* Apply the hpa_offset to the region base address */ hpa = hpa_offset + p->res->start; + /* An addr_trans helper is defined for XOR math */ + if (cxlrd->addr_trans) + hpa = cxlrd->addr_trans(cxlrd, hpa, p->interleave_ways); + if (!cxl_is_hpa_in_range(hpa, cxlr, cxled->pos)) return ULLONG_MAX; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 534e25e2f0a4..f0c3bd377259 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -432,12 +432,14 @@ struct cxl_switch_decoder { struct cxl_root_decoder; typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, int pos); +typedef u64 (*cxl_addr_trans_fn)(struct cxl_root_decoder *cxlrd, u64 hpa, int ways); /** * struct cxl_root_decoder - Static platform CXL address decoder * @res: host / parent resource for region allocations * @region_id: region id for next region provisioning event * @calc_hb: which host bridge covers the n'th position by granularity + * @addr_trans: dpa->hpa address translation helper * @platform_data: platform specific configuration data * @range_lock: sync region autodiscovery by address range * @qos_class: QoS performance class cookie @@ -447,6 +449,7 @@ struct cxl_root_decoder { struct resource *res; atomic_t region_id; cxl_calc_hb_fn calc_hb; + cxl_addr_trans_fn addr_trans; void *platform_data; struct mutex range_lock; int qos_class; @@ -773,7 +776,8 @@ bool is_switch_decoder(struct device *dev); bool is_endpoint_decoder(struct device *dev); struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, unsigned int nr_targets, - cxl_calc_hb_fn calc_hb); + cxl_calc_hb_fn calc_hb, + cxl_addr_trans_fn addr_trans); struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, unsigned int nr_targets); From patchwork Fri Apr 26 19:51:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Schofield X-Patchwork-Id: 13645322 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FCBED2F5 for ; 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a="10067043" X-IronPort-AV: E=Sophos;i="6.07,233,1708416000"; d="scan'208";a="10067043" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 12:51:12 -0700 X-CSE-ConnectionGUID: cJebSmnyRgKZSWHdPi3yEw== X-CSE-MsgGUID: B/bldb9mT2mfeWxgHmL6vw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,233,1708416000"; d="scan'208";a="56432095" Received: from aschofie-mobl2.amr.corp.intel.com (HELO localhost) ([10.212.224.120]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 12:51:11 -0700 From: alison.schofield@intel.com To: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams Cc: linux-cxl@vger.kernel.org Subject: [PATCH 2/3] cxl/region: Verify target positions using the ordered target list Date: Fri, 26 Apr 2024 12:51:06 -0700 Message-Id: X-Mailer: git-send-email 2.40.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Alison Schofield When a root decoder is configured the interleave target list is read from the BIOS populated CFMWS structure. Per the CXL spec 3.1 Table 9-22 the target list is in interleave order. The CXL driver populates its decoder target list in the same order and stores it in 'struct cxl_switch_decoder' field "@target: active ordered target list in current decoder configuration" Given the promise of an ordered list, the driver can stop duplicating the work of BIOS and simply check target positions against the ordered list during region configuration. The simplified check against the ordered list is presented here. A follow-on patch will remove the unused code. For Modulo arithmetic this is not a fix, only a simplification. For XOR arithmetic this is a fix for HB IW of 6,12. Fixes: f9db85bfec0d ("cxl/acpi: Support CXL XOR Interleave Math (CXIMS)") Signed-off-by: Alison Schofield --- drivers/cxl/core/region.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 5c186e0a39b9..3c20f8364b26 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1559,10 +1559,17 @@ static int cxl_region_attach_position(struct cxl_region *cxlr, const struct cxl_dport *dport, int pos) { struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); + struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd; + struct cxl_decoder *cxld = &cxlsd->cxld; + int iw = cxld->interleave_ways; struct cxl_port *iter; int rc; - if (cxlrd->calc_hb(cxlrd, pos) != dport) { + if (dev_WARN_ONCE(&cxld->dev, iw != cxlsd->nr_targets, + "misconfigured root decoder\n")) + return -ENXIO; + + if (dport != cxlrd->cxlsd.target[pos % iw]) { dev_dbg(&cxlr->dev, "%s:%s invalid target position for %s\n", dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), dev_name(&cxlrd->cxlsd.cxld.dev)); From patchwork Fri Apr 26 19:51:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Schofield X-Patchwork-Id: 13645323 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADE0218C36 for ; Fri, 26 Apr 2024 19:51:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714161075; cv=none; b=GAPPPS5oF7PhXjBYhtBqU9DEffgUxxKVUYhjAfNi0fJDCc+lu1N/1F9agoHOLZMmI7IELynScN9W5XGA9U3Af6SAU6lIIP8g+jeUmQroiVYDB0AiLOz+FUznUTGMmSeFTl97Tn24HQf8O4PICqvdv1aFPWldu3CpLtfOsP25kow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714161075; c=relaxed/simple; bh=NFJXm3iyWKqaVL5Z0YwMz6K4H642wrrgkNSmXR8EjiA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gXefqLvZuB09GwKn1/lTlpBaalDEerbwBycikgSvKeGp3fwcrMuQFY66OICQqsnh/sgEIW6UydGmJjZdAldqEBHDnGw0qoW+UBQsRcRtXeL/KtQg8hCxKoqkoehSCw1ZDXlkzTAzXx0/y2UgHv+le39LSPtbVBtVfBdH2Rzy/a0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=H4qYyrFS; arc=none smtp.client-ip=192.198.163.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="H4qYyrFS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714161074; x=1745697074; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NFJXm3iyWKqaVL5Z0YwMz6K4H642wrrgkNSmXR8EjiA=; b=H4qYyrFSOGeKCKDKRhLtWr7L874HIq40N8JIJkVMQ2BKz0sSJM918Iss 5j1hJ8V5AOm53k0Dmk5uBJ3dAA892lB86eru0lTi2cW8g3ZbQrc3OBoFr JRs31REPKAGx1Vewop1d5GmB0KFMICwWh8+7NF9BdIh5pyl/bydoy5vD6 1zQFiwAo8ORYoeZR6PE3OeWslrOzGheqXvhxjadRDM9ATOrcXN+ycf1Rw VBBRfqKwSNYvS447hkN7G5NtBvNWYsNcYuSN6Ykp7uiugN3ZDXHDWeBW7 lZQqzaNscSfpFQseIm35Fg2HPoPp1Jr8W41PmYgAEkSUQt9cXRaWQSieW g==; X-CSE-ConnectionGUID: 4b8L5MSyTCGegMTUeovOJQ== X-CSE-MsgGUID: /krSmvTcS2qMofi4QTDJRw== X-IronPort-AV: E=McAfee;i="6600,9927,11056"; a="10067046" X-IronPort-AV: E=Sophos;i="6.07,233,1708416000"; d="scan'208";a="10067046" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 12:51:12 -0700 X-CSE-ConnectionGUID: EKV5DOcFRv2eVI6+ui13/Q== X-CSE-MsgGUID: P8EEfea+TNaFs4b4DGcBaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,233,1708416000"; d="scan'208";a="56432098" Received: from aschofie-mobl2.amr.corp.intel.com (HELO localhost) ([10.212.224.120]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2024 12:51:12 -0700 From: alison.schofield@intel.com To: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams Cc: linux-cxl@vger.kernel.org Subject: [PATCH 3/3] cxl: Remove defunct code calculating host bridge target positions Date: Fri, 26 Apr 2024 12:51:07 -0700 Message-Id: <30d1bb5362c68a4d045dbd0f4a3c9593e21058f5.1714159486.git.alison.schofield@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Alison Schofield The CXL Spec 3.1 Table 9-22 requires that the BIOS populate the CFMWS target list in interleave target order. This means that the calculations the CXL driver added to determine positions when XOR math is in use, along with the entire XOR vs Modulo call back setup is not needed. A prior patch added a common method to verify positions. Remove the now unused code related to the cxl_calc_hb_fn. Signed-off-by: Alison Schofield Reviewed-by: Dan Williams --- drivers/cxl/acpi.c | 63 ++--------------------------------------- drivers/cxl/core/port.c | 18 ------------ drivers/cxl/cxl.h | 6 ---- 3 files changed, 3 insertions(+), 84 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 519e933b5a4b..67ab3cd52ead 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -22,58 +22,6 @@ static const guid_t acpi_cxl_qtg_id_guid = GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071, 0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52); -/* - * Find a targets entry (n) in the host bridge interleave list. - * CXL Specification 3.0 Table 9-22 - */ -static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw, - int ig) -{ - int i = 0, n = 0; - u8 eiw; - - /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */ - if (iw != 3) { - for (i = 0; i < cximsd->nr_maps; i++) - n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i; - } - /* IW: 3,6,12 add a modulo calculation to 'n' */ - if (!is_power_of_2(iw)) { - if (ways_to_eiw(iw, &eiw)) - return -1; - hpa &= GENMASK_ULL(51, eiw + ig); - n |= do_div(hpa, 3) << i; - } - return n; -} - -static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos) -{ - struct cxl_cxims_data *cximsd = cxlrd->platform_data; - struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd; - struct cxl_decoder *cxld = &cxlsd->cxld; - int ig = cxld->interleave_granularity; - int iw = cxld->interleave_ways; - int n = 0; - u64 hpa; - - if (dev_WARN_ONCE(&cxld->dev, - cxld->interleave_ways != cxlsd->nr_targets, - "misconfigured root decoder\n")) - return NULL; - - hpa = cxlrd->res->start + pos * ig; - - /* Entry (n) is 0 for no interleave (iw == 1) */ - if (iw != 1) - n = cxl_xor_calc_n(hpa, cximsd, iw, ig); - - if (n < 0) - return NULL; - - return cxlrd->cxlsd.target[n]; -} - static u64 restore_xor_pos(u64 hpa, u64 map) { int restore_value, restore_pos = 0; @@ -364,7 +312,6 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws, struct cxl_root_decoder *cxlrd; struct device *dev = ctx->dev; cxl_addr_trans_fn addr_trans; - cxl_calc_hb_fn cxl_calc_hb; struct cxl_decoder *cxld; unsigned int ways, i, ig; struct resource *res; @@ -404,16 +351,12 @@ static int __cxl_parse_cfmws(struct acpi_cedt_cfmws *cfmws, if (rc) goto err_insert; - if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { - cxl_calc_hb = cxl_hb_modulo; + if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) addr_trans = NULL; - - } else { - cxl_calc_hb = cxl_hb_xor; + else addr_trans = cxl_xor_trans; - } - cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb, addr_trans); + cxlrd = cxl_root_decoder_alloc(root_port, ways, addr_trans); if (IS_ERR(cxlrd)) return PTR_ERR(cxlrd); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index cd4f004f5372..93a3a3982a57 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1733,21 +1733,6 @@ static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd, return 0; } -struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos) -{ - struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd; - struct cxl_decoder *cxld = &cxlsd->cxld; - int iw; - - iw = cxld->interleave_ways; - if (dev_WARN_ONCE(&cxld->dev, iw != cxlsd->nr_targets, - "misconfigured root decoder\n")) - return NULL; - - return cxlrd->cxlsd.target[pos % iw]; -} -EXPORT_SYMBOL_NS_GPL(cxl_hb_modulo, CXL); - static struct lock_class_key cxl_decoder_key; /** @@ -1807,7 +1792,6 @@ static int cxl_switch_decoder_init(struct cxl_port *port, * cxl_root_decoder_alloc - Allocate a root level decoder * @port: owning CXL root of this decoder * @nr_targets: static number of downstream targets - * @calc_hb: which host bridge covers the n'th position by granularity * @addr_trans: address translation helper function * * Return: A new cxl decoder to be registered by cxl_decoder_add(). A @@ -1817,7 +1801,6 @@ static int cxl_switch_decoder_init(struct cxl_port *port, */ struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, unsigned int nr_targets, - cxl_calc_hb_fn calc_hb, cxl_addr_trans_fn addr_trans) { struct cxl_root_decoder *cxlrd; @@ -1840,7 +1823,6 @@ struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, return ERR_PTR(rc); } - cxlrd->calc_hb = calc_hb; cxlrd->addr_trans = addr_trans; mutex_init(&cxlrd->range_lock); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index f0c3bd377259..adc9f785f938 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -430,15 +430,12 @@ struct cxl_switch_decoder { }; struct cxl_root_decoder; -typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, - int pos); typedef u64 (*cxl_addr_trans_fn)(struct cxl_root_decoder *cxlrd, u64 hpa, int ways); /** * struct cxl_root_decoder - Static platform CXL address decoder * @res: host / parent resource for region allocations * @region_id: region id for next region provisioning event - * @calc_hb: which host bridge covers the n'th position by granularity * @addr_trans: dpa->hpa address translation helper * @platform_data: platform specific configuration data * @range_lock: sync region autodiscovery by address range @@ -448,7 +445,6 @@ typedef u64 (*cxl_addr_trans_fn)(struct cxl_root_decoder *cxlrd, u64 hpa, int wa struct cxl_root_decoder { struct resource *res; atomic_t region_id; - cxl_calc_hb_fn calc_hb; cxl_addr_trans_fn addr_trans; void *platform_data; struct mutex range_lock; @@ -776,9 +772,7 @@ bool is_switch_decoder(struct device *dev); bool is_endpoint_decoder(struct device *dev); struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, unsigned int nr_targets, - cxl_calc_hb_fn calc_hb, cxl_addr_trans_fn addr_trans); -struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, unsigned int nr_targets); int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);