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An endpoint with ATS enabled may send Translation Requests and Translated Memory Requests, which look just like Normal Memory Requests with a non-zero AT field. So a root controller that ignores the AT field may simply forward the request to the IOMMU as a Normal Memory Request, which could end badly. In any case, the endpoint will be unusable. The ats-supported property allows the OS to only enable ATS in endpoints if the root controller can handle ATS requests. Only add the property to pcie-host-ecam-generic for the moment. For non-generic root controllers, availability of ATS can be inferred from the compatible string. Signed-off-by: Jean-Philippe Brucker Reviewed-by: Rob Herring Reviewed-by: Liviu Dudau --- From a while ago: https://lore.kernel.org/all/20200219222454.GA16221@bogus/ --- Documentation/devicetree/bindings/pci/host-generic-pci.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml index d25423aa71674..94d4a4914a483 100644 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml @@ -110,6 +110,12 @@ properties: iommu-map-mask: true msi-parent: true + ats-supported: + description: + Indicates that a PCIe host controller supports ATS, and can handle Memory + Requests with Address Type (AT). + type: boolean + required: - compatible - reg From patchwork Mon Apr 29 11:39:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 13646674 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 882FD46452 for ; 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Mon, 29 Apr 2024 04:43:08 -0700 (PDT) Received: from localhost.localdomain ([2.221.137.100]) by smtp.gmail.com with ESMTPSA id j28-20020a05600c1c1c00b0041bfb176a87sm7006611wms.27.2024.04.29.04.43.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 04:43:08 -0700 (PDT) From: Jean-Philippe Brucker To: will@kernel.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, liviu.dudau@arm.com, sudeep.holla@arm.com, joro@8bytes.org Cc: robin.murphy@arm.com, nicolinc@nvidia.com, ketanp@nvidia.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Jean-Philippe Brucker Subject: [PATCH 2/3] iommu/of: Support ats-supported device-tree property Date: Mon, 29 Apr 2024 12:39:38 +0100 Message-ID: <20240429113938.192706-4-jean-philippe@linaro.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240429113938.192706-2-jean-philippe@linaro.org> References: <20240429113938.192706-2-jean-philippe@linaro.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Device-tree declares whether a PCI root-complex supports ATS by setting the "ats-supported" property. Copy this flag into device fwspec to let IOMMU drivers quickly check if they can enable ATS for a device. Signed-off-by: Jean-Philippe Brucker Tested-by: Ketan Patil Reviewed-by: Jason Gunthorpe Reviewed-by: Liviu Dudau Reviewed-by: Robin Murphy Reviewed-by: Nicolin Chen --- drivers/iommu/of_iommu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 3afe0b48a48db..082b94c2b3291 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -105,6 +105,14 @@ static int of_iommu_configure_device(struct device_node *master_np, of_iommu_configure_dev(master_np, dev); } +static void of_pci_check_device_ats(struct device *dev, struct device_node *np) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (fwspec && of_property_read_bool(np, "ats-supported")) + fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS; +} + /* * Returns: * 0 on success, an iommu was configured @@ -147,6 +155,7 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, pci_request_acs(); err = pci_for_each_dma_alias(to_pci_dev(dev), of_pci_iommu_init, &info); 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Mon, 29 Apr 2024 04:43:09 -0700 (PDT) From: Jean-Philippe Brucker To: will@kernel.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, liviu.dudau@arm.com, sudeep.holla@arm.com, joro@8bytes.org Cc: robin.murphy@arm.com, nicolinc@nvidia.com, ketanp@nvidia.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Jean-Philippe Brucker Subject: [PATCH 3/3] arm64: dts: fvp: Enable PCIe ATS for Base RevC FVP Date: Mon, 29 Apr 2024 12:39:39 +0100 Message-ID: <20240429113938.192706-5-jean-philippe@linaro.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240429113938.192706-2-jean-philippe@linaro.org> References: <20240429113938.192706-2-jean-philippe@linaro.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Declare that the host controller supports ATS, so the OS can enable it for ATS-capable PCIe endpoints. Signed-off-by: Jean-Philippe Brucker Acked-by: Sudeep Holla --- arch/arm64/boot/dts/arm/fvp-base-revc.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 60472d65a3557..85f1c15cc65d0 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -243,6 +243,7 @@ pci: pci@40000000 { iommu-map = <0x0 &smmu 0x0 0x10000>; dma-coherent; + ats-supported; }; smmu: iommu@2b400000 {