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[176.184.44.142]) by smtp.gmail.com with ESMTPSA id z6-20020adff1c6000000b00343ad4bca7dsm30431276wro.85.2024.04.29.14.30.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:30:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/13] accel/tcg: Restrict qemu_plugin_vcpu_exit_hook() to TCG plugins Date: Mon, 29 Apr 2024 23:30:38 +0200 Message-ID: <20240429213050.55177-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org qemu_plugin_vcpu_exit_hook() is specific to TCG plugins, so must be restricted to it in cpu_common_unrealizefn(), similarly to how qemu_plugin_create_vcpu_state() is restricted in the cpu_common_realizefn() counterpart. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/core/cpu-common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index cbafc79033..f2826d0409 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -30,7 +30,9 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "trace.h" +#ifdef CONFIG_PLUGIN #include "qemu/plugin.h" +#endif CPUState *cpu_by_arch_id(int64_t id) { @@ -226,9 +228,11 @@ static void cpu_common_unrealizefn(DeviceState *dev) CPUState *cpu = CPU(dev); /* Call the plugin hook before clearing the cpu is fully unrealized */ +#ifdef CONFIG_PLUGIN if (tcg_enabled()) { qemu_plugin_vcpu_exit_hook(cpu); } +#endif /* NOTE: latest generic point before the cpu is fully unrealized */ cpu_exec_unrealizefn(cpu); From patchwork Mon Apr 29 21:30:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7BFCFC4345F for ; Mon, 29 Apr 2024 21:31:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1Yal-00078N-9E; Mon, 29 Apr 2024 17:31:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1Yab-00076W-9z for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:12 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s1YaX-0003JJ-Ep for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:06 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-41b9dff6be8so24521035e9.3 for ; Mon, 29 Apr 2024 14:31:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714426263; x=1715031063; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EhMIv0nTX41VJaDT2tW5U63m9lk1MTRg8M20jzTt/L4=; b=tC0sfCAnBc8RsG0aWErESMsHQNoIOPjwmKaH1Y45RD7Y6sAvOASMVBTBLwY14T5UHC YwEsNYkuQ3WmRRO020HbXr9YKK8v3c84rKavBur7zy1hCLjysEnu79Gx/56CTrN9vgdQ LJco/8TYJdowYbxZdfUZJRtQ/NnwjyuVsaqlOBaV9PD4XhvgzBB6o7I31GgXxlxnc8pZ ZOLD7kEFb0+/IcNv9fEXVWFxmRzxSfWwa5QpyqGCFr8NzjcdLaZL49j99hi6n4c/6TuM RHv79tpHku2G7iYIcospNsgCPb9MV9FUKa3CRdzWgOjLX5EoXoE+BYDeqxfLHsKptfeP iwcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714426263; x=1715031063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EhMIv0nTX41VJaDT2tW5U63m9lk1MTRg8M20jzTt/L4=; b=rFAZXCavGkwf7IKql8S0W5nt5Y3QTvZwlScfOROyd9jEr+dGye43PWhyo7tjgGR9su qQqD42UQ/3z5vWRql1hqtU0iLyFpbOLVnfW+Wk1aXIUiEx8rmDDZ0ktKCfRuvnSkp6ab Jdi8J0KYvyTvQueumHGEqzQR5AToes8iJQWpW3yVlZzPTCFxHSRggjAurHxeZgBavUI4 Oo/tOCXXyav0X/+4UxCjrCTkqab1gpNJdGfZOnUnOmW0mRhwQ/JgPFamP9L96vwzlRNB Y6AgKnBHCeT6GC5fWD9YT7fO8xVHNxuiuzKLs1NG2v3jVGBNTJizOSBr4s5TAtbSBVxw l+dg== X-Gm-Message-State: AOJu0Yz+2n/jE5ufKtryKj0kMBMiF18SU5QdkcjtumptZxuA2TVCW1Pk pr/6m1qrItytIc2nwJ6Q8wd6/c0QXbmyeEzXdpaxKOhvF7O3d+Nzbd85MZNse9kNzf0GIRjmS0I j254= X-Google-Smtp-Source: AGHT+IEWJXG9gu8Ew+eJsYjg7wBx7Ck2jDv9C/jKNMJLOn36Xbq9mniwkvfaZrAGp7f+FSIPOgCDPw== X-Received: by 2002:a5d:6b08:0:b0:34b:b0ac:c63c with SMTP id v8-20020a5d6b08000000b0034bb0acc63cmr6937152wrw.66.1714426263310; Mon, 29 Apr 2024 14:31:03 -0700 (PDT) Received: from m1x-phil.lan (bny92-h02-176-184-44-142.dsl.sta.abo.bbox.fr. [176.184.44.142]) by smtp.gmail.com with ESMTPSA id n4-20020a5d4844000000b00349f098f4a6sm30322098wrs.53.2024.04.29.14.31.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:02 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 02/13] accel/tcg: Restrict cpu_plugin_mem_cbs_enabled() to TCG Date: Mon, 29 Apr 2024 23:30:39 +0200 Message-ID: <20240429213050.55177-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org So far cpu_plugin_mem_cbs_enabled() is only called from TCG, so reduce it to accel/tcg/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <5f59c754-44e5-4743-a2dd-87ef8e13eadf@linaro.org> --- accel/tcg/internal-common.h | 17 +++++++++++++++++ include/hw/core/cpu.h | 17 ----------------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index df317e7496..5061687900 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -24,6 +24,23 @@ static inline bool cpu_in_serial_context(CPUState *cs) return !tcg_cflags_has(cs, CF_PARALLEL) || cpu_in_exclusive_context(cs); } +/** + * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled? + * @cs: CPUState pointer + * + * The memory callbacks are installed if a plugin has instrumented an + * instruction for memory. This can be useful to know if you want to + * force a slow path for a series of memory accesses. + */ +static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) +{ +#ifdef CONFIG_PLUGIN + return !!cpu->plugin_mem_cbs; +#else + return false; +#endif +} + void tcg_cpu_exit(CPUState *cpu); #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index beb37342e9..55555be618 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1109,23 +1109,6 @@ void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); #endif -/** - * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled? - * @cs: CPUState pointer - * - * The memory callbacks are installed if a plugin has instrumented an - * instruction for memory. This can be useful to know if you want to - * force a slow path for a series of memory accesses. - */ -static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) -{ -#ifdef CONFIG_PLUGIN - return !!cpu->plugin_mem_cbs; -#else - return false; -#endif -} - /** * cpu_get_address_space: * @cpu: CPU to get address space from From patchwork Mon Apr 29 21:30:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F627C4345F for ; Mon, 29 Apr 2024 21:32:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1Yal-00078X-QK; Mon, 29 Apr 2024 17:31:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1Yaf-000771-FS for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:15 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s1Yac-0003Jv-PB for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:12 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-41b9dff6be8so24521665e9.3 for ; Mon, 29 Apr 2024 14:31:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714426269; x=1715031069; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=359wWRi32Y2oOVdKpxTRSnqSjs36xauPX3xPDGvVHF0=; b=F0uAxXbPnWHIZWxviKtyUwjoL5EK1RsFxgEMUoQCdP08xzunn0iRcmh+c788GM5b0L MPh2xZBCv6VnIpv3EbWGaNC6filalxvNRCLKrBLGSwzC/dY2BcP1NhtcL4xcLNc+TJY6 /DQuDdiJyH/AsUwABJ0OV8Bqugzy2kS83+GPU2OIa5ka/O7TyIghpgLo+SRCALN+YHgg 5fkTHE1nfaWKi2ugMxB8+9De69MqMsdogvm9hxYCC1u1FhOFqCv6/6bAl11EjFr6hYKi jwJnivvJf8MRsnTDoodwbmj09+TAFwnMc6apyB0xWCXPw3oAl1QlVqxmVFdfzmmhLwxv naRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714426269; x=1715031069; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=359wWRi32Y2oOVdKpxTRSnqSjs36xauPX3xPDGvVHF0=; b=IfK6w9Sx3dRQP6zUs7DU2Hg9HlLl9e+gUG2S1XqdRfnZjcg3XRWmBkdGyQRUqsgdR3 6GOZo+HvRlJpZ5x6mVClsxjwOD5k7QylB8v9yPyeRb2UH4e4530VFhPlIImxnzbfL3RM XDB3HTY8fdfSLhM4r00onxSJ7YBJakMtIiEWaR65oQg3Im7QCm7FTC1dE+ltUdxgPi1c CFVPRCvGb8cnmELhtJ3roPDzZqQXLsN85LXYl0rECs7OR0/HpuYr17Nsj16s9sdwylVb wyoHgUPSdqDKPjin8dxgZeJY+6RaCvrLeqbcLlLkq0e0rp8V6BxUo8x2ZLsBDIYxenZB WHaA== X-Gm-Message-State: AOJu0Yz+atr6/ly2K9cAvCyMeTpwem4Ecr8hSVbwO551X5p01IDg6+Zi RaOF/ezq8q9wuWAgkzcZpqG2oEm6NmCgNHwQwyjcodW1l8myevngovjNVBb5tdjVpJXGoKWIHXo CfRM= X-Google-Smtp-Source: AGHT+IErxhbSSahcLTMN/ODB/8NDHWHDm1uAlhTeFmZLza4zefq5CZ9ySmanzU751lq/Nszukgghbw== X-Received: by 2002:adf:f04e:0:b0:34c:b8fa:9768 with SMTP id t14-20020adff04e000000b0034cb8fa9768mr5327988wro.51.1714426268756; Mon, 29 Apr 2024 14:31:08 -0700 (PDT) Received: from m1x-phil.lan (bny92-h02-176-184-44-142.dsl.sta.abo.bbox.fr. [176.184.44.142]) by smtp.gmail.com with ESMTPSA id b10-20020a5d4d8a000000b0034cf989dbf5sm4320744wru.44.2024.04.29.14.31.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/13] accel/tcg: Move @plugin_mem_cbs from CPUState to CPUNegativeOffsetState Date: Mon, 29 Apr 2024 23:30:40 +0200 Message-ID: <20240429213050.55177-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org @plugin_mem_cbs is accessed by tcg generated code, move it to CPUNegativeOffsetState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/internal-common.h | 2 +- include/hw/core/cpu.h | 13 +++++++------ include/qemu/plugin.h | 2 +- accel/tcg/plugin-gen.c | 5 +++-- plugins/core.c | 2 +- 5 files changed, 13 insertions(+), 11 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 5061687900..867426500f 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -35,7 +35,7 @@ static inline bool cpu_in_serial_context(CPUState *cs) static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) { #ifdef CONFIG_PLUGIN - return !!cpu->plugin_mem_cbs; + return !!cpu->neg.plugin_mem_cbs; #else return false; #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 55555be618..571ef3e514 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -342,9 +342,16 @@ typedef union IcountDecr { * CPUNegativeOffsetState: Elements of CPUState most efficiently accessed * from CPUArchState, via small negative offsets. * @can_do_io: True if memory-mapped IO is allowed. + * @plugin_mem_cbs: active plugin memory callbacks */ typedef struct CPUNegativeOffsetState { CPUTLB tlb; +#ifdef CONFIG_PLUGIN + /* + * The callback pointer are accessed via TCG (see gen_empty_mem_helper). + */ + GArray *plugin_mem_cbs; +#endif IcountDecr icount_decr; bool can_do_io; } CPUNegativeOffsetState; @@ -416,7 +423,6 @@ struct qemu_work_item; * @kvm_fd: vCPU file descriptor for KVM. * @work_mutex: Lock to prevent multiple access to @work_list. * @work_list: List of pending asynchronous work. - * @plugin_mem_cbs: active plugin memory callbacks * @plugin_state: per-CPU plugin state * @ignore_memory_transaction_failures: Cached copy of the MachineState * flag of the same name: allows the board to suppress calling of the @@ -509,11 +515,6 @@ struct CPUState { QemuLockCnt in_ioctl_lock; #ifdef CONFIG_PLUGIN - /* - * The callback pointer stays in the main CPUState as it is - * accessed via TCG (see gen_empty_mem_helper). - */ - GArray *plugin_mem_cbs; CPUPluginState *plugin_state; #endif diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h index 41db748eda..99a32446e9 100644 --- a/include/qemu/plugin.h +++ b/include/qemu/plugin.h @@ -229,7 +229,7 @@ void qemu_plugin_add_dyn_cb_arr(GArray *arr); static inline void qemu_plugin_disable_mem_helpers(CPUState *cpu) { - cpu->plugin_mem_cbs = NULL; + cpu->neg.plugin_mem_cbs = NULL; } /** diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index cd78ef94a1..fd268c79b5 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -178,7 +178,7 @@ static void gen_empty_mem_helper(void) TCGv_ptr ptr = tcg_temp_ebb_new_ptr(); tcg_gen_movi_ptr(ptr, 0); - tcg_gen_st_ptr(ptr, tcg_env, offsetof(CPUState, plugin_mem_cbs) - + tcg_gen_st_ptr(ptr, tcg_env, offsetof(CPUState, neg.plugin_mem_cbs) - offsetof(ArchCPU, env)); tcg_temp_free_ptr(ptr); } @@ -634,7 +634,8 @@ void plugin_gen_disable_mem_helpers(void) return; } tcg_gen_st_ptr(tcg_constant_ptr(NULL), tcg_env, - offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.plugin_mem_cbs) - + offsetof(ArchCPU, env)); } static void plugin_gen_tb_udata(const struct qemu_plugin_tb *ptb, diff --git a/plugins/core.c b/plugins/core.c index 09c98382f5..a097d02788 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -496,7 +496,7 @@ void exec_inline_op(struct qemu_plugin_dyn_cb *cb, int cpu_index) void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, MemOpIdx oi, enum qemu_plugin_mem_rw rw) { - GArray *arr = cpu->plugin_mem_cbs; + GArray *arr = cpu->neg.plugin_mem_cbs; size_t i; if (arr == NULL) { From patchwork Mon Apr 29 21:30:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 453A8C4345F for ; Mon, 29 Apr 2024 21:32:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1Yb3-0007Fz-FK; Mon, 29 Apr 2024 17:31:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1Yak-000788-5J for qemu-devel@nongnu.org; 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[176.184.44.142]) by smtp.gmail.com with ESMTPSA id bg5-20020a05600c3c8500b00419f419236fsm34246626wmb.41.2024.04.29.14.31.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 04/13] accel/tcg: Move @plugin_state from CPUState to TCG AccelCPUState Date: Mon, 29 Apr 2024 23:30:41 +0200 Message-ID: <20240429213050.55177-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org @plugin_state is specific to TCG accelerator, move it to its AccelCPUState. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- TODO: check dubious include of "accel/tcg/vcpu-state.h" in hw/core/cpu-common.c. --- accel/tcg/vcpu-state.h | 5 +++++ include/hw/core/cpu.h | 5 ----- accel/tcg/plugin-gen.c | 4 +++- hw/core/cpu-common.c | 3 ++- plugins/core.c | 7 ++++--- 5 files changed, 14 insertions(+), 10 deletions(-) diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h index e30368edae..35c2695a77 100644 --- a/accel/tcg/vcpu-state.h +++ b/accel/tcg/vcpu-state.h @@ -10,11 +10,16 @@ /** * AccelCPUState: vCPU fields specific to TCG accelerator + * @plugin_state: per-CPU plugin state */ struct AccelCPUState { #ifdef CONFIG_USER_ONLY TaskState *ts; #endif /* !CONFIG_USER_ONLY */ + +#ifdef CONFIG_PLUGIN + CPUPluginState *plugin_state; +#endif /* CONFIG_PLUGIN */ }; #ifdef CONFIG_USER_ONLY diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 571ef3e514..91e793e590 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -423,7 +423,6 @@ struct qemu_work_item; * @kvm_fd: vCPU file descriptor for KVM. * @work_mutex: Lock to prevent multiple access to @work_list. * @work_list: List of pending asynchronous work. - * @plugin_state: per-CPU plugin state * @ignore_memory_transaction_failures: Cached copy of the MachineState * flag of the same name: allows the board to suppress calling of the * CPU do_transaction_failed hook function. @@ -514,10 +513,6 @@ struct CPUState { /* Use by accel-block: CPU is executing an ioctl() */ QemuLockCnt in_ioctl_lock; -#ifdef CONFIG_PLUGIN - CPUPluginState *plugin_state; -#endif - /* TODO Move common fields from CPUArchState here. */ int cpu_index; int cluster_index; diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index fd268c79b5..88d720d549 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -52,6 +52,7 @@ #include "exec/plugin-gen.h" #include "exec/translator.h" #include "exec/helper-proto-common.h" +#include "accel/tcg/vcpu-state.h" #define HELPER_H "accel/tcg/plugin-helpers.h" #include "exec/helper-info.c.inc" @@ -872,7 +873,8 @@ bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db, { bool ret = false; - if (test_bit(QEMU_PLUGIN_EV_VCPU_TB_TRANS, cpu->plugin_state->event_mask)) { + if (test_bit(QEMU_PLUGIN_EV_VCPU_TB_TRANS, + cpu->accel->plugin_state->event_mask)) { struct qemu_plugin_tb *ptb = tcg_ctx->plugin_tb; int i; diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index f2826d0409..0e5ebbe050 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -31,6 +31,7 @@ #include "hw/qdev-properties.h" #include "trace.h" #ifdef CONFIG_PLUGIN +#include "accel/tcg/vcpu-state.h" // ??? #include "qemu/plugin.h" #endif @@ -215,7 +216,7 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp) /* Plugin initialization must wait until the cpu start executing code */ #ifdef CONFIG_PLUGIN if (tcg_enabled()) { - cpu->plugin_state = qemu_plugin_create_vcpu_state(); + cpu->accel->plugin_state = qemu_plugin_create_vcpu_state(); async_run_on_cpu(cpu, qemu_plugin_vcpu_init__async, RUN_ON_CPU_NULL); } #endif diff --git a/plugins/core.c b/plugins/core.c index a097d02788..722224e5d8 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -28,6 +28,7 @@ #include "exec/tb-flush.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" +#include "accel/tcg/vcpu-state.h" #include "plugin.h" struct qemu_plugin_cb { @@ -55,7 +56,7 @@ struct qemu_plugin_ctx *plugin_id_to_ctx_locked(qemu_plugin_id_t id) static void plugin_cpu_update__async(CPUState *cpu, run_on_cpu_data data) { - bitmap_copy(cpu->plugin_state->event_mask, + bitmap_copy(cpu->accel->plugin_state->event_mask, &data.host_ulong, QEMU_PLUGIN_EV_MAX); tcg_flush_jmp_cache(cpu); } @@ -396,7 +397,7 @@ qemu_plugin_vcpu_syscall(CPUState *cpu, int64_t num, uint64_t a1, uint64_t a2, struct qemu_plugin_cb *cb, *next; enum qemu_plugin_event ev = QEMU_PLUGIN_EV_VCPU_SYSCALL; - if (!test_bit(ev, cpu->plugin_state->event_mask)) { + if (!test_bit(ev, cpu->accel->plugin_state->event_mask)) { return; } @@ -418,7 +419,7 @@ void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_t num, int64_t ret) struct qemu_plugin_cb *cb, *next; enum qemu_plugin_event ev = QEMU_PLUGIN_EV_VCPU_SYSCALL_RET; - if (!test_bit(ev, cpu->plugin_state->event_mask)) { + if (!test_bit(ev, cpu->accel->plugin_state->event_mask)) { return; } From patchwork Mon Apr 29 21:30:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B65AEC19F4F for ; Mon, 29 Apr 2024 21:33:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1Yb8-0007Nw-R1; Mon, 29 Apr 2024 17:31:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1Yav-0007FJ-Gh for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:31 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s1Yan-0003KY-Ck for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:26 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-41b794510cdso31088925e9.2 for ; Mon, 29 Apr 2024 14:31:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714426279; x=1715031079; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ooSUJZwGp/lYPuvOeREBaY5/HVZbZHNsZQAPgbRFeRs=; b=sue0DB3EgTzl20AX6XeR/+Phuwu0oeEcA3WSiG4XAyedjldl+4//gVrXYFzzpN6GZ+ zPKNDjb0RhBxMFJ+o5UEg1W/RUJhM7t8z/K8lvQHcC2wlkUTYFsxCSjWfEBUEX8oEw1Y dD7Gzf2cGO3fd+Rpo5m2cZfXHmco1WevvBKvC97fQy+CoLbUAIT4xJkK/YxGq2JT++RI h86Ha52FMRLKaCJFl9sAdXlHEvSV+MKVD9EvZBUnCARg/eMuTG+QL1KMWhXXJKhp9sGf WP5mjkO95PegmNquM2xyM9VnVX7TNUQXMppT0F+/3QlSZcvfq9xVzvrkqgFL0ZL9YMJj wgiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714426279; x=1715031079; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ooSUJZwGp/lYPuvOeREBaY5/HVZbZHNsZQAPgbRFeRs=; b=G1nGsfHlkB1S5HYVIS17R6rzA42/oCB8TqsSAgNq3tpvWI+DL2NVTWOrXcXSByUudH UIMnD6zyXof6HRldrWGyic4Yhfq6u5Xig21k1+CUNsvN2D1Fjlhk5VsCd7D0xfl9Xc3B Bc1/awxPIkKb/fkxY7i/Wbq06PmFu3lSNvHdKL0pUUOhvM9JIk/suPtmwKJnVwMPsDAk pB4+1UVvt8IrPsMaa0ZTwnomYeF/Bfd/V3iy9/1yfTP6SV+3wVOC9r7V4XSQdfp+75jy pZ65Dcihi4fosmg1bQjvZsn/DLkyC2uMVFUmTK/eB36xbiYY8okzSbiFpGiOgxV02QrI 0yeA== X-Gm-Message-State: AOJu0YyIhhHeytOORS7akbya+/WT8MsdxOiuC7nC9Wv7VeNVCcj/ZSWU T6aAJzqdpxaqpbOmr7UhGY6KaRQvqCxUwO/EVrt3h4MdWXAUh7m/rDkf3hY8v+yvkmw0qZ0Pdyj uLtA= X-Google-Smtp-Source: AGHT+IHTLhnzJgdX1MLF377SlYnpHOf53mblCsNumTl6t3g4OYyZUac6+HbghKjLZ+dOElKl32HaIA== X-Received: by 2002:a05:600c:5025:b0:41a:a4d1:a896 with SMTP id n37-20020a05600c502500b0041aa4d1a896mr752165wmr.16.1714426279546; Mon, 29 Apr 2024 14:31:19 -0700 (PDT) Received: from m1x-phil.lan (bny92-h02-176-184-44-142.dsl.sta.abo.bbox.fr. [176.184.44.142]) by smtp.gmail.com with ESMTPSA id p8-20020a5d48c8000000b0034af40b2efdsm22308632wrs.108.2024.04.29.14.31.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/13] accel/tcg: Restrict IcountDecr / can_do_io / CPUTLB to TCG Date: Mon, 29 Apr 2024 23:30:42 +0200 Message-ID: <20240429213050.55177-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IcountDecr union, the can_do_io field, the CPUTLB* structures and the "exec/tlb-common.h" header are only required for TCG. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-16-philmd@linaro.org> --- include/exec/tlb-common.h | 4 ++++ include/hw/core/cpu.h | 9 ++++++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h index dc5a5faa0b..a529c9f056 100644 --- a/include/exec/tlb-common.h +++ b/include/exec/tlb-common.h @@ -19,6 +19,10 @@ #ifndef EXEC_TLB_COMMON_H #define EXEC_TLB_COMMON_H 1 +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + #define CPU_TLB_ENTRY_BITS 5 /* Minimalized TLB entry for use by TCG fast path. */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 91e793e590..47b499f9f1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -27,7 +27,6 @@ #include "exec/vaddr.h" #include "exec/memattrs.h" #include "exec/mmu-access-type.h" -#include "exec/tlb-common.h" #include "qapi/qapi-types-run-state.h" #include "qemu/bitmap.h" #include "qemu/rcu_queue.h" @@ -256,6 +255,9 @@ typedef struct CPUTLBEntryFull { } extra; } CPUTLBEntryFull; +#ifdef CONFIG_TCG +#include "exec/tlb-common.h" + /* * Data elements that are per MMU mode, minus the bits accessed by * the TCG fast path. @@ -311,11 +313,9 @@ typedef struct CPUTLBCommon { * negative offsets are at the end of the struct. */ typedef struct CPUTLB { -#ifdef CONFIG_TCG CPUTLBCommon c; CPUTLBDesc d[NB_MMU_MODES]; CPUTLBDescFast f[NB_MMU_MODES]; -#endif } CPUTLB; /* @@ -337,6 +337,7 @@ typedef union IcountDecr { #endif } u16; } IcountDecr; +#endif /** * CPUNegativeOffsetState: Elements of CPUState most efficiently accessed @@ -345,6 +346,7 @@ typedef union IcountDecr { * @plugin_mem_cbs: active plugin memory callbacks */ typedef struct CPUNegativeOffsetState { +#ifdef CONFIG_TCG CPUTLB tlb; #ifdef CONFIG_PLUGIN /* @@ -354,6 +356,7 @@ typedef struct CPUNegativeOffsetState { #endif IcountDecr icount_decr; bool can_do_io; +#endif } CPUNegativeOffsetState; struct KVMState; From patchwork Mon Apr 29 21:30:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50F83C19F4F for ; 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[176.184.44.142]) by smtp.gmail.com with ESMTPSA id a9-20020a05600c348900b0041bb11ff5a7sm12390100wmq.8.2024.04.29.14.31.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 06/13] accel/tcg: Move @jmp_env from CPUState to TCG AccelCPUState Date: Mon, 29 Apr 2024 23:30:43 +0200 Message-ID: <20240429213050.55177-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=philmd@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org @jmp_env is specific to TCG accelerator, move it to its AccelCPUState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-17-philmd@linaro.org> --- accel/tcg/internal-common.h | 1 + accel/tcg/tcg-accel-ops.h | 1 + accel/tcg/vcpu-state.h | 2 ++ include/hw/core/cpu.h | 1 - accel/tcg/cpu-exec-common.c | 2 +- accel/tcg/cpu-exec.c | 6 +++--- 6 files changed, 8 insertions(+), 5 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 867426500f..cb507053f5 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -11,6 +11,7 @@ #include "exec/cpu-common.h" #include "exec/translation-block.h" +#include "accel/tcg/vcpu-state.h" extern int64_t max_delay; extern int64_t max_advance; diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h index 44c4079972..ed41a087a3 100644 --- a/accel/tcg/tcg-accel-ops.h +++ b/accel/tcg/tcg-accel-ops.h @@ -13,6 +13,7 @@ #define TCG_ACCEL_OPS_H #include "sysemu/cpus.h" +#include "accel/tcg/vcpu-state.h" void tcg_cpu_destroy(CPUState *cpu); int tcg_cpu_exec(CPUState *cpu); diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h index 35c2695a77..3a0ea2d47a 100644 --- a/accel/tcg/vcpu-state.h +++ b/accel/tcg/vcpu-state.h @@ -13,6 +13,8 @@ * @plugin_state: per-CPU plugin state */ struct AccelCPUState { + sigjmp_buf jmp_env; + #ifdef CONFIG_USER_ONLY TaskState *ts; #endif /* !CONFIG_USER_ONLY */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 47b499f9f1..f1fe43dbea 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -475,7 +475,6 @@ struct CPUState { int64_t icount_budget; int64_t icount_extra; uint64_t random_seed; - sigjmp_buf jmp_env; QemuMutex work_mutex; QSIMPLEQ_HEAD(, qemu_work_item) work_list; diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index bc9b1a260e..ec45482305 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -38,7 +38,7 @@ void cpu_loop_exit(CPUState *cpu) cpu->neg.can_do_io = true; /* Undo any setting in generated code. */ qemu_plugin_disable_mem_helpers(cpu); - siglongjmp(cpu->jmp_env, 1); + siglongjmp(cpu->accel->jmp_env, 1); } void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 9af66bc191..46ad16f911 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -553,7 +553,7 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu) * support such a thing. We'd have to properly register unwind info * for the JIT for EH, rather that just for GDB. * - * Alternative 2: Set and restore cpu->jmp_env in tb_gen_code to + * Alternative 2: Set and restore cpu->accel->jmp_env in tb_gen_code to * capture the cpu_loop_exit longjmp, perform the cleanup, and * jump again to arrive here. */ @@ -577,7 +577,7 @@ void cpu_exec_step_atomic(CPUState *cpu) uint32_t flags, cflags; int tb_exit; - if (sigsetjmp(cpu->jmp_env, 0) == 0) { + if (sigsetjmp(cpu->accel->jmp_env, 0) == 0) { start_exclusive(); g_assert(cpu == current_cpu); g_assert(!cpu->running); @@ -1038,7 +1038,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) static int cpu_exec_setjmp(CPUState *cpu, SyncClocks *sc) { /* Prepare setjmp context for exception handling. */ - if (unlikely(sigsetjmp(cpu->jmp_env, 0) != 0)) { + if (unlikely(sigsetjmp(cpu->accel->jmp_env, 0) != 0)) { cpu_exec_longjmp_cleanup(cpu); } From patchwork Mon Apr 29 21:30:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80F62C4345F for ; Mon, 29 Apr 2024 21:32:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1YbA-0007Uo-I2; Mon, 29 Apr 2024 17:31:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1Yb1-0007Gw-5z for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:37 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s1Yay-0003LK-J4 for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:34 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-41ba1ba55e8so25917175e9.1 for ; Mon, 29 Apr 2024 14:31:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714426290; x=1715031090; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hnf3o4XnFK2bwHRx7vZnChEV3e4FPyGXBQfB4lUUGyk=; b=VoTCsT6gy9TroiuqOPYT9hx1xJktA0zfPDstINDygDSZUU19hBOxs8e27+N77yR0Av Z9kXoxiN8Y4aLJtC7mD0l9W7DOGaNYVrIZ2XGBKHSA3UEud01NM/Qc97AIt7lkmNPKic RScNatR4OoVd92+3iBGus6Y0DGYFfMqlf03BELPUHJI5wzQlBU9py+YIYdyYGzz+tw8y ONCl14BdbencIwuK/QqTNRvT3ld39wPZoQF4JQO3pPbTo2BjtbvIfZfhLTbg5AK8eBgo 2nqYX548+kHx90WkpMmInyarn8U5JJWanyIWcfss2/G86dN7XTbPXjwTvrMl0aiNqRLr AMdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714426290; x=1715031090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hnf3o4XnFK2bwHRx7vZnChEV3e4FPyGXBQfB4lUUGyk=; b=tki7bpX9G/GBzH0ry7pH71AHdu3rm1Hh2JS5dohiDtpOfDGD6kHSw9lytxqpIaqQEo a1jQLfLxms88IDuHFw80zH66YCvr/kBPP5CdXIrGPyj1TvxN6/O6EJ8Mw7znJ5uzsT4x 7BJQDAkUUnojt+ARyedFNrO57GEOjX/bRwkNqqG6g10AOM8dxlGib3gyR8iKVN9maGrw 1osw0Rn9zKdmIUItIoMPCdMcm+t2oVlmr9L7K9oNP0FpzOYWWt9epRteswIfCivEMUMt 35i1dMDGLQ4zNTCm7k9KgrESEZFi3FlcZanzJaa5wWMFkoiS67nJNPfQY01/wwJznNS9 UZhQ== X-Gm-Message-State: AOJu0YzkaAMmLxpW0sBwPGVTfMiBS17ij91Mux3+9aRvoIu0dKMvXgBR JrmyV951IyF6a7wxMdcKdvomqeZ0dW/91CGVbgLa8PUeS+TwRuLHIVzrMrcNrCAmes2j0KYC9WP 0l5Y= X-Google-Smtp-Source: AGHT+IGsTQ5w+J4lZdE0kS6E7TG0UDgkOvzzx899QQeeeZFYBZJUp7idODr/l6K2+kcAuj8lVgySYw== X-Received: by 2002:a05:600c:a41:b0:418:fe93:22d0 with SMTP id c1-20020a05600c0a4100b00418fe9322d0mr680520wmq.11.1714426289844; Mon, 29 Apr 2024 14:31:29 -0700 (PDT) Received: from m1x-phil.lan (bny92-h02-176-184-44-142.dsl.sta.abo.bbox.fr. [176.184.44.142]) by smtp.gmail.com with ESMTPSA id p6-20020a05600c468600b0041563096e15sm47015125wmo.5.2024.04.29.14.31.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:29 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/13] accel/tcg: Move @cflags_next_tb from CPUState to TCG AccelCPUState Date: Mon, 29 Apr 2024 23:30:44 +0200 Message-ID: <20240429213050.55177-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org @cflags_next_tb is specific to TCG accelerator, move it to its AccelCPUState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-19-philmd@linaro.org> --- accel/tcg/vcpu-state.h | 2 ++ include/hw/core/cpu.h | 1 - accel/tcg/cpu-exec.c | 12 ++++++------ accel/tcg/tb-maint.c | 4 ++-- accel/tcg/tcg-accel-ops.c | 1 + accel/tcg/translate-all.c | 2 +- accel/tcg/watchpoint.c | 5 +++-- hw/core/cpu-common.c | 1 - 8 files changed, 15 insertions(+), 13 deletions(-) diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h index 3a0ea2d47a..5b09279140 100644 --- a/accel/tcg/vcpu-state.h +++ b/accel/tcg/vcpu-state.h @@ -13,6 +13,8 @@ * @plugin_state: per-CPU plugin state */ struct AccelCPUState { + uint32_t cflags_next_tb; + sigjmp_buf jmp_env; #ifdef CONFIG_USER_ONLY diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index f1fe43dbea..97a0baf874 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -468,7 +468,6 @@ struct CPUState { bool crash_occurred; bool exit_request; int exclusive_context_count; - uint32_t cflags_next_tb; /* updates protected by BQL */ uint32_t interrupt_request; int singlestep_enabled; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 46ad16f911..55235d3e5e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -720,7 +720,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (replay_has_exception() && cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0) { /* Execute just one insn to trigger exception pending in the log */ - cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) + cpu->accel->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) | CF_NOIRQ | 1; } #endif @@ -783,7 +783,7 @@ static inline bool icount_exit_request(CPUState *cpu) if (!icount_enabled()) { return false; } - if (cpu->cflags_next_tb != -1 && !(cpu->cflags_next_tb & CF_USE_ICOUNT)) { + if (!(cpu->accel->cflags_next_tb == -1 || cpu->accel->cflags_next_tb & CF_USE_ICOUNT)) { return false; } return cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0; @@ -797,7 +797,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * skip checking here. Any pending interrupts will get picked up * by the next TB we execute under normal cflags. */ - if (cpu->cflags_next_tb != -1 && cpu->cflags_next_tb & CF_NOIRQ) { + if (cpu->accel->cflags_next_tb != -1 && cpu->accel->cflags_next_tb & CF_NOIRQ) { return false; } @@ -947,7 +947,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, if (insns_left > 0 && insns_left < tb->icount) { assert(insns_left <= CF_COUNT_MASK); assert(cpu->icount_extra == 0); - cpu->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left; + cpu->accel->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left; } #endif } @@ -979,11 +979,11 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) * have CF_INVALID set, -1 is a convenient invalid value that * does not require tcg headers for cpu_common_reset. */ - cflags = cpu->cflags_next_tb; + cflags = cpu->accel->cflags_next_tb; if (cflags == -1) { cflags = curr_cflags(cpu); } else { - cpu->cflags_next_tb = -1; + cpu->accel->cflags_next_tb = -1; } if (check_for_breakpoints(cpu, pc, &cflags)) { diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 19ae6793f3..2d5faca9fd 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1084,7 +1084,7 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc) if (current_tb_modified) { /* Force execution of one insn next time. */ CPUState *cpu = current_cpu; - cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(current_cpu); + cpu->accel->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(current_cpu); return true; } return false; @@ -1154,7 +1154,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, if (current_tb_modified) { page_collection_unlock(pages); /* Force execution of one insn next time. */ - current_cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(current_cpu); + current_cpu->accel->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(current_cpu); mmap_unlock(); cpu_loop_exit_noexc(current_cpu); } diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 56bbad9fcd..d9132a5835 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -89,6 +89,7 @@ static void tcg_cpu_reset_hold(CPUState *cpu) qatomic_set(&cpu->neg.icount_decr.u32, 0); cpu->neg.can_do_io = true; + cpu->accel->cflags_next_tb = -1; } /* mask must never be zero, except for A20 change call */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b67adce20e..3a8199a761 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -631,7 +631,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) * operations only (which execute after completion) so we don't * double instrument the instruction. */ - cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | n; + cpu->accel->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | n; if (qemu_loglevel_mask(CPU_LOG_EXEC)) { vaddr pc = cpu->cc->get_pc(cpu); diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index d3aab11458..0a40bfdc85 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -26,6 +26,7 @@ #include "sysemu/replay.h" #include "hw/core/tcg-cpu-ops.h" #include "hw/core/cpu.h" +#include "accel/tcg/vcpu-state.h" /* * Return true if this watchpoint address matches the specified @@ -100,7 +101,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, */ if (!cpu->neg.can_do_io) { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); + cpu->accel->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); cpu_loop_exit_restore(cpu, ra); } /* @@ -132,7 +133,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, cpu_loop_exit(cpu); } else { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); + cpu->accel->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); mmap_unlock(); cpu_loop_exit_noexc(cpu); } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 0e5ebbe050..073eb75ad0 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -124,7 +124,6 @@ static void cpu_common_reset_hold(Object *obj, ResetType type) cpu->icount_extra = 0; cpu->exception_index = -1; cpu->crash_occurred = false; - cpu->cflags_next_tb = -1; cpu_exec_reset_hold(cpu); } From patchwork Mon Apr 29 21:30:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7739FC04FFE for ; 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[176.184.44.142]) by smtp.gmail.com with ESMTPSA id p8-20020a05600c358800b00418f72d9027sm40703434wmq.18.2024.04.29.14.31.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:34 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/13] accel/tcg: Move @iommu_notifiers from CPUState to TCG AccelCPUState Date: Mon, 29 Apr 2024 23:30:45 +0200 Message-ID: <20240429213050.55177-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=philmd@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org @iommu_notifiers is specific to TCG system emulation, move it to AccelCPUState. Restrict TCG specific code in system/physmem.c, adding an empty stub for tcg_register_iommu_notifier(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-20-philmd@linaro.org> --- accel/tcg/vcpu-state.h | 3 +++ include/hw/core/cpu.h | 3 --- system/physmem.c | 37 ++++++++++++++++++++++++++++--------- 3 files changed, 31 insertions(+), 12 deletions(-) diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h index 5b09279140..51e54ca535 100644 --- a/accel/tcg/vcpu-state.h +++ b/accel/tcg/vcpu-state.h @@ -19,6 +19,9 @@ struct AccelCPUState { #ifdef CONFIG_USER_ONLY TaskState *ts; +#else + /* track IOMMUs whose translations we've cached in the TCG TLB */ + GArray *iommu_notifiers; #endif /* !CONFIG_USER_ONLY */ #ifdef CONFIG_PLUGIN diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 97a0baf874..f3cbb944eb 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -539,9 +539,6 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; - /* track IOMMUs whose translations we've cached in the TCG TLB */ - GArray *iommu_notifiers; - /* * MUST BE LAST in order to minimize the displacement to CPUArchState. */ diff --git a/system/physmem.c b/system/physmem.c index 44e477a1a5..1e003e42bb 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -27,6 +27,8 @@ #include "qemu/madvise.h" #ifdef CONFIG_TCG +#include "exec/translate-all.h" +#include "accel/tcg/vcpu-state.h" #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ @@ -578,6 +580,8 @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, return mr; } +#ifdef CONFIG_TCG + typedef struct TCGIOMMUNotifier { IOMMUNotifier n; MemoryRegion *mr; @@ -614,17 +618,20 @@ static void tcg_register_iommu_notifier(CPUState *cpu, TCGIOMMUNotifier *notifier = NULL; int i; - for (i = 0; i < cpu->iommu_notifiers->len; i++) { - notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); + for (i = 0; i < cpu->accel->iommu_notifiers->len; i++) { + notifier = g_array_index(cpu->accel->iommu_notifiers, + TCGIOMMUNotifier *, i); if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) { break; } } - if (i == cpu->iommu_notifiers->len) { + if (i == cpu->accel->iommu_notifiers->len) { /* Not found, add a new entry at the end of the array */ - cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1); + cpu->accel->iommu_notifiers = g_array_set_size(cpu->accel->iommu_notifiers, + i + 1); notifier = g_new0(TCGIOMMUNotifier, 1); - g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier; + g_array_index(cpu->accel->iommu_notifiers, + TCGIOMMUNotifier *, i) = notifier; notifier->mr = mr; notifier->iommu_idx = iommu_idx; @@ -656,19 +663,31 @@ void tcg_iommu_free_notifier_list(CPUState *cpu) int i; TCGIOMMUNotifier *notifier; - for (i = 0; i < cpu->iommu_notifiers->len; i++) { - notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i); + for (i = 0; i < cpu->accel->iommu_notifiers->len; i++) { + notifier = g_array_index(cpu->accel->iommu_notifiers, + TCGIOMMUNotifier *, i); memory_region_unregister_iommu_notifier(notifier->mr, ¬ifier->n); g_free(notifier); } - g_array_free(cpu->iommu_notifiers, true); + g_array_free(cpu->accel->iommu_notifiers, true); } void tcg_iommu_init_notifier_list(CPUState *cpu) { - cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *)); + cpu->accel->iommu_notifiers = g_array_new(false, true, + sizeof(TCGIOMMUNotifier *)); } +#else + +static void tcg_register_iommu_notifier(CPUState *cpu, + IOMMUMemoryRegion *iommu_mr, + int iommu_idx) +{ +} + +#endif + /* Called from RCU critical section */ MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr, From patchwork Mon Apr 29 21:30:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 710DAC25B4F for ; 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[176.184.44.142]) by smtp.gmail.com with ESMTPSA id u5-20020a05600c138500b0041c5151dc1csm4286616wmf.29.2024.04.29.14.31.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/13] accel/tcg: Move @tb_jmp_cache from CPUState to TCG AccelCPUState Date: Mon, 29 Apr 2024 23:30:46 +0200 Message-ID: <20240429213050.55177-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=philmd@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org @tb_jmp_cache is specific to TCG accelerator, move it to its AccelCPUState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-21-philmd@linaro.org> --- accel/tcg/tb-jmp-cache.h | 4 ++-- accel/tcg/vcpu-state.h | 2 ++ include/hw/core/cpu.h | 2 -- include/qemu/typedefs.h | 1 - accel/tcg/cpu-exec.c | 7 +++---- accel/tcg/cputlb.c | 2 +- accel/tcg/tb-maint.c | 2 +- accel/tcg/translate-all.c | 5 +++-- 8 files changed, 12 insertions(+), 13 deletions(-) diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h index 184bb3e3e2..c3a505e394 100644 --- a/accel/tcg/tb-jmp-cache.h +++ b/accel/tcg/tb-jmp-cache.h @@ -22,12 +22,12 @@ * non-NULL value of 'tb'. Strictly speaking pc is only needed for * CF_PCREL, but it's used always for simplicity. */ -struct CPUJumpCache { +typedef struct CPUJumpCache { struct rcu_head rcu; struct { TranslationBlock *tb; vaddr pc; } array[TB_JMP_CACHE_SIZE]; -}; +} CPUJumpCache; #endif /* ACCEL_TCG_TB_JMP_CACHE_H */ diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h index 51e54ca535..0cb58ba734 100644 --- a/accel/tcg/vcpu-state.h +++ b/accel/tcg/vcpu-state.h @@ -7,6 +7,7 @@ #define ACCEL_TCG_VCPU_STATE_H #include "hw/core/cpu.h" +#include "tb-jmp-cache.h" /** * AccelCPUState: vCPU fields specific to TCG accelerator @@ -16,6 +17,7 @@ struct AccelCPUState { uint32_t cflags_next_tb; sigjmp_buf jmp_env; + CPUJumpCache tb_jmp_cache; #ifdef CONFIG_USER_ONLY TaskState *ts; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index f3cbb944eb..6e6e946b66 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -483,8 +483,6 @@ struct CPUState { AddressSpace *as; MemoryRegion *memory; - CPUJumpCache *tb_jmp_cache; - GArray *gdb_regs; int gdb_num_regs; int gdb_num_g_regs; diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 36f2825725..daf9009332 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -44,7 +44,6 @@ typedef struct CPUAddressSpace CPUAddressSpace; typedef struct CPUArchState CPUArchState; typedef struct CPUPluginState CPUPluginState; typedef struct CpuInfoFast CpuInfoFast; -typedef struct CPUJumpCache CPUJumpCache; typedef struct CPUState CPUState; typedef struct CPUTLBEntryFull CPUTLBEntryFull; typedef struct DeviceListener DeviceListener; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 55235d3e5e..8f8e1fa948 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -261,7 +261,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc, tcg_debug_assert(!(cflags & CF_INVALID)); hash = tb_jmp_cache_hash_func(pc); - jc = cpu->tb_jmp_cache; + jc = &cpu->accel->tb_jmp_cache; tb = qatomic_read(&jc->array[hash].tb); if (likely(tb && @@ -1004,7 +1004,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) * for the fast lookup */ h = tb_jmp_cache_hash_func(pc); - jc = cpu->tb_jmp_cache; + jc = &cpu->accel->tb_jmp_cache; jc->array[h].pc = pc; qatomic_set(&jc->array[h].tb, tb); } @@ -1083,7 +1083,6 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) tcg_target_initialized = true; } - cpu->tb_jmp_cache = g_new0(CPUJumpCache, 1); tlb_init(cpu); #ifndef CONFIG_USER_ONLY tcg_iommu_init_notifier_list(cpu); @@ -1101,5 +1100,5 @@ void tcg_exec_unrealizefn(CPUState *cpu) #endif /* !CONFIG_USER_ONLY */ tlb_destroy(cpu); - g_free_rcu(cpu->tb_jmp_cache, rcu); + g_free_rcu(&cpu->accel->tb_jmp_cache, rcu); } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index cdb3e12dfb..eaa60d1da2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -156,7 +156,7 @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, static void tb_jmp_cache_clear_page(CPUState *cpu, vaddr page_addr) { - CPUJumpCache *jc = cpu->tb_jmp_cache; + CPUJumpCache *jc = &cpu->accel->tb_jmp_cache; int i, i0; if (unlikely(!jc)) { diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 2d5faca9fd..83758648f2 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -888,7 +888,7 @@ static void tb_jmp_cache_inval_tb(TranslationBlock *tb) uint32_t h = tb_jmp_cache_hash_func(tb->pc); CPU_FOREACH(cpu) { - CPUJumpCache *jc = cpu->tb_jmp_cache; + CPUJumpCache *jc = &cpu->accel->tb_jmp_cache; if (qatomic_read(&jc->array[h].tb) == tb) { qatomic_set(&jc->array[h].tb, NULL); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 3a8199a761..ca1e193633 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -652,13 +652,14 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) */ void tcg_flush_jmp_cache(CPUState *cpu) { - CPUJumpCache *jc = cpu->tb_jmp_cache; + CPUJumpCache *jc; /* During early initialization, the cache may not yet be allocated. */ - if (unlikely(jc == NULL)) { + if (unlikely(cpu->accel == NULL)) { return; } + jc = &cpu->accel->tb_jmp_cache; for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) { qatomic_set(&jc->array[i].tb, NULL); } From patchwork Mon Apr 29 21:30:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37CEBC4345F for ; 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[176.184.44.142]) by smtp.gmail.com with ESMTPSA id p6-20020a05600c468600b0041563096e15sm47015588wmo.5.2024.04.29.14.31.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v2 10/13] accel/tcg: Remove NULL check in tcg_flush_jmp_cache() Date: Mon, 29 Apr 2024 23:30:47 +0200 Message-ID: <20240429213050.55177-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org I /think/ this check added in commit 4e4fa6c12d ("accel/tcg: Complete cpu initialization before registration") is now unnecessary, but I don't have the WASM reproducer mentioned in: https://lore.kernel.org/qemu-devel/20221027141856.w5umjgklawgu7pqv@heavy/ to confirm. Ilya, do you mind testing? If so, we could squash this with the previous patch. Cc: Ilya Leoshkevich Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/translate-all.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ca1e193633..9b02f21b23 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -652,14 +652,8 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) */ void tcg_flush_jmp_cache(CPUState *cpu) { - CPUJumpCache *jc; + CPUJumpCache *jc = &cpu->accel->tb_jmp_cache; - /* During early initialization, the cache may not yet be allocated. */ - if (unlikely(cpu->accel == NULL)) { - return; - } - - jc = &cpu->accel->tb_jmp_cache; for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) { qatomic_set(&jc->array[i].tb, NULL); } From patchwork Mon Apr 29 21:30:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78B54C4345F for ; Mon, 29 Apr 2024 21:33:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1Ybb-0008E4-T4; Mon, 29 Apr 2024 17:32:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1YbL-0007oB-45 for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:58 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s1YbI-0003N3-Th for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:31:54 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-41ba1ba55ebso24100145e9.1 for ; Mon, 29 Apr 2024 14:31:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714426311; x=1715031111; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RalDqVPJ3rLs2jYwmC3Tt03XCZdQnhUJqO3vFzpn9o4=; b=U8r1Gt1nKqdxzgfdcCKq+VLyqkp9yD8fqSlvOBCBOjsHUM9PJ0ROmvJ8+LhAwAexbE m4stLI8J6dfPOOK/mbFF7IhGyREhMq2PiMduWYJ3rLAzRdnkhUMRronLhY0MklL+BaFv b9uY395zCRMStyjyXaYIhdcbAObdAJkNFQnZnmsEqkvketG/ITzWosYzt0wS6oJTlSfw Qyu43HheE5u1xDsrqWsw1HsgpgmvVa9ADSgo2lRtckDz1/4g8Y6mqdYskHRKJaO1i3Lk hu0sk7FlKiPwaqfJ2xnqi26+hgpx9P/FoLsbTl/0GbSAKjaWxtKmsNVG4YiyZs4jmHRD 8AIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714426311; x=1715031111; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RalDqVPJ3rLs2jYwmC3Tt03XCZdQnhUJqO3vFzpn9o4=; b=GSrviS5RrgCowH0IVKMSa5+38mRQtI1liFRK45T15Ppa3L3rA3VkISqMCvTN9n4PJ1 ipicDYvlkDb3i8yyC+IoiBaLAl8DUuucTD9ixfvtbxsjrGb1AFwwG4weIM40ZC3nf9lX T4r5/0oT06g3734tcDRsO4kBw577hk/2N7jYSUthr7gp82+O+f9kXnNDgccClp/l4D2r BHTUFHUISmG1AGcvl6Ry3uj+c9PziwXm0J8wdG0Obc3yT0olzayUai9zu+cSi7poszPU YJq9TW3GOUvI6q9Yu+vHf2OsxfnA4WkZwEhxhABUY4sFdsVO1tKUTNrqk4DewTsnB9At TWEw== X-Gm-Message-State: AOJu0YyEbR9DLXlGaAVXJ5+28yHFz2O6CZWxrvv2BWcRDneNXKlo4Qnc 777cKJgarOrB/ur2WbBY+jEmxcXqF9Fwoh4YGQIJD0Ty+9MpCJakVLmc/SbV8hzmi2YPqp9B639 NSD4= X-Google-Smtp-Source: AGHT+IH5igrkr78z5cS2s+aJfV6/vtNImjqovSUZnwC3o5wZIJ1pUhhkfrdW4Ld2FGZdT00TY/77GQ== X-Received: by 2002:a05:600c:3b8c:b0:41b:143b:5c2d with SMTP id n12-20020a05600c3b8c00b0041b143b5c2dmr7885753wms.28.1714426311015; Mon, 29 Apr 2024 14:31:51 -0700 (PDT) Received: from m1x-phil.lan (bny92-h02-176-184-44-142.dsl.sta.abo.bbox.fr. [176.184.44.142]) by smtp.gmail.com with ESMTPSA id o14-20020a05600c510e00b00419f572671dsm34316236wms.20.2024.04.29.14.31.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 11/13] accel/tcg: Move @tcg_cflags from CPUState to TCG AccelCPUState Date: Mon, 29 Apr 2024 23:30:48 +0200 Message-ID: <20240429213050.55177-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org @tcg_cflags is specific to TCG accelerator, move it to its AccelCPUState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-23-philmd@linaro.org> --- accel/tcg/vcpu-state.h | 2 ++ include/hw/core/cpu.h | 4 +--- accel/tcg/cpu-exec.c | 6 +++--- linux-user/main.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h index 0cb58ba734..6c12bd17df 100644 --- a/accel/tcg/vcpu-state.h +++ b/accel/tcg/vcpu-state.h @@ -11,9 +11,11 @@ /** * AccelCPUState: vCPU fields specific to TCG accelerator + * @cflags: Pre-computed cflags for this cpu. * @plugin_state: per-CPU plugin state */ struct AccelCPUState { + uint32_t cflags; uint32_t cflags_next_tb; sigjmp_buf jmp_env; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6e6e946b66..14e96aae85 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -394,9 +394,8 @@ struct qemu_work_item; * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER * QOM parent. - * Under TCG this value is propagated to @tcg_cflags. + * Under TCG this value is propagated to @accel->cflags. * See TranslationBlock::TCG CF_CLUSTER_MASK. - * @tcg_cflags: Pre-computed cflags for this cpu. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU core. * @running: #true if CPU is currently running (lockless). @@ -515,7 +514,6 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; int cluster_index; - uint32_t tcg_cflags; uint32_t halted; int32_t exception_index; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8f8e1fa948..84fd041aec 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -149,17 +149,17 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) bool tcg_cflags_has(CPUState *cpu, uint32_t flags) { - return cpu->tcg_cflags & flags; + return cpu->accel->cflags & flags; } void tcg_cflags_set(CPUState *cpu, uint32_t flags) { - cpu->tcg_cflags |= flags; + cpu->accel->cflags |= flags; } uint32_t curr_cflags(CPUState *cpu) { - uint32_t cflags = cpu->tcg_cflags; + uint32_t cflags = cpu->accel->cflags; /* * Record gdb single-step. We should be exiting the TB by raising diff --git a/linux-user/main.c b/linux-user/main.c index 5f7f03f4b0..8be06627da 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -241,7 +241,7 @@ CPUArchState *cpu_copy(CPUArchState *env) /* Reset non arch specific state */ cpu_reset(new_cpu); - new_cpu->tcg_cflags = cpu->tcg_cflags; + new_cpu->accel->cflags = cpu->accel->cflags; memcpy(new_env, env, sizeof(CPUArchState)); #if defined(TARGET_I386) || defined(TARGET_X86_64) new_env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, From patchwork Mon Apr 29 21:30:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41832C19F4F for ; Mon, 29 Apr 2024 21:32:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1Ybf-0008QI-C5; Mon, 29 Apr 2024 17:32:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1YbR-000801-Gy for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:32:03 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s1YbP-0003Qk-3e for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:32:01 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-41bab13ca80so23217915e9.0 for ; Mon, 29 Apr 2024 14:31:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714426316; x=1715031116; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tfSxeazt7Q51HYWou2L26AE+iHM/oq4pGi/blYA/P4Y=; b=ICfY/fMgQzNBivJPUrXqqN5v25t0E0Nj7BgaJGGS7k9F/FZOc27jcF9nVbW/WphESH IEsArkkSSJuXteHG/bC23DU280ILCOMocLxNLrOCs7H1zWtFKIIw+Yc2nVQrHlmloOxK HorkdvPsfRt47ic6zUt2C9XCAO4r30kQ2YHKTpXwSBuwkYudwbtMNolpa6EfaPAe4UzW PmM2uPacIutAvXtO0nA9fReWnq3UVInoqT2IBgcba4J/o48sqVlJpwneIYtjtzFLUqF/ OZiuNrwWVSIBIZf/BX6YIfSWyXXCVX5KH+2gMzn6cd++Ir58Efnytq/OS0brdZAscWNI T/GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714426316; x=1715031116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tfSxeazt7Q51HYWou2L26AE+iHM/oq4pGi/blYA/P4Y=; b=QXX+iGgo+hoYIU5knbQIDBuVGn2cktugwxA+q37ZGpYTg2f5yIsQo2Gd48JE/FBTzs C1yiaIm7r3o8Mrw+K1HwMBAM+PWk+rtArrcP1WLKkdqyiL9YSqcQsnKIXCmTZ4Az79l0 7HiiLrWWUf0FKphdgR7qdWD08z2MBW3eagfoZQIaBtvVZcsVTQZpdVYALA0IT/aul+PV jPvSyY2u5cZrpKzRhDwNIjGp+yZ69dxkN2WmmkdfdMdJex4+9zvmGpOFfNsy5jnUxasy 5sI1theVhnMVpf4JQ8GeBUrRq5soGOOQZx/BgJNCN16Q3Jax1qyQ8bfrnkMvyzph/XQi Q+lg== X-Gm-Message-State: AOJu0YyjHulAQWcGVk1wvTbPcyIFR415Ns4wpWpleWrBFOtdj4Vkkdet 89vsVbAhKRpH3v308KjU800kklM9PXMOY4pOEvnz50c626D6LI6C6rOz6NBACSH+D6CsbkFYXjf RMps= X-Google-Smtp-Source: AGHT+IE8iSh08CH90dVsvjuLVxjDAp5bMaQPzt39SOvA08+w543WKyWb09aubBDK4W0uM1zhUxh2NQ== X-Received: by 2002:a05:600c:4ecb:b0:418:b9fa:43e9 with SMTP id g11-20020a05600c4ecb00b00418b9fa43e9mr10427431wmq.29.1714426316239; Mon, 29 Apr 2024 14:31:56 -0700 (PDT) Received: from m1x-phil.lan (bny92-h02-176-184-44-142.dsl.sta.abo.bbox.fr. [176.184.44.142]) by smtp.gmail.com with ESMTPSA id e7-20020a5d65c7000000b00349eb6eae3esm30745100wrw.4.2024.04.29.14.31.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:31:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 12/13] accel/tcg: Restrict icount to system emulation Date: Mon, 29 Apr 2024 23:30:49 +0200 Message-ID: <20240429213050.55177-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org So far we don't support icount on user emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-24-philmd@linaro.org> --- accel/tcg/cpu-exec.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 84fd041aec..1f618f6c2e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -780,6 +780,9 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) static inline bool icount_exit_request(CPUState *cpu) { +#if defined(CONFIG_USER_ONLY) + return false; +#else if (!icount_enabled()) { return false; } @@ -787,6 +790,7 @@ static inline bool icount_exit_request(CPUState *cpu) return false; } return cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0; +#endif } static inline bool cpu_handle_interrupt(CPUState *cpu, @@ -801,12 +805,14 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, return false; } +#if !defined(CONFIG_USER_ONLY) /* Clear the interrupt flag now since we're processing * cpu->interrupt_request and cpu->exit_request. * Ensure zeroing happens before reading cpu->exit_request or * cpu->interrupt_request (see also smp_wmb in cpu_exit()) */ qatomic_set_mb(&cpu->neg.icount_decr.u16.high, 0); +#endif /* !CONFIG_USER_ONLY */ if (unlikely(qatomic_read(&cpu->interrupt_request))) { int interrupt_request; From patchwork Mon Apr 29 21:30:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13647766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C9F1C4345F for ; Mon, 29 Apr 2024 21:32:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s1Ybv-0000Ks-9J; Mon, 29 Apr 2024 17:32:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s1YbV-00083E-Gt for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:32:07 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s1YbT-0003Rd-Fq for qemu-devel@nongnu.org; Mon, 29 Apr 2024 17:32:05 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-41c7ac71996so6467355e9.3 for ; Mon, 29 Apr 2024 14:32:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714426321; x=1715031121; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v2SW+/jg7KyBmqHR72nO3ki7+1M5U4SybhOT6/FbSqI=; b=wLJKqUHqRIjURHzdX5/Juuywnaoqh9xtaZy8Hvt6cQGyW4S+fXpyKOlbR6A5lJCbd4 DSvp/ATBVEyJ6csp2wH0yhO02Fcd1EYdHmO++1x6yAF9GHzoVp4e6e/+Id3FPYEJaEJX 0A9anjprktUVVig4xKYcoJVCAh8FeyejQ5aRZKfQwRhQRBuxnTySm4jcR87J6Xe7NqR3 kw+AqGgDY1iYIrWhJmGZg9dO7MM/N4uEgI6uODiiyiFq760lvea0SOksimWvpVkBOcv1 2GJYLUCBH96ntOgsbC4LSPGQQzq3G29FX/hu9fWdFYX9CNmt33TJ7FKZGh8VrSGCZ4DZ FKuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714426321; x=1715031121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v2SW+/jg7KyBmqHR72nO3ki7+1M5U4SybhOT6/FbSqI=; b=OGsnCG/LiUtg8vLOFXfzf5M5s6FEqs2JJeLRFm0ii+3kEhBvFoSRZ/47v8/i7/H+Gc fnJrmveqNeLR7dorTodx/qf8yxIK3cvcbbDC9tcAlgVXBnzSRr56zcVFpj47P30kA4SD kQlv+4SUgMuRH0TXHU7vxpYsftbck9f4fZJA/nxIzXGjDG1mlV2ojUWWy8T+trQJ6vbc IlxL+AxfEGx+//GaZyy0YgaYBwhJSuKOH+AfwwniiCy5xT4MeyASLFvmymloAeTUT1Jz v6qkFGqQ2IpyBJbsA/araokwomPTo25lgD4cPYYy6Ty7bsdrDU9OyubYUaHM8TWQUcqW K4UQ== X-Gm-Message-State: AOJu0YwyrX2PhP+BZ4sKhAi3blUiGqAmV9VhYDzieiqMU3zr9JFukrKA Hk4gCXdsKZzvZ3v5k1ySCTgE2/+1+MJYHYEuHRIZzLZrfq3sW2uAUlGI55uVwt7qdoU/3yycuV9 qx54= X-Google-Smtp-Source: AGHT+IFQgSlCSS0IpCSB/SPTvzirChnBXnGahzno3vQ4eP7ea7AVbRd1fC2h0+Ji+pRVzhUvnoFmQw== X-Received: by 2002:a05:600c:3d0c:b0:41c:7bd:5a84 with SMTP id bh12-20020a05600c3d0c00b0041c07bd5a84mr3851793wmb.17.1714426321615; Mon, 29 Apr 2024 14:32:01 -0700 (PDT) Received: from m1x-phil.lan (bny92-h02-176-184-44-142.dsl.sta.abo.bbox.fr. [176.184.44.142]) by smtp.gmail.com with ESMTPSA id n2-20020adfe342000000b00343eac2acc4sm30470654wrj.111.2024.04.29.14.32.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Apr 2024 14:32:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 13/13] accel/tcg: Move icount fields from CPUState to TCG AccelCPUState Date: Mon, 29 Apr 2024 23:30:50 +0200 Message-ID: <20240429213050.55177-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240429213050.55177-1-philmd@linaro.org> References: <20240429213050.55177-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Both @icount_budget and @icount_extra fields are specific to TCG accelerator, move them to its AccelCPUState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-25-philmd@linaro.org> --- accel/tcg/vcpu-state.h | 4 ++++ include/hw/core/cpu.h | 3 --- accel/tcg/cpu-exec.c | 14 +++++++------- accel/tcg/icount-common.c | 7 ++++--- accel/tcg/tcg-accel-ops-icount.c | 14 +++++++------- accel/tcg/tcg-accel-ops.c | 1 + hw/core/cpu-common.c | 1 - 7 files changed, 23 insertions(+), 21 deletions(-) diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h index 6c12bd17df..7fff5413e9 100644 --- a/accel/tcg/vcpu-state.h +++ b/accel/tcg/vcpu-state.h @@ -12,6 +12,7 @@ /** * AccelCPUState: vCPU fields specific to TCG accelerator * @cflags: Pre-computed cflags for this cpu. + * @icount_extra: Instructions until next timer event. * @plugin_state: per-CPU plugin state */ struct AccelCPUState { @@ -24,6 +25,9 @@ struct AccelCPUState { #ifdef CONFIG_USER_ONLY TaskState *ts; #else + int64_t icount_budget; + int64_t icount_extra; + /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; #endif /* !CONFIG_USER_ONLY */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 14e96aae85..c0c28befd3 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -409,7 +409,6 @@ struct qemu_work_item; * @unplug: Indicates a pending CPU unplug request. * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU * @singlestep_enabled: Flags for single-stepping. - * @icount_extra: Instructions until next timer event. * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the * AddressSpaces this CPU has) * @num_ases: number of CPUAddressSpaces in @cpu_ases @@ -470,8 +469,6 @@ struct CPUState { /* updates protected by BQL */ uint32_t interrupt_request; int singlestep_enabled; - int64_t icount_budget; - int64_t icount_extra; uint64_t random_seed; QemuMutex work_mutex; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 1f618f6c2e..7c21542e52 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -74,7 +74,7 @@ static void align_clocks(SyncClocks *sc, CPUState *cpu) return; } - cpu_icount = cpu->icount_extra + cpu->neg.icount_decr.u16.low; + cpu_icount = cpu->accel->icount_extra + cpu->neg.icount_decr.u16.low; sc->diff_clk += icount_to_ns(sc->last_cpu_icount - cpu_icount); sc->last_cpu_icount = cpu_icount; @@ -125,7 +125,7 @@ static void init_delay_params(SyncClocks *sc, CPUState *cpu) sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock; sc->last_cpu_icount - = cpu->icount_extra + cpu->neg.icount_decr.u16.low; + = cpu->accel->icount_extra + cpu->neg.icount_decr.u16.low; if (sc->diff_clk < max_delay) { max_delay = sc->diff_clk; } @@ -718,7 +718,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (cpu->exception_index < 0) { #ifndef CONFIG_USER_ONLY if (replay_has_exception() - && cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0) { + && cpu->neg.icount_decr.u16.low + cpu->accel->icount_extra == 0) { /* Execute just one insn to trigger exception pending in the log */ cpu->accel->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) | CF_NOIRQ | 1; @@ -789,7 +789,7 @@ static inline bool icount_exit_request(CPUState *cpu) if (!(cpu->accel->cflags_next_tb == -1 || cpu->accel->cflags_next_tb & CF_USE_ICOUNT)) { return false; } - return cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0; + return cpu->neg.icount_decr.u16.low + cpu->accel->icount_extra == 0; #endif } @@ -941,9 +941,9 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, /* Ensure global icount has gone forward */ icount_update(cpu); /* Refill decrementer and continue execution. */ - int32_t insns_left = MIN(0xffff, cpu->icount_budget); + int32_t insns_left = MIN(0xffff, cpu->accel->icount_budget); cpu->neg.icount_decr.u16.low = insns_left; - cpu->icount_extra = cpu->icount_budget - insns_left; + cpu->accel->icount_extra = cpu->accel->icount_budget - insns_left; /* * If the next tb has more instructions than we have left to @@ -952,7 +952,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, */ if (insns_left > 0 && insns_left < tb->icount) { assert(insns_left <= CF_COUNT_MASK); - assert(cpu->icount_extra == 0); + assert(cpu->accel->icount_extra == 0); cpu->accel->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left; } #endif diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index 8d3d3a7e9d..ff503f8e96 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -38,6 +38,7 @@ #include "sysemu/cpu-timers.h" #include "sysemu/cpu-throttle.h" #include "sysemu/cpu-timers-internal.h" +#include "accel/tcg/vcpu-state.h" /* * ICOUNT: Instruction Counter @@ -71,8 +72,8 @@ static void icount_enable_adaptive(void) */ static int64_t icount_get_executed(CPUState *cpu) { - return (cpu->icount_budget - - (cpu->neg.icount_decr.u16.low + cpu->icount_extra)); + return (cpu->accel->icount_budget - + (cpu->neg.icount_decr.u16.low + cpu->accel->icount_extra)); } /* @@ -83,7 +84,7 @@ static int64_t icount_get_executed(CPUState *cpu) static void icount_update_locked(CPUState *cpu) { int64_t executed = icount_get_executed(cpu); - cpu->icount_budget -= executed; + cpu->accel->icount_budget -= executed; qatomic_set_i64(&timers_state.qemu_icount, timers_state.qemu_icount + executed); diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c index 9e1ae66f65..75073ec23f 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -112,16 +112,16 @@ void icount_prepare_for_run(CPUState *cpu, int64_t cpu_budget) * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt */ g_assert(cpu->neg.icount_decr.u16.low == 0); - g_assert(cpu->icount_extra == 0); + g_assert(cpu->accel->icount_extra == 0); replay_mutex_lock(); - cpu->icount_budget = MIN(icount_get_limit(), cpu_budget); - insns_left = MIN(0xffff, cpu->icount_budget); + cpu->accel->icount_budget = MIN(icount_get_limit(), cpu_budget); + insns_left = MIN(0xffff, cpu->accel->icount_budget); cpu->neg.icount_decr.u16.low = insns_left; - cpu->icount_extra = cpu->icount_budget - insns_left; + cpu->accel->icount_extra = cpu->accel->icount_budget - insns_left; - if (cpu->icount_budget == 0) { + if (cpu->accel->icount_budget == 0) { /* * We're called without the BQL, so must take it while * we're calling timer handlers. @@ -139,8 +139,8 @@ void icount_process_data(CPUState *cpu) /* Reset the counters */ cpu->neg.icount_decr.u16.low = 0; - cpu->icount_extra = 0; - cpu->icount_budget = 0; + cpu->accel->icount_extra = 0; + cpu->accel->icount_budget = 0; replay_account_executed_instructions(); diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index d9132a5835..3b28cab0b5 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -89,6 +89,7 @@ static void tcg_cpu_reset_hold(CPUState *cpu) qatomic_set(&cpu->neg.icount_decr.u32, 0); cpu->neg.can_do_io = true; + cpu->accel->icount_extra = 0; cpu->accel->cflags_next_tb = -1; } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 073eb75ad0..c8e6f63943 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -121,7 +121,6 @@ static void cpu_common_reset_hold(Object *obj, ResetType type) cpu->interrupt_request = 0; cpu->halted = cpu->start_powered_off; cpu->mem_io_pc = 0; - cpu->icount_extra = 0; cpu->exception_index = -1; cpu->crash_occurred = false;