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([2001:8f8:1d3a:4eb3:9dcd:1735:fcaa:e2]) by smtp.gmail.com with ESMTPSA id rn24-20020a170906d93800b00a52433f0907sm402630ejb.37.2024.05.02.03.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 May 2024 03:36:34 -0700 (PDT) From: Dmitrii Bundin To: dmitrii.bundin.a@gmail.com Cc: airlied@gmail.com, bp@suse.de, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, gongruiqi1@huawei.com, intel-gfx@lists.freedesktop.org, jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, linux-kernel@vger.kernel.org, michal.wajdeczko@intel.com, rdunlap@infradead.org, rodrigo.vivi@intel.com, tursulin@ursulin.net Subject: [PATCH RESEND] drm/i915/guc: Fix UB due to signed int overflow Date: Thu, 2 May 2024 13:36:18 +0300 Message-Id: <20240502103618.129017-1-dmitrii.bundin.a@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240413031747.2416581-1-dmitrii.bundin.a@gmail.com> References: <20240413031747.2416581-1-dmitrii.bundin.a@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Fix compile errors of the form "FIELD_PREP: mask is not constant" caused by signed integer constant overflow. Files affected: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c Reproducible with gcc 7.5 See https://lore.kernel.org/r/YkwQ6%2BtIH8GQpuct@zn.tnic for the gory details as to why it triggers with older gccs only. Signed-off-by: Dmitrii Bundin --- drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h index 58012edd4eb0..8814d4cd371c 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h @@ -29,7 +29,7 @@ */ #define GUC_KLV_LEN_MIN 1u -#define GUC_KLV_0_KEY (0xffff << 16) +#define GUC_KLV_0_KEY (0xffffU << 16) #define GUC_KLV_0_LEN (0xffff << 0) #define GUC_KLV_n_VALUE (0xffffffff << 0)