From patchwork Thu May 2 10:40:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 13651592 Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B4F160DCF; Thu, 2 May 2024 10:40:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.15.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646420; cv=none; b=EtcvTWw+eV28DS5uqtxPOpEfX3ZXF5WW35/2qY2s+7sKQxXcfPBLy2sqOiW5rcAUPL+Ir8i6b3h51YJ/u+pyMTT1Lp3Fh1pIB+63aLl7vgVu7+Sw999o68I2YyQIDvaMhlUFeOvk40SV8iaDjS6I8dpc7voAvEEsZW8MJM5x3XY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646420; c=relaxed/simple; bh=gMCt5Iq5T+zQRh8ES75BAko3Tzsm5Fh8qCw+HGMCgfY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QrkBMhmXdr1TU/576Wio8inj01W2krCgmmV7lyBRm+NzxkPRPlYjs0XF12mbKVieJoIk6KIQ59UbdhkuSy6fNd7YHtTp2vRtyseA7Vu20a5cBrx2cxLzIqfsniCEadNXGWD0XDdMN70hc7gSP0euZAd/Jj7j3AlQIwj/T4SPbTI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net; spf=pass smtp.mailfrom=gmx.net; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b=QgNZ/ikm; arc=none smtp.client-ip=212.227.15.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmx.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b="QgNZ/ikm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmx.net; s=s31663417; t=1714646409; x=1715251209; i=j.neuschaefer@gmx.net; bh=L/WjbQC0Uxb9SVhmo+C44+NRCf/fM7QYCwbjyktZyvc=; h=X-UI-Sender-Class:From:Date:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding:Message-Id:References:In-Reply-To:To:Cc: cc:content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=QgNZ/ikmcNhUGzkceWnmNKR1XAtmX/MqYLTS5gMGSJlziMyl6mCqekrLqU0YMoqn a5APTpQ8X/Srp2rIFKGP8gOf2F/l/yZVthgkvE/YmnaEVBQx4zx1Y9UoGWCQmMzFW CMOpWAMyPsGhEdVi8T9jO652dnFr4TKE2hwltpe30IjzQK01WQwjha6VWZF6GA8vP pioa/EaMamj0YpPxInbPXE3kGXRpKhLFKa1gSWXy9qd/2O+xl1hvsS4DlyhlxsX/6 nTnBj/S4+JbyQUPZtReD0k7+xXFVa0zaQtu65HVibscPysGq+uuiKLiOm03dmQ+iB RSB69sErV8Vcr1dtlw== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([89.1.59.78]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1M6Ue3-1s00sy1x97-008Ty4; Thu, 02 May 2024 12:40:09 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Date: Thu, 02 May 2024 12:40:00 +0200 Subject: [PATCH v12 1/6] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240502-wpcm-clk-v12-1-1d065d58df07@gmx.net> References: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> In-Reply-To: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> To: openbmc@lists.ozlabs.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Philipp Zabel , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714646407; l=5540; i=j.neuschaefer@gmx.net; s=20240329; h=from:subject:message-id; bh=QPzdQUVDkB9QA3Xv6+gOkAHNqMRKKV6HeNLuZ6QtTHg=; b=jScqKHaCCM4wpdas5Q8IEiC4+jogSt+C1vQr+GGxaIt6XfDYmvN+772+LvhvyDRnzJBRzMxHO zAksyNaZt2MBGDJhh+vgxSzsnl+BbabtBP/njIrJDrVRcUgpzPz/TbB X-Developer-Key: i=j.neuschaefer@gmx.net; a=ed25519; pk=NIe0bK42wNaX/C4bi6ezm7NJK0IQE+8MKBm7igFMIS4= X-Provags-ID: V03:K1:5VER75uzSdDA4mmQwpBXPbQfADXqztMpC36lRk/cg57psmjNCBa yCGWxgpVP9EE//NF79nzToYwLyFiRyUyb3QbyNfILj+8mDSCVP6S4lX5W/wPiJUc1tjg9c1 hR+wk99j1Z8JPY43DXXLYHVwqzPiWCt0IVdJEomraXDyJpujPi0B6RIMo7gtJt+o8oyjGCQ EyczDx7WrKWPKprax3RUQ== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:EtsfR5Rcu8o=;zumcOV0z+TRMIQaNPiRveTY8YfO e1nQ+aq3bItzoUKp+4vtKDa5GWn1C9kh4fC8hr27vtInhefUDVz3pAgnzFwEa88sYPkYbQcbs 99Jho5WPf/rPalxfndgidW6NGYEUIMzBp06gLmKJpYaC/sir1LF+gGjoX1MwEObJk7OK9lRUa Zx3DtPtUnVV9mOMi9O8WLrQar483eXl9XgD/h3vPMwFFg+EpifiIEkL7cF4qSQNmx96QLD0sq DKeft5gMruVR7TG1TAHSnTIV42Umk/bwkJ6cr3O154vGqBwyfkgSTVGB0j+i/htD591jZ/FEh /UAvPFk7iByrhdsYG6+BhORRjpGuT+owOnavhVmTMMMYZYVKriOgdGeghl5oTM3MyGqL9CKg0 KtYArW9fc42UXiy+9/fExpsbz7mTToXIW5JasI8HgDw80zBMVV6m8WSFreHgmKvsAaeoA0MkR fF4Nv823auZAeFSF8C4rk/6d/E7iXon9rLL6BSHoI4CAnLpAXvg6K3mh4DCbkr2k0DG7slD1Y eN3qDtmbl6RKVILw0oLECAhZXZSw6osdZojVTXXuOhGzBGtN5ZqIPhlVkTNKZGHuYASzzNlXr u3AOi/jKB3nTRqGL+2o1+whtbo9I46ESZCzinQlsSTv2W6r+LPeeKZfqy/aosUAsGlQl2uyiw tEgxM8B4VlBW3LJt7rjsYWE+BYWXS0JEqf1e5+zUJJ5xetyIXsmGaTh+Bn99fNs15Gl0okPGN v0Gv6c/USYPKPoFM0hjRM9JusV0uEmUW7ZOYh0XVXGasgWFnHEm5OdBAVnCZXO+LwGHgNauPR mmigDerSHeHMIBjNUrPGfyYTk7jwyRg8EhGUCtry4KpsQ= The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski --- v10-v11: - no changes v9: - Remove clock-output-names in example, because it's now unnecessary due to driver improvements v5-v8: - no changes v4: - https://lore.kernel.org/lkml/20220610072141.347795-4-j.neuschaefer@gmx.net/ - Add R-b tag v3: - Change clock-output-names and clock-names from "refclk" to "ref", suggested by Krzysztof Kozlowski v2: - https://lore.kernel.org/lkml/20220429172030.398011-5-j.neuschaefer@gmx.net/ - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.net/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 65 +++++++++++++++++++++ include/dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 ++++++++++++++++++++++ 2 files changed, 132 insertions(+) -- 2.43.0 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 00000000000000..93521cf68a040f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neuschäfer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: ref + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 00000000000000..86e1c895921b71 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */ From patchwork Thu May 2 10:40:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 13651595 Received: from mout.gmx.net (mout.gmx.net [212.227.15.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 861AF62A02; Thu, 2 May 2024 10:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.15.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646422; cv=none; b=U3BoXs4TNBA7Hk1jRRBs0vf3Dmsv9pmxAqLBMnllG4jqR4iRPoGuwbsfMIFWHFcu1YgG9omR93zcYozpSMsSNYrJhTCEt9R/1ql1fP4U+QeJYDWO3ZPwfm4dpMsc26kjmJd7VClikfgHIcLbWOe4fHjFJBVrpoCewBXPnFu2Ajk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646422; c=relaxed/simple; bh=JGRuPp5f7tdBTXkrWe9oHs1o3E3gbeMCdlehVi8h2jw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PKsGLSuuOE0RgInirH3U0TXeNYbJYclBv11LT0o5xv0dXkW7oTpsKF6rqdNnMc81B99cp219Ea+6CXsGPeUfg5yRzAQ0NOosrfP1dSojU9f0HLWo6oT1urQqmb5ChjJHctVE3D3cacEBa2xI6wg5CmV5vivqT7sa7lMTWvEojRQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net; spf=pass smtp.mailfrom=gmx.net; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b=XBLWkNmf; arc=none smtp.client-ip=212.227.15.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmx.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b="XBLWkNmf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmx.net; s=s31663417; t=1714646410; x=1715251210; i=j.neuschaefer@gmx.net; bh=n2e88QE5epBSVSFicZ+xqo5ic/O/WtKAyeT8qBcSr5U=; h=X-UI-Sender-Class:From:Date:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding:Message-Id:References:In-Reply-To:To:Cc: cc:content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=XBLWkNmfCJ1LedKg3QzKOShdZwoK6kFYjyQw/5JCleg+m/Gjyccbsf6m5QDis+k3 O+4SPBRi7Iug7uD6urGq49hnCnmmdCs31cgjhoWPS25aA7/v4GEaF3BRN7k0DWtn+ uqyR3c5esbjjICJewjr7m+RH8akfkXXKRUeTk0ZxJv42irC2RsoDzTCjVtnTWvchF Kizs2Dd1Z0zUs+MgcHu52zY3WfHFmhcp0C7AJWsBPGNybVObj+Ca/cL6VZU1R55qZ p/1RemQ6Jd+U4Z/1H0+OysAXQCC0IS+XW6g9I2KvGDFRD03IZek87QaqmAxVGguZ8 YaICM0tgtth2wcK7vg== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([89.1.59.78]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MIwzA-1sLedM12Lq-00LJxi; Thu, 02 May 2024 12:40:10 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Date: Thu, 02 May 2024 12:40:01 +0200 Subject: [PATCH v12 2/6] clk: Introduce devm_clk_hw_register_divider_table_parent_data() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240502-wpcm-clk-v12-2-1d065d58df07@gmx.net> References: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> In-Reply-To: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> To: openbmc@lists.ozlabs.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Philipp Zabel , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714646407; l=1760; i=j.neuschaefer@gmx.net; s=20240329; h=from:subject:message-id; bh=VjLniaHS+bKcYFjCZNozqsTADYqMusOVNK5lpprhRBg=; b=sX4JaPRF9uqkZaXe/H1tOsITjWEPOfX/cwh/WwBgOmdfDzoHO0R2RxVm1FhomjMVU8eItiw57 TLL9wD7ORzjBP1MKzRgE1q4qCvMKspuYEz8Rmmb1TruJORjL9UNGrzD X-Developer-Key: i=j.neuschaefer@gmx.net; a=ed25519; pk=NIe0bK42wNaX/C4bi6ezm7NJK0IQE+8MKBm7igFMIS4= X-Provags-ID: V03:K1:+DtwGYQjt2x8GVjHjT0VdQrQ5fiyA2Cpx2yeh9o2vTCRIYKNWoU OJ62sDPJ3xaCTsmcqVyLNjeHcft6kh70vSEzkYGZMED6eI9Mz4FHzqDLzhWVJAk0JTbDv6w jp5yVlw/MiWWmdhY7Af9U5GnOegLYn4JEBN5X71PXHNytZs7tHQ8COnZvnpUOptn5EP4ty8 rxFlstpwa0tybgy5hjOzw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:czppJQZDsyY=;SpRHVuFG/OdBmW0gPVgXKhqSBVm YV0f5C289zEt29eERNBiaRHOsFpIj9KKOACl5VF2fZ/rYfd+JdS/xbZdkED2eGeIElq9xIi4J /sLh5tNaYBPvdSVYxzoOxVjQKu8gPeLpxxwS6fJS5HtIsXkTTibRrwRlWi2ObhoQNPZkX4kcZ 8/VznYrGJixio/PJTyLxHB3ziFnhEFpQPUSQwPf1hyh+DJptEGzcn9kq2yGhD+0lvJ9MFwLNA TrKORAVJb22FzCR0ySckD01/63k5WW9zYCbzqNMOQHmssGuAWvRiBI/vdN+C5FR6c66v9YzGq Ll3Vj0yT/f9v9JioU3zGRZZ/oCetZbi2hiXVPaY2bZVTgWYK0horYBwpH2ekbVb1w17cT6Z5r Jf+tGIHqphyhvnmr4nA/2/4U10PqkfLZQPzCPV+IgXmib3D4maloXooUTd1Lflsdsy8h07qlr 56fYoI8PKWea1Z38iucmfzaRCPhU7wv2Qk+Mb9Wk4c8N0SfA+zoZhes++qNAdrNmEa2iXDu1f Th5QMhX5XwDzxkW9g6s6FwEqvjy7VoGEtXf+WmnuyZQ9UW50aZ/B64WpQACoT5BBRQfKNdoOm AB7d040y4Cwn8+mu4Ron1IuU59qhQNltazJwJAIJWxP/dQkgX+mUzvQueQiIXmX9zthktzy4I wsF4XUVJPGmU+SXsQxsMRYJlfiT0sxP2G4Jc4XuLzszN28pejtWYjcC/gfi8Q5QWrw4qo21oS VIhpKFQomIbcjuECA/afO5g0SE6PX/i4I02TNJ4CsisT6+7F9/m9X46mxrAHABgQwUIeI/faD SXpzTkZnmBpAR4yUtTI4YvOSSIpuT7se3CDE4LL0JuJro= Introduce the devm pendant to clk_hw_register_divider_table_parent_data. Signed-off-by: Jonathan Neuschäfer --- include/linux/clk-provider.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.43.0 diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 4a537260f6557d..5d537d0776a11f 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -932,6 +932,28 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, (width), (clk_divider_flags), (table), \ (lock)) +/** + * devm_clk_hw_register_divider_table_parent_data - register a table based divider clock + * with the clock framework (devres variant) + * @dev: device registering this clock + * @name: name of this clock + * @parent_data: parent clk data + * @flags: framework-specific flags + * @reg: register address to adjust divider + * @shift: number of bits to shift the bitfield + * @width: width of the bitfield + * @clk_divider_flags: divider-specific flags for this clock + * @table: array of divider/value pairs ending with a div set to 0 + * @lock: shared register lock for this clock + */ +#define devm_clk_hw_register_divider_table_parent_data(dev, name, parent_data, flags, \ + reg, shift, width, \ + clk_divider_flags, table, lock) \ + __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \ + NULL, (parent_data), (flags), (reg), (shift), \ + (width), (clk_divider_flags), (table), \ + (lock)) + void clk_unregister_divider(struct clk *clk); void clk_hw_unregister_divider(struct clk_hw *hw); From patchwork Thu May 2 10:40:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 13651593 Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8607F56B7B; Thu, 2 May 2024 10:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.15.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646421; cv=none; b=fGvQI5Dx4JkQvAXESQBN9Lptyrq0nWrEVUMrxRd2u2iQpzNpg6NUzxN4IPLcxZEOKkzB7Nd1nhmIqgiD0rcv93j0n5l23/UlrO6B5tGALXrxKkLKutOc6R5rqn27UEJ3BwgIdM0E/FVrj+hUZXyxu5UVIZo8ax1lN+S8ZQ7UXhc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646421; c=relaxed/simple; bh=O+bEwrnwg4S4cWN+/eKT9QwEoL56qOFANcTDwM8x0Jk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sSfd5mb+Yz7mXtg6bxss0Mge2zGvkjss+Zwei+35r2eLJpBaXvRAeV6GugB1k4lcLLjbBk5OtYulsA9fH/V23niVQpXYkpm0KMtJtvx3aENOG50rDe+cBYN2vEs6UZz/kuOet9sWxREXwPsQdqPiERbpOv2RUNvMBef31Zgyi1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net; spf=pass smtp.mailfrom=gmx.net; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b=cDDWlnqe; arc=none smtp.client-ip=212.227.15.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmx.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b="cDDWlnqe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmx.net; s=s31663417; t=1714646411; x=1715251211; i=j.neuschaefer@gmx.net; bh=mi0PezsKxlt4YHnZxxM0jZD6ggEqlUX2jNwgc7Ancas=; h=X-UI-Sender-Class:From:Date:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding:Message-Id:References:In-Reply-To:To:Cc: cc:content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=cDDWlnqeeZFFzxvFuSEHECtppp8V3bO4d0UkuCq3A5b73duZ4OZldbbzH0h+ta5k SbW2Kj7CgMwu+w4azimZSIEq+Vi06vhkqPKgIG8Pxw4nkEg2hHqrBa0bmIVAqrT8l 8S58133jSf5PKlaJR5E8BhZsdbiePGT29Yt1ZGs3pOrjegow9LXg3yiRqYGoQBxDd V54n9fQAnvdgFuEySX5S++5GMwWQsYwmCbpcs91ZOFCGgAxyrrvWtT8Th23H8htXf RWed7gP1ZhOCUJPbWZfE4olMjlj+HbHzpbZ4pA+QXcfWpGMtz9iw1/gkm3GmPgGhH YiBS7YbZr2PrVjfOcQ== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([89.1.59.78]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MvsEn-1stcLN3h0p-00sxJe; Thu, 02 May 2024 12:40:10 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Date: Thu, 02 May 2024 12:40:02 +0200 Subject: [PATCH v12 3/6] clk: provider: Address documentation pitfall in struct clk_parent_data Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240502-wpcm-clk-v12-3-1d065d58df07@gmx.net> References: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> In-Reply-To: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> To: openbmc@lists.ozlabs.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Philipp Zabel , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714646407; l=1209; i=j.neuschaefer@gmx.net; s=20240329; h=from:subject:message-id; bh=1uiYw4A/lLLh/mTtdxttn1wy5i6b5KyOE0h65+zswio=; b=q8eunMEY8w2HoF/7ikaMihIPI7LizlxmNI2AG/eDzXjlhl2U+uKHSEJT5Ym5KVbp87uTYyrJE AsUnl9akjWMChwF/fhXANkLvLIj7hWB8pZfRegYAJxtuh1LWZmKKMIZ X-Developer-Key: i=j.neuschaefer@gmx.net; a=ed25519; pk=NIe0bK42wNaX/C4bi6ezm7NJK0IQE+8MKBm7igFMIS4= X-Provags-ID: V03:K1:3o8FPKXfGjyk93wzOJ3/PA3/k/PDZ5csIAPUA7P5cEj1cE6h3Ft O8DBykUoXJLl5+vki/ykwSOk338sas9GAaDAp4a/4AVcQUSRxU2aGDTxXoc6Ui84Zc3kiNt NJfqgol6F557lCLuXn9wGKWqMZbYiuAPIsvZtz+vMfWByLLri5v9NKzn1qEpZjvA0ICVrna BlJyDfttl367Tv7+wr7Wg== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:rtAsOuEidkw=;ZNWcbyZHMyEKVXpZBIBuhL/i8/B e95tM5/mT/kG6qejGhOA9k8j4QINJtxDZf9bFnWv12BUJjIkcI3D+HdZGDbmAXLGFUqOByZuK trU+p1lm1TyWfZ6WSzUyM43lnvOJE4BTEuHqGqq7dMwotwRpE6EItROCIykUvm6/8Qpyvkbck 6XLsFjPlEYtadw1g44uWWI0MXsROdRY7mEzzu2byQ8V1zq2YuPDWWMRj2p6khcMHtttkmsLp3 G5jvBGtzpGuEsPIeam4CevcY1cHnzqpBhBoggZZlFnXCuUI8b1CCnnHHgOvYTbkVUT9ex+j1T jVdiGH5iKEr1GKQ7C2gimWr/Vnny84wkgLxOlE7cJKu/innA3po25mf1uRQi1BLEo26D3BfvB elPPat1dqFTf3BcSlZdXdV3qWMdaARZU3Q+7y8KUHc9d3iiyKNqAl6W+KAe697sbOxmFVxP5p YP8GAy5f3+CVMvDyxiLOGwl46mnXNmG3sF/k9qFrBNxVYNWVJzkYvvIz4hBMG+FaCpVkTJgJO PVGoN16Qu84/FrBPtpJF03gClgU4oJ+6wGAJtnYnhIkSxmE8SO1NGM2zBikST3G9OpHjQ0JHA taEQN2XluwoYFiF+aDZGSUJRgiL8zWjJ+HM+aGlviWgKYVfiUD7nKLTM71MpZuTU5YJHwqpVR TYfiv9cd4Q43U2FlA+ENxUD3GYLQMzKafcLStVAx/Mf7XRwswxew69TpX/wyek7Huu8PXJ7yU LZ6d7pHahHwMLc8+lbnofYDw3CHu+m9zOTKccJJHwRG+vedJHF6r54a+hKpJJM0xqjUcjdw9l Oa/tjKX7wcS/SujMgT9JfzT+WEPMTIPVHuRZLK6ffOWsA= For some reason, I understood the description of .index to mean an index into the list of clocks defined by the provider itself. This is not the case, and it caused me much confusion. Let's be a bit more explicit for those who read the documentation after me. Signed-off-by: Jonathan Neuschäfer --- include/linux/clk-provider.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.43.0 diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 5d537d0776a11f..88bdada390c772 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -273,7 +273,9 @@ struct clk_ops { * @hw: parent clk_hw pointer (used for clk providers with internal clks) * @fw_name: parent name local to provider registering clk * @name: globally unique parent name (used as a fallback) - * @index: parent index local to provider registering clk (if @fw_name absent) + * @index: parent index local to provider registering clk (if @fw_name absent). + * Note that this is not an index into the provider's own clocks but + * into its list of parents! */ struct clk_parent_data { const struct clk_hw *hw; From patchwork Thu May 2 10:40:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 13651597 Received: from mout.gmx.net (mout.gmx.net [212.227.15.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7EF164CE1; Thu, 2 May 2024 10:40:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.15.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646423; cv=none; b=Qt9U3/BzCa5BkJ9GFy2LtaYkTLG/CHkFP/HFIhbsgV48bDSlYRv2rMSgonFZ/dnp38zmTP1VqTGh38bvuapH9u2s/xgMN9OMXAUwLZJMtQOsYujmtEKXXDkwb6O56L1jDjZxQd/9o0EdfDpTLuhe+yfN9hJJ0etSG/MWKvMiNTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646423; c=relaxed/simple; bh=PsOAhD87v2rudFky9mbrnX0Iaw6zgWZq+OxC/Uc983E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i1/rKybA3BegrFNorvc2pwZdbHmeA5DRdWqNPwzBlsuzDGSzvBvh6PuW09VwOnIPxVkL7FcKXn8fWg1yI7IBhlEDFADfbA1feGiiHd14fm/BtpvRTDvMvhnvuN8T7/iVkFyjLOJLxaf/EYdMJKAICpOqBy3jSuAP+PWN6//kB/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net; spf=pass smtp.mailfrom=gmx.net; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b=Jg8Gfe21; arc=none smtp.client-ip=212.227.15.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmx.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b="Jg8Gfe21" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmx.net; s=s31663417; t=1714646411; x=1715251211; i=j.neuschaefer@gmx.net; bh=dklvWoDTcs2ZcyzzLa5WGCFsugD5VSmp2zIVjmINOMo=; h=X-UI-Sender-Class:From:Date:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding:Message-Id:References:In-Reply-To:To:Cc: cc:content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=Jg8Gfe214QOWT4BU9E0hQvTlxeYkyy1/re03faOe+M5d31F1RrdL50x+iG4UrFTD 4Mt2lrMVJ6hqeEwmWXgJtX5fupEOtsXEkje7pXiec0mimyHe6f5REDW7zJ3jCzRgG G7TvWEP14pqUgpOoGlz51CM5HAaRPyeB47KOvPQC8+78pmQyDd+g26IT85DJjONPP rISu2RngwdAyxIHBv3pWapeuxUSFMwzhpqYW0GHYwfCD9xcxV1TegSAd+beEpmr47 78ZN8zK2h3R/f7e+ncD/KJiajlwZodSZ0TP+KI6k0ntjIxucmCslIcN8sZcmvQ4zQ V09s1ZzRjTVGTGTGyA== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([89.1.59.78]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1M8QWA-1ry6952IFs-004Pjy; Thu, 02 May 2024 12:40:11 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Date: Thu, 02 May 2024 12:40:03 +0200 Subject: [PATCH v12 4/6] clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240502-wpcm-clk-v12-4-1d065d58df07@gmx.net> References: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> In-Reply-To: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> To: openbmc@lists.ozlabs.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Philipp Zabel , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714646407; l=18702; i=j.neuschaefer@gmx.net; s=20240329; h=from:subject:message-id; bh=CnpmnTxCPw0ZHYlAwXR+9/ZSlVlvc95MlZAI2y8gBo0=; b=cfcm0aT48EUF199a1yofwCNTD8yO+6PFBGVo0ggQ40vQzgh2dPgJOttIfMNdTL82YDN2yPshg Y4njONX2D1FD5HJGKLJVypj3NPGKxYPlVwXOsgUXXlbCdeekmmhOgKY X-Developer-Key: i=j.neuschaefer@gmx.net; a=ed25519; pk=NIe0bK42wNaX/C4bi6ezm7NJK0IQE+8MKBm7igFMIS4= X-Provags-ID: V03:K1:jnU9cFFuQFi7J5o/1ETIVh/ySc+b5TiDwALXWbFp3G+LFRBddWd l1PL+CTC1Y2Bl2p/bAaOeS2HtkUODBdZxzFk+oT882pujWkxwy4vy8wbqi/PRnjBm33pv00 ePBzORVDXLI11mi1IpjPhVNq98iLvHKFlJnANUf17p3bVgQ0/CbqYOOJO5EiHw4hajZwb4H 1CatE1SlXW+mNSgphC/0w== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:FlYGRevWqnY=;jAC2DJvnX32y7agU1g4JX133vKu ycQAWTQ49FZ/ORmrZ2XfNTjBiut/xI7DXtQGZ9fb32QFlpiF4s+c3sFrFCCKbcrwhbTOpItB1 L94ap8eeBlWar800D1YwI2Q+klSrjtl4rj1RTl8CRuMSi5Bki67yX5XhCgMVsUf7sdgmNuEtZ fV/PpNyMO3WdC4hhEIZJ3r5hcc4AKD9nHqEbYTuUvf0RZqih7OO/w5hL2q3gX1CzXsES67LHV DF0dqm9zn/AJ3PtvLQoCp5mHaJ+H4C/ZdI/oKBBZVO5GipK/6tbPcSjenWCqgmLvw7cFYaCCa wDJVOVv0AnM80kd9/X5+ggnMzJPkKNKYOmldVNJyPlErh4qgkSIAi8fLOMcEBUN+EnlN5rN5n hs5asbHIIDnK7HGRt6iRyJ++ufobFwCcyYrBPssNrYOGYhIk834X7abb/KyJV4GmTjEP1OjfT xbyqhFRiKRK1O0uZvKzSjStVp1OJuTttyPLWwyqm/ShntwRP+wVJwlwA9H8/TRpTRncIVyenI ZQSYCvwrGo8d2/pZKWFlKAxW4748GWceB0Cuiw65M2doXevO0luJrsZB67aKrFgz2yNr0qUOT nCLtFG5K8Qz4Kf9OsRCXrDZkD51bsUO8jV8Xu2HLv8V4zG35yxc24q5Clp7axTP/ssp7eT9rB PdVHD4/NCGuedhIKCD4qVLiA0umWq+3nZa6Krbvb7pQuyf29X4OSARpkkKZrdDTtNEGBbAiZU 9Y43xKEFHrbBtnWE3GeUseF2TRNiP+4BbTy4u11/AfHzCp6eJcTse/xooGVUOrWLwJTzLXSmV mMaLZDIQX/75GOQthviXrLDvSTh3dQQEqgoBZ4C4RLGVI= This driver implements the following features w.r.t. the clock and reset controller in the WPCM450 SoC: - It calculates the rates for all clocks managed by the clock controller - It leaves the clock tree mostly unchanged, except that it enables/ disables clock gates based on usage. - It exposes the reset lines managed by the controller using the Generic Reset Controller subsystem - A few clocks are marked as critical because they don't have consumers in the common clock framework: - CPU clock - timer clocks, because the timer-npcm7xx driver (in its current shape) can't depend on a platform driver (clk-wpcm450), but the timer clocks must not be disabled NOTE: If the driver and the corresponding devicetree node are present, the driver will disable "unused" clocks. This is problem until the clock relations are properly declared in the devicetree (in a later patch). Until then, the clk_ignore_unused kernel parameter can be used as a workaround. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Joel Stanley --- v12: - Switch ref clock inputs to .fw_name = "ref" - Use .hw to refer to internal clocks - Remove unnecessary pr_fmt definition - Convert to a platform driver, to avoid use of .name; use devm_ API - Mark timer0/1 clocks as critical - Update copyright year to 2024 - Split reset controller initialization into a separate function - Change MODULE_LICENSE to "GPL" according to commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity") v11: - no changes v10: - select RESET_{CONTROLLER,SIMPLE} from CLK_WPCM450 instead of messing with the 'default' statement v9: - Apply comments made by Stephen Boyd - Move to drivers/clk/nuvoton/ directory - Update SPDX license identifier from GPL-2.0 to GPL-2.0-only - Rename clk_np variable to np - Use of_clk_hw_register - Refer to clock parents by .fw_name v8: - https://lore.kernel.org/lkml/20230428190226.1304326-3-j.neuschaefer@gmx.net/ - Use %pe format specifier throughout the driver, as suggested by Philipp Zabel - Add Joel's R-b v7: - https://lore.kernel.org/lkml/20230422220240.322572-3-j.neuschaefer@gmx.net/ - Simplify error handling by not deallocating resources v6: - Enable RESET_SIMPLE based on ARCH_WPCM450, not ARCH_NPCM, as suggested by Tomer Maimon v5: - https://lore.kernel.org/lkml/20221104161850.2889894-6-j.neuschaefer@gmx.net/ - Switch to using clk_parent_data v4: - Fix reset controller initialization v3: - Change reference clock name from "refclk" to "ref" - Remove unused variable in return path of wpcm450_clk_register_pll - Remove unused divisor tables v2: - no changes --- drivers/clk/Makefile | 2 +- drivers/clk/nuvoton/Kconfig | 10 +- drivers/clk/nuvoton/Makefile | 1 + drivers/clk/nuvoton/clk-wpcm450.c | 455 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 466 insertions(+), 2 deletions(-) -- 2.43.0 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 14fa8d4ecc1fbe..cdeb2ecf3a8e99 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -107,7 +107,7 @@ endif obj-y += mstar/ obj-y += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ -obj-$(CONFIG_ARCH_MA35) += nuvoton/ +obj-y += nuvoton/ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ diff --git a/drivers/clk/nuvoton/Kconfig b/drivers/clk/nuvoton/Kconfig index fe4b7f62f46704..908881654b2e91 100644 --- a/drivers/clk/nuvoton/Kconfig +++ b/drivers/clk/nuvoton/Kconfig @@ -3,7 +3,7 @@ config COMMON_CLK_NUVOTON bool "Nuvoton clock controller common support" - depends on ARCH_MA35 || COMPILE_TEST + depends on ARCH_MA35 || ARCH_NPCM || COMPILE_TEST default y help Say y here to enable common clock controller for Nuvoton platforms. @@ -16,4 +16,12 @@ config CLK_MA35D1 help Build the clock controller driver for MA35D1 SoC. +config CLK_WPCM450 + bool "Nuvoton WPCM450 clock/reset controller support" + default y + select RESET_CONTROLLER + select RESET_SIMPLE + help + Build the clock and reset controller driver for the WPCM450 SoC. + endif diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile index c3c59dd9f2aaab..b130f0d3889ca0 100644 --- a/drivers/clk/nuvoton/Makefile +++ b/drivers/clk/nuvoton/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1.o obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-divider.o obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-pll.o +obj-$(CONFIG_CLK_WPCM450) += clk-wpcm450.o diff --git a/drivers/clk/nuvoton/clk-wpcm450.c b/drivers/clk/nuvoton/clk-wpcm450.c new file mode 100644 index 00000000000000..9a0f9c0bd8e6c8 --- /dev/null +++ b/drivers/clk/nuvoton/clk-wpcm450.c @@ -0,0 +1,455 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Nuvoton WPCM450 clock and reset controller driver. + * + * Copyright (C) 2024 Jonathan Neuschäfer + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct wpcm450_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_wpcm450_clk_pll(_hw) container_of(_hw, struct wpcm450_clk_pll, hw) + +#define PLLCON_FBDV GENMASK(24, 16) +#define PLLCON_PRST BIT(13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long wpcm450_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + unsigned long fbdv, indv, otdv; + u64 rate; + u32 pllcon; + + if (parent_rate == 0) + return 0; + + pllcon = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, pllcon) + 1; + fbdv = FIELD_GET(PLLCON_FBDV, pllcon) + 1; + otdv = FIELD_GET(PLLCON_OTDV, pllcon) + 1; + + rate = (u64)parent_rate * fbdv; + do_div(rate, indv * otdv); + + return rate; +} + +static int wpcm450_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + + return !(pllcon & PLLCON_PRST); +} + +static void wpcm450_clk_pll_disable(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + pllcon |= PLLCON_PRST | PLLCON_PWDEN; + writel(pllcon, pll->pllcon); +} + +static const struct clk_ops wpcm450_clk_pll_ops = { + .recalc_rate = wpcm450_clk_pll_recalc_rate, + .is_enabled = wpcm450_clk_pll_is_enabled, + .disable = wpcm450_clk_pll_disable +}; + +static struct clk_hw * +wpcm450_clk_register_pll(struct device *dev, void __iomem *pllcon, const char *name, + const struct clk_parent_data *parent, unsigned long flags) +{ + struct wpcm450_clk_pll *pll; + struct clk_init_data init = {}; + int ret; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &wpcm450_clk_pll_ops; + init.parent_data = parent; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + ret = devm_clk_hw_register(dev, &pll->hw); + if (ret) { + devm_kfree(dev, pll); + return ERR_PTR(ret); + } + + return &pll->hw; +} + +// Additional clock indexes for internal use. +enum { + WPCM450_CLK_REF = -1, + WPCM450_CLK_REFDIV2 = WPCM450_NUM_CLKS, + WPCM450_CLK_PLL0, + WPCM450_CLK_PLL1, + WPCM450_CLK_CPUSEL, + WPCM450_CLK_CLKOUT, + WPCM450_CLK_UARTSEL, + WPCM450_CLK_HUARTSEL, + WPCM450_CLK_CPU, + WPCM450_CLK_ADCDIV, + WPCM450_CLK_APB, + WPCM450_CLK_AHB, + WPCM450_CLK_AHB3, + WPCM450_CLK_UART, + WPCM450_NUM_CLKS_TOTAL +}; + +static struct clk_parent_data index_to_parent_data(struct clk_hw **hws, int index) +{ + struct clk_parent_data parent_data = {}; + + if (index == WPCM450_CLK_REF) + parent_data.fw_name = "ref"; + else + parent_data.hw = hws[index]; + + return parent_data; +} + +static size_t index_to_parent_data_array(struct clk_hw **hws, + const int *indexes, size_t num_indexes, + struct clk_parent_data *parent_data, + size_t num_parent_data) +{ + size_t i; + + for (i = 0; i < min(num_parent_data, num_indexes); i++) + parent_data[i] = index_to_parent_data(hws, indexes[i]); + + return i; +} + +#define REG_CLKEN 0x00 +#define REG_CLKSEL 0x04 +#define REG_CLKDIV 0x08 +#define REG_PLLCON0 0x0c +#define REG_PLLCON1 0x10 +#define REG_PMCON 0x14 +#define REG_IRQWAKECON 0x18 +#define REG_IRQWAKEFLAG 0x1c +#define REG_IPSRST 0x20 + +struct wpcm450_pll_data { + const char *name; + int index; + int parent; + unsigned int reg; + unsigned long flags; +}; + +static const struct wpcm450_pll_data pll_data[] = { + { "pll0", WPCM450_CLK_PLL0, WPCM450_CLK_REF, REG_PLLCON0, 0 }, + { "pll1", WPCM450_CLK_PLL1, WPCM450_CLK_REF, REG_PLLCON1, 0 }, +}; + +struct wpcm450_clksel_data { + const char *name; + int index; + const int *parents; + unsigned int num_parents; + const u32 *table; + int shift; + int width; + unsigned long flags; +}; + +static const u32 parent_table[] = { 0, 1, 2 }; + +static const int default_parents[] = { + WPCM450_CLK_PLL0, + WPCM450_CLK_PLL1, + WPCM450_CLK_REF, +}; + +static const int huart_parents[] = { + WPCM450_CLK_REF, + WPCM450_CLK_REFDIV2, +}; + +static const struct wpcm450_clksel_data clksel_data[] = { + { "cpusel", WPCM450_CLK_CPUSEL, default_parents, ARRAY_SIZE(default_parents), + parent_table, 0, 2, CLK_IS_CRITICAL }, + { "clkout", WPCM450_CLK_CLKOUT, default_parents, ARRAY_SIZE(default_parents), + parent_table, 2, 2, 0 }, + { "usbphy", WPCM450_CLK_USBPHY, default_parents, ARRAY_SIZE(default_parents), + parent_table, 6, 2, 0 }, + { "uartsel", WPCM450_CLK_UARTSEL, default_parents, ARRAY_SIZE(default_parents), + parent_table, 8, 2, 0 }, + { "huartsel", WPCM450_CLK_HUARTSEL, huart_parents, ARRAY_SIZE(huart_parents), + parent_table, 10, 1, 0 }, +}; + +static const struct clk_div_table div_fixed2[] = { + { .val = 0, .div = 2 }, + { } +}; + +struct wpcm450_clkdiv_data { + const char *name; + int index; + int parent; + int div_flags; + const struct clk_div_table *table; + int shift; + int width; + unsigned long flags; +}; + +static struct wpcm450_clkdiv_data clkdiv_data_early[] = { + { "ref/2", WPCM450_CLK_REFDIV2, WPCM450_CLK_REF, 0, div_fixed2, 0, 0 }, +}; + +static const struct wpcm450_clkdiv_data clkdiv_data[] = { + { "cpu", WPCM450_CLK_CPU, WPCM450_CLK_CPUSEL, 0, div_fixed2, 0, 0, CLK_IS_CRITICAL }, + { "adcdiv", WPCM450_CLK_ADCDIV, WPCM450_CLK_REF, CLK_DIVIDER_POWER_OF_TWO, NULL, 28, 2, 0 }, + { "ahb", WPCM450_CLK_AHB, WPCM450_CLK_CPU, CLK_DIVIDER_POWER_OF_TWO, NULL, 24, 2, 0 }, + { "apb", WPCM450_CLK_APB, WPCM450_CLK_AHB, CLK_DIVIDER_POWER_OF_TWO, NULL, 26, 2, 0 }, + { "uart", WPCM450_CLK_UART, WPCM450_CLK_UARTSEL, 0, NULL, 16, 4, 0 }, + { "ahb3", WPCM450_CLK_AHB3, WPCM450_CLK_AHB, CLK_DIVIDER_POWER_OF_TWO, NULL, 8, 2, 0 }, +}; + +struct wpcm450_clken_data { + const char *name; + int index; + int parent; + unsigned long flags; +}; + +static const struct wpcm450_clken_data clken_data[] = { + { "fiu", WPCM450_CLK_FIU, WPCM450_CLK_AHB3, 0 }, + { "xbus", WPCM450_CLK_XBUS, WPCM450_CLK_AHB3, 0 }, + { "kcs", WPCM450_CLK_KCS, WPCM450_CLK_APB, 0 }, + { "shm", WPCM450_CLK_SHM, WPCM450_CLK_AHB3, 0 }, + { "usb1", WPCM450_CLK_USB1, WPCM450_CLK_AHB, 0 }, + { "emc0", WPCM450_CLK_EMC0, WPCM450_CLK_AHB, 0 }, + { "emc1", WPCM450_CLK_EMC1, WPCM450_CLK_AHB, 0 }, + { "usb0", WPCM450_CLK_USB0, WPCM450_CLK_AHB, 0 }, + { "peci", WPCM450_CLK_PECI, WPCM450_CLK_APB, 0 }, + { "aes", WPCM450_CLK_AES, WPCM450_CLK_APB, 0 }, + { "uart0", WPCM450_CLK_UART0, WPCM450_CLK_UART, 0 }, + { "uart1", WPCM450_CLK_UART1, WPCM450_CLK_UART, 0 }, + { "smb2", WPCM450_CLK_SMB2, WPCM450_CLK_APB, 0 }, + { "smb3", WPCM450_CLK_SMB3, WPCM450_CLK_APB, 0 }, + { "smb4", WPCM450_CLK_SMB4, WPCM450_CLK_APB, 0 }, + { "smb5", WPCM450_CLK_SMB5, WPCM450_CLK_APB, 0 }, + { "huart", WPCM450_CLK_HUART, WPCM450_CLK_HUARTSEL, 0 }, + { "pwm", WPCM450_CLK_PWM, WPCM450_CLK_APB, 0 }, + { "timer0", WPCM450_CLK_TIMER0, WPCM450_CLK_REFDIV2, CLK_IS_CRITICAL }, + { "timer1", WPCM450_CLK_TIMER1, WPCM450_CLK_REFDIV2, CLK_IS_CRITICAL }, + { "timer2", WPCM450_CLK_TIMER2, WPCM450_CLK_REFDIV2, 0 }, + { "timer3", WPCM450_CLK_TIMER3, WPCM450_CLK_REFDIV2, 0 }, + { "timer4", WPCM450_CLK_TIMER4, WPCM450_CLK_REFDIV2, 0 }, + { "mft0", WPCM450_CLK_MFT0, WPCM450_CLK_APB, 0 }, + { "mft1", WPCM450_CLK_MFT1, WPCM450_CLK_APB, 0 }, + { "wdt", WPCM450_CLK_WDT, WPCM450_CLK_REFDIV2, 0 }, + { "adc", WPCM450_CLK_ADC, WPCM450_CLK_ADCDIV, 0 }, + { "sdio", WPCM450_CLK_SDIO, WPCM450_CLK_AHB, 0 }, + { "sspi", WPCM450_CLK_SSPI, WPCM450_CLK_APB, 0 }, + { "smb0", WPCM450_CLK_SMB0, WPCM450_CLK_APB, 0 }, + { "smb1", WPCM450_CLK_SMB1, WPCM450_CLK_APB, 0 }, +}; + +static DEFINE_SPINLOCK(wpcm450_clk_lock); + +static int wpcm450_reset_probe(struct platform_device *pdev, void __iomem *clk_base) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct reset_simple_data *reset; + + reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.nr_resets = WPCM450_NUM_RESETS; + reset->rcdev.ops = &reset_simple_ops; + reset->rcdev.of_node = np; + reset->membase = clk_base + REG_IPSRST; + return devm_reset_controller_register(dev, &reset->rcdev); +} + +static int wpcm450_clk_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + struct clk_hw **hws; + struct clk_hw *hw; + void __iomem *clk_base; + int i, ret; + + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + resource_size_t map_size; + + clk_base = devm_of_iomap(dev, np, 0, &map_size); + if (IS_ERR(clk_base)) { + dev_err(dev, "failed to map registers\n"); + return PTR_ERR(clk_base); + } + + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, WPCM450_NUM_CLKS_TOTAL), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num = WPCM450_NUM_CLKS; + hws = clk_data->hws; + + for (i = 0; i < WPCM450_NUM_CLKS_TOTAL; i++) + hws[i] = ERR_PTR(-ENOENT); + + /* PLLs */ + for (i = 0; i < ARRAY_SIZE(pll_data); i++) { + const struct wpcm450_pll_data *data = &pll_data[i]; + struct clk_parent_data parent = index_to_parent_data(hws, data->parent); + + hw = wpcm450_clk_register_pll(dev, clk_base + data->reg, data->name, + &parent, data->flags); + if (IS_ERR(hw)) { + dev_err(dev, "Failed to register PLL: %pe\n", hw); + return PTR_ERR(hw); + } + clk_data->hws[data->index] = hw; + } + + /* Early divisors (REF/2) */ + for (i = 0; i < ARRAY_SIZE(clkdiv_data_early); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data_early[i]; + struct clk_parent_data parent = index_to_parent_data(hws, data->parent); + + hw = devm_clk_hw_register_divider_table_parent_data(dev, data->name, &parent, + data->flags, + clk_base + REG_CLKDIV, + data->shift, data->width, + data->div_flags, data->table, + &wpcm450_clk_lock); + + if (IS_ERR(hw)) { + dev_err(dev, "Failed to register div table: %pe\n", hw); + return PTR_ERR(hw); + } + clk_data->hws[data->index] = hw; + } + + /* Selects/muxes */ + for (i = 0; i < ARRAY_SIZE(clksel_data); i++) { + const struct wpcm450_clksel_data *data = &clksel_data[i]; + struct clk_parent_data parents[4]; + size_t num_parents = index_to_parent_data_array(hws, + data->parents, data->num_parents, parents, + ARRAY_SIZE(parents)); + + hw = devm_clk_hw_register_mux_parent_data_table(dev, data->name, parents, + num_parents, data->flags, + clk_base + REG_CLKSEL, data->shift, + data->width, 0, NULL, + &wpcm450_clk_lock); + + if (IS_ERR(hw)) { + dev_err(dev, "Failed to register mux: %pe\n", hw); + return PTR_ERR(hw); + } + clk_data->hws[data->index] = hw; + } + + /* Divisors */ + for (i = 0; i < ARRAY_SIZE(clkdiv_data); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data[i]; + struct clk_parent_data parent = index_to_parent_data(hws, data->parent); + + hw = devm_clk_hw_register_divider_table_parent_data(dev, data->name, &parent, + data->flags, + clk_base + REG_CLKDIV, + data->shift, data->width, + data->div_flags, data->table, + &wpcm450_clk_lock); + + if (IS_ERR(hw)) { + dev_err(dev, "Failed to register divider: %pe\n", hw); + return PTR_ERR(hw); + } + clk_data->hws[data->index] = hw; + } + + /* Enables/gates */ + for (i = 0; i < ARRAY_SIZE(clken_data); i++) { + const struct wpcm450_clken_data *data = &clken_data[i]; + struct clk_parent_data parent = index_to_parent_data(hws, data->parent); + + hw = devm_clk_hw_register_gate_parent_data(dev, data->name, &parent, data->flags, + clk_base + REG_CLKEN, data->index, + data->flags, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + dev_err(dev, "Failed to register gate: %pe\n", hw); + return PTR_ERR(hw); + } + clk_data->hws[data->index] = hw; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) + dev_err(dev, "Failed to add DT provider: %pe\n", ERR_PTR(ret)); + + ret = wpcm450_reset_probe(pdev, clk_base); + if (ret) + dev_err(dev, "Failed to register reset controller: %pe\n", ERR_PTR(ret)); + + return 0; +} + +static const struct of_device_id wpcm450_of_match[] = { + { .compatible = "nuvoton,wpcm450-clk" }, + {} +}; +MODULE_DEVICE_TABLE(of, wpcm450_of_match); + +static struct platform_driver wpcm450_clk_driver = { + .driver = { + .name = "wpcm450-clk", + .of_match_table = wpcm450_of_match, + }, + .probe = wpcm450_clk_probe, +}; +module_platform_driver(wpcm450_clk_driver); + +MODULE_AUTHOR("Jonathan Neuschäfer "); +MODULE_DESCRIPTION("Nuvoton WPCM450 clock and reset controller driver"); +MODULE_LICENSE("GPL"); From patchwork Thu May 2 10:40:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 13651594 Received: from mout.gmx.net (mout.gmx.net [212.227.15.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 862176341B; Thu, 2 May 2024 10:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.15.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646421; cv=none; b=lohvp/M1IJBMFDlyMKMArGEiuE2LcBcnJ9LsZ6z4vkkEgRUJiVyCoMA2ZLq6nix8qU44929FCW7oCnZORM1vZtAacGCscueyBD/adjtGlNA4TPZzoik07tlIZY7mzOWe2riD37pow6HlrxmISbhFoaCKvmJ3/5IPb3WF8973Qsg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646421; c=relaxed/simple; bh=bdyAkeRgqSrFufI3kQJoEmI1WCv8IK5atLvcmX85qw4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gAydHUq9Wh+NboEQRD/nG0YjC+E5F+NKP6VZXGLL55fixPavNep/JaItFpVQ7VDJv+Cjnws2gzcU0OI4XMRdLOnEPe3PH8CrRk4h/kJHUyWFkBYuTnLXmldHg+3KU6AfVC14CE3ly25+5nS9GW3V5ZGzAMuiROtR3Abh0q5o2+w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net; spf=pass smtp.mailfrom=gmx.net; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b=UikdJYio; arc=none smtp.client-ip=212.227.15.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmx.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b="UikdJYio" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmx.net; s=s31663417; t=1714646412; x=1715251212; i=j.neuschaefer@gmx.net; bh=z1H4srJHNcb5BIAMp3q2n7Fh/jbh0k/UyMAjnW8Y9nc=; h=X-UI-Sender-Class:From:Date:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding:Message-Id:References:In-Reply-To:To:Cc: cc:content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=UikdJYioSQF8uPPg53dS8rTEKkmNuE1LibEAWBDnpFb0IMJEZn020rprsjCQ4OAe xGuX96nDaIrPBAzxo4fS/4+WUITs7sYRVHqO85mJeczjJsgOzYDf8LlIly/22jh6b iNaADUyUS47rYvpp0kSoEaRky3cftgCfcdHQatLK6PxWJs2gGJLQe1ShhgMaASQVQ CTUjV+vnlibAt9AmpDkYF3hF7Y8UgivasVjwV8Ta5M281Ofm+rb2rPdmBoDPnpmZ6 5jOLhvTofMxsAhzZ3iZTq+qbFF78k4XCr9WfX7Xbsb3FMwU1RkrxwZWN+ORlCY7qM 5FZT9mJ0oG7Do4nnHg== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([89.1.59.78]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MqJqD-1sNm870YD5-00ncTL; Thu, 02 May 2024 12:40:12 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Date: Thu, 02 May 2024 12:40:04 +0200 Subject: [PATCH v12 5/6] ARM: dts: wpcm450: Remove clock-output-names from reference clock node Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240502-wpcm-clk-v12-5-1d065d58df07@gmx.net> References: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> In-Reply-To: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> To: openbmc@lists.ozlabs.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Philipp Zabel , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714646407; l=1382; i=j.neuschaefer@gmx.net; s=20240329; h=from:subject:message-id; bh=gdIaqrhURYiTo/eMHHjfcL4TfUOiwQNCqwm1DTjUKA4=; b=OP6jhR/C4oActZcDuSaLndojZtPMU9nA9yO2ZP246uduoCxMjJs+i/3eD11t3zb4gc0vzZn7N Y0jx39i0l5aAIuFbcqwB4uD2ouhSsYpLd/Zac913joFMyEYhStCl5ix X-Developer-Key: i=j.neuschaefer@gmx.net; a=ed25519; pk=NIe0bK42wNaX/C4bi6ezm7NJK0IQE+8MKBm7igFMIS4= X-Provags-ID: V03:K1:omJQWa2Zw/JDFvnJS03bMn41/4c06GZlk1ALxo7nu80AxMaIIxU E7mQs5VQjbnR7yJBxJNDTcBC3VMmXgzexq5Ora5rS9qHLkyVsRolJxLHYBcjjZ+Vu7EzECI 7KSus8nHHJJppPwSanQF/SstH08zXy8FE2u90TBdkOND6SwxaPwhTY/nkUUTTGYQKDGdiJr PgHXNDJLwEJDcW3AjPC7Q== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:lznP2l3Hivk=;93JLoiaSYioywxUVJEbcH+Pg5Mm oT8Ff2Z1eiKx5hKpTr5so5sSBVkv7tNhku1GqOd/mjVGRvGdFvLz77B4uiRTODGyWCYbNVQeu hqs9ArUZofqWQqPlYlJjTi6KQqAFJt1rg1B01Q7jCHCJTVORYMRK8YljxE+zobt/4hRvYuQNK XAhaLoOQrUWdgUPtx4TsK9F7UfNYA8Pj64b5Axf27VNmwIun6K/Pzzvj/KzHSgJYevvC1sHle Ola8/l55l1WDFMAPZJKhQXm21wSF5StT1fnn15VmCaSrlhE95jc+aDVsD5tMrnqxST3AKlzE8 tM4MURbv2xdE1WIDu85P5aiyK4apatTgcNzd9iLZMQ+wJmv3joTsL38Oyr0hAxyIa2CkyQRes 7KgatOLCc0AgsQ6SHXL5dxgIpTmiKu3T8fPXQZPWf064le93MbJgHNn9fnYGomWQhueopLQGs cSOiFATSCSt3ZGyInuSRZdvWSdEXGv98C6WFuF5h59mKNGqmhn8sXBMXuJNmXHkbvP12ex3/r pjb5ig5PRpNPfKQ8u8q7XI9GR+XCE8KcnCWlSdLfHQKG1kdx0sIR7i/ShT9d5WnGQf1+TCKV+ BVqTmJRgTc1sLqZ1UImyR/HsBRMYME2UPQnDlGIwQW5EIDxduiWydhurmV3dC/1vnzpcQBgnn n+6gNX8YPacdV+lAIF2dXo/T+6n8AySITA+SEVuFxCryId4aRx+xsx4HUBm8gz/zqGnpT4I6T zQ6Q4D+k6KApbSoxUgI0J1hA2WT/oUAS4S9pvfgRcH0nWRp6M1JUSKNAG0Ag6Q70nLlJcuHSO QAGOFCRW+dOvEe27Le1dh4WTZuvVn3bTZFPvpV2PsmVbk= A previous version of the as-yet unmerged clk-wpcm450 driver[1] used the output name, but in the current iteration it doesn't rely on it anymore. Thus it can be removed from the devicetree. Preserve the "reference" naming aspect in the node name instead. [1]: Added in "clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver" Fixes: 362e8be2ec04a6 ("ARM: dts: wpcm450: Add clock controller node") Signed-off-by: Jonathan Neuschäfer --- v12: - rename node to clock-ref, because it isn't necessarily 48MHz, just by board design recommendation v11: - Specify since when clock-output-names is unnecessary v10: - no changes v9: - New patch --- arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.43.0 diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi index 6e1f0f164cb4f5..ff153858801ccf 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi @@ -37,10 +37,9 @@ clk24m: clock-24mhz { #clock-cells = <0>; }; - refclk: clock-48mhz { + refclk: clock-ref { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; - clock-output-names = "ref"; clock-frequency = <48000000>; #clock-cells = <0>; }; From patchwork Thu May 2 10:40:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 13651596 Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FFD2605BB; Thu, 2 May 2024 10:40:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.15.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646422; cv=none; b=L6WqYzIpuBoaT97y81YBhSuu9PRdhNNetotY16Fb6wTTyLkPTZu9X2RoqKVaKQvxSKn3GVi0ah8SH5XQGXvTblC3nfgbChqG8dDISPqtNNi0ZmUC194HDdMtKUxYq+EBBb/FZDYvOfagBSzVPm0k1zoIjk5oSZZAzf42ID7DW/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714646422; c=relaxed/simple; bh=ScRaDhIpV127IN2u4IRMxbcJ62UMUy4jPlUrmCzVMKY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=J7Gduiy4GZeaXJJoZ2zm9/B37gKsHCf69nK6StLzrbUGBOthX0hQXeOFziKNoLJvHod0Oy8LAzR2amV3baqh6fsYsikqhpb2Cy4RrjgNA9VyeY72vflPk9SzJpRFx/SOnMWcW1NIw5DjnAHpJNdx9hTXavaPfr5xnkaTTlh2XlM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net; spf=pass smtp.mailfrom=gmx.net; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b=hxRrl8zu; arc=none smtp.client-ip=212.227.15.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmx.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b="hxRrl8zu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmx.net; s=s31663417; t=1714646412; x=1715251212; i=j.neuschaefer@gmx.net; bh=6OXJA6Op8AyXGG0UDDxLGH3tvgeicFvPJqUw6T5kUbc=; h=X-UI-Sender-Class:From:Date:Subject:MIME-Version:Content-Type: Content-Transfer-Encoding:Message-Id:References:In-Reply-To:To:Cc: cc:content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=hxRrl8zuChzw55RMQflwp7LKbYiPFy0ZZt8yx8NZ/Dq4g/FCU31fUP3+FmwR3exN TF8U2y79hG2fWEX7VhYBgzLn5dowiT1R5GAU51LrqgANiVsWk0/5DgQJtiX89Ptya LP509nGTPoKexTIIo7QT0TUebmRmoFsFRagEOYj/ZXffpmyd+k75r8FCk91CR7kSW 8Xt7WK3kHD71rZZdkGW1zvRuO0DYOLcjBivEXh9Gy+xS5sjG4Qq9BaiJqZelQFQyd uPDYTuO5eChJKxLwT062m8ysSW/OxLb9SUTW6zM9YmdchYC/XD0mkTuQtK+hU40bq w3c8BBruMWTXhVMJpQ== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([89.1.59.78]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MVNAr-1sBRu72x6N-00QZRI; Thu, 02 May 2024 12:40:12 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Date: Thu, 02 May 2024 12:40:05 +0200 Subject: [PATCH v12 6/6] ARM: dts: wpcm450: Switch clocks to clock controller Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240502-wpcm-clk-v12-6-1d065d58df07@gmx.net> References: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> In-Reply-To: <20240502-wpcm-clk-v12-0-1d065d58df07@gmx.net> To: openbmc@lists.ozlabs.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Philipp Zabel , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714646407; l=3443; i=j.neuschaefer@gmx.net; s=20240329; h=from:subject:message-id; bh=kTIwYF9CzV7EiefFtPbjPQBui0vN/ls9WsnRdurtK5Q=; b=i5Nq00oyRbu3AdZD8yy38vGM7GdRnEMZs+mGG+3ay/O/Wyfg8NaGHyiZFF5+okDYgRRB5h3DN Q5d4gVOoKhUB7XDLKtjAK4YSHebPDyraHUvCX+G5sAcIoTajJGKy06S X-Developer-Key: i=j.neuschaefer@gmx.net; a=ed25519; pk=NIe0bK42wNaX/C4bi6ezm7NJK0IQE+8MKBm7igFMIS4= X-Provags-ID: V03:K1:hIS1j75iLlGFzDqsq+dZOPH9oD8RRwRngZCC2XzrPED0kjl9VzG tctJWpzU85h5nTaGYuPEsGU2Ky/yE9g/qqf1HuxSBl3vHOK0DM4Aa48KUwfcYciYcMbCZL1 JdT/xpRZRmdNe7nDiUp4nYSPbm7NKM2foniMSld5PbS15DUIClvJq9fZNvvKxsNE2wtYhtW yF23+xG8cKN2iKxoG4Z0g== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:utNei+oMAA8=;d1JrV2fj7oGow4bds/UHwSLcGsk NF95oW2ztrNogQOM35PCLwCEQcGiQXhqQpgYD9hDo0x5RxsvxnAKrx8Y2tF318a8FTSOPIRB2 UQt2DRubFbpXhYu07L65+mjg2u512e6XjbffsrnMSlzhcozhuN/Iwz0kBt9K8VLfFJjwh8Hc/ vlV8XGLc/+nhD21Ts04HnFowEZ7cE49/BNBdC3AwM1jZLZ2cL74jcUjFiZTtfcHPSC6I075gi 06kuJazbup6OcY+w9Qjsf9Hqkvp/4XBPBSopB90ydCdFSAFueeEwaNg5zPyr8Wmr3iVfG1qR1 Btc5IbQrdFeFp5axBdVGJ1lm/9BgcGghiGZzihlHgXkq6ILkA+kAtjopoMCZ9CyAoRZ48FuWK pFvRPRlPO5HbVPg0fWsMCoNsyE8CCL1gTf9UTRR0kG3cSF2yw58Xi+f0ZZ4+rqNCe1oUJ2jNp TbZEMOQYNPFklJU7G/HITEBaCP9+c8ny9ibM/8Hd0m80pr7NCmXYwP0tCWeqlsQX7Wogq7Zpz LSqQChOTl2fopbHLj/aGi8IdiaStThcN0T/AXa2OAR01zPV0IDiu9YMC14vOv+tknIDRVmRvK ge8Lxb7NcGjSLXVpWFP+0Cb9m4vjTM3oO3PYUrW95Vb9/kHRgldm3DjtjK66mBrjsOo++HlXw l1QFtAHIbe7XZVLIKBgn7l6tVgq1VCEc9go2lW392HBwERZrdPdeVm14KE5+bFxylnQ6eDs+i jOoD35HXeK89INu8Y0QXSGqslX4n1phWKTF6GHvCkl9nhM9XrJqkpQTtvHEG+zRI/p+cbcCNC o6sIB36qBvzXd0FdcapQCnmhJhNm5j5umVdX1J80AbQRQ= This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neuschäfer --- It's probably best to delay merging of this patch until after the driver is merged; I'm including it here for review, and in case someone wants to set up a shared branch between the clock and devicetree parts. v12: - work around timer-npcm7xx driver issue by providing timer clock separately v11: - no changes v10: - Reintroducing this patch as part of the clock/reset controller series --- arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi | 32 ++++++++++++++++---------- 1 file changed, 20 insertions(+), 12 deletions(-) -- 2.43.0 diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi index ff153858801ccf..daf4d399ecab4c 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi @@ -2,6 +2,7 @@ // Copyright 2021 Jonathan Neuschäfer #include +#include / { compatible = "nuvoton,wpcm450"; @@ -30,13 +31,6 @@ cpu@0 { }; }; - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - refclk: clock-ref { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; @@ -44,6 +38,19 @@ refclk: clock-ref { #clock-cells = <0>; }; + refclk_div2: clock-refdiv2 { + /* + * reference oscillator divided by 2, as a workaround because + * the npcm7xx-timer driver needs its clock earlier than the + * clk-wpcm450 driver (as a platform driver) can provide it. + */ + compatible = "fixed-factor-clock"; + clocks = <&refclk>; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <2>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -70,7 +77,7 @@ serial0: serial@b8000000 { reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART0>; pinctrl-names = "default"; pinctrl-0 = <&bsp_pins>; status = "disabled"; @@ -81,7 +88,7 @@ serial1: serial@b8000100 { reg = <0xb8000100 0x20>; reg-shift = <2>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART1>; status = "disabled"; }; @@ -89,14 +96,15 @@ timer0: timer@b8001000 { compatible = "nuvoton,wpcm450-timer"; interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb8001000 0x1c>; - clocks = <&clk24m>; + clocks = <&refclk_div2>, + <&refclk_div2>; }; watchdog0: watchdog@b800101c { compatible = "nuvoton,wpcm450-wdt"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb800101c 0x4>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_WDT>; }; aic: interrupt-controller@b8002000 { @@ -480,7 +488,7 @@ fiu: spi-controller@c8000000 { #size-cells = <0>; reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; reg-names = "control", "memory"; - clocks = <&clk 0>; + clocks = <&clk WPCM450_CLK_FIU>; nuvoton,shm = <&shm>; status = "disabled"; };