From patchwork Fri May 3 04:31:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shay Drori X-Patchwork-Id: 13652342 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2046.outbound.protection.outlook.com [40.107.92.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E7FE634; Fri, 3 May 2024 04:31:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.46 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714710706; cv=fail; b=F37PcjyOIxPAQVfcmZ+E5P7yGp9JFckL0M9Baf9oW/ZBCJP7zQ+O5m4K6xKc1b0JQTr6GLfhglU2WvwgnaourFzLYucO6lflaOPXqA9yXb8o1P1BXtkUPc65ZVxiUDl9uqQUec0XQ3OyjB0Q522G0Q1O/B9yurGJrHuULBdxD0Y= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714710706; c=relaxed/simple; bh=51kjt+hCIAgodL0LC6lKjJ32ynUG0tgC+2EjuBwT9M0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=X5oRmRCNpBnHZ4VVs4oZKQQ+LY+sxhnw1fWjsX0SM8mHlw2/+AQeccKUQl77SuUBbAtWhrDjpPheEyz9miTusWDTAGKe8A+e21YO1avjliRUV3+5/Sf1dHaeJgwu0p11G5J6rBLwwZWSfBwQef6ieunACWYAtGTsjsCT49x9g5U= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=BU+LV8ny; arc=fail smtp.client-ip=40.107.92.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="BU+LV8ny" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CWs9Vq+g3M7oCt2Blf6dQD20vCP9m0iELP+pjeKBrv5fhCC2FiN8+2r/eYO4bUL3gBf9iSNKiunLFP6D9eMzPieX1aGsDamd0i69uUrY71tMu/3dXvyi2rCT9yYy1Zy4tKHLeGyGJtPSUIZ57lnLVj8xlWgpbh3oTPa7Z1C5XcvGGNO4wgHNoQu3v6X5J2fYBDETD6wvCilx8+NgtrxnwhzbjjN0LCU+5+ajfIUrnRNUcjYw/ml2glbo2fUjsYRqOBrIvqXizf40jOExv2eO8t139+nfscLv2XBtJi1Gw7rzehglEp8GC9PaH4zRMnYsn7DABUvWzOa5G5OizK4sHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=o43M//Q3E05qemzg04xcarxPSMabLzzu2UyTxhGyd6o=; b=CIIEZag6qvfe2gEZ+QgxIGKpfizsGkA/GLiTglxrCO8jpm9Mhlz6PRQQK5qS7rb8Mk7wm11FLruUdyu/XLz6Ve+bl5m/Lp0u3WuDr++0VfnssogMZbKEth/L9LdDbfvLBw0le/bI6AhS0vADHVWsqkFPlIpOkGZni9BUuplwtxoQEZEOUqWpB0TFoBm2gbUKhCb/s14UrrxdxJUCqvZSAVlAqBBH4ha4k1X4mzI0oy11MoRpMDGL7ZRjVlQOeaggUGLcN2tVvT79SgDEvZBdI/Vg1KJD0uWAf+ZD4E4zimn+MCgvUSiKd/mUeMImiTtCQtZCtdSKpF97h9tybZu9BQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=o43M//Q3E05qemzg04xcarxPSMabLzzu2UyTxhGyd6o=; b=BU+LV8nySsKLtdIBbGjNTx7yk8hA8N85wDFivWflIBMnTbMA+43K4dQ9xpsnsHczjZDuIuHVOX8yRrRtAsVpY3Oa/ShpD4lbeCnD6QHyA9HOV8UN+i64ZLdJG1cdW8Rqe5M50LVdPqeL50jD49RhepM0LWW/YmEFXNRQPdV9XPrdt7kQH8s0cDb0ikLNZT96vphz6hp9ahouvQqfczEC/GoZ/DoYs1wLUCO7eWDMKfatX1RB+T6knpJ4R0tc2/SJR62Gyz/FYMttFDv0dolIzTeARK4rTE+RPWhKsDdt6duwQBdkvn01IktKAAbRwBgxN2feqVYJ5oRmg6t2YpCo2Q== Received: from BL1PR13CA0127.namprd13.prod.outlook.com (2603:10b6:208:2bb::12) by LV3PR12MB9236.namprd12.prod.outlook.com (2603:10b6:408:1a5::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.29; Fri, 3 May 2024 04:31:41 +0000 Received: from BL02EPF0001A0FC.namprd03.prod.outlook.com (2603:10b6:208:2bb:cafe::e9) by BL1PR13CA0127.outlook.office365.com (2603:10b6:208:2bb::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.32 via Frontend Transport; Fri, 3 May 2024 04:31:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A0FC.mail.protection.outlook.com (10.167.242.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.18 via Frontend Transport; Fri, 3 May 2024 04:31:40 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 May 2024 21:31:25 -0700 Received: from nps-server-23.mtl.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 May 2024 21:31:20 -0700 From: Shay Drory To: , , , , , , CC: , , , , , Shay Drory , "Parav Pandit" Subject: [PATCH 1/2] driver core: auxiliary bus: show auxiliary device IRQs Date: Fri, 3 May 2024 07:31:03 +0300 Message-ID: <20240503043104.381938-2-shayd@nvidia.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20240503043104.381938-1-shayd@nvidia.com> References: <20240503043104.381938-1-shayd@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FC:EE_|LV3PR12MB9236:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b35903e-2cdf-4717-e8c5-08dc6b29ee0d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|1800799015|36860700004|7416005; X-Microsoft-Antispam-Message-Info: 0ONkJnB4jGkjOcOZOyptoOFKepwl+ELWK2WzEKRA/8LyybxupXiEt5z+RtOrwkEPOjnDoWPVl/NGcXLEpwrbyZ+qEH+yTHRhLnbUnbCbrIcTlFZtmFS8nBvSdn390ggqPqtEugcC64uk37DL9ftcM2iwDAtF6Z2WzLMVuYvx/xWHqqMXDhxaQa4UQq9kFYl7KfVfvpWOLhDKJJVVc79aBC36QAObG/TP22BzRsiDSksfiZYC88AdnAkcnIZO/4iBOeUkPG5Yb2NX1kY3SSDGwE+R+ngUGHUCo5NQ9UHnUxAmFIvSskQbE6Sy536FlYv0HbMSZ38tOpmJBex22pi3yIxsPM73MEAVv8uFvNgw8ZiGzxc3IrSSd4wNGFozL9dRq/8IFG0etohTJDzb0uP5QnlFnPhtIYUb1vTmtlux2pSa4ZWVq+eDgZ3hkHfTD0e02cEXEOSpQOsATUHL+fBgMj4kfCBlyXRwEbPe5DVB5v4XK88dBKnNByuWgIDMhLPbbIDMcbBKlwBuC2kyAE8DCQDEzI+6LJhFHpKa6E3GSO06ObQhgQhytg+gqpSbXz5gl2M59loc4kUXcqL8KZE37Y2hpv7sWE2wlzhqd5oZYB6iN7+kY0rzMfH8O/Fpw3EQr+JKazNpuqGw0gi3SG1QN2Q38Ly09PiBjfYLo9PMTbt+K2EplgzXGiSoXHwYZFU/eC60X4/cd2+jhIWaBdFjegKlCO0oB9PN7uqFE7jdoqqWxCRIJFVmufAb6OXZPjQd/SOdcTe3w0FS4UyJwFn/t6Rc3F7qK5pobCvYhbnYuiGDMykXK2SMXYE2wj3nuk0cfTCat+URKwWPXFlw7aL+KpDcBgndlR2bGkrkzcPOF+CQvw9AAqsBEaWJaNKemJmQMj+6yfBG8Qh5tG1BpOH6QcTc81Ve9TFfrz76OIymLplcwAXgqdRoklA9BNj0F+4p9tqvr25M6+OpXiHYuo/8oXKUcShuhD8kQWE/5ZGRQeM3k7DWKjg50pdmdu3a9ZK3xGNtbPYW+quRwhnj0v/nyaEwa728wDFvDZaQJYp1J2A6exh7T9+bcqEwuk2agGRP9XzBFPbeqWrHgmARDuAURT5gwTGywgR0Zh0UcGX7vehfJdF8tcdvfQrY6jI8WQM7YtO5Nx61IFNx5C03wkkmRTwZi47S5qy9fWi0edxP8J0dSY42DKiPvgr4dTpmMUMqA3C94i9Q2iAO3AZToquDeMFv86p/wvWXNEaSFJ0c6HZQ8TsRPNES0MiEJs/u3/xAvDe7/wBRzu7vSes4Uv4vPjsJv5pvZ+nUMH2v/BAuWF7+rzG9FVTaj0u0BehyfC0VVQjsET2lE5u60i2vguYM4tIeKfEx0SQpd3oodRmoHRRJzoNFq+7Op4ZKcYVwY+7z X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(1800799015)(36860700004)(7416005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 04:31:40.9612 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b35903e-2cdf-4717-e8c5-08dc6b29ee0d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9236 PCI subfunctions (SF) are anchored on the auxiliary bus. PCI physical and virtual functions are anchored on the PCI bus; the irq information of each such function is visible to users via sysfs directory "msi_irqs" containing file for each irq entry. However, for PCI SFs such information is unavailable. Due to this users have no visibility on IRQs used by the SFs. Secondly, an SF is a multi function device supporting rdma, netdevice and more. Without irq information at the bus level, the user is unable to view or use the affinity of the SF IRQs. Hence to match to the equivalent PCI PFs and VFs, add "irqs" directory, for supporting auxiliary devices, containing file for each irq entry. Additionally, the PCI SFs sometimes share the IRQs with peer SFs. This information is also not available to the users. To overcome this limitation, each irq sysfs entry shows if irq is exclusive or shared. For example: $ ls /sys/bus/auxiliary/devices/mlx5_core.sf.1/irqs/ 50 51 52 53 54 55 56 57 58 $ cat /sys/bus/auxiliary/devices/mlx5_core.sf.1/irqs/52 exclusive Reviewed-by: Parav Pandit Signed-off-by: Shay Drory --- Documentation/ABI/testing/sysfs-bus-auxiliary | 14 ++ drivers/base/auxiliary.c | 170 +++++++++++++++++- include/linux/auxiliary_bus.h | 15 +- 3 files changed, 196 insertions(+), 3 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-auxiliary diff --git a/Documentation/ABI/testing/sysfs-bus-auxiliary b/Documentation/ABI/testing/sysfs-bus-auxiliary new file mode 100644 index 000000000000..3b8299d49d9e --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-auxiliary @@ -0,0 +1,14 @@ +What: /sys/bus/auxiliary/devices/.../irqs/ +Date: April, 2024 +Contact: Shay Drory +Description: + The /sys/devices/.../irqs directory contains a variable set of + files, with each file is named as irq number similar to PCI PF + or VF's irq number located in msi_irqs directory. + +What: /sys/bus/auxiliary/devices/.../irqs/ +Date: April, 2024 +Contact: Shay Drory +Description: + auxiliary devices can share IRQs. This attribute indicates if + the irq is shared with other SFs or exclusively used by the SF. diff --git a/drivers/base/auxiliary.c b/drivers/base/auxiliary.c index d3a2c40c2f12..5c0efa2081b8 100644 --- a/drivers/base/auxiliary.c +++ b/drivers/base/auxiliary.c @@ -158,6 +158,167 @@ * }; */ +#ifdef CONFIG_SYSFS +/* Xarray of irqs to determine if irq is exclusive or shared. */ +static DEFINE_XARRAY(irqs); +/* Protects insertions into the irtqs xarray. */ +static DEFINE_MUTEX(irqs_lock); + +struct auxiliary_irq_info { + struct device_attribute sysfs_attr; + int irq; +}; + +static struct attribute *auxiliary_irq_attrs[] = { + NULL +}; + +static const struct attribute_group auxiliary_irqs_group = { + .name = "irqs", + .attrs = auxiliary_irq_attrs, +}; + +/** + * Auxiliary devices can share IRQs. Expose to user whether the provided IRQ is + * shared or exclusive. + */ +static ssize_t auxiliary_irq_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct auxiliary_irq_info *info = + container_of(attr, struct auxiliary_irq_info, sysfs_attr); + + if (refcount_read(xa_load(&irqs, info->irq)) > 1) + return sysfs_emit(buf, "%s\n", "shared"); + else + return sysfs_emit(buf, "%s\n", "exclusive"); +} + +static void auxiliary_irq_destroy(int irq) +{ + refcount_t *ref; + + xa_lock(&irqs); + ref = xa_load(&irqs, irq); + if (refcount_dec_and_test(ref)) { + __xa_erase(&irqs, irq); + kfree(ref); + } + xa_unlock(&irqs); +} + +static int auxiliary_irq_create(int irq) +{ + refcount_t *ref; + int ret = 0; + + mutex_lock(&irqs_lock); + ref = xa_load(&irqs, irq); + if (ref && refcount_inc_not_zero(ref)) + goto out; + + ref = kzalloc(sizeof(ref), GFP_KERNEL); + if (!ref) { + ret = -ENOMEM; + goto out; + } + + refcount_set(ref, 1); + ret = xa_insert(&irqs, irq, ref, GFP_KERNEL); + if (ret) + kfree(ref); + +out: + mutex_unlock(&irqs_lock); + return ret; +} + +/** + * auxiliary_device_sysfs_irq_add - add a sysfs entry for the given IRQ + * @auxdev: auxiliary bus device to add the sysfs entry. + * @irq: The associated Linux interrupt number. + * + * This function should be called after auxiliary device have successfully + * received the irq. + */ +int auxiliary_device_sysfs_irq_add(struct auxiliary_device *auxdev, int irq) +{ + struct device *dev = &auxdev->dev; + struct auxiliary_irq_info *info; + int ret; + + ret = auxiliary_irq_create(irq); + if (ret) + return ret; + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + ret = -ENOMEM; + goto info_err; + } + + sysfs_attr_init(&info->sysfs_attr.attr); + info->sysfs_attr.attr.name = kasprintf(GFP_KERNEL, "%d", irq); + if (!info->sysfs_attr.attr.name) { + ret = -ENOMEM; + goto name_err; + } + info->irq = irq; + info->sysfs_attr.attr.mode = 0444; + info->sysfs_attr.show = auxiliary_irq_mode_show; + + ret = xa_insert(&auxdev->irqs, irq, info, GFP_KERNEL); + if (ret) + goto auxdev_xa_err; + + ret = sysfs_add_file_to_group(&dev->kobj, &info->sysfs_attr.attr, + auxiliary_irqs_group.name); + if (ret) + goto sysfs_add_err; + + return 0; + +sysfs_add_err: + xa_erase(&auxdev->irqs, irq); +auxdev_xa_err: + kfree(info->sysfs_attr.attr.name); +name_err: + kfree(info); +info_err: + auxiliary_irq_destroy(irq); + return ret; +} +EXPORT_SYMBOL(auxiliary_device_sysfs_irq_add); + +/** + * auxiliary_device_sysfs_irq_remove - remove a sysfs entry for the given IRQ + * @auxdev: auxiliary bus device to add the sysfs entry. + * @irq: the IRQ to remove. + * + * This function should be called to remove an IRQ sysfs entry. + */ +void auxiliary_device_sysfs_irq_remove(struct auxiliary_device *auxdev, int irq) +{ + struct auxiliary_irq_info *info = xa_load(&auxdev->irqs, irq); + struct device *dev = &auxdev->dev; + + if (WARN_ON(!info)) + return; + + sysfs_remove_file_from_group(&dev->kobj, &info->sysfs_attr.attr, + auxiliary_irqs_group.name); + xa_erase(&auxdev->irqs, irq); + kfree(info->sysfs_attr.attr.name); + kfree(info); + auxiliary_irq_destroy(irq); +} +EXPORT_SYMBOL(auxiliary_device_sysfs_irq_remove); + +#else /* CONFIG_SYSFS */ +int auxiliary_device_sysfs_irq_add(struct auxiliary_device *auxdev, int irq) {return 0; } +void auxiliary_device_sysfs_irq_remove(struct auxiliary_device *auxdev, int irq) {} +#endif + static const struct auxiliary_device_id *auxiliary_match_id(const struct auxiliary_device_id *id, const struct auxiliary_device *auxdev) { @@ -295,6 +456,7 @@ EXPORT_SYMBOL_GPL(auxiliary_device_init); * __auxiliary_device_add - add an auxiliary bus device * @auxdev: auxiliary bus device to add to the bus * @modname: name of the parent device's driver module + * @irqs_sysfs_enable: whether to enable IRQs sysfs * * This is the third step in the three-step process to register an * auxiliary_device. @@ -310,7 +472,8 @@ EXPORT_SYMBOL_GPL(auxiliary_device_init); * parameter. Only if a user requires a custom name would this version be * called directly. */ -int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname) +int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname, + bool irqs_sysfs_enable) { struct device *dev = &auxdev->dev; int ret; @@ -325,6 +488,11 @@ int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname) dev_err(dev, "auxiliary device dev_set_name failed: %d\n", ret); return ret; } + if (irqs_sysfs_enable) { + auxdev->groups[0] = &auxiliary_irqs_group; + xa_init(&auxdev->irqs); + dev->groups = auxdev->groups; + } ret = device_add(dev); if (ret) diff --git a/include/linux/auxiliary_bus.h b/include/linux/auxiliary_bus.h index de21d9d24a95..c95c46bacfc7 100644 --- a/include/linux/auxiliary_bus.h +++ b/include/linux/auxiliary_bus.h @@ -58,6 +58,9 @@ * in * @name: Match name found by the auxiliary device driver, * @id: unique identitier if multiple devices of the same name are exported, + * @irqs: irqs xarray contains irq indices which are used by the device, + * @groups: first group is for irqs sysfs directory; it is a NULL terminated + * array, * * An auxiliary_device represents a part of its parent device's functionality. * It is given a name that, combined with the registering drivers @@ -138,6 +141,8 @@ struct auxiliary_device { struct device dev; const char *name; + struct xarray irqs; + const struct attribute_group *groups[2]; u32 id; }; @@ -209,8 +214,14 @@ static inline struct auxiliary_driver *to_auxiliary_drv(struct device_driver *dr } int auxiliary_device_init(struct auxiliary_device *auxdev); -int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname); -#define auxiliary_device_add(auxdev) __auxiliary_device_add(auxdev, KBUILD_MODNAME) +int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname, + bool irqs_sysfs_enable); +#define auxiliary_device_add(auxdev) __auxiliary_device_add(auxdev, KBUILD_MODNAME, false) +#define auxiliary_device_add_with_irqs(auxdev) \ + __auxiliary_device_add(auxdev, KBUILD_MODNAME, true) + +int auxiliary_device_sysfs_irq_add(struct auxiliary_device *auxdev, int irq); +void auxiliary_device_sysfs_irq_remove(struct auxiliary_device *auxdev, int irq); static inline void auxiliary_device_uninit(struct auxiliary_device *auxdev) { From patchwork Fri May 3 04:31:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shay Drori X-Patchwork-Id: 13652343 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2065.outbound.protection.outlook.com [40.107.244.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B978ED9; Fri, 3 May 2024 04:31:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.65 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714710706; cv=fail; b=YjKNOyo5wRsQRFlNYJ1lKKlTQk1J9hcBpqVNVLQcLc396RBwqujbZ9IZo48GSAY7WZiMMD1pdY0dnedHX5wdpoDAjs/DYZy7EWKh9ZKfUDL/PTYqalkBFpRfVQrgeJCT8veklWTjwAlrOnH9a1XNrlnInlxMRjJhErM9Wfv51Gw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714710706; c=relaxed/simple; bh=UkmuWBhgwe7W7Ey7mLX0XsK/Piq5HUsvs6fk0gg98YY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I4KstOW8LGK7hh2KU4kscnLCuxB232sZY8rMcFtsmdI0GZq+edLvco7cLDmpBpS9s1JeVujJMrWruNHhc3LMdz6VRt+G4mNYeNZJMKomeFp9k/5kLenmNpd+1DrZSoTfed6NDDGVD+Bex9VU1b5JrGVjxOVnHogLAqo4JmSK48c= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=W3+wn3Vd; arc=fail smtp.client-ip=40.107.244.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="W3+wn3Vd" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GfyuIGrNtFzgIQ0xd6nOrLjDGLhHlmC3KKzfJ0NO81htRGAfJPfFgLuccLgU23aRi+LEiVOO32VtEv5aVdj+XoSKr/C6MJauUsmMGvRYYd7gsWtHOPFwu0bpxdy4HuRWfFHFPtwG72zfKDjvPR3t6c74Fibvy2GOFdqMzjfY7lFsBlj+uZuu6mYdGx/tAaNcSgaBzri8cvrEuFGQtYIIXrRIGKWEhdpWi9nUT507L1WeIEuCV+k/w+rdYGDK8pA+mYWJUp8ITF9BBzvEhSyokp5MFspu3QkzGLdEy0rr7hcFT3/3OvoOjFfsGMXxVwm+zqEbNqbikL1fLHPEmDfc0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=88q5CsuIipzXnJmRy8n8Ex9QsBkf5TgTwqR37k3RL0Q=; b=SBZp4FT+xn+CrjO+2w2yB0PrSnqNLQu6ew3U/zvywp9Y943H3CYzpxnCuVpiwdleYCqH/CviOjXDCK6HuKWtMc81GeGoFRGGJR87oW3QRiBG3sH5BZQHBpxnARtLTaN+/doNpN6DyuibXhJuGS+rDCDcbINnU3d4dgkUDBwJlMUYNW8c/balxvyBK+ndBfzWMl0hWJQIxKEZItlB6nuzPaLVWgXXD39PlCpRBcDgSyGLbjaH7orojaIQ8/OMgSOp0fH4wbcMHm/sBtpqeKlpnB6wKKsITJOhSrPSI1rONOha9IPgynZfhbp05OfgJl01Q1cTlpbMf64GYfdU030BHQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=88q5CsuIipzXnJmRy8n8Ex9QsBkf5TgTwqR37k3RL0Q=; b=W3+wn3VdJusUWQJElnXjZTVxswDpc+wBlR4gK76xIfCrI4r2mVAW6UE/rwe5KW+GEYXjnAHqv05LflWfZKRA48ZMdNIerkMMRBoq9Bq9ruCpIt2MNce2gSrII8XvC7wqDMIJMCqzLImGHmLqRk8CTsR2hK4l25Bga3D5tRSG2cFTe1iIf+sWfYPe6Qfw4LUAdJrYeQo4toMGMuUuKJ42EPBKOJ37gVW9p4Vxp50kJe1PyCXXzFzVdWtkX8QmrtCVMsiTFNaN2s6Zx1cFxz8JVkjpGApzhm/PRvHWQwMiwXqWLhhi0ASpX6CmpgIZqyO1avkmNhdqk4Hl5NxsydDWaA== Received: from BN9PR03CA0954.namprd03.prod.outlook.com (2603:10b6:408:108::29) by DS0PR12MB7605.namprd12.prod.outlook.com (2603:10b6:8:13d::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.35; Fri, 3 May 2024 04:31:42 +0000 Received: from BN3PEPF0000B373.namprd21.prod.outlook.com (2603:10b6:408:108:cafe::69) by BN9PR03CA0954.outlook.office365.com (2603:10b6:408:108::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.35 via Frontend Transport; Fri, 3 May 2024 04:31:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN3PEPF0000B373.mail.protection.outlook.com (10.167.243.170) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.0 via Frontend Transport; Fri, 3 May 2024 04:31:41 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 May 2024 21:31:29 -0700 Received: from nps-server-23.mtl.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 2 May 2024 21:31:25 -0700 From: Shay Drory To: , , , , , , CC: , , , , , Shay Drory , "Parav Pandit" Subject: [PATCH 2/2] net/mlx5: Expose SFs IRQs Date: Fri, 3 May 2024 07:31:04 +0300 Message-ID: <20240503043104.381938-3-shayd@nvidia.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20240503043104.381938-1-shayd@nvidia.com> References: <20240503043104.381938-1-shayd@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B373:EE_|DS0PR12MB7605:EE_ X-MS-Office365-Filtering-Correlation-Id: 7014dbe8-2575-4b8b-507a-08dc6b29ee99 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|36860700004|7416005; X-Microsoft-Antispam-Message-Info: bc24N7qhdgpGl6RtNsxq81O2nX8ufwt2WZZMbX5lpd1aE2Jnz9XLtLCBoV07WNBXBZusQvfrYDFpmdzqkFncdcrLWpFIYTx07jAQUwjfVpe9cVUijMsoMNYa1JjyDxrGyyNRqXH7eTCMTZT2+nmAcVj8PHqDP1HwVkb/TXeMf1HcxNsIpvy9iU68YmZbXknxbimrl8ChCcVb253YmklCfpH/d6JQX6447ZXfYadaStTZYqfXMmw3Yy6RzY+6YzoCMH4xNJcmhOnXUG9gxYa2ji8SEHtfVwt7FFq450NvS56k5yOrQys19Aluf7nR3pqcKyfCrQOCWJUZRxrzE21zwODPd+bHtOT84mVXQAyfat3wCGImYrRrHrc2yUggl6BVOZli6Ke2uVYLawSvXenOLuDslbL3zbnKK1o829dVweiVBUinCBeOu3O6RS4JkFv+CqOqc49BNng5ifoCZjtivDoA24awG26dplV/zwp/k62cTnMoI1UCT6gjj82W+sJXA52uIgPNbioFU5xRmvg+BwLbGL3y/esbrf3lNvZ3UcJIx08gWX491qCAdOFJhpebswGcdraJlfqStkd1v9euTf9PE0tn7sjgG62j7il6h+VtJ+Zaxc86p9sGA5NFNfln21VtRcdbuGzlwr0DiMGeoSJHDTKgPvzzKFMSPJ92CJ0YdjKMV3AlksW3zrrKzniBllyOLUrQwyZI3lZtHZyALH3wxl2ml3+dg0/g6Jz8EzNw8DF39wU0XuraYx0zKdYMKD/NXcxHY6YaRtKdxLCFNBGfwOoaQvl6/LzpKt/ujbc9mzVjURPlyKfWgC4pSMtZUhBy8JQplVZtDTMT6g7XFIMoA0XaldMBE3KZyLDjrrNiRacqpD8A22Tfu656qnMULHQMOkFs68YaN7YyX561M2EcPXxK897O+7rbqFYqqZVi0A5vphKioOCgvd7quauO3DSARrSTeJMRaaPQK2o5ljkOwWrpG5ThB6EDFe5Q0Q1NWck5B6r9HiAcsbM2NvjSxlKEVBgk9tD5SSZcHqUQh+UgBFIQjdbYD4eNvL7mjS+8p1ZCEe+NgS/fkBbJq8ptrFUj2i1ck46703rba/3SfAZCf8I51VyTVi+vVk3RHJjDTBuCNNIS4BRVhT4IKbWmwOP+cXY7iqRj83aqZwOIA46g0hkMp5TXhF+Cl18hF3WBKgyK+kTF9YMKs4hMe7O6iSkur/7RpjFfzPrtb+a0oF5bO5BfJSBvxwhRiCa42RUQWIfweicpaM6rVYaaOxTiqkZNQTV9BXqDwi+k9F7QXfi0O4b3eK+4KXZtyCFGG/t7eZ5O4ESZCuGpo/FOMMlgKgxTFZvUrupMQnqp/MAh+eNeD+1YlHkSOYLlrxgt2D8= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(36860700004)(7416005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 04:31:41.8592 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7014dbe8-2575-4b8b-507a-08dc6b29ee99 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B373.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7605 Expose the sysfs files for the IRQs that the mlx5 PCI SFs are using. These entries are similar to PCI PFs and VFs in 'msi_irqs' directory. Reviewed-by: Parav Pandit Signed-off-by: Shay Drory --- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 6 +++--- .../ethernet/mellanox/mlx5/core/irq_affinity.c | 15 ++++++++++++++- .../net/ethernet/mellanox/mlx5/core/mlx5_core.h | 6 ++++++ .../net/ethernet/mellanox/mlx5/core/mlx5_irq.h | 12 ++++++++---- drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c | 12 +++++++++--- .../net/ethernet/mellanox/mlx5/core/sf/dev/dev.c | 2 +- 6 files changed, 41 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 40a6cb052a2d..85b93bac2529 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -708,7 +708,7 @@ static int create_async_eqs(struct mlx5_core_dev *dev) err1: mlx5_cmd_allowed_opcode(dev, CMD_ALLOWED_OPCODE_ALL); mlx5_eq_notifier_unregister(dev, &table->cq_err_nb); - mlx5_ctrl_irq_release(table->ctrl_irq); + mlx5_ctrl_irq_release(dev, table->ctrl_irq); return err; } @@ -723,7 +723,7 @@ static void destroy_async_eqs(struct mlx5_core_dev *dev) cleanup_async_eq(dev, &table->cmd_eq, "cmd"); mlx5_cmd_allowed_opcode(dev, CMD_ALLOWED_OPCODE_ALL); mlx5_eq_notifier_unregister(dev, &table->cq_err_nb); - mlx5_ctrl_irq_release(table->ctrl_irq); + mlx5_ctrl_irq_release(dev, table->ctrl_irq); } struct mlx5_eq *mlx5_get_async_eq(struct mlx5_core_dev *dev) @@ -911,7 +911,7 @@ static int comp_irq_request_sf(struct mlx5_core_dev *dev, u16 vecidx) af_desc.is_managed = 1; cpumask_copy(&af_desc.mask, cpu_online_mask); cpumask_andnot(&af_desc.mask, &af_desc.mask, &table->used_cpus); - irq = mlx5_irq_affinity_request(pool, &af_desc); + irq = mlx5_irq_affinity_request(dev, pool, &af_desc); if (IS_ERR(irq)) return PTR_ERR(irq); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c index 612e666ec263..9803ab0029b8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c @@ -112,15 +112,18 @@ irq_pool_find_least_loaded(struct mlx5_irq_pool *pool, const struct cpumask *req /** * mlx5_irq_affinity_request - request an IRQ according to the given mask. + * @dev: mlx5 core device which is requesting the IRQ. * @pool: IRQ pool to request from. * @af_desc: affinity descriptor for this IRQ. * * This function returns a pointer to IRQ, or ERR_PTR in case of error. */ struct mlx5_irq * -mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, struct irq_affinity_desc *af_desc) +mlx5_irq_affinity_request(struct mlx5_core_dev *dev, struct mlx5_irq_pool *pool, + struct irq_affinity_desc *af_desc) { struct mlx5_irq *least_loaded_irq, *new_irq; + int ret; mutex_lock(&pool->lock); least_loaded_irq = irq_pool_find_least_loaded(pool, &af_desc->mask); @@ -152,6 +155,13 @@ mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, struct irq_affinity_desc * mlx5_irq_get_index(least_loaded_irq)), pool->name, mlx5_irq_read_locked(least_loaded_irq) / MLX5_EQ_REFS_PER_IRQ); unlock: + if (mlx5_irq_pool_is_sf_pool(pool)) { + ret = auxiliary_device_sysfs_irq_add(mlx5_sf_coredev_to_adev(dev), + mlx5_irq_get_irq(least_loaded_irq)); + if (ret) + mlx5_core_err(dev, "Failed to create sysfs entry for irq %d\n", + mlx5_irq_get_irq(least_loaded_irq)); + } mutex_unlock(&pool->lock); return least_loaded_irq; } @@ -164,6 +174,9 @@ void mlx5_irq_affinity_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *i cpu = cpumask_first(mlx5_irq_get_affinity_mask(irq)); synchronize_irq(pci_irq_vector(pool->dev->pdev, mlx5_irq_get_index(irq))); + if (mlx5_irq_pool_is_sf_pool(pool)) + auxiliary_device_sysfs_irq_remove(mlx5_sf_coredev_to_adev(dev), + mlx5_irq_get_irq(irq)); if (mlx5_irq_put(irq)) if (pool->irqs_per_cpu) cpu_put(pool, cpu); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index 58732f44940f..469d86afbfb4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -320,6 +320,12 @@ static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev) return dev->coredev_type == MLX5_COREDEV_SF; } +static inline struct auxiliary_device * +mlx5_sf_coredev_to_adev(struct mlx5_core_dev *mdev) +{ + return container_of(mdev->device, struct auxiliary_device, dev); +} + int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx); void mlx5_mdev_uninit(struct mlx5_core_dev *dev); int mlx5_init_one(struct mlx5_core_dev *dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_irq.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_irq.h index 1088114e905d..0881e961d8b1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_irq.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_irq.h @@ -25,7 +25,7 @@ int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev, int devfn, int mlx5_get_default_msix_vec_count(struct mlx5_core_dev *dev, int num_vfs); struct mlx5_irq *mlx5_ctrl_irq_request(struct mlx5_core_dev *dev); -void mlx5_ctrl_irq_release(struct mlx5_irq *ctrl_irq); +void mlx5_ctrl_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *ctrl_irq); struct mlx5_irq *mlx5_irq_request(struct mlx5_core_dev *dev, u16 vecidx, struct irq_affinity_desc *af_desc, struct cpu_rmap **rmap); @@ -36,13 +36,15 @@ int mlx5_irq_attach_nb(struct mlx5_irq *irq, struct notifier_block *nb); int mlx5_irq_detach_nb(struct mlx5_irq *irq, struct notifier_block *nb); struct cpumask *mlx5_irq_get_affinity_mask(struct mlx5_irq *irq); int mlx5_irq_get_index(struct mlx5_irq *irq); +int mlx5_irq_get_irq(const struct mlx5_irq *irq); struct mlx5_irq_pool; #ifdef CONFIG_MLX5_SF struct mlx5_irq *mlx5_irq_affinity_irq_request_auto(struct mlx5_core_dev *dev, struct cpumask *used_cpus, u16 vecidx); -struct mlx5_irq *mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, - struct irq_affinity_desc *af_desc); +struct mlx5_irq * +mlx5_irq_affinity_request(struct mlx5_core_dev *dev, struct mlx5_irq_pool *pool, + struct irq_affinity_desc *af_desc); void mlx5_irq_affinity_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *irq); #else static inline @@ -53,7 +55,8 @@ struct mlx5_irq *mlx5_irq_affinity_irq_request_auto(struct mlx5_core_dev *dev, } static inline struct mlx5_irq * -mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, struct irq_affinity_desc *af_desc) +mlx5_irq_affinity_request(struct mlx5_core_dev *dev, struct mlx5_irq_pool *pool, + struct irq_affinity_desc *af_desc) { return ERR_PTR(-EOPNOTSUPP); } @@ -61,6 +64,7 @@ mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, struct irq_affinity_desc * static inline void mlx5_irq_affinity_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *irq) { + mlx5_irq_release_vector(irq); } #endif #endif /* __MLX5_IRQ_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c index 4dcf995cb1a2..831efde44b2d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -365,6 +365,11 @@ struct cpumask *mlx5_irq_get_affinity_mask(struct mlx5_irq *irq) return irq->mask; } +int mlx5_irq_get_irq(const struct mlx5_irq *irq) +{ + return irq->map.virq; +} + int mlx5_irq_get_index(struct mlx5_irq *irq) { return irq->map.index; @@ -438,11 +443,12 @@ static void _mlx5_irq_release(struct mlx5_irq *irq) /** * mlx5_ctrl_irq_release - release a ctrl IRQ back to the system. + * @dev: mlx5 device that releasing the IRQ. * @ctrl_irq: ctrl IRQ to be released. */ -void mlx5_ctrl_irq_release(struct mlx5_irq *ctrl_irq) +void mlx5_ctrl_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *ctrl_irq) { - _mlx5_irq_release(ctrl_irq); + mlx5_irq_affinity_irq_release(dev, ctrl_irq); } /** @@ -471,7 +477,7 @@ struct mlx5_irq *mlx5_ctrl_irq_request(struct mlx5_core_dev *dev) /* Allocate the IRQ in index 0. The vector was already allocated */ irq = irq_pool_request_vector(pool, 0, &af_desc, NULL); } else { - irq = mlx5_irq_affinity_request(pool, &af_desc); + irq = mlx5_irq_affinity_request(dev, pool, &af_desc); } return irq; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c index 99219ea52c4b..39fad18fc58c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c @@ -127,7 +127,7 @@ static void mlx5_sf_dev_add(struct mlx5_core_dev *dev, u16 sf_index, u16 fn_id, goto add_err; } - err = auxiliary_device_add(&sf_dev->adev); + err = auxiliary_device_add_with_irqs(&sf_dev->adev); if (err) { auxiliary_device_uninit(&sf_dev->adev); goto add_err;