From patchwork Fri May 3 06:34:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3DE2C25B10 for ; Fri, 3 May 2024 06:34:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D2A4112832; Fri, 3 May 2024 06:34:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Mgr76j6X"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1F44210F231 for ; Fri, 3 May 2024 06:34:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714718066; x=1746254066; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=97uVAvlIQu+4ZibaYCj9DsAMWhz7KzkJDF3YtBgI8Qg=; b=Mgr76j6XZmvbE8xrbv8M8N9t1bq2VGm+zjyVdZjn6E9aM8Gi9ZSS1A6I tXR9M5UHmUWdX+Nz9sJPSA/7+xwBWW0ObvXwTsjcqkmTI6sj4sXIJeIle YDtlwvP68PEQn0YyWVVInofl3qaYdc1BbJh6CnNEUtwvZwcI2cjdlMjK+ g7QgK19uvlWWu1nbdV34rDl6ilOWLsHJYkzgu740lbfbYoVfFKi5/d+ko fQT00Fa7jsdMOaN7VY/6OlQSy30BHqtp2idjGQEq79ftCqYnpOZw3Uen4 R32wP1wtV+lcEDLj0Wge2ufXDZuBarwOAJ+9LclvlsyyPDKQ48wsCMrQt A==; X-CSE-ConnectionGUID: WRoIE+7WRE2+/lNMvPA0Wg== X-CSE-MsgGUID: JMtakWZdQ+S1NbUU3qYGLw== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302301" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302301" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:26 -0700 X-CSE-ConnectionGUID: zL4rhcfcSE+9Zkegf/NDAw== X-CSE-MsgGUID: hQJrVoZ0SnCkdrGCgF3RbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558681" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:24 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 01/12] drm/i915/psr: Rename has_psr2 as has_sel_update Date: Fri, 3 May 2024 09:34:02 +0300 Message-Id: <20240503063413.1008135-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We are going to reuse has_psr2 for panel_replay as well. Rename it as has_sel_update to avoid confusion. v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp v2: Rebase Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++----- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index ccaa4cb2809b..1da4c122c52e 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -251,9 +251,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, drm_printf(&p, "sdp split: %s\n", str_enabled_disabled(pipe_config->sdp_split_enable)); - drm_printf(&p, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n", + drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n", str_enabled_disabled(pipe_config->has_psr), - str_enabled_disabled(pipe_config->has_psr2), + str_enabled_disabled(pipe_config->has_sel_update), str_enabled_disabled(pipe_config->has_panel_replay), str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 273323f30ae2..0ae18b07ac87 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5320,7 +5320,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, */ if (current_config->has_panel_replay || pipe_config->has_panel_replay) { PIPE_CONF_CHECK_BOOL(has_psr); - PIPE_CONF_CHECK_BOOL(has_psr2); + PIPE_CONF_CHECK_BOOL(has_sel_update); PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); PIPE_CONF_CHECK_BOOL(has_panel_replay); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 62f7a30c37dc..6747c10da298 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1189,7 +1189,7 @@ struct intel_crtc_state { /* PSR is supported but might not be enabled due the lack of enabled planes */ bool has_psr; - bool has_psr2; + bool has_sel_update; bool enable_psr2_sel_fetch; bool enable_psr2_su_region_et; bool req_psr2_sdp_prior_scanline; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e05e25cd4a94..0755bdfc8d3d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2660,7 +2660,7 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, vsc); - } else if (crtc_state->has_psr2) { + } else if (crtc_state->has_sel_update) { /* * [PSR2 without colorimetry] * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 151dcd0c45b6..984f13d8c0c8 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 */ - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) { + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f5b33335a9ae..a2f7d998d342 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 dpcd_val = DP_PSR_ENABLE; - if (crtc_state->has_psr2) { + if (crtc_state->has_sel_update) { /* Enable ALPM at sink for psr2 */ if (!crtc_state->has_panel_replay) { drm_dp_dpcd_writeb(&intel_dp->aux, @@ -1639,7 +1639,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (!crtc_state->has_psr) return; - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); + crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state); } void intel_psr_get_config(struct intel_encoder *encoder, @@ -1672,7 +1672,7 @@ void intel_psr_get_config(struct intel_encoder *encoder, pipe_config->has_psr = true; } - pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; + pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); if (!intel_dp->psr.psr2_enabled) @@ -1960,7 +1960,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); - intel_dp->psr.psr2_enabled = crtc_state->has_psr2; + intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; intel_dp->psr.busy_frontbuffer_bits = 0; intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; @@ -2688,7 +2688,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); needs_to_disable |= !new_crtc_state->has_psr; needs_to_disable |= !new_crtc_state->active_planes; - needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; + needs_to_disable |= new_crtc_state->has_sel_update != psr->psr2_enabled; needs_to_disable |= DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled; From patchwork Fri May 3 06:34:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3556AC4345F for ; Fri, 3 May 2024 06:34:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 14800112834; Fri, 3 May 2024 06:34:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kLcqOpts"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 92B591122C1 for ; Fri, 3 May 2024 06:34:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714718068; x=1746254068; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=13YNItMtokEWRbPdDmGTAwq5/WzagRS8IzsU4aURIMU=; b=kLcqOptskxLgmAvaB4SCioDPKG/nNNNNPQPkc2GIRRg1etzjI8MpT3zn vSk8/rsDAH+oR9j8TsVTIeLsV9FxOUdiDQOAX04BRWE52o19aOii4qq48 WbIFsIhTQ5F/8+aJ5iq7f5XquCg3d4ZnjFOxcNgM82ydbYmflZgIyKRA0 z0yYiMVKYZ341+b0GhU5J/YsYn9jk5ROb5H9wMBtOamfEXsa6DXRKvjRI 9HGIWEq8o+2tHNlIMmRJYINvmu+53dYbjnC25r4MejfLSUwYMv31yxwYL lq3rTzisINmJcgSWDEnvuV7bG0j+s4cbFdxgH9sIDdlTbXeRwKDI/6GR2 g==; X-CSE-ConnectionGUID: VFZ/75USQEG0rnlLVgkeQA== X-CSE-MsgGUID: +ZKyuh1bQ4q3/GY+iNGuoQ== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302302" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302302" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:28 -0700 X-CSE-ConnectionGUID: H4YtOz0gQEeOHUV1vjUw6g== X-CSE-MsgGUID: 0Ljt6nyHQEeHA5HNTaipog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558685" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:26 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 02/12] drm/i915/display: Do not print "psr: enabled" for on Panel Replay Date: Fri, 3 May 2024 09:34:03 +0300 Message-Id: <20240503063413.1008135-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" After setting has_psr for panel replay as well crtc state dump is improperly printing "psr: enabled" for Panel Replay as well. Fix this by checking also has_panel_replay. Fixes: 5afa6e496098 ("drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 1da4c122c52e..bddcc9edeab4 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -252,7 +252,8 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, str_enabled_disabled(pipe_config->sdp_split_enable)); drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n", - str_enabled_disabled(pipe_config->has_psr), + str_enabled_disabled(pipe_config->has_psr && + !pipe_config->has_panel_replay), str_enabled_disabled(pipe_config->has_sel_update), str_enabled_disabled(pipe_config->has_panel_replay), str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); From patchwork Fri May 3 06:34:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85574C10F16 for ; Fri, 3 May 2024 06:34:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 16934112835; Fri, 3 May 2024 06:34:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eUW3LQi2"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 079BF1122C1 for ; Fri, 3 May 2024 06:34:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714718069; x=1746254069; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bIjNGpLd442lBCqK3+yWagH4iUW7/8KdiGmklZCH+7U=; b=eUW3LQi2et85DnkfBNWBd32ExmoCB1qA8U8azlc5yvGKmtb1ztAL9Ry7 dCIonYZ3T4SvjCTXtNGxeeoCpmZqYTUQyZT/LMVKYIfgZtKdclvU7tEuG 1u0tMOxnXLsfA7DVRvVBvj991ocReDy1EtLH4vQRy3/BCTjq7Nsh0iE7L zpj41TYIfCZrwh6hkB4j0cpqmb4Iqc7ntxcVmOLMspEhQB3eGhqTj6zru IShKZD0+B8XyYPQ9ogZfM0ghY9z7GDaMVO6cYZAx6oi9i7VhGGe7tq6Y4 1755Dht3uGHOChPWZfDwIhonHJM0L7VO8kcFaegMUvetsh/3whc9BU7Mt w==; X-CSE-ConnectionGUID: O0ozxCpOSyiffdoGZZEimw== X-CSE-MsgGUID: A6z38nVIQJ25TD2nVsxCuw== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302306" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302306" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:29 -0700 X-CSE-ConnectionGUID: S8cm6OAkTpGN/CS5P64dqg== X-CSE-MsgGUID: Tm/qc5+ASxmZghKSRa+GGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558688" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:27 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 03/12] drm/i915/dp: Use always vsc revision 0x6 for Panel Replay Date: Fri, 3 May 2024 09:34:04 +0300 Message-Id: <20240503063413.1008135-4-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We are about to enable Panel Replay Selective update mode. Vsc revision 0x6 for Panel Replay no matter if it is selective update or full frame update mode. Take this into account when preparing VSC SDP package. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0755bdfc8d3d..5731aa84992e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2660,14 +2660,6 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, vsc); - } else if (crtc_state->has_sel_update) { - /* - * [PSR2 without colorimetry] - * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 - * 3D stereo + PSR/PSR2 + Y-coordinate. - */ - vsc->revision = 0x4; - vsc->length = 0xe; } else if (crtc_state->has_panel_replay) { /* * [Panel Replay without colorimetry info] @@ -2676,6 +2668,14 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, */ vsc->revision = 0x6; vsc->length = 0x10; + } else if (crtc_state->has_sel_update) { + /* + * [PSR2 without colorimetry] + * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 + * 3D stereo + PSR/PSR2 + Y-coordinate. + */ + vsc->revision = 0x4; + vsc->length = 0xe; } else { /* * [PSR1] From patchwork Fri May 3 06:34:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D942C4345F for ; Fri, 3 May 2024 06:34:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C90E91122C1; Fri, 3 May 2024 06:34:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="T3cHkfa2"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id A8B631122C1 for ; Fri, 3 May 2024 06:34:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714718071; x=1746254071; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wjFS1+NbG2Vvr7sQVgcyDtGvUeFHdIugMx1Q11+bLFs=; b=T3cHkfa27O0VgPM0lnMNXaYpBNgVoWKa6CD3SBoCboGqoP0f9UcF2M0I EwLTF7250GPcNArYXtnlt/fd2u/BVRoIJJ0DupFsTQVwcNN4af5vUdg5J auMyiIah5nFOvWX71qpscnegEeqONnT9K9BRIfVCmjeRatHeG4FCc055X JlkLIrFnn9F4bXyOLvDoaVTjTi0fEAcmxXgzmF/ok9hIMF7Gue0NoXOYC /uR/EHBJgeUafOOYzorInJbeNFm8nmrSQl53zbisreXl8MAMSED2dYuh+ bFozU10LyYLL4BYzWfdw4FLykBiwMboLdfckmRRtaxbcBmixAVyVF7l9p g==; X-CSE-ConnectionGUID: XGYMJADSTUKbXu1bEsBHHA== X-CSE-MsgGUID: c/UGAdPuQ+6aRwweowuD8Q== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302308" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302308" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:31 -0700 X-CSE-ConnectionGUID: 52KteBUaR0+hvMg4Ud6CSQ== X-CSE-MsgGUID: T7FvAO9GR1GsMvl84cAu4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558693" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:29 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 04/12] drm/i915/psr: Rename psr2_enabled as sel_update_enabled Date: Fri, 3 May 2024 09:34:05 +0300 Message-Id: <20240503063413.1008135-5-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We are about to reuse psr2_enabled for panel replay as well. Rename it as sel_update_enabled to avoid confusion. v3: Rebase v2: Rebase Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- .../drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 52 +++++++++---------- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 6747c10da298..150e6c8e0320 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1695,7 +1695,7 @@ struct intel_psr { unsigned int busy_frontbuffer_bits; bool sink_psr2_support; bool link_standby; - bool psr2_enabled; + bool sel_update_enabled; bool psr2_sel_fetch_enabled; bool psr2_sel_fetch_cff_enabled; bool req_psr2_sdp_prior_scanline; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a2f7d998d342..af18728460c9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -356,12 +356,12 @@ static void psr_irq_control(struct intel_dp *intel_dp) } static void psr_event_print(struct drm_i915_private *i915, - u32 val, bool psr2_enabled) + u32 val, bool sel_update_enabled) { drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); - if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) + if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled) drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); @@ -389,7 +389,7 @@ static void psr_event_print(struct drm_i915_private *i915, drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); if (val & PSR_EVENT_LPSP_MODE_EXIT) drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); - if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) + if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled) drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); } @@ -417,7 +417,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0); - psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled); + psr_event_print(dev_priv, val, intel_dp->psr.sel_update_enabled); } } @@ -1672,10 +1672,10 @@ void intel_psr_get_config(struct intel_encoder *encoder, pipe_config->has_psr = true; } - pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; + pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); - if (!intel_dp->psr.psr2_enabled) + if (!intel_dp->psr.sel_update_enabled) goto unlock; if (HAS_PSR2_SEL_FETCH(dev_priv)) { @@ -1711,7 +1711,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) /* psr1, psr2 and panel-replay are mutually exclusive.*/ if (intel_dp->psr.panel_replay_enabled) dg2_activate_panel_replay(intel_dp); - else if (intel_dp->psr.psr2_enabled) + else if (intel_dp->psr.sel_update_enabled) hsw_activate_psr2(intel_dp); else hsw_activate_psr1(intel_dp); @@ -1770,7 +1770,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) struct intel_psr *psr = &intel_dp->psr; u32 alpm_ctl; - if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.psr2_enabled && + if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && !intel_dp_is_edp(intel_dp))) return; @@ -1894,7 +1894,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, */ wm_optimization_wa(intel_dp, crtc_state); - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { if (DISPLAY_VER(dev_priv) == 9) intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, PSR2_VSC_ENABLE_PROG_HEADER | @@ -1960,7 +1960,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); - intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; + intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; intel_dp->psr.busy_frontbuffer_bits = 0; intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; @@ -1981,7 +1981,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n"); } else { drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", - intel_dp->psr.psr2_enabled ? "2" : "1"); + intel_dp->psr.sel_update_enabled ? "2" : "1"); /* * Panel replay has to be enabled before link training: doing it @@ -2021,7 +2021,7 @@ static void intel_psr_exit(struct intel_dp *intel_dp) if (intel_dp->psr.panel_replay_enabled) { intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), TRANS_DP2_PANEL_REPLAY_ENABLE, 0); - } else if (intel_dp->psr.psr2_enabled) { + } else if (intel_dp->psr.sel_update_enabled) { tgl_disallow_dc3co_on_psr2_exit(intel_dp); val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder), @@ -2044,7 +2044,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) i915_reg_t psr_status; u32 psr_status_mask; - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { psr_status = EDP_PSR2_STATUS(cpu_transcoder); psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; } else { @@ -2072,7 +2072,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n"); else drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", - intel_dp->psr.psr2_enabled ? "2" : "1"); + intel_dp->psr.sel_update_enabled ? "2" : "1"); intel_psr_exit(intel_dp); intel_psr_wait_exit_locked(intel_dp); @@ -2085,7 +2085,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, wa_16013835468_bit_get(intel_dp), 0); - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { /* Wa_16012604467:adlp,mtl[a0,b0] */ if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, @@ -2114,12 +2114,12 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_psr_get_enable_sink_offset(intel_dp), 0); if (!intel_dp->psr.panel_replay_enabled && - intel_dp->psr.psr2_enabled) + intel_dp->psr.sel_update_enabled) drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); intel_dp->psr.enabled = false; intel_dp->psr.panel_replay_enabled = false; - intel_dp->psr.psr2_enabled = false; + intel_dp->psr.sel_update_enabled = false; intel_dp->psr.psr2_sel_fetch_enabled = false; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; } @@ -2688,7 +2688,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); needs_to_disable |= !new_crtc_state->has_psr; needs_to_disable |= !new_crtc_state->active_planes; - needs_to_disable |= new_crtc_state->has_sel_update != psr->psr2_enabled; + needs_to_disable |= new_crtc_state->has_sel_update != psr->sel_update_enabled; needs_to_disable |= DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled; @@ -2806,7 +2806,7 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat if (!intel_dp->psr.enabled) continue; - if (intel_dp->psr.psr2_enabled) + if (intel_dp->psr.sel_update_enabled) ret = _psr2_ready_for_pipe_update_locked(intel_dp); else ret = _psr1_ready_for_pipe_update_locked(intel_dp); @@ -2827,7 +2827,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) if (!intel_dp->psr.enabled) return false; - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { reg = EDP_PSR2_STATUS(cpu_transcoder); mask = EDP_PSR2_STATUS_STATE_MASK; } else { @@ -3068,7 +3068,7 @@ tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || + if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || !intel_dp->psr.active) return; @@ -3266,7 +3266,7 @@ static void psr_alpm_check(struct intel_dp *intel_dp) u8 val; int r; - if (!psr->psr2_enabled) + if (!psr->sel_update_enabled) return; r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); @@ -3446,7 +3446,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) const char *status = "unknown"; u32 val, status_val; - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { static const char * const live_status[] = { "IDLE", "CAPTURE", @@ -3510,7 +3510,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) if (psr->panel_replay_enabled) status = "Panel Replay Enabled"; else if (psr->enabled) - status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; + status = psr->sel_update_enabled ? "PSR2 enabled" : "PSR1 enabled"; else status = "disabled"; seq_printf(m, "PSR mode: %s\n", status); @@ -3525,7 +3525,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) if (psr->panel_replay_enabled) { val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder)); enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; - } else if (psr->psr2_enabled) { + } else if (psr->sel_update_enabled) { val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)); enabled = val & EDP_PSR2_ENABLE; } else { @@ -3551,7 +3551,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) seq_printf(m, "Last exit at: %lld\n", psr->last_exit); } - if (psr->psr2_enabled) { + if (psr->sel_update_enabled) { u32 su_frames_val[3]; int frame; From patchwork Fri May 3 06:34:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 641D6C25B10 for ; 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X-CSE-ConnectionGUID: OrlVcNUjTDqsObzhkCJZyg== X-CSE-MsgGUID: P/XAt6LvTb+weVG3MoYD8A== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302312" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302312" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:32 -0700 X-CSE-ConnectionGUID: Mhru9ibUR+izdzKukJSxgA== X-CSE-MsgGUID: U1H/ntMtTLKDAxYHlnBQLQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558701" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:30 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 05/12] drm/panelreplay: dpcd register definition for panelreplay SU Date: Fri, 3 May 2024 09:34:06 +0300 Message-Id: <20240503063413.1008135-6-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add definitions for panel replay selective update v2: Remove unnecessary Cc from commit message Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- include/drm/display/drm_dp.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 0b032faa8cf2..906949ca3cee 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -548,6 +548,12 @@ # define DP_PANEL_REPLAY_SUPPORT (1 << 0) # define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) +#define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1 +# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5) + +#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY 0xb2 +#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY 0xb4 + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ From patchwork Fri May 3 06:34:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D64FEC10F16 for ; Fri, 3 May 2024 06:34:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B796112839; Fri, 3 May 2024 06:34:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UXfhZo/i"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 90085112837 for ; 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02 May 2024 23:34:34 -0700 X-CSE-ConnectionGUID: dX6eL8OzQI6+maehEatQCQ== X-CSE-MsgGUID: lPu1I24wRSO3CdCva3E6bQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558713" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:32 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 06/12] drm/i915/psr: Detect panel replay selective update support Date: Fri, 3 May 2024 09:34:07 +0300 Message-Id: <20240503063413.1008135-7-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add new boolean to store panel replay selective update support of sink into intel_psr struct. Detect panel replay selective update support and store it into this new boolean. v3: Clear sink_panel_replay_su_support in intel_dp_detect v2: Merge adding new boolean into this patch Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++++++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 150e6c8e0320..a693728f8344 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1719,6 +1719,7 @@ struct intel_psr { u16 su_y_granularity; bool source_panel_replay_support; bool sink_panel_replay_support; + bool sink_panel_replay_su_support; bool panel_replay_enabled; u32 dc3co_exitline; u32 dc3co_exit_delay; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5731aa84992e..180f23f7b383 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5858,6 +5858,7 @@ intel_dp_detect(struct drm_connector *connector, memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); intel_dp->psr.sink_panel_replay_support = false; + intel_dp->psr.sink_panel_replay_su_support = false; intel_dp_mst_disconnect(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index af18728460c9..b94f8e33ed1f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -520,9 +520,15 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) return; } - drm_dbg_kms(&i915->drm, - "Panel replay is supported by panel\n"); intel_dp->psr.sink_panel_replay_support = true; + + if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT) + intel_dp->psr.sink_panel_replay_su_support = true; + + drm_dbg_kms(&i915->drm, + "Panel replay %sis supported by panel\n", + intel_dp->psr.sink_panel_replay_su_support ? + "selective_update " : ""); } static void _psr_init_dpcd(struct intel_dp *intel_dp) From patchwork Fri May 3 06:34:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 975F7C4345F for ; Fri, 3 May 2024 06:34:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1761811283A; Fri, 3 May 2024 06:34:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Oal/k7xV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 528DE11283A for ; Fri, 3 May 2024 06:34:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714718076; x=1746254076; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hmV08wrDo5meNJn9XyzFU7cFYtuhEKiU0pEXrCfMV/A=; b=Oal/k7xVfatignMU0dleCjOc+5hqj0V8yQWDzBRGGrnkC24hn86UN4LH qnK4HrlBQEam6WGEcMjc8UguHaSxSiDYI9RCzepvWF22nAdA6eY1PovOH EymTl2RHNdlQlisj+fPM+/jCvIzE7eFLBhmv8RlaoDAeYjzA6I4f3c7kJ K/ZT9qSzOcRwcJZyfFMlJsofcrYmbeMhntNwbk/Z2m7zYI16I7+yIRokg vhfRy5Beyr+gjTNh7JmMjamFJHyz8CaZGNKI+npuWc16P9fQ3oQAjDtF8 LyICwKItw/0oRzc1Hf1A0BelriGIFhamHPcXuPNMvgILuQ9YeZOAD3Ka6 A==; X-CSE-ConnectionGUID: 46DUhiHqSPab6PTGq9gmSw== X-CSE-MsgGUID: 0iWIH1OrQIenDzGYomEx3Q== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302316" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302316" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:35 -0700 X-CSE-ConnectionGUID: b7PgpDS4TOOxM9hqVdWgDA== X-CSE-MsgGUID: zQNuugcxQR6jIDWwYhIwAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558721" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:33 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 07/12] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay Date: Fri, 3 May 2024 09:34:08 +0300 Message-Id: <20240503063413.1008135-8-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently intel_dp_get_su_granularity doesn't support panel replay. This fix modifies it to support panel replay as well. v4: - use drm_dp_dpcd_readb instead of drm_dp_dpcd_read - ensure return value is 0 if drm_dp_dpcd_readb fails v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY v2: rely on PSR definitions on common bits Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 62 +++++++++++++++++++++--- 1 file changed, 55 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b94f8e33ed1f..5e5ef432b931 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -466,6 +466,40 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) return val; } +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) +{ + u8 su_capability = 0; + + if (intel_dp->psr.sink_panel_replay_su_support) + drm_dp_dpcd_readb(&intel_dp->aux, + DP_PANEL_PANEL_REPLAY_CAPABILITY, + &su_capability); + else + su_capability = intel_dp->psr_dpcd[1]; + + return su_capability; +} + +static unsigned int +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) +{ + return intel_dp->psr.sink_panel_replay_su_support ? + DP_PANEL_PANEL_REPLAY_X_GRANULARITY : + DP_PSR2_SU_X_GRANULARITY; +} + +static unsigned int +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) +{ + return intel_dp->psr.sink_panel_replay_su_support ? + DP_PANEL_PANEL_REPLAY_Y_GRANULARITY : + DP_PSR2_SU_Y_GRANULARITY; +} + +/* + * Note: Bits related to granularity are same in panel replay and psr + * registers. Rely on PSR definitions on these "common" bits. + */ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -473,18 +507,29 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) u16 w; u8 y; - /* If sink don't have specific granularity requirements set legacy ones */ - if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { + /* + * TODO: Do we need to take into account panel supporting both PSR and + * Panel replay? + */ + + /* + * If sink don't have specific granularity requirements set legacy + * ones. + */ + if (!(intel_dp_get_su_capability(intel_dp) & + DP_PSR2_SU_GRANULARITY_REQUIRED)) { /* As PSR2 HW sends full lines, we do not care about x granularity */ w = 4; y = 4; goto exit; } - r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); + r = drm_dp_dpcd_read(&intel_dp->aux, + intel_dp_get_su_x_granularity_offset(intel_dp), + &w, 2); if (r != 2) drm_dbg_kms(&i915->drm, - "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); + "Unable to read selective update x granularity\n"); /* * Spec says that if the value read is 0 the default granularity should * be used instead. @@ -492,10 +537,12 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) if (r != 2 || w == 0) w = 4; - r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); + r = drm_dp_dpcd_read(&intel_dp->aux, + intel_dp_get_su_y_granularity_offset(intel_dp), + &y, 1); if (r != 1) { drm_dbg_kms(&i915->drm, - "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); + "Unable to read selective update y granularity\n"); y = 4; } if (y == 0) @@ -588,7 +635,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) if (intel_dp->psr_dpcd[0]) _psr_init_dpcd(intel_dp); - if (intel_dp->psr.sink_psr2_support) + if (intel_dp->psr.sink_psr2_support || + intel_dp->psr.sink_panel_replay_su_support) intel_dp_get_su_granularity(intel_dp); } From patchwork Fri May 3 06:34:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E43AC10F16 for ; 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X-CSE-ConnectionGUID: NCB/3WZ1SY6q6r1LJtwl/g== X-CSE-MsgGUID: viyVI2fsQ6uDxWCAk1BmWQ== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302317" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302317" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:36 -0700 X-CSE-ConnectionGUID: 9hkie/lRTbOeM6/a0sD4fA== X-CSE-MsgGUID: Euygj68NS6OxPKaoLZNH/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558724" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:35 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to track it's status Date: Fri, 3 May 2024 09:34:09 +0300 Message-Id: <20240503063413.1008135-9-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DP Panel replay uses SRD_STATUS to track it's status despite selective update mode. Bspec: 53370, 68920 v3: - do not use PSR2_STATUS for PSR1 v2: - use intel_dp_is_edp to differentiate - modify debugfs status as well Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 5e5ef432b931..8f23df5cd5a8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2860,7 +2860,8 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat if (!intel_dp->psr.enabled) continue; - if (intel_dp->psr.sel_update_enabled) + if (intel_dp_is_edp(intel_dp) && + intel_dp->psr.sel_update_enabled) ret = _psr2_ready_for_pipe_update_locked(intel_dp); else ret = _psr1_ready_for_pipe_update_locked(intel_dp); @@ -2881,7 +2882,8 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) if (!intel_dp->psr.enabled) return false; - if (intel_dp->psr.sel_update_enabled) { + if (!intel_dp->psr.panel_replay_enabled && + intel_dp->psr.sel_update_enabled) { reg = EDP_PSR2_STATUS(cpu_transcoder); mask = EDP_PSR2_STATUS_STATE_MASK; } else { @@ -3500,7 +3502,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) const char *status = "unknown"; u32 val, status_val; - if (intel_dp->psr.sel_update_enabled) { + if (intel_dp_is_edp(intel_dp) && intel_dp->psr.sel_update_enabled) { static const char * const live_status[] = { "IDLE", "CAPTURE", From patchwork Fri May 3 06:34:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18371C4345F for ; Fri, 3 May 2024 06:34:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8481F11283C; Fri, 3 May 2024 06:34:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="il1nGffg"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id D3FFE11283C for ; Fri, 3 May 2024 06:34:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714718078; x=1746254078; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G+XCDBFQicvVew/WBuxU4pp28stMGXaFi83759HGhnA=; b=il1nGffgbS/MoaaxHF1kFlOYJnF0o8vgmCWRd6YKocr9jLXR74xVlDjC HfzhjIU6KXf6shmBIkNKc/lfAiJDLVEadhrqbmLdUF6CfN2xunaiVvS4U qw9Nj7J5mqCsNG4hb1PUfSc0vSAM3pa0XfCDL30CP9/PhyzZmQNHbE/J+ UqknMZhbc+yskALsjK3SmmsUqa8Q2TxhrZWCliyeRv9pzr182KDSaeRjk JWxgg9CZq7VnndMvWA/B/yrVI+hXYSGX9ThN3YJaNjGo1TmozRv8F6WDZ IeSHt+I/c1b5RVCxoX15On5ZlF0wz3qTDmuFMey8eW4Rw0lYSlrBYe6kb Q==; X-CSE-ConnectionGUID: aCoEy8k2Qu+RGRnK6YFgXg== X-CSE-MsgGUID: d5Ylb0sNSGe6qfcZwv46Hg== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302321" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302321" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:38 -0700 X-CSE-ConnectionGUID: avbzwrkATnq7KEzm2KvS0w== X-CSE-MsgGUID: WAeBcajZTf6kw7XsMKduyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558738" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:36 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 09/12] drm/i915/psr: Do not apply workarounds in case of panel replay Date: Fri, 3 May 2024 09:34:10 +0300 Message-Id: <20240503063413.1008135-10-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" There are some workarounds that are not applicable for panel replay. Do not apply these if panel replay is used. Bspec: 66624, 50422 Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++- drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++++------ 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 984f13d8c0c8..50dd8eb9012e 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1251,7 +1251,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 */ - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) { + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update && + !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; } @@ -1259,7 +1260,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, /* Wa_14016291713 */ if ((IS_DISPLAY_VER(i915, 12, 13) || IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) && - crtc_state->has_psr) { + crtc_state->has_psr && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 5f6deceaf8ba..0faf2afa1c09 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -532,7 +532,8 @@ void hsw_write_infoframe(struct intel_encoder *encoder, 0); /* Wa_14013475917 */ - if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC)) + if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && + !crtc_state->has_panel_replay && type == DP_SDP_VSC)) val |= hsw_infoframe_enable(type); if (type == DP_SDP_VSC) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8f23df5cd5a8..f2eca0db47fd 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1959,13 +1959,15 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, * All supported adlp panels have 1-based X granularity, this may * cause issues if non-supported panels are used. */ - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || - IS_ALDERLAKE_P(dev_priv)) + if (!intel_dp->psr.panel_replay_enabled && + (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || + IS_ALDERLAKE_P(dev_priv))) intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), 0, ADLP_1_BASED_X_GRANULARITY); /* Wa_16012604467:adlp,mtl[a0,b0] */ - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) + if (!intel_dp->psr.panel_replay_enabled && + IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0, MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); @@ -2141,7 +2143,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) if (intel_dp->psr.sel_update_enabled) { /* Wa_16012604467:adlp,mtl[a0,b0] */ - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) + if (!intel_dp->psr.panel_replay_enabled && + IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, MTL_CLKGATE_DIS_TRANS(cpu_transcoder), MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -2627,8 +2630,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, goto skip_sel_fetch_set_loop; /* Wa_14014971492 */ - if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || - IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) && + if (!crtc_state->has_panel_replay && + ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || + IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) && crtc_state->splitter.enable) crtc_state->psr2_su_area.y1 = 0; From patchwork Fri May 3 06:34:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F41CC10F16 for ; Fri, 3 May 2024 06:34:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1668411283F; Fri, 3 May 2024 06:34:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="B8zREdiM"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 503F211283C for ; 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02 May 2024 23:34:39 -0700 X-CSE-ConnectionGUID: J7mTBDq2Tlm5/Tw6ziYzPQ== X-CSE-MsgGUID: xzH4pTqpSWyg6UTHwBg9og== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558741" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:37 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 10/12] drm/i915/psr: Update PSR module parameter descriptions Date: Fri, 3 May 2024 09:34:11 +0300 Message-Id: <20240503063413.1008135-11-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We are re-using PSR module parameters for panel replay. Update module parameter descriptions with panel replay information: enable_psr: -1 (default) == follow what is in VBT 0 == disable PSR/PR 1 == Allow PSR1 and PR full frame update 2 == allow PSR1/PSR2 and PR Selective Update enable_psr2_sel_fetch 0 == disable selective fetch for PSR and PR 1 (default) == allow selective fetch for PSR PR Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display_params.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index 1799a6643128..aebdb7b59dbf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -106,7 +106,8 @@ intel_display_param_named_unsafe(enable_fbc, int, 0400, intel_display_param_named_unsafe(enable_psr, int, 0400, "Enable PSR " - "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) " + "(0=disabled, 1=enable up to PSR1 and Panel Replay full frame update, " + "2=enable up to PSR2 and Panel Replay Selective Update) " "Default: -1 (use per-chip default)"); intel_display_param_named(psr_safest_params, bool, 0400, @@ -116,7 +117,7 @@ intel_display_param_named(psr_safest_params, bool, 0400, "Default: 0"); intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, - "Enable PSR2 selective fetch " + "Enable PSR2 and Panel Replay selective fetch " "(0=disabled, 1=enabled) " "Default: 1"); From patchwork Fri May 3 06:34:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E4C3C4345F for ; Fri, 3 May 2024 06:34:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5DEB11283D; Fri, 3 May 2024 06:34:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="IyXGiV+a"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id B8AB911283D for ; Fri, 3 May 2024 06:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714718081; x=1746254081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HJ2R/L8dWp0t8fHF2C108JVrTsUZc8Zn52FPUgb1mSA=; b=IyXGiV+aRkwIWs69qvgwqqW+rr89vs2o2nTvFlRMempEJSyh+nHOo0rW /RX8Nl0ZLhgkRxEy9hD5/tSoAL7ixz3nZIhI2EEE4AXJ3zUQsUxvsUsqc hPWdemz80gqONbdZXYz6b0bR3hiaNA5wmvlstIvWt91WoKIfbhVIMk8f4 8GbYwx9FQo0GhDo97Uy+9wfieBCg783thok+FaBI5kq0KIyLA7nJkSybP 2uxuVJYEsdKLR1nrR36SjveYQf9NUYIREgvBh4Wcz881yEzWEJHLmRGdF RewnQSusocjwQWRf7yvQ8fVj1bAcwHNRbBqUo8Ag6k3fQgwx7IJiBTZzD w==; X-CSE-ConnectionGUID: PZ4/MeW/S6qXJ1wDInrIhQ== X-CSE-MsgGUID: eGUP8IaaTsWbtWVgGS3+Ug== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302324" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302324" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:41 -0700 X-CSE-ConnectionGUID: aO8Od+fxSD6LdVZkIPiN0w== X-CSE-MsgGUID: Uo4jmQQNRDynpwFiZzwVpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558744" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:39 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v9 11/12] drm/i915/psr: Split intel_psr2_config_valid for panel replay Date: Fri, 3 May 2024 09:34:12 +0300 Message-Id: <20240503063413.1008135-12-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Part of intel_psr2_config_valid is valid for panel replay. rename it as intel_sel_update_config_valid. Split psr2 specific part and name it as intel_psr2_config_valid. v3: - move early transport check to psr2 specific check - check intel_psr2_config_valid only for non-Panel Replay case v2: - use psr2_global_enabled for panel replay as well - goto unsupported instead of return when global enabled check fails Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 76 ++++++++++++++---------- 1 file changed, 46 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f2eca0db47fd..2198448fdb27 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1142,9 +1142,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, return false; } - if (psr2_su_region_et_valid(intel_dp)) - crtc_state->enable_psr2_su_region_et = true; - return crtc_state->enable_psr2_sel_fetch = true; } @@ -1515,11 +1512,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (!psr2_global_enabled(intel_dp)) { - drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); - return false; - } - /* * DSC and PSR2 cannot be enabled simultaneously. If a requested * resolution requires DSC to be enabled, priority is given to DSC @@ -1532,12 +1524,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (crtc_state->crc_enabled) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); - return false; - } - if (DISPLAY_VER(dev_priv) >= 12) { psr_max_h = 5120; psr_max_v = 3200; @@ -1588,30 +1574,60 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (HAS_PSR2_SEL_FETCH(dev_priv)) { - if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && - !HAS_PSR_HW_TRACKING(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); - return false; - } - } - - if (!psr2_granularity_check(intel_dp, crtc_state)) { - drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); - goto unsupported; - } - if (!crtc_state->enable_psr2_sel_fetch && (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", crtc_hdisplay, crtc_vdisplay, psr_max_h, psr_max_v); - goto unsupported; + return false; } tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); + + if (psr2_su_region_et_valid(intel_dp)) + crtc_state->enable_psr2_su_region_et = true; + + return true; +} + +static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if (HAS_PSR2_SEL_FETCH(dev_priv) && + !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && + !HAS_PSR_HW_TRACKING(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); + goto unsupported; + } + + if (!psr2_global_enabled(intel_dp)) { + drm_dbg_kms(&dev_priv->drm, "Selective update disabled by flag\n"); + goto unsupported; + } + + if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state)) + goto unsupported; + + if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 || + !intel_dp->psr.sink_panel_replay_su_support)) + goto unsupported; + + if (crtc_state->crc_enabled) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled because it would inhibit pipe CRC calculation\n"); + goto unsupported; + } + + if (!psr2_granularity_check(intel_dp, crtc_state)) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled, SU granularity not compatible\n"); + goto unsupported; + } + return true; unsupported: @@ -1693,7 +1709,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (!crtc_state->has_psr) return; - crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state); + crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); } void intel_psr_get_config(struct intel_encoder *encoder, From patchwork Fri May 3 06:34:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13652466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2BA85C25B10 for ; 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X-CSE-ConnectionGUID: YRp6YYOBSUedzgHtBGiLow== X-CSE-MsgGUID: iLFUYrEoRs+z3ElpE76R6Q== X-IronPort-AV: E=McAfee;i="6600,9927,11062"; a="14302327" X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="14302327" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:42 -0700 X-CSE-ConnectionGUID: +4fFPLw8Q62+I4dKQvmaWQ== X-CSE-MsgGUID: TL9wn82RSe20cjgobTegjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,247,1708416000"; d="scan'208";a="50558747" Received: from azaki-mobl.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.32.146]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2024 23:34:40 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= , Kunal Joshi Subject: [PATCH v9 12/12] drm/i915/psr: Add panel replay sel update support to debugfs interface Date: Fri, 3 May 2024 09:34:13 +0300 Message-Id: <20240503063413.1008135-13-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240503063413.1008135-1-jouni.hogander@intel.com> References: <20240503063413.1008135-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add panel replay selective update support to debugfs status interface. In case of sink supporting panel replay we will print out: Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes and PSR mode will look like this if printing out enabled panel replay selective update: PSR mode: Panel Replay Selective Update Enabled Current PSR and panel replay printouts remain same. Cc: Kunal Joshi Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 2198448fdb27..2ad7964998e0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3575,7 +3575,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) if (psr->sink_support) seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); - seq_printf(m, ", Panel Replay = %s\n", str_yes_no(psr->sink_panel_replay_support)); + seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); + seq_printf(m, ", Panel Replay Selective Update = %s\n", + str_yes_no(psr->sink_panel_replay_su_support)); if (!(psr->sink_support || psr->sink_panel_replay_support)) return 0; @@ -3584,9 +3586,10 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) mutex_lock(&psr->lock); if (psr->panel_replay_enabled) - status = "Panel Replay Enabled"; + status = psr->sel_update_enabled ? "Panel Replay Selective Update Enabled" : + "Panel Replay Enabled"; else if (psr->enabled) - status = psr->sel_update_enabled ? "PSR2 enabled" : "PSR1 enabled"; + status = psr->sel_update_enabled ? "PSR2" : "PSR1"; else status = "disabled"; seq_printf(m, "PSR mode: %s\n", status);