From patchwork Mon May 6 12:37:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25412C10F16 for ; Mon, 6 May 2024 12:38:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3xbJ-00015V-Hw; Mon, 06 May 2024 08:37:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3xbB-00014Q-CF for qemu-devel@nongnu.org; Mon, 06 May 2024 08:37:41 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s3xb9-0001vQ-Ij for qemu-devel@nongnu.org; Mon, 06 May 2024 08:37:41 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-34dc9065606so1000711f8f.1 for ; Mon, 06 May 2024 05:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714999058; x=1715603858; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ms63JUeYQatGE3m9Aklqy6cJtKRUtl0Fpr26HXH+Ppg=; b=yJl95uhKu3XnnmZ+O2az6cjAje8ewLyCDTo18UXuYzhLyhQZw1OrINE4guC/qJz11n 1lO7dsySJqwldGoPSwFf1a/SLIzra5+7OdyKH/4/6Og8gcBNE90aSMMu3eDoZVmqNYN5 NXXfYqdxLhTfz51KIXHophVUSD+1ZgTm0Pei/ZcmNEkimdZl6FyUUwjp52sPzsd8MG4e jo3e8XZVt8hYQ3DYL3voZTL94QNW47H7LhuMzEfkBiQt5MFkdPxMvkvf8KeVEp4w9BT2 RwEipIS14rT2knUeCR3wsgBUpHSfeb6kG3eE6dZ2scOnVVRWiGd2HFz32j6ojSihx55X KNYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714999058; x=1715603858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ms63JUeYQatGE3m9Aklqy6cJtKRUtl0Fpr26HXH+Ppg=; b=pjMsF/9+oCePwbgG9bOXm6XP1IAUzSDmJ1Pm48gryX/a5V73hdd3p34F3ESeMwYvCj 8Rltdq5KIe6GFq1rPxOBATp8XOqlbz0MCq/PM4+itO2YnLJCaNUs6oTwPRn+csGC/vko wFI6am4ByYNaPv53KEMXecsFDwUEEaIdcYpauI0Ns0npFC4t7TIcCR62XGM8Weis/VXY JFqH4UUgOmDo8rowq5l6UCUEpnfrYGfyHQPsV++PSA6m+HqzzLjM/8cals31D55LB2Fc CDpK02favKs4wBKBCZ+6YhK1RNgj04QZWARhzr3kRqTLo4hnCl4nvCAViwdhMC21ofgF UG7g== X-Gm-Message-State: AOJu0YxcAcTswyFH7W+WswlkWYE8t6x9+4ijtgwNmUFWUYJUKEtkCZrU 3UNC8+tlMwHMQpLC+NJxqjNWlhJs+iHpAvCeH3t2aNg9mJOBC6rGVGRHOLohPqWN3KD3UsFzmgT o X-Google-Smtp-Source: AGHT+IHhArs3ahEP39ku8hZOue724Vz8Vt2Oqb0zLhk7z5sQ0d3SBJRntiNf16s3MhwBDU863+cu/A== X-Received: by 2002:a5d:4c91:0:b0:34d:a37d:d383 with SMTP id z17-20020a5d4c91000000b0034da37dd383mr11873247wrs.22.1714999057721; Mon, 06 May 2024 05:37:37 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id t3-20020a05600001c300b0034df7313bf1sm10715987wrx.0.2024.05.06.05.37.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:37:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 01/28] exec/cpu: Indent TARGET_PAGE_foo definitions Date: Mon, 6 May 2024 14:37:01 +0200 Message-ID: <20240506123728.65278-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The TARGET_PAGE_foo definitions are defined with multiple level of #ifdef'ry. Indent it a bit for clarity. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240427155714.53669-6-philmd@linaro.org> --- include/exec/cpu-all.h | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 032c6d990e..14fd40046d 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -139,19 +139,20 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val #ifdef TARGET_PAGE_BITS_VARY # include "exec/page-vary.h" extern const TargetPageBits target_page; -#ifdef CONFIG_DEBUG_TCG -#define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; }) -#define TARGET_PAGE_MASK ({ assert(target_page.decided); \ - (target_long)target_page.mask; }) +# ifdef CONFIG_DEBUG_TCG +# define TARGET_PAGE_BITS ({ assert(target_page.decided); \ + target_page.bits; }) +# define TARGET_PAGE_MASK ({ assert(target_page.decided); \ + (target_long)target_page.mask; }) +# else +# define TARGET_PAGE_BITS target_page.bits +# define TARGET_PAGE_MASK ((target_long)target_page.mask) +# endif +# define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) #else -#define TARGET_PAGE_BITS target_page.bits -#define TARGET_PAGE_MASK ((target_long)target_page.mask) -#endif -#define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) -#else -#define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS -#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) -#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) +# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS +# define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) +# define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) #endif #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) From patchwork Mon May 6 12:37:02 2024 Content-Type: text/plain; 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Mon, 06 May 2024 05:37:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: BALATON Zoltan , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PULL 02/28] exec/cpu: Rename PAGE_BITS macro to PAGE_RWX Date: Mon, 6 May 2024 14:37:02 +0200 Message-ID: <20240506123728.65278-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: BALATON Zoltan This macro can be used to abbreviate PAGE_READ | PAGE_WRITE | PAGE_EXEC for which PAGE_RWX is a better name and renaming it also shows it is not related to TARGET_PAGE_BITS. Signed-off-by: BALATON Zoltan Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240505121008.44A0D4E602D@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-common.h | 2 +- accel/tcg/user-exec.c | 2 +- bsd-user/mmap.c | 6 +++--- linux-user/elfload.c | 2 +- linux-user/mmap.c | 2 +- target/cris/mmu.c | 4 ++-- target/microblaze/helper.c | 2 +- 7 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 8812ba744d..a4bb4e6680 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -212,7 +212,7 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); #define PAGE_READ 0x0001 #define PAGE_WRITE 0x0002 #define PAGE_EXEC 0x0004 -#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) +#define PAGE_RWX (PAGE_READ | PAGE_WRITE | PAGE_EXEC) #define PAGE_VALID 0x0008 /* * Original state of the write flag (used when tracking self-modifying code) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1c621477ad..a81e3cc920 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -765,7 +765,7 @@ int page_unprotect(target_ulong address, uintptr_t pc) if (prot & PAGE_EXEC) { prot = (prot & ~PAGE_EXEC) | PAGE_READ; } - mprotect((void *)g2h_untagged(start), len, prot & PAGE_BITS); + mprotect((void *)g2h_untagged(start), len, prot & PAGE_RWX); } mmap_unlock(); diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index 3ef11b2807..c785615392 100644 --- a/bsd-user/mmap.c +++ b/bsd-user/mmap.c @@ -96,7 +96,7 @@ int target_mprotect(abi_ulong start, abi_ulong len, int prot) end = host_end; } ret = mprotect(g2h_untagged(host_start), - qemu_host_page_size, prot1 & PAGE_BITS); + qemu_host_page_size, prot1 & PAGE_RWX); if (ret != 0) goto error; host_start += qemu_host_page_size; @@ -107,7 +107,7 @@ int target_mprotect(abi_ulong start, abi_ulong len, int prot) prot1 |= page_get_flags(addr); } ret = mprotect(g2h_untagged(host_end - qemu_host_page_size), - qemu_host_page_size, prot1 & PAGE_BITS); + qemu_host_page_size, prot1 & PAGE_RWX); if (ret != 0) goto error; host_end -= qemu_host_page_size; @@ -174,7 +174,7 @@ static int mmap_frag(abi_ulong real_start, return -1; prot1 = prot; } - prot1 &= PAGE_BITS; + prot1 &= PAGE_RWX; prot_new = prot | prot1; if (fd != -1) { diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f9461d2844..41fae2b520 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2361,7 +2361,7 @@ static bool zero_bss(abi_ulong start_bss, abi_ulong end_bss, if (start_bss < align_bss) { int flags = page_get_flags(start_bss); - if (!(flags & PAGE_BITS)) { + if (!(flags & PAGE_RWX)) { /* * The whole address space of the executable was reserved * at the start, therefore all pages will be VALID. diff --git a/linux-user/mmap.c b/linux-user/mmap.c index be3b9a68eb..66a1631094 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -117,7 +117,7 @@ static void shm_region_rm_complete(abi_ptr start, abi_ptr last) static int validate_prot_to_pageflags(int prot) { int valid = PROT_READ | PROT_WRITE | PROT_EXEC | TARGET_PROT_SEM; - int page_flags = (prot & PAGE_BITS) | PAGE_VALID; + int page_flags = (prot & PAGE_RWX) | PAGE_VALID; #ifdef TARGET_AARCH64 { diff --git a/target/cris/mmu.c b/target/cris/mmu.c index b574ec6e5b..c25c31c9f8 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -333,7 +333,7 @@ int cris_mmu_translate(struct cris_mmu_result *res, if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) { res->phy = vaddr; - res->prot = PAGE_BITS; + res->prot = PAGE_RWX; goto done; } @@ -344,7 +344,7 @@ int cris_mmu_translate(struct cris_mmu_result *res, miss = 0; base = cris_mmu_translate_seg(env, seg); res->phy = base | (0x0fffffff & vaddr); - res->prot = PAGE_BITS; + res->prot = PAGE_RWX; } else { miss = cris_mmu_translate_page(res, env, vaddr, access_type, is_user, debug); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index d25c9eb4d3..ff5f86ddc2 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -51,7 +51,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (mmu_idx == MMU_NOMMU_IDX) { /* MMU disabled or not available. */ address &= TARGET_PAGE_MASK; - prot = PAGE_BITS; + prot = PAGE_RWX; tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, TARGET_PAGE_SIZE); return true; From patchwork Mon May 6 12:37:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14A9EC41513 for ; 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Mon, 06 May 2024 05:37:58 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id m9-20020a05600c4f4900b0041bf7da4200sm16058113wmq.33.2024.05.06.05.37.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:37:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 03/28] exec/cpu: Remove obsolete PAGE_RESERVED definition Date: Mon, 6 May 2024 14:37:03 +0200 Message-ID: <20240506123728.65278-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We stopped using the PAGE_RESERVED definition in commit 50d25c8aec ("accel/tcg: Drop PAGE_RESERVED for CONFIG_BSD"). This completes commit 2e9a5713f0 ("Remove PAGE_RESERVED"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240427155714.53669-7-philmd@linaro.org> --- include/exec/cpu-all.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 14fd40046d..104c5dd2da 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -157,10 +157,6 @@ extern const TargetPageBits target_page; #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) -#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) -/* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0100 -#endif /* * For linux-user, indicates that the page is mapped with the same semantics * in both guest and host. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240427155714.53669-8-philmd@linaro.org> --- include/exec/cpu-all.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 104c5dd2da..c4dada5b44 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -157,12 +157,6 @@ extern const TargetPageBits target_page; #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) -/* - * For linux-user, indicates that the page is mapped with the same semantics - * in both guest and host. - */ -#define PAGE_PASSTHROUGH 0x0800 - #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); From patchwork Mon May 6 12:37:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8927C10F16 for ; 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Mon, 06 May 2024 05:38:15 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id o9-20020a5d47c9000000b0034d7a555047sm10585574wrc.96.2024.05.06.05.38.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:38:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Nicholas Piggin , Richard Henderson Subject: [PULL 05/28] exec/cpu: Extract page-protection definitions to page-protection.h Date: Mon, 6 May 2024 14:37:05 +0200 Message-ID: <20240506123728.65278-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Extract page-protection definitions from "exec/cpu-all.h" to "exec/page-protection.h". The list of files requiring the new header was generated using: $ git grep -wE \ 'PAGE_(READ|WRITE|EXEC|RWX|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)' Signed-off-by: Philippe Mathieu-Daudé Acked-by: Nicholas Piggin Acked-by: Richard Henderson Message-Id: <20240427155714.53669-3-philmd@linaro.org> --- MAINTAINERS | 1 + bsd-user/bsd-mem.h | 1 + bsd-user/qemu.h | 1 + include/exec/cpu-all.h | 1 + include/exec/cpu-common.h | 31 +-------------------- include/exec/page-protection.h | 41 ++++++++++++++++++++++++++++ include/semihosting/uaccess.h | 1 + target/arm/cpu.h | 1 + target/ppc/internal.h | 1 + target/ppc/mmu-radix64.h | 2 ++ accel/tcg/cputlb.c | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/user-exec.c | 1 + bsd-user/mmap.c | 1 + bsd-user/signal.c | 1 + cpu-target.c | 1 + hw/ppc/ppc440_bamboo.c | 1 + hw/ppc/sam460ex.c | 1 + hw/ppc/virtex_ml507.c | 1 + linux-user/arm/cpu_loop.c | 1 + linux-user/elfload.c | 1 + linux-user/mmap.c | 1 + linux-user/signal.c | 1 + linux-user/syscall.c | 1 + system/physmem.c | 1 + target/alpha/helper.c | 1 + target/arm/ptw.c | 1 + target/arm/tcg/m_helper.c | 1 + target/arm/tcg/mte_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/avr/helper.c | 1 + target/cris/mmu.c | 1 + target/hppa/mem_helper.c | 1 + target/hppa/translate.c | 1 + target/i386/tcg/sysemu/excp_helper.c | 1 + target/loongarch/tcg/tlb_helper.c | 1 + target/m68k/helper.c | 1 + target/microblaze/helper.c | 1 + target/microblaze/mmu.c | 1 + target/mips/sysemu/physaddr.c | 1 + target/mips/tcg/sysemu/tlb_helper.c | 1 + target/openrisc/mmu.c | 1 + target/ppc/mmu-hash32.c | 1 + target/ppc/mmu-hash64.c | 1 + target/ppc/mmu-radix64.c | 1 + target/ppc/mmu_common.c | 1 + target/ppc/mmu_helper.c | 1 + target/riscv/cpu_helper.c | 1 + target/riscv/pmp.c | 1 + target/riscv/vector_helper.c | 1 + target/rx/cpu.c | 1 + target/s390x/mmu_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/sh4/helper.c | 1 + target/sparc/ldst_helper.c | 1 + target/sparc/mmu_helper.c | 1 + target/tricore/helper.c | 1 + target/xtensa/mmu_helper.c | 1 + target/xtensa/op_helper.c | 1 + 59 files changed, 100 insertions(+), 30 deletions(-) create mode 100644 include/exec/page-protection.h diff --git a/MAINTAINERS b/MAINTAINERS index 2f08cc528e..595808fc96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -167,6 +167,7 @@ F: include/exec/target_long.h F: include/exec/helper*.h F: include/exec/helper*.h.inc F: include/exec/helper-info.c.inc +F: include/exec/page-protection.h F: include/sysemu/cpus.h F: include/sysemu/tcg.h F: include/hw/core/tcg-cpu-ops.h diff --git a/bsd-user/bsd-mem.h b/bsd-user/bsd-mem.h index 21d9bab889..eef6b222d9 100644 --- a/bsd-user/bsd-mem.h +++ b/bsd-user/bsd-mem.h @@ -56,6 +56,7 @@ #include #include "qemu-bsd.h" +#include "exec/page-protection.h" extern struct bsd_shm_regions bsd_shm_regions[]; extern abi_ulong target_brk; diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index a916724de9..322177de16 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -34,6 +34,7 @@ extern char **environ; #include "target_os_signal.h" #include "target.h" #include "exec/gdbstub.h" +#include "exec/page-protection.h" #include "qemu/clang-tsa.h" #include "qemu-os.h" diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c4dada5b44..6f09b86e7f 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -19,6 +19,7 @@ #ifndef CPU_ALL_H #define CPU_ALL_H +#include "exec/page-protection.h" #include "exec/cpu-common.h" #include "exec/memory.h" #include "exec/tswap.h" diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index a4bb4e6680..78f2c381b1 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -14,6 +14,7 @@ #endif #include "hw/core/cpu.h" #include "tcg/debug-assert.h" +#include "exec/page-protection.h" #define EXCP_INTERRUPT 0x10000 /* async interruption */ #define EXCP_HLT 0x10001 /* hlt instruction reached */ @@ -208,36 +209,6 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); G_NORETURN void cpu_loop_exit(CPUState *cpu); G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); -/* same as PROT_xxx */ -#define PAGE_READ 0x0001 -#define PAGE_WRITE 0x0002 -#define PAGE_EXEC 0x0004 -#define PAGE_RWX (PAGE_READ | PAGE_WRITE | PAGE_EXEC) -#define PAGE_VALID 0x0008 -/* - * Original state of the write flag (used when tracking self-modifying code) - */ -#define PAGE_WRITE_ORG 0x0010 -/* - * Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() - */ -#define PAGE_WRITE_INV 0x0020 -/* For use with page_set_flags: page is being replaced; target_data cleared. */ -#define PAGE_RESET 0x0040 -/* For linux-user, indicates that the page is MAP_ANON. */ -#define PAGE_ANON 0x0080 - -/* Target-specific bits that will be used via page_get_flags(). */ -#define PAGE_TARGET_1 0x0200 -#define PAGE_TARGET_2 0x0400 - -/* - * For linux-user, indicates that the page is mapped with the same semantics - * in both guest and host. - */ -#define PAGE_PASSTHROUGH 0x0800 - /* accel/tcg/cpu-exec.c */ int cpu_exec(CPUState *cpu); diff --git a/include/exec/page-protection.h b/include/exec/page-protection.h new file mode 100644 index 0000000000..c43231af8b --- /dev/null +++ b/include/exec/page-protection.h @@ -0,0 +1,41 @@ +/* + * QEMU page protection definitions. + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1+ + */ +#ifndef EXEC_PAGE_PROT_COMMON_H +#define EXEC_PAGE_PROT_COMMON_H + +/* same as PROT_xxx */ +#define PAGE_READ 0x0001 +#define PAGE_WRITE 0x0002 +#define PAGE_EXEC 0x0004 +#define PAGE_RWX (PAGE_READ | PAGE_WRITE | PAGE_EXEC) +#define PAGE_VALID 0x0008 +/* + * Original state of the write flag (used when tracking self-modifying code) + */ +#define PAGE_WRITE_ORG 0x0010 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 + +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0200 +#define PAGE_TARGET_2 0x0400 + +/* + * For linux-user, indicates that the page is mapped with the same semantics + * in both guest and host. + */ +#define PAGE_PASSTHROUGH 0x0800 + +#endif diff --git a/include/semihosting/uaccess.h b/include/semihosting/uaccess.h index dd289af8dd..c2fa5a655d 100644 --- a/include/semihosting/uaccess.h +++ b/include/semihosting/uaccess.h @@ -17,6 +17,7 @@ #include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/tswap.h" +#include "exec/page-protection.h" #define get_user_u64(val, addr) \ ({ uint64_t val_ = 0; \ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a550bcd25f..c17264c239 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -26,6 +26,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "exec/gdbstub.h" +#include "exec/page-protection.h" #include "qapi/qapi-types-common.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 601c0b533f..98b41a970c 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -20,6 +20,7 @@ #include "exec/breakpoint.h" #include "hw/registerfields.h" +#include "exec/page-protection.h" /* PM instructions */ typedef enum { diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index 4c768aa5cc..c5c04a1527 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -3,6 +3,8 @@ #ifndef CONFIG_USER_ONLY +#include "exec/page-protection.h" + /* Radix Quadrants */ #define R_EADDR_MASK 0x3FFFFFFFFFFFFFFF #define R_EADDR_VALID_MASK 0xC00FFFFFFFFFFFFF diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 953c437ba9..cdb3e12dfb 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -21,6 +21,7 @@ #include "qemu/main-loop.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/memory.h" #include "exec/cpu_ldst.h" #include "exec/cputlb.h" diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index da39a43bd8..19ae6793f3 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "exec/log.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/tb-flush.h" #include "exec/translate-all.h" #include "sysemu/tcg.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a81e3cc920..d34313a612 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -25,6 +25,7 @@ #include "qemu/rcu.h" #include "exec/cpu_ldst.h" #include "exec/translate-all.h" +#include "exec/page-protection.h" #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index c785615392..f3a4f1712d 100644 --- a/bsd-user/mmap.c +++ b/bsd-user/mmap.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ #include "qemu/osdep.h" +#include "exec/page-protection.h" #include "qemu.h" diff --git a/bsd-user/signal.c b/bsd-user/signal.c index b2faf1d0dd..8b6654b91d 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu.h" +#include "exec/page-protection.h" #include "user/tswap-target.h" #include "gdbstub/user.h" #include "signal-common.h" diff --git a/cpu-target.c b/cpu-target.c index f88649c299..5af120e8aa 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -21,6 +21,7 @@ #include "qapi/error.h" #include "exec/target_page.h" +#include "exec/page-protection.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index e18f57efce..73f80cf706 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -15,6 +15,7 @@ #include "qemu/units.h" #include "qemu/datadir.h" #include "qemu/error-report.h" +#include "exec/page-protection.h" #include "net/net.h" #include "hw/pci/pci.h" #include "hw/boards.h" diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index d42b677898..8dc75fb9f0 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -21,6 +21,7 @@ #include "kvm_ppc.h" #include "sysemu/device_tree.h" #include "sysemu/block-backend.h" +#include "exec/page-protection.h" #include "hw/loader.h" #include "elf.h" #include "exec/memory.h" diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index d02f330650..c49da1f46f 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/datadir.h" #include "qemu/units.h" +#include "exec/page-protection.h" #include "cpu.h" #include "hw/sysbus.h" #include "hw/char/serial.h" diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index db1a41e27f..ec665862d9 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -24,6 +24,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "exec/page-protection.h" #include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 41fae2b520..746e22b275 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -8,6 +8,7 @@ #include "qemu.h" #include "user/tswap-target.h" +#include "exec/page-protection.h" #include "user/guest-base.h" #include "user-internals.h" #include "signal-common.h" diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 66a1631094..72b30279a2 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -20,6 +20,7 @@ #include #include "trace.h" #include "exec/log.h" +#include "exec/page-protection.h" #include "qemu.h" #include "user-internals.h" #include "user-mmap.h" diff --git a/linux-user/signal.c b/linux-user/signal.c index 05dc4afb52..63ac2df53b 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "gdbstub/user.h" +#include "exec/page-protection.h" #include "hw/core/tcg-cpu-ops.h" #include diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 41659b63f5..6a492c9d35 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -25,6 +25,7 @@ #include "qemu/plugin.h" #include "tcg/startup.h" #include "target_mman.h" +#include "exec/page-protection.h" #include #include #include diff --git a/system/physmem.c b/system/physmem.c index 1a81c226ba..44e477a1a5 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -31,6 +31,7 @@ #endif /* CONFIG_TCG */ #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/target_page.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" diff --git a/target/alpha/helper.c b/target/alpha/helper.c index c5e4958f8b..2f1000c99f 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 31ae43f60e..4476b32ff5 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -11,6 +11,7 @@ #include "qemu/range.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "cpu.h" #include "internals.h" #include "cpu-features.h" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index d1f1e02acc..23d7f73035 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -16,6 +16,7 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #ifdef CONFIG_TCG #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index d971b81370..037ac6dd60 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 6853f58c19..dd49e67d7a 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index eeca415c43..345708a1b3 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" #include "exec/helper-proto.h" diff --git a/target/cris/mmu.c b/target/cris/mmu.c index c25c31c9f8..d51008c541 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "mmu.h" #ifdef DEBUG diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 84785b5a5c..d09877afd7 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" #include "trace.h" diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 42fa480950..6d45611888 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -22,6 +22,7 @@ #include "disas/disas.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/helper-proto.h" diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index 7a57b7dd10..8fb05b1f53 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "tcg/helper-tcg.h" typedef struct TranslateParams { diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 57f5308632..d6331f9b0b 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -13,6 +13,7 @@ #include "internals.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "cpu-csr.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 7a91f33b17..7967ad13cb 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "gdbstub/helpers.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index ff5f86ddc2..5d3259ce31 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "qemu/host-utils.h" #include "exec/log.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 234006634e..2423ac6172 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" static unsigned int tlb_decode_size(unsigned int f) { diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 5c5184e136..505781d84c 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "../internal.h" static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 119eae771e..3ba6d369a6 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internal.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 603c26715e..c632d5230b 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "hw/loader.h" diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 3976416840..6dfedab11d 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" #include "internal.h" diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index d645c0bb94..5a0d80feda 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -21,6 +21,7 @@ #include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/hw_accel.h" diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 690dff7a49..8daf71d2db 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 751403f1c8..4fde7fd3bf 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -25,6 +25,7 @@ #include "mmu-hash64.h" #include "mmu-hash32.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index c071b4d5e2..b35a93c198 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -25,6 +25,7 @@ #include "mmu-hash64.h" #include "mmu-hash32.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fc090d729a..8ad546a45a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -24,6 +24,7 @@ #include "internals.h" #include "pmu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2a76b611a0..9eea397e72 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "trace.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index fa139040f8..1b4d5a8e37 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -23,6 +23,7 @@ #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/page-protection.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index e3dfb09722..c1a592e893 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index fbb2f1b4d4..f3a2f25a5c 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -24,6 +24,7 @@ #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "trace.h" #include "hw/hw.h" #include "hw/s390x/storage-keys.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 557831def4..6a308c5553 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "tcg_s390x.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "hw/core/tcg-cpu-ops.h" #include "qemu/int128.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 7c6f9d374a..6702910627 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/log.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 2846a86cc4..7bdf99e0c0 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -23,6 +23,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "asi.h" diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index ad1591d9fd..9ff06026b8 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "qemu/qemu-print.h" #include "trace.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 76bd226370..7014255f77 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -20,6 +20,7 @@ #include "hw/registerfields.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 47063b0a57..997b21d389 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -33,6 +33,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/page-protection.h" #define XTENSA_MPU_SEGMENT_MASK 0x0000001f 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=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 06/28] accel/tcg: Use cpu_loop_exit_requested() in cpu_loop_exec_tb() Date: Mon, 6 May 2024 14:37:06 +0200 Message-ID: <20240506123728.65278-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Do not open-code cpu_loop_exit_requested(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428214915.10339-9-philmd@linaro.org> --- accel/tcg/cpu-exec.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 225e5fbd3e..c18a7e2b85 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -900,8 +900,6 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, vaddr pc, TranslationBlock **last_tb, int *tb_exit) { - int32_t insns_left; - trace_exec_tb(tb, pc); tb = cpu_tb_exec(cpu, tb, tb_exit); if (*tb_exit != TB_EXIT_REQUESTED) { @@ -910,8 +908,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, } *last_tb = NULL; - insns_left = qatomic_read(&cpu->neg.icount_decr.u32); - if (insns_left < 0) { + if (cpu_loop_exit_requested(cpu)) { /* Something asked us to stop executing chained TBs; just * continue round the main loop. Whatever requested the exit * will also have set something else (eg exit_request or @@ -928,7 +925,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, /* Ensure global icount has gone forward */ icount_update(cpu); /* Refill decrementer and continue execution. */ - insns_left = MIN(0xffff, cpu->icount_budget); + int32_t insns_left = MIN(0xffff, cpu->icount_budget); cpu->neg.icount_decr.u16.low = insns_left; cpu->icount_extra = cpu->icount_budget - insns_left; From patchwork Mon May 6 12:37:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74326C25B5F for ; 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Mon, 06 May 2024 05:38:27 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id a7-20020adfed07000000b0034d839bed92sm10581414wro.64.2024.05.06.05.38.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:38:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 07/28] accel/tcg: Access tcg_cflags with getter / setter Date: Mon, 6 May 2024 14:37:07 +0200 Message-ID: <20240506123728.65278-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Access the CPUState::tcg_cflags via tcg_cflags_has() and tcg_cflags_set() helpers. Mechanical change using the following Coccinelle spatch script: @@ expression cpu; expression flags; @@ - cpu->tcg_cflags & flags + tcg_cflags_has(cpu, flags) @@ expression cpu; expression flags; @@ - (tcg_cflags_has(cpu, flags)) + tcg_cflags_has(cpu, flags) @@ expression cpu; expression flags; @@ - cpu->tcg_cflags |= flags; + tcg_cflags_set(cpu, flags); Then manually moving the declarations, and adding both tcg_cflags_has() and tcg_cflags_set() definitions. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240427155714.53669-15-philmd@linaro.org> --- accel/tcg/internal-common.h | 3 ++- include/exec/cpu-common.h | 7 +++++++ include/exec/exec-all.h | 3 --- accel/tcg/cpu-exec.c | 10 ++++++++++ accel/tcg/tcg-accel-ops.c | 2 +- linux-user/mmap.c | 8 ++++---- linux-user/syscall.c | 4 ++-- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/i386/helper.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/tcg/exception.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/tcg/tcg-cpu.c | 4 ++-- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- 23 files changed, 44 insertions(+), 29 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index edefd0dcb7..ead53cb8a5 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -9,6 +9,7 @@ #ifndef ACCEL_TCG_INTERNAL_COMMON_H #define ACCEL_TCG_INTERNAL_COMMON_H +#include "exec/cpu-common.h" #include "exec/translation-block.h" extern int64_t max_delay; @@ -20,7 +21,7 @@ extern int64_t max_advance; */ static inline bool cpu_in_serial_context(CPUState *cs) { - return !(cs->tcg_cflags & CF_PARALLEL) || cpu_in_exclusive_context(cs); + return !tcg_cflags_has(cs, CF_PARALLEL) || cpu_in_exclusive_context(cs); } #endif diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 78f2c381b1..8bc397e251 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -178,6 +178,13 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, void list_cpus(void); #ifdef CONFIG_TCG + +bool tcg_cflags_has(CPUState *cpu, uint32_t flags); +void tcg_cflags_set(CPUState *cpu, uint32_t flags); + +/* current cflags for hashing/comparison */ +uint32_t curr_cflags(CPUState *cpu); + /** * cpu_unwind_state_data: * @cpu: the cpu context diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 4c5e470581..2cd7b8f61b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -510,9 +510,6 @@ static inline void tb_set_page_addr1(TranslationBlock *tb, #endif } -/* current cflags for hashing/comparison */ -uint32_t curr_cflags(CPUState *cpu); - /* TranslationBlock invalidate API */ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c18a7e2b85..9af66bc191 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -147,6 +147,16 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) } #endif /* CONFIG USER ONLY */ +bool tcg_cflags_has(CPUState *cpu, uint32_t flags) +{ + return cpu->tcg_cflags & flags; +} + +void tcg_cflags_set(CPUState *cpu, uint32_t flags) +{ + cpu->tcg_cflags |= flags; +} + uint32_t curr_cflags(CPUState *cpu) { uint32_t cflags = cpu->tcg_cflags; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 2c7b0cc09e..1433e38f40 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -62,7 +62,7 @@ void tcg_cpu_init_cflags(CPUState *cpu, bool parallel) cflags |= parallel ? CF_PARALLEL : 0; cflags |= icount_enabled() ? CF_USE_ICOUNT : 0; - cpu->tcg_cflags |= cflags; + tcg_cflags_set(cpu, cflags); } void tcg_cpu_destroy(CPUState *cpu) diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 72b30279a2..4d09a72fad 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -960,8 +960,8 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, */ if (ret != -1 && (flags & MAP_TYPE) != MAP_PRIVATE) { CPUState *cpu = thread_cpu; - if (!(cpu->tcg_cflags & CF_PARALLEL)) { - cpu->tcg_cflags |= CF_PARALLEL; + if (!tcg_cflags_has(cpu, CF_PARALLEL)) { + tcg_cflags_set(cpu, CF_PARALLEL); tb_flush(cpu); } } @@ -1400,8 +1400,8 @@ abi_ulong target_shmat(CPUArchState *cpu_env, int shmid, * supported by the host -- anything that requires EXCP_ATOMIC will not * be atomic with respect to an external process. */ - if (!(cpu->tcg_cflags & CF_PARALLEL)) { - cpu->tcg_cflags |= CF_PARALLEL; + if (!tcg_cflags_has(cpu, CF_PARALLEL)) { + tcg_cflags_set(cpu, CF_PARALLEL); tb_flush(cpu); } diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 6a492c9d35..1b42e80f9a 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6583,8 +6583,8 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, * generate code for parallel execution and flush old translations. * Do this now so that the copy gets CF_PARALLEL too. */ - if (!(cpu->tcg_cflags & CF_PARALLEL)) { - cpu->tcg_cflags |= CF_PARALLEL; + if (!tcg_cflags_has(cpu, CF_PARALLEL)) { + tcg_cflags_set(cpu, CF_PARALLEL); tb_flush(cpu); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fdc3eda318..77f8c9c748 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1941,7 +1941,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) /* Use pc-relative instructions in system-mode */ - cs->tcg_cflags |= CF_PCREL; + tcg_cflags_set(cs, CF_PCREL); #endif /* If we needed to query the host kernel for the CPU features diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 71ce62a4c2..f53e1192b1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -55,7 +55,7 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */ } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a56bb4b075..64cc05cca7 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -257,7 +257,7 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) static void hexagon_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc; } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 3831cb6db2..393a81988d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -48,7 +48,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, { HPPACPU *cpu = HPPA_CPU(cs); - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); #ifdef CONFIG_USER_ONLY cpu->env.iaoq_f = tb->pc; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index aa3b2d8391..25c0702ca1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7371,7 +7371,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) /* Use pc-relative instructions in system-mode */ - cs->tcg_cflags |= CF_PCREL; + tcg_cflags_set(cs, CF_PCREL); #endif if (cpu->apic_id == UNASSIGNED_APIC_ID) { diff --git a/target/i386/helper.c b/target/i386/helper.c index 23ccb23a5b..48d1513a35 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -523,7 +523,7 @@ static inline target_ulong get_memio_eip(CPUX86State *env) } /* Per x86_restore_state_to_opc. */ - if (cs->tcg_cflags & CF_PCREL) { + if (tcg_cflags_has(cs, CF_PCREL)) { return (env->eip & TARGET_PAGE_MASK) | data[0]; } else { return data[0] - env->segs[R_CS].base; diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 1ebba043f4..96da1a685e 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,7 +336,7 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) static void loongarch_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); set_pc(cpu_env(cs), tb->pc); } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9eb7374ccd..41ad47d04c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -99,7 +99,7 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); cpu->env.pc = tb->pc; cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; } diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 13275d1ded..4886d087b2 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -81,7 +81,7 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { CPUMIPSState *env = cpu_env(cs); - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); env->active_tc.PC = tb->pc; env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= tb->flags & MIPS_HFLAG_BMASK; diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c index 5baa25348e..9ce5e2ceac 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -93,7 +93,7 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) CPUMIPSState *env = cpu_env(cs); if ((env->hflags & MIPS_HFLAG_BMASK) != 0 - && !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) { + && !tcg_cflags_has(cs, CF_PCREL) && env->active_tc.PC != tb->pc) { env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); env->hflags &= ~MIPS_HFLAG_BMASK; return true; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index d711035cf5..fdaaa09fc8 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -45,7 +45,7 @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs, { OpenRISCCPU *cpu = OPENRISC_CPU(cs); - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); cpu->env.pc = tb->pc; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b5b95e052d..40054a391a 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -96,7 +96,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, CPURISCVState *env = &cpu->env; RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); if (xl == MXL_RV32) { env->pc = (int32_t) tb->pc; @@ -890,7 +890,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) CPURISCVState *env = &cpu->env; Error *local_err = NULL; - CPU(cs)->tcg_cflags |= CF_PCREL; + tcg_cflags_set(CPU(cs), CF_PCREL); if (cpu->cfg.ext_sstc) { riscv_timer_init(cpu); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c1a592e893..8a584f0a11 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -46,7 +46,7 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, { RXCPU *cpu = RX_CPU(cs); - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); cpu->env.pc = tb->pc; } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 43e35ec2ca..618aa7154e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -47,7 +47,7 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, { SuperHCPU *cpu = SUPERH_CPU(cs); - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); cpu->env.pc = tb->pc; cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; } @@ -74,7 +74,7 @@ static bool superh_io_recompile_replay_branch(CPUState *cs, CPUSH4State *env = cpu_env(cs); if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) - && !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) { + && !tcg_cflags_has(cs, CF_PCREL) && env->pc != tb->pc) { env->pc -= 2; env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); return true; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 485d416925..685485c654 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -702,7 +702,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, { SPARCCPU *cpu = SPARC_CPU(cs); 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Mon, 06 May 2024 05:38:33 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id g4-20020a5d5404000000b0034ca136f0e9sm10605321wrv.88.2024.05.06.05.38.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:38:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 08/28] accel/tcg: Move user definition of cpu_interrupt() to user-exec.c Date: Mon, 6 May 2024 14:37:08 +0200 Message-ID: <20240506123728.65278-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-4-philmd@linaro.org> --- accel/tcg/translate-all.c | 9 --------- accel/tcg/user-exec.c | 8 ++++++++ 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 83cc14fbde..fdf6d8ac19 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -644,15 +644,6 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) cpu_loop_exit_noexc(cpu); } -#else /* CONFIG_USER_ONLY */ - -void cpu_interrupt(CPUState *cpu, int mask) -{ - g_assert(bql_locked()); - cpu->interrupt_request |= mask; - qatomic_set(&cpu->neg.icount_decr.u16.high, -1); -} - #endif /* CONFIG_USER_ONLY */ /* diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index d34313a612..80d24540ed 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -24,6 +24,7 @@ #include "qemu/bitops.h" #include "qemu/rcu.h" #include "exec/cpu_ldst.h" +#include "qemu/main-loop.h" #include "exec/translate-all.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" @@ -38,6 +39,13 @@ __thread uintptr_t helper_retaddr; //#define DEBUG_SIGNAL +void cpu_interrupt(CPUState *cpu, int mask) +{ + g_assert(bql_locked()); + cpu->interrupt_request |= mask; + qatomic_set(&cpu->neg.icount_decr.u16.high, -1); +} + /* * Adjust the pc to pass to cpu_restore_state; return the memop type. */ From patchwork Mon May 6 12:37:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5ABEBC25B10 for ; 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Mon, 06 May 2024 05:38:39 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id fl25-20020a05600c0b9900b0041e9c1d6f4esm6712931wmb.48.2024.05.06.05.38.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:38:39 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 09/28] accel/tcg: Update CPUNegativeOffsetState::can_do_io field documentation Date: Mon, 6 May 2024 14:37:09 +0200 Message-ID: <20240506123728.65278-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The @can_do_io field got moved from CPUState to CPUNegativeOffsetState in commit 464dacf609 ("accel/tcg: Move can_do_io to CPUNegativeOffsetState"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-14-philmd@linaro.org> --- include/hw/core/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 46b99a7ea5..173349b0bd 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -338,9 +338,10 @@ typedef union IcountDecr { } u16; } IcountDecr; -/* - * Elements of CPUState most efficiently accessed from CPUArchState, - * via small negative offsets. +/** + * CPUNegativeOffsetState: Elements of CPUState most efficiently accessed + * from CPUArchState, via small negative offsets. + * @can_do_io: True if memory-mapped IO is allowed. */ typedef struct CPUNegativeOffsetState { CPUTLB tlb; @@ -400,7 +401,6 @@ struct qemu_work_item; * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU * @singlestep_enabled: Flags for single-stepping. * @icount_extra: Instructions until next timer event. - * @neg.can_do_io: True if memory-mapped IO is allowed. * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the * AddressSpaces this CPU has) * @num_ases: number of CPUAddressSpaces in @cpu_ases From patchwork Mon May 6 12:37:10 2024 Content-Type: text/plain; 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Mon, 06 May 2024 05:38:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 10/28] accel/tcg: Restrict qemu_plugin_vcpu_exit_hook() to TCG plugins Date: Mon, 6 May 2024 14:37:10 +0200 Message-ID: <20240506123728.65278-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=philmd@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org qemu_plugin_vcpu_exit_hook() is specific to TCG plugins, so must be restricted to it in cpu_common_unrealizefn(), similarly to how qemu_plugin_create_vcpu_state() is restricted in the cpu_common_realizefn() counterpart. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240429213050.55177-2-philmd@linaro.org> --- hw/core/cpu-common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index a72d48d9e1..0f0a247f56 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -30,7 +30,9 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "trace.h" +#ifdef CONFIG_PLUGIN #include "qemu/plugin.h" +#endif CPUState *cpu_by_arch_id(int64_t id) { @@ -236,9 +238,11 @@ static void cpu_common_unrealizefn(DeviceState *dev) CPUState *cpu = CPU(dev); /* Call the plugin hook before clearing the cpu is fully unrealized */ +#ifdef CONFIG_PLUGIN if (tcg_enabled()) { qemu_plugin_vcpu_exit_hook(cpu); } +#endif /* NOTE: latest generic point before the cpu is fully unrealized */ cpu_exec_unrealizefn(cpu); From patchwork Mon May 6 12:37:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83DEAC25B5F for ; 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Mon, 06 May 2024 05:38:51 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id v6-20020a5d6106000000b0034d743eb8dfsm10598284wrt.29.2024.05.06.05.38.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:38:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 11/28] accel/tcg: Restrict cpu_plugin_mem_cbs_enabled() to TCG Date: Mon, 6 May 2024 14:37:11 +0200 Message-ID: <20240506123728.65278-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org So far cpu_plugin_mem_cbs_enabled() is only called from TCG, so reduce it to accel/tcg/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <5f59c754-44e5-4743-a2dd-87ef8e13eadf@linaro.org> --- accel/tcg/internal-common.h | 17 +++++++++++++++++ include/hw/core/cpu.h | 17 ----------------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index ead53cb8a5..cbeff39e3e 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -24,4 +24,21 @@ static inline bool cpu_in_serial_context(CPUState *cs) return !tcg_cflags_has(cs, CF_PARALLEL) || cpu_in_exclusive_context(cs); } +/** + * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled? + * @cs: CPUState pointer + * + * The memory callbacks are installed if a plugin has instrumented an + * instruction for memory. This can be useful to know if you want to + * force a slow path for a series of memory accesses. + */ +static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) +{ +#ifdef CONFIG_PLUGIN + return !!cpu->plugin_mem_cbs; +#else + return false; +#endif +} + #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 173349b0bd..a001bafcf8 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1111,23 +1111,6 @@ void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); #endif -/** - * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled? - * @cs: CPUState pointer - * - * The memory callbacks are installed if a plugin has instrumented an - * instruction for memory. This can be useful to know if you want to - * force a slow path for a series of memory accesses. - */ -static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) -{ -#ifdef CONFIG_PLUGIN - return !!cpu->plugin_mem_cbs; -#else - return false; -#endif -} - /** * cpu_get_address_space: * @cpu: CPU to get address space from From patchwork Mon May 6 12:37:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47488C10F16 for ; Mon, 6 May 2024 12:39:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3xcw-0004Fm-3m; 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Mon, 06 May 2024 05:38:58 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id n15-20020adff08f000000b00343eac2acc4sm10630140wro.111.2024.05.06.05.38.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:38:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 12/28] accel/tcg: Move @plugin_mem_cbs from CPUState to CPUNegativeOffsetState Date: Mon, 6 May 2024 14:37:12 +0200 Message-ID: <20240506123728.65278-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org @plugin_mem_cbs is accessed by tcg generated code, move it to CPUNegativeOffsetState. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240429213050.55177-4-philmd@linaro.org> --- accel/tcg/internal-common.h | 2 +- include/hw/core/cpu.h | 13 +++++++------ include/qemu/plugin.h | 2 +- accel/tcg/plugin-gen.c | 6 +++--- plugins/core.c | 2 +- 5 files changed, 13 insertions(+), 12 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index cbeff39e3e..cff43d221b 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -35,7 +35,7 @@ static inline bool cpu_in_serial_context(CPUState *cs) static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) { #ifdef CONFIG_PLUGIN - return !!cpu->plugin_mem_cbs; + return !!cpu->neg.plugin_mem_cbs; #else return false; #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index a001bafcf8..6efd7353be 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -342,9 +342,16 @@ typedef union IcountDecr { * CPUNegativeOffsetState: Elements of CPUState most efficiently accessed * from CPUArchState, via small negative offsets. * @can_do_io: True if memory-mapped IO is allowed. + * @plugin_mem_cbs: active plugin memory callbacks */ typedef struct CPUNegativeOffsetState { CPUTLB tlb; +#ifdef CONFIG_PLUGIN + /* + * The callback pointer are accessed via TCG (see gen_empty_mem_helper). + */ + GArray *plugin_mem_cbs; +#endif IcountDecr icount_decr; bool can_do_io; } CPUNegativeOffsetState; @@ -416,7 +423,6 @@ struct qemu_work_item; * @kvm_fd: vCPU file descriptor for KVM. * @work_mutex: Lock to prevent multiple access to @work_list. * @work_list: List of pending asynchronous work. - * @plugin_mem_cbs: active plugin memory callbacks * @plugin_state: per-CPU plugin state * @ignore_memory_transaction_failures: Cached copy of the MachineState * flag of the same name: allows the board to suppress calling of the @@ -511,11 +517,6 @@ struct CPUState { QemuLockCnt in_ioctl_lock; #ifdef CONFIG_PLUGIN - /* - * The callback pointer stays in the main CPUState as it is - * accessed via TCG (see gen_empty_mem_helper). - */ - GArray *plugin_mem_cbs; CPUPluginState *plugin_state; #endif diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h index 18062528c1..b535bfd5de 100644 --- a/include/qemu/plugin.h +++ b/include/qemu/plugin.h @@ -180,7 +180,7 @@ void qemu_plugin_add_dyn_cb_arr(GArray *arr); static inline void qemu_plugin_disable_mem_helpers(CPUState *cpu) { - cpu->plugin_mem_cbs = NULL; + cpu->neg.plugin_mem_cbs = NULL; } /** diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 3db74ae9bf..49f5d1c2e4 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -55,7 +55,7 @@ static void gen_enable_mem_helper(struct qemu_plugin_tb *ptb, * Tracking memory accesses performed from helpers requires extra work. * If an instruction is emulated with helpers, we do two things: * (1) copy the CB descriptors, and keep track of it so that they can be - * freed later on, and (2) point CPUState.plugin_mem_cbs to the + * freed later on, and (2) point CPUState.neg.plugin_mem_cbs to the * descriptors, so that we can read them at run-time * (i.e. when the helper executes). * This run-time access is performed from qemu_plugin_vcpu_mem_cb. @@ -90,14 +90,14 @@ static void gen_enable_mem_helper(struct qemu_plugin_tb *ptb, qemu_plugin_add_dyn_cb_arr(arr); tcg_gen_st_ptr(tcg_constant_ptr((intptr_t)arr), tcg_env, - offsetof(CPUState, plugin_mem_cbs) - + offsetof(CPUState, neg.plugin_mem_cbs) - offsetof(ArchCPU, env)); } static void gen_disable_mem_helper(void) { tcg_gen_st_ptr(tcg_constant_ptr(0), tcg_env, - offsetof(CPUState, plugin_mem_cbs) - + offsetof(CPUState, neg.plugin_mem_cbs) - offsetof(ArchCPU, env)); } diff --git a/plugins/core.c b/plugins/core.c index 081323dafc..1e58a57bf1 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -533,7 +533,7 @@ void exec_inline_op(struct qemu_plugin_dyn_cb *cb, int cpu_index) void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, MemOpIdx oi, enum qemu_plugin_mem_rw rw) { - GArray *arr = cpu->plugin_mem_cbs; + GArray *arr = cpu->neg.plugin_mem_cbs; size_t i; if (arr == NULL) { From patchwork Mon May 6 12:37:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AAA0DC25B10 for ; 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Mon, 06 May 2024 05:39:05 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id h11-20020adfe98b000000b00343d1d09550sm10622257wrm.60.2024.05.06.05.39.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:39:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 13/28] user: Forward declare TaskState type definition Date: Mon, 6 May 2024 14:37:13 +0200 Message-ID: <20240506123728.65278-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Forward declare TaskState in "qemu/typedefs.h" so we can use it in generic headers like "hw/cpu/core.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-9-philmd@linaro.org> --- bsd-user/qemu.h | 4 ++-- include/qemu/typedefs.h | 1 + linux-user/qemu.h | 4 ++-- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 322177de16..1780f485d6 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -76,7 +76,7 @@ struct emulated_sigtable { /* * NOTE: we force a big alignment so that the stack stored after is aligned too */ -typedef struct TaskState { +struct TaskState { pid_t ts_tid; /* tid (or pid) of this task */ struct TaskState *next; @@ -114,7 +114,7 @@ typedef struct TaskState { /* This thread's sigaltstack, if it has one */ struct target_sigaltstack sigaltstack_used; -} __attribute__((aligned(16))) TaskState; +} __attribute__((aligned(16))); static inline TaskState *get_task_state(CPUState *cs) { diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 50c277cf0b..36f2825725 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -134,6 +134,7 @@ typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; typedef struct TCGCPUOps TCGCPUOps; typedef struct TCGHelperInfo TCGHelperInfo; +typedef struct TaskState TaskState; typedef struct TranslationBlock TranslationBlock; typedef struct VirtIODevice VirtIODevice; typedef struct Visitor Visitor; diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 263f445ff1..7df4645c2b 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -95,7 +95,7 @@ struct emulated_sigtable { target_siginfo_t info; }; -typedef struct TaskState { +struct TaskState { pid_t ts_tid; /* tid (or pid) of this task */ #ifdef TARGET_ARM # ifdef TARGET_ABI32 @@ -158,7 +158,7 @@ typedef struct TaskState { /* Start time of task after system boot in clock ticks */ uint64_t start_boottime; -} TaskState; +}; static inline TaskState *get_task_state(CPUState *cs) { From patchwork Mon May 6 12:37:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655404 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65366C10F16 for ; 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Mon, 06 May 2024 05:39:11 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c351400b0041be4065adasm16097989wmq.22.2024.05.06.05.39.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:39:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 14/28] user: Declare get_task_state() once in 'accel/tcg/vcpu-state.h' Date: Mon, 6 May 2024 14:37:14 +0200 Message-ID: <20240506123728.65278-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=philmd@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org While each user emulation implentation defines its own TaskState structure, both use the same get_task_state() declaration, in particular in common code (such gdbstub). Declare the method once in "accel/tcg/vcpu-state.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-10-philmd@linaro.org> --- accel/tcg/vcpu-state.h | 18 ++++++++++++++++++ bsd-user/qemu.h | 6 +----- linux-user/qemu.h | 6 +----- 3 files changed, 20 insertions(+), 10 deletions(-) create mode 100644 accel/tcg/vcpu-state.h diff --git a/accel/tcg/vcpu-state.h b/accel/tcg/vcpu-state.h new file mode 100644 index 0000000000..e407d914df --- /dev/null +++ b/accel/tcg/vcpu-state.h @@ -0,0 +1,18 @@ +/* + * SPDX-FileContributor: Philippe Mathieu-Daudé + * SPDX-FileCopyrightText: 2023 Linaro Ltd. + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ACCEL_TCG_VCPU_STATE_H +#define ACCEL_TCG_VCPU_STATE_H + +#include "hw/core/cpu.h" + +#ifdef CONFIG_USER_ONLY +static inline TaskState *get_task_state(const CPUState *cs) +{ + return cs->opaque; +} +#endif + +#endif diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 1780f485d6..9d2fc7148e 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -36,6 +36,7 @@ extern char **environ; #include "exec/gdbstub.h" #include "exec/page-protection.h" #include "qemu/clang-tsa.h" +#include "accel/tcg/vcpu-state.h" #include "qemu-os.h" /* @@ -116,11 +117,6 @@ struct TaskState { struct target_sigaltstack sigaltstack_used; } __attribute__((aligned(16))); -static inline TaskState *get_task_state(CPUState *cs) -{ - return cs->opaque; -} - void stop_all_tasks(void); extern const char *interp_prefix; extern const char *qemu_uname_release; diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 7df4645c2b..2e90a97175 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -8,6 +8,7 @@ #include "syscall_defs.h" #include "target_syscall.h" +#include "accel/tcg/vcpu-state.h" /* * This is the size of the host kernel's sigset_t, needed where we make @@ -160,11 +161,6 @@ struct TaskState { uint64_t start_boottime; }; -static inline TaskState *get_task_state(CPUState *cs) -{ - return cs->opaque; -} - abi_long do_brk(abi_ulong new_brk); int do_guest_openat(CPUArchState *cpu_env, int dirfd, const char *pathname, int flags, mode_t mode, bool safe); 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Mon, 06 May 2024 05:39:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 15/28] user: Use get_task_state() helper Date: Mon, 6 May 2024 14:37:15 +0200 Message-ID: <20240506123728.65278-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Get the TaskState pointer calling get_task_state(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240428221450.26460-11-philmd@linaro.org> --- gdbstub/gdbstub.c | 3 ++- gdbstub/user-target.c | 4 ++-- linux-user/syscall.c | 4 ++-- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 9c2b8b5d0a..b3574997ea 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -32,6 +32,7 @@ #include "exec/gdbstub.h" #include "gdbstub/syscalls.h" #ifdef CONFIG_USER_ONLY +#include "accel/tcg/vcpu-state.h" #include "gdbstub/user.h" #else #include "hw/cpu/cluster.h" @@ -1661,7 +1662,7 @@ static void handle_query_supported(GArray *params, void *user_ctx) #if defined(CONFIG_USER_ONLY) #if defined(CONFIG_LINUX) - if (gdbserver_state.c_cpu->opaque) { + if (get_task_state(gdbserver_state.c_cpu)) { g_string_append(gdbserver_state.str_buf, ";qXfer:auxv:read+"); } g_string_append(gdbserver_state.str_buf, ";QCatchSyscalls+"); diff --git a/gdbstub/user-target.c b/gdbstub/user-target.c index 6646684a4c..a9c6c64512 100644 --- a/gdbstub/user-target.c +++ b/gdbstub/user-target.c @@ -216,7 +216,7 @@ void gdb_handle_query_offsets(GArray *params, void *user_ctx) { TaskState *ts; - ts = gdbserver_state.c_cpu->opaque; + ts = get_task_state(gdbserver_state.c_cpu); g_string_printf(gdbserver_state.str_buf, "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx @@ -252,7 +252,7 @@ void gdb_handle_query_xfer_auxv(GArray *params, void *user_ctx) offset = get_param(params, 0)->val_ul; len = get_param(params, 1)->val_ul; - ts = gdbserver_state.c_cpu->opaque; + ts = get_task_state(gdbserver_state.c_cpu); saved_auxv = ts->info->saved_auxv; auxv_len = ts->info->auxv_len; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 1b42e80f9a..b9b5a387b3 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6463,7 +6463,7 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, case PR_GET_TID_ADDRESS: { - TaskState *ts = env_cpu(env)->opaque; + TaskState *ts = get_task_state(env_cpu(env)); return put_user_ual(ts->child_tidptr, arg2); } @@ -8124,7 +8124,7 @@ static int open_self_maps_2(void *opaque, target_ulong guest_start, static int open_self_maps_1(CPUArchState *env, int fd, bool smaps) { struct open_self_maps_data d = { - .ts = env_cpu(env)->opaque, + .ts = get_task_state(env_cpu(env)), .host_maps = read_self_maps(), .fd = fd, .smaps = smaps From patchwork Mon May 6 12:37:16 2024 Content-Type: text/plain; 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Mon, 06 May 2024 05:39:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Juergen Gross , Vikram Garhwal , Stefano Stabellini , =?utf-8?q?Alex_Benn=C3=A9e?= , "Edgar E . Iglesias" , David Hildenbrand , Peter Xu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 16/28] softmmu: let qemu_map_ram_ptr() use qemu_ram_ptr_length() Date: Mon, 6 May 2024 14:37:16 +0200 Message-ID: <20240506123728.65278-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Juergen Gross qemu_map_ram_ptr() and qemu_ram_ptr_length() share quite some code, so modify qemu_ram_ptr_length() a little bit and use it for qemu_map_ram_ptr(), too. Signed-off-by: Juergen Gross Signed-off-by: Vikram Garhwal Reviewed-by: Stefano Stabellini Reviewed-by: Alex Bennée Message-Id: <20240227223501.28475-4-vikram.garhwal@amd.com> Reviewed-by: Edgar E. Iglesias Signed-off-by: Edgar E. Iglesias Acked-by: David Hildenbrand Reviewed-by: Peter Xu Message-ID: <20240430164939.925307-2-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- system/physmem.c | 56 ++++++++++++++++++++---------------------------- 1 file changed, 23 insertions(+), 33 deletions(-) diff --git a/system/physmem.c b/system/physmem.c index 44e477a1a5..8278e31c1a 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -2189,43 +2189,17 @@ void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) } #endif /* !_WIN32 */ -/* Return a host pointer to ram allocated with qemu_ram_alloc. - * This should not be used for general purpose DMA. Use address_space_map - * or address_space_rw instead. For local memory (e.g. video ram) that the - * device owns, use memory_region_get_ram_ptr. - * - * Called within RCU critical section. - */ -void *qemu_map_ram_ptr(RAMBlock *block, ram_addr_t addr) -{ - if (block == NULL) { - block = qemu_get_ram_block(addr); - addr -= block->offset; - } - - if (xen_enabled() && block->host == NULL) { - /* We need to check if the requested address is in the RAM - * because we don't want to map the entire memory in QEMU. - * In that case just map until the end of the page. - */ - if (block->offset == 0) { - return xen_map_cache(addr, 0, 0, false); - } - - block->host = xen_map_cache(block->offset, block->max_length, 1, false); - } - return ramblock_ptr(block, addr); -} - -/* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr - * but takes a size argument. +/* + * Return a host pointer to guest's ram. * * Called within RCU critical section. */ static void *qemu_ram_ptr_length(RAMBlock *block, ram_addr_t addr, hwaddr *size, bool lock) { - if (*size == 0) { + hwaddr len = 0; + + if (size && *size == 0) { return NULL; } @@ -2233,7 +2207,10 @@ static void *qemu_ram_ptr_length(RAMBlock *block, ram_addr_t addr, block = qemu_get_ram_block(addr); addr -= block->offset; } - *size = MIN(*size, block->max_length - addr); + if (size) { + *size = MIN(*size, block->max_length - addr); + len = *size; + } if (xen_enabled() && block->host == NULL) { /* We need to check if the requested address is in the RAM @@ -2241,7 +2218,7 @@ static void *qemu_ram_ptr_length(RAMBlock *block, ram_addr_t addr, * In that case just map the requested area. */ if (block->offset == 0) { - return xen_map_cache(addr, *size, lock, lock); + return xen_map_cache(addr, len, lock, lock); } block->host = xen_map_cache(block->offset, block->max_length, 1, lock); @@ -2250,6 +2227,19 @@ static void *qemu_ram_ptr_length(RAMBlock *block, ram_addr_t addr, return ramblock_ptr(block, addr); } +/* + * Return a host pointer to ram allocated with qemu_ram_alloc. + * This should not be used for general purpose DMA. Use address_space_map + * or address_space_rw instead. For local memory (e.g. video ram) that the + * device owns, use memory_region_get_ram_ptr. + * + * Called within RCU critical section. + */ +void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) +{ + return qemu_ram_ptr_length(ram_block, addr, NULL, false); +} + /* Return the offset of a hostpointer within a ramblock */ ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host) { From patchwork Mon May 6 12:37:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB3C3C41513 for ; Mon, 6 May 2024 12:39:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3xd3-0005La-IN; Mon, 06 May 2024 08:39:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3xd0-000535-OG for qemu-devel@nongnu.org; Mon, 06 May 2024 08:39:35 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s3xcy-0002BF-Lj for qemu-devel@nongnu.org; Mon, 06 May 2024 08:39:34 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-41ba1ba5592so12617735e9.1 for ; Mon, 06 May 2024 05:39:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714999171; x=1715603971; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vPkYetppSsjPcJRijyPbZW3TmA+wkAdtU1ccC5YsPog=; b=hf0bccvLPsJ3T279ELV5hRP8x7mJNaqgetWH4sWKJ3kiFIjq8zl5+LEZN6xiSL4OIm yqqg0CQ9dUDdzLOflj9mtJ2v+v8y/Nq0MEOJmH/I3gAWx0O1hG2LAQW2BGo03dp0Aq85 8KsGN2tN0XzaDCPkQQ984aoYx9bXIkeR973M41V7+WlzIUD6pmgfSTx4Rp2ziF7A+g8R BbY6B6r3D/vIjGvDV5W0a1ugO7Vdv9rdkhhpbtBRYssj3EQ3tvTeT8X0M7KtQvfYM+eV np+7equ/PqWRmdi4TCORQEV3J1QXYln/mR6XzS4OENmo5FOKEZg1Z0XQ6LgVj4HPetVu xntw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714999171; x=1715603971; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vPkYetppSsjPcJRijyPbZW3TmA+wkAdtU1ccC5YsPog=; b=BPoHyhZRJB5IStndVvoia/+qVZOhQfXVexyqT33xSzLh08eEFa2EM1OOdVCyzQF0BY KthQKxJMkyNVJBX9i6sigDU907PhGy7Sm1QiZ/QJJwpCpAUGfbL439UvCOZCyto7yuK0 aO8Cqf5x+I0d/2KVRzKZcC88tKqSaHS6xF1KbE9Ma5i089xZ/79yzg1qRegSPNYJ1sTw zgWeBI8dThxX+raBxXiqmlf1NqFYkfg5jwQxJ/W3nr0AVbeWf8KwyB1KigUM4Lwz1FvL yvarajInVj6dgiNr3aCg9zXP+QavyhUXmA9f3wFE3RyYYYLC4zWapsXLswCsYOSUhJpJ /V4w== X-Gm-Message-State: AOJu0YzYgODdqrzYXptT2gxtPnAVPdakFky2drdwFPrrcoxp1plqb9hC bvOryzIqChZdM22Lf80LeXNQaNNxFuD7P2ErJZkHs4CcFkBfNcf90qEV8/I20E/WKieTRl4anyb k X-Google-Smtp-Source: AGHT+IFMwT2CU499T0HLrxuDWtAES8yxvtF878ta820SmEae4RndjeuacLoAIPnzOFdGp5hduuZ1Dg== X-Received: by 2002:a05:600c:4f02:b0:41b:d973:24c1 with SMTP id l2-20020a05600c4f0200b0041bd97324c1mr9426655wmq.12.1714999170931; Mon, 06 May 2024 05:39:30 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id bg5-20020a05600c3c8500b0041bbec72670sm16031875wmb.39.2024.05.06.05.39.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:39:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Juergen Gross , Stefano Stabellini , "Edgar E . Iglesias" , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PULL 17/28] xen: let xen_ram_addr_from_mapcache() return -1 in case of not found entry Date: Mon, 6 May 2024 14:37:17 +0200 Message-ID: <20240506123728.65278-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Juergen Gross Today xen_ram_addr_from_mapcache() will either abort() or return 0 in case it can't find a matching entry for a pointer value. Both cases are bad, so change that to return an invalid address instead. Signed-off-by: Juergen Gross Reviewed-by: Stefano Stabellini Message-Id: <20231005181629.4046-5-vikram.garhwal@amd.com> Signed-off-by: Edgar E. Iglesias Reviewed-by: Alex Bennée Reviewed-by: Edgar E. Iglesias Message-ID: <20240430164939.925307-3-edgar.iglesias@gmail.com> [PMD: Keep xen_ram_addr_from_mapcache_not_found trace event] Signed-off-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index 7f59080ba7..7771c6cb91 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -395,12 +395,8 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) } if (!found) { trace_xen_ram_addr_from_mapcache_not_found(ptr); - QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { - trace_xen_ram_addr_from_mapcache_found(reventry->paddr_index, - reventry->vaddr_req); - } - abort(); - return 0; + mapcache_unlock(); + return RAM_ADDR_INVALID; } entry = &mapcache->entry[paddr_index % mapcache->nr_buckets]; @@ -409,7 +405,7 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) } if (!entry) { trace_xen_ram_addr_from_mapcache_not_in_cache(ptr); - raddr = 0; + raddr = RAM_ADDR_INVALID; } else { raddr = (reventry->paddr_index << MCACHE_BUCKET_SHIFT) + ((unsigned long) ptr - (unsigned long) entry->vaddr_base); From patchwork Mon May 6 12:37:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD86AC25B10 for ; Mon, 6 May 2024 12:40:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3xdM-00086M-VN; Mon, 06 May 2024 08:39:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3xdK-0007qD-IT for qemu-devel@nongnu.org; Mon, 06 May 2024 08:39:54 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s3xd5-0002Cr-8c for qemu-devel@nongnu.org; Mon, 06 May 2024 08:39:54 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-41ba1ba55e8so11241215e9.1 for ; Mon, 06 May 2024 05:39:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714999177; x=1715603977; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K5u2rheGkOka+/vzLNLtDhnD9hQYgNI374jkL3ZGkPc=; b=FZ+BtUvJPefmr+BMqwJ1EnSz3CGn0xq5QgeJhWeYSaWUGkWVY5cjYBIIxAun97ALYm hvKTKpNrZ6J2SWk7DkQtWKd84tT//bEloJDgIlj9mXlxgyybRxhDrVhGOBD7cV4CBLIv zMO70Kl6zJJXopDnwflMS2vvoGLP7tS9ZHfMTEQN86NLgatENIs4gs9W33FHXTi5gS8Y UJTjqL1DcposzVt9dFia8AmrmHznLkIFd9J2/TSF4pG32qneQNRalTyNPq6j68MKazFi ASvZTAd0QDrCXb/Yv+KRZ5qcDmz9INve7/cDU/waK9I4fEPQW/RIRZJOmjNQ8hH0++i+ CdoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714999177; x=1715603977; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K5u2rheGkOka+/vzLNLtDhnD9hQYgNI374jkL3ZGkPc=; b=ei09O9qv9XK/k7jlfp48Bx6Bset609aq6fCkvjQ1Qh04EeacuwoBglL+4C2YX6d1Zz 6PH1RZnnoWjzP8wR8LKn2RtFTFGliiuitfVc/P/Xzvj4DtJJuFJqeVL+pG9r0keL2B0H XygcYqeiLB5zhTGZPa6vVis2Lfec3Sq/jZpTvx6oyS/YmV4vqY0hSbro15GJRlibvtK6 nQ/H6gGLKNytTo9RonFsCmG2wHDtxXXI0reBKxyxUawFDCKpaZm5PVaja+O2qb6GM1x7 g1NPre5Uy01MNeeu3J+vk73+Sf4XXFDI9uLTvQKGkIfUeySAvQ0KRCoJ4K40x9laU2OU m66Q== X-Gm-Message-State: AOJu0YxhVrESxIhu6KuzqXDk69q+Alzq5lrvd2e03jeO14jjljcQbJZp Yf7/KDv5TZsXWYNDyNdfb77HKxdeW5SRJPvzorqjyXkAIijluYgOKVLJuBGmqVYyP0rT+noYONH x X-Google-Smtp-Source: AGHT+IGLz2ZAUAXBGxzk59Qi/pFWQGF4bvX4V1r7EYcJjsqxyYUKqVqIeHYv8Csis1DoITvakX8xiQ== X-Received: by 2002:a05:600c:4446:b0:41b:4de0:7bff with SMTP id v6-20020a05600c444600b0041b4de07bffmr7626181wmn.35.1714999177047; Mon, 06 May 2024 05:39:37 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id i16-20020a05600c355000b0041b61504565sm16142382wmq.28.2024.05.06.05.39.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:39:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Stefano Stabellini Subject: [PULL 18/28] xen: mapcache: Refactor lock functions for multi-instance Date: Mon, 6 May 2024 14:37:18 +0200 Message-ID: <20240506123728.65278-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Make the lock functions take MapCache * as argument. This is in preparation for supporting multiple caches. No functional changes. Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefano Stabellini Message-ID: <20240430164939.925307-4-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index 7771c6cb91..c27be6abee 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -74,14 +74,14 @@ typedef struct MapCache { static MapCache *mapcache; -static inline void mapcache_lock(void) +static inline void mapcache_lock(MapCache *mc) { - qemu_mutex_lock(&mapcache->lock); + qemu_mutex_lock(&mc->lock); } -static inline void mapcache_unlock(void) +static inline void mapcache_unlock(MapCache *mc) { - qemu_mutex_unlock(&mapcache->lock); + qemu_mutex_unlock(&mc->lock); } static inline int test_bits(int nr, int size, const unsigned long *addr) @@ -369,9 +369,9 @@ uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size, { uint8_t *p; - mapcache_lock(); + mapcache_lock(mapcache); p = xen_map_cache_unlocked(phys_addr, size, lock, dma); - mapcache_unlock(); + mapcache_unlock(mapcache); return p; } @@ -384,7 +384,7 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) ram_addr_t raddr; int found = 0; - mapcache_lock(); + mapcache_lock(mapcache); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { if (reventry->vaddr_req == ptr) { paddr_index = reventry->paddr_index; @@ -395,7 +395,7 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) } if (!found) { trace_xen_ram_addr_from_mapcache_not_found(ptr); - mapcache_unlock(); + mapcache_unlock(mapcache); return RAM_ADDR_INVALID; } @@ -410,7 +410,7 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) raddr = (reventry->paddr_index << MCACHE_BUCKET_SHIFT) + ((unsigned long) ptr - (unsigned long) entry->vaddr_base); } - mapcache_unlock(); + mapcache_unlock(mapcache); return raddr; } @@ -481,9 +481,9 @@ static void xen_invalidate_map_cache_entry_bh(void *opaque) { XenMapCacheData *data = opaque; - mapcache_lock(); + mapcache_lock(mapcache); xen_invalidate_map_cache_entry_unlocked(data->buffer); - mapcache_unlock(); + mapcache_unlock(mapcache); aio_co_wake(data->co); } @@ -499,9 +499,9 @@ void coroutine_mixed_fn xen_invalidate_map_cache_entry(uint8_t *buffer) xen_invalidate_map_cache_entry_bh, &data); qemu_coroutine_yield(); } else { - mapcache_lock(); + mapcache_lock(mapcache); xen_invalidate_map_cache_entry_unlocked(buffer); - mapcache_unlock(); + mapcache_unlock(mapcache); } } @@ -513,7 +513,7 @@ void xen_invalidate_map_cache(void) /* Flush pending AIO before destroying the mapcache */ bdrv_drain_all(); - mapcache_lock(); + mapcache_lock(mapcache); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { if (!reventry->dma) { @@ -547,7 +547,7 @@ void xen_invalidate_map_cache(void) mapcache->last_entry = NULL; - mapcache_unlock(); + mapcache_unlock(mapcache); } static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, @@ -607,8 +607,8 @@ uint8_t *xen_replace_cache_entry(hwaddr old_phys_addr, { uint8_t *p; - mapcache_lock(); + mapcache_lock(mapcache); p = xen_replace_cache_entry_unlocked(old_phys_addr, new_phys_addr, size); - mapcache_unlock(); + mapcache_unlock(mapcache); return p; } From patchwork Mon May 6 12:37:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB31AC25B5F for ; Mon, 6 May 2024 12:40:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3xdQ-0000K4-QM; Mon, 06 May 2024 08:40:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3xdO-0008O7-KY for qemu-devel@nongnu.org; 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Mon, 06 May 2024 05:39:43 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id m9-20020a05600c4f4900b0041bf7da4200sm16063851wmq.33.2024.05.06.05.39.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:39:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= , Stefano Stabellini Subject: [PULL 19/28] xen: mapcache: Refactor xen_map_cache for multi-instance Date: Mon, 6 May 2024 14:37:19 +0200 Message-ID: <20240506123728.65278-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Make xen_map_cache take a MapCache as argument. This is in prepaparation to support multiple map caches. No functional changes. Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefano Stabellini Message-ID: <20240430164939.925307-5-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index c27be6abee..9e0a56b41b 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -240,7 +240,8 @@ static void xen_remap_bucket(MapCacheEntry *entry, g_free(err); } -static uint8_t *xen_map_cache_unlocked(hwaddr phys_addr, hwaddr size, +static uint8_t *xen_map_cache_unlocked(MapCache *mc, + hwaddr phys_addr, hwaddr size, uint8_t lock, bool dma) { MapCacheEntry *entry, *pentry = NULL, @@ -269,16 +270,16 @@ tryagain: test_bit_size = XC_PAGE_SIZE; } - if (mapcache->last_entry != NULL && - mapcache->last_entry->paddr_index == address_index && + if (mc->last_entry != NULL && + mc->last_entry->paddr_index == address_index && !lock && !size && test_bits(address_offset >> XC_PAGE_SHIFT, test_bit_size >> XC_PAGE_SHIFT, - mapcache->last_entry->valid_mapping)) { + mc->last_entry->valid_mapping)) { trace_xen_map_cache_return( - mapcache->last_entry->vaddr_base + address_offset + mc->last_entry->vaddr_base + address_offset ); - return mapcache->last_entry->vaddr_base + address_offset; + return mc->last_entry->vaddr_base + address_offset; } /* size is always a multiple of MCACHE_BUCKET_SIZE */ @@ -291,7 +292,7 @@ tryagain: cache_size = MCACHE_BUCKET_SIZE; } - entry = &mapcache->entry[address_index % mapcache->nr_buckets]; + entry = &mc->entry[address_index % mc->nr_buckets]; while (entry && (lock || entry->lock) && entry->vaddr_base && (entry->paddr_index != address_index || entry->size != cache_size || @@ -326,10 +327,10 @@ tryagain: if(!test_bits(address_offset >> XC_PAGE_SHIFT, test_bit_size >> XC_PAGE_SHIFT, entry->valid_mapping)) { - mapcache->last_entry = NULL; + mc->last_entry = NULL; #ifdef XEN_COMPAT_PHYSMAP - if (!translated && mapcache->phys_offset_to_gaddr) { - phys_addr = mapcache->phys_offset_to_gaddr(phys_addr, size); + if (!translated && mc->phys_offset_to_gaddr) { + phys_addr = mc->phys_offset_to_gaddr(phys_addr, size); translated = true; goto tryagain; } @@ -342,7 +343,7 @@ tryagain: return NULL; } - mapcache->last_entry = entry; + mc->last_entry = entry; if (lock) { MapCacheRev *reventry = g_new0(MapCacheRev, 1); entry->lock++; @@ -352,16 +353,16 @@ tryagain: abort(); } reventry->dma = dma; - reventry->vaddr_req = mapcache->last_entry->vaddr_base + address_offset; - reventry->paddr_index = mapcache->last_entry->paddr_index; + reventry->vaddr_req = mc->last_entry->vaddr_base + address_offset; + reventry->paddr_index = mc->last_entry->paddr_index; reventry->size = entry->size; - QTAILQ_INSERT_HEAD(&mapcache->locked_entries, reventry, next); + QTAILQ_INSERT_HEAD(&mc->locked_entries, reventry, next); } trace_xen_map_cache_return( - mapcache->last_entry->vaddr_base + address_offset + mc->last_entry->vaddr_base + address_offset ); - return mapcache->last_entry->vaddr_base + address_offset; + return mc->last_entry->vaddr_base + address_offset; } uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size, @@ -370,7 +371,7 @@ uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size, uint8_t *p; mapcache_lock(mapcache); - p = xen_map_cache_unlocked(phys_addr, size, lock, dma); + p = xen_map_cache_unlocked(mapcache, phys_addr, size, lock, dma); mapcache_unlock(mapcache); return p; } From patchwork Mon May 6 12:37:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7E0EC25B10 for ; Mon, 6 May 2024 12:40:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3xdK-0007ql-Qv; Mon, 06 May 2024 08:39:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3xdJ-0007bq-0l for qemu-devel@nongnu.org; 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Mon, 06 May 2024 05:39:49 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id je8-20020a05600c1f8800b0041bf28aa11dsm15935813wmb.42.2024.05.06.05.39.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:39:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Stefano Stabellini , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Subject: [PULL 20/28] xen: mapcache: Refactor xen_remap_bucket for multi-instance Date: Mon, 6 May 2024 14:37:20 +0200 Message-ID: <20240506123728.65278-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Add MapCache argument to xen_remap_bucket in preparation to support multiple map caches. No functional changes. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240430164939.925307-6-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index 9e0a56b41b..6bb3e0b362 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -139,7 +139,8 @@ void xen_map_cache_init(phys_offset_to_gaddr_t f, void *opaque) mapcache->entry = g_malloc0(size); } -static void xen_remap_bucket(MapCacheEntry *entry, +static void xen_remap_bucket(MapCache *mc, + MapCacheEntry *entry, void *vaddr, hwaddr size, hwaddr address_index, @@ -313,14 +314,14 @@ tryagain: if (!entry) { entry = g_new0(MapCacheEntry, 1); pentry->next = entry; - xen_remap_bucket(entry, NULL, cache_size, address_index, dummy); + xen_remap_bucket(mc, entry, NULL, cache_size, address_index, dummy); } else if (!entry->lock) { if (!entry->vaddr_base || entry->paddr_index != address_index || entry->size != cache_size || !test_bits(address_offset >> XC_PAGE_SHIFT, test_bit_size >> XC_PAGE_SHIFT, entry->valid_mapping)) { - xen_remap_bucket(entry, NULL, cache_size, address_index, dummy); + xen_remap_bucket(mc, entry, NULL, cache_size, address_index, dummy); } } @@ -588,7 +589,7 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, trace_xen_replace_cache_entry_dummy(old_phys_addr, new_phys_addr); - xen_remap_bucket(entry, entry->vaddr_base, + xen_remap_bucket(mapcache, entry, entry->vaddr_base, cache_size, address_index, false); if (!test_bits(address_offset >> XC_PAGE_SHIFT, test_bit_size >> XC_PAGE_SHIFT, From patchwork Mon May 6 12:37:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655400 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 141D3C10F16 for ; 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Mon, 06 May 2024 05:39:55 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id b12-20020a5d4d8c000000b0034e65b8b43fsm8616106wru.8.2024.05.06.05.39.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:39:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Stefano Stabellini , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Subject: [PULL 21/28] xen: mapcache: Break out xen_ram_addr_from_mapcache_single Date: Mon, 6 May 2024 14:37:21 +0200 Message-ID: <20240506123728.65278-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Break out xen_ram_addr_from_mapcache_single(), a multi-cache aware version of xen_ram_addr_from_mapcache. No functional changes. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240430164939.925307-7-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index 6bb3e0b362..1927334e9f 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -377,7 +377,7 @@ uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size, return p; } -ram_addr_t xen_ram_addr_from_mapcache(void *ptr) +static ram_addr_t xen_ram_addr_from_mapcache_single(MapCache *mc, void *ptr) { MapCacheEntry *entry = NULL; MapCacheRev *reventry; @@ -386,8 +386,8 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) ram_addr_t raddr; int found = 0; - mapcache_lock(mapcache); - QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { + mapcache_lock(mc); + QTAILQ_FOREACH(reventry, &mc->locked_entries, next) { if (reventry->vaddr_req == ptr) { paddr_index = reventry->paddr_index; size = reventry->size; @@ -397,11 +397,11 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) } if (!found) { trace_xen_ram_addr_from_mapcache_not_found(ptr); - mapcache_unlock(mapcache); + mapcache_unlock(mc); return RAM_ADDR_INVALID; } - entry = &mapcache->entry[paddr_index % mapcache->nr_buckets]; + entry = &mc->entry[paddr_index % mc->nr_buckets]; while (entry && (entry->paddr_index != paddr_index || entry->size != size)) { entry = entry->next; } @@ -412,10 +412,15 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) raddr = (reventry->paddr_index << MCACHE_BUCKET_SHIFT) + ((unsigned long) ptr - (unsigned long) entry->vaddr_base); } - mapcache_unlock(mapcache); + mapcache_unlock(mc); return raddr; } +ram_addr_t xen_ram_addr_from_mapcache(void *ptr) +{ + return xen_ram_addr_from_mapcache_single(mapcache, ptr); +} + static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer) { MapCacheEntry *entry = NULL, *pentry = NULL; From patchwork Mon May 6 12:37:22 2024 Content-Type: text/plain; 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Mon, 06 May 2024 05:40:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= Subject: [PULL 22/28] xen: mapcache: Refactor xen_replace_cache_entry_unlocked Date: Mon, 6 May 2024 14:37:22 +0200 Message-ID: <20240506123728.65278-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Add MapCache argument to xen_replace_cache_entry_unlocked in preparation for supporting multiple map caches. No functional change. Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240430164939.925307-8-edgar.iglesias@gmail.com> [PMD: Remove last global mapcache pointer, reported by sstabellini] Signed-off-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index 1927334e9f..96c422981e 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -557,7 +557,8 @@ void xen_invalidate_map_cache(void) mapcache_unlock(mapcache); } -static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, +static uint8_t *xen_replace_cache_entry_unlocked(MapCache *mc, + hwaddr old_phys_addr, hwaddr new_phys_addr, hwaddr size) { @@ -579,7 +580,7 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, cache_size += MCACHE_BUCKET_SIZE - (cache_size % MCACHE_BUCKET_SIZE); } - entry = &mapcache->entry[address_index % mapcache->nr_buckets]; + entry = &mc->entry[address_index % mc->nr_buckets]; while (entry && !(entry->paddr_index == address_index && entry->size == cache_size)) { entry = entry->next; @@ -594,7 +595,7 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, trace_xen_replace_cache_entry_dummy(old_phys_addr, new_phys_addr); - xen_remap_bucket(mapcache, entry, entry->vaddr_base, + xen_remap_bucket(mc, entry, entry->vaddr_base, cache_size, address_index, false); if (!test_bits(address_offset >> XC_PAGE_SHIFT, test_bit_size >> XC_PAGE_SHIFT, @@ -615,7 +616,8 @@ uint8_t *xen_replace_cache_entry(hwaddr old_phys_addr, uint8_t *p; mapcache_lock(mapcache); - p = xen_replace_cache_entry_unlocked(old_phys_addr, new_phys_addr, size); + p = xen_replace_cache_entry_unlocked(mapcache, old_phys_addr, + new_phys_addr, size); mapcache_unlock(mapcache); return p; } From patchwork Mon May 6 12:37:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2166CC10F16 for ; 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Mon, 06 May 2024 05:40:07 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id j30-20020a5d6e5e000000b0034db5f648a8sm10669808wrz.77.2024.05.06.05.40.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:40:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Stefano Stabellini , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Subject: [PULL 23/28] xen: mapcache: Refactor xen_invalidate_map_cache_entry_unlocked Date: Mon, 6 May 2024 14:37:23 +0200 Message-ID: <20240506123728.65278-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Add MapCache argument to xen_invalidate_map_cache_entry_unlocked. This is in preparation for supporting multiple map caches. No functional changes. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240430164939.925307-9-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index 96c422981e..3e6a1a0a93 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -421,7 +421,8 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) return xen_ram_addr_from_mapcache_single(mapcache, ptr); } -static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer) +static void xen_invalidate_map_cache_entry_unlocked(MapCache *mc, + uint8_t *buffer) { MapCacheEntry *entry = NULL, *pentry = NULL; MapCacheRev *reventry; @@ -429,7 +430,7 @@ static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer) hwaddr size; int found = 0; - QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { + QTAILQ_FOREACH(reventry, &mc->locked_entries, next) { if (reventry->vaddr_req == buffer) { paddr_index = reventry->paddr_index; size = reventry->size; @@ -439,7 +440,7 @@ static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer) } if (!found) { trace_xen_invalidate_map_cache_entry_unlocked_not_found(buffer); - QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { + QTAILQ_FOREACH(reventry, &mc->locked_entries, next) { trace_xen_invalidate_map_cache_entry_unlocked_found( reventry->paddr_index, reventry->vaddr_req @@ -447,15 +448,15 @@ static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer) } return; } - QTAILQ_REMOVE(&mapcache->locked_entries, reventry, next); + QTAILQ_REMOVE(&mc->locked_entries, reventry, next); g_free(reventry); - if (mapcache->last_entry != NULL && - mapcache->last_entry->paddr_index == paddr_index) { - mapcache->last_entry = NULL; + if (mc->last_entry != NULL && + mc->last_entry->paddr_index == paddr_index) { + mc->last_entry = NULL; } - entry = &mapcache->entry[paddr_index % mapcache->nr_buckets]; + entry = &mc->entry[paddr_index % mc->nr_buckets]; while (entry && (entry->paddr_index != paddr_index || entry->size != size)) { pentry = entry; entry = entry->next; @@ -489,7 +490,7 @@ static void xen_invalidate_map_cache_entry_bh(void *opaque) XenMapCacheData *data = opaque; mapcache_lock(mapcache); - xen_invalidate_map_cache_entry_unlocked(data->buffer); + xen_invalidate_map_cache_entry_unlocked(mapcache, data->buffer); mapcache_unlock(mapcache); aio_co_wake(data->co); @@ -507,7 +508,7 @@ void coroutine_mixed_fn xen_invalidate_map_cache_entry(uint8_t *buffer) qemu_coroutine_yield(); } else { mapcache_lock(mapcache); - xen_invalidate_map_cache_entry_unlocked(buffer); + xen_invalidate_map_cache_entry_unlocked(mapcache, buffer); mapcache_unlock(mapcache); } } From patchwork Mon May 6 12:37:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AAA52C10F16 for ; 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Mon, 06 May 2024 05:40:13 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id d18-20020adfef92000000b0034c71090653sm10579327wro.57.2024.05.06.05.40.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:40:12 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Stefano Stabellini , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Subject: [PULL 24/28] xen: mapcache: Break out xen_invalidate_map_cache_single() Date: Mon, 6 May 2024 14:37:24 +0200 Message-ID: <20240506123728.65278-25-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Break out xen_invalidate_map_cache_single(). No functional changes. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240430164939.925307-10-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index 3e6a1a0a93..c8a0f4fbc2 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -513,17 +513,14 @@ void coroutine_mixed_fn xen_invalidate_map_cache_entry(uint8_t *buffer) } } -void xen_invalidate_map_cache(void) +static void xen_invalidate_map_cache_single(MapCache *mc) { unsigned long i; MapCacheRev *reventry; - /* Flush pending AIO before destroying the mapcache */ - bdrv_drain_all(); + mapcache_lock(mc); - mapcache_lock(mapcache); - - QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { + QTAILQ_FOREACH(reventry, &mc->locked_entries, next) { if (!reventry->dma) { continue; } @@ -531,8 +528,8 @@ void xen_invalidate_map_cache(void) reventry->vaddr_req); } - for (i = 0; i < mapcache->nr_buckets; i++) { - MapCacheEntry *entry = &mapcache->entry[i]; + for (i = 0; i < mc->nr_buckets; i++) { + MapCacheEntry *entry = &mc->entry[i]; if (entry->vaddr_base == NULL) { continue; @@ -553,9 +550,17 @@ void xen_invalidate_map_cache(void) entry->valid_mapping = NULL; } - mapcache->last_entry = NULL; + mc->last_entry = NULL; - mapcache_unlock(mapcache); + mapcache_unlock(mc); +} + +void xen_invalidate_map_cache(void) +{ + /* Flush pending AIO before destroying the mapcache */ + bdrv_drain_all(); + + xen_invalidate_map_cache_single(mapcache); } static uint8_t *xen_replace_cache_entry_unlocked(MapCache *mc, From patchwork Mon May 6 12:37:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E407C41513 for ; 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Mon, 06 May 2024 05:40:19 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id t12-20020a05600c198c00b0041becb7ff05sm15710181wmq.26.2024.05.06.05.40.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:40:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Stefano Stabellini , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Subject: [PULL 25/28] xen: mapcache: Break out xen_map_cache_init_single() Date: Mon, 6 May 2024 14:37:25 +0200 Message-ID: <20240506123728.65278-26-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Break out xen_map_cache_init_single() in preparation for adding multiple map caches. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini Message-ID: <20240430164939.925307-11-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/xen/xen-mapcache.c | 57 ++++++++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 23 deletions(-) diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index c8a0f4fbc2..6fb2db2612 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -93,23 +93,44 @@ static inline int test_bits(int nr, int size, const unsigned long *addr) return 0; } -void xen_map_cache_init(phys_offset_to_gaddr_t f, void *opaque) +static MapCache *xen_map_cache_init_single(phys_offset_to_gaddr_t f, + void *opaque, + unsigned long max_size) { unsigned long size; + MapCache *mc; + + mc = g_new0(MapCache, 1); + + mc->phys_offset_to_gaddr = f; + mc->opaque = opaque; + qemu_mutex_init(&mc->lock); + + QTAILQ_INIT(&mc->locked_entries); + + mc->max_mcache_size = max_size; + + mc->nr_buckets = + (((mc->max_mcache_size >> XC_PAGE_SHIFT) + + (1UL << (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT)) - 1) >> + (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT)); + + size = mc->nr_buckets * sizeof(MapCacheEntry); + size = (size + XC_PAGE_SIZE - 1) & ~(XC_PAGE_SIZE - 1); + trace_xen_map_cache_init(mc->nr_buckets, size); + mc->entry = g_malloc0(size); + return mc; +} + +void xen_map_cache_init(phys_offset_to_gaddr_t f, void *opaque) +{ struct rlimit rlimit_as; - - mapcache = g_new0(MapCache, 1); - - mapcache->phys_offset_to_gaddr = f; - mapcache->opaque = opaque; - qemu_mutex_init(&mapcache->lock); - - QTAILQ_INIT(&mapcache->locked_entries); + unsigned long max_mcache_size; if (geteuid() == 0) { rlimit_as.rlim_cur = RLIM_INFINITY; rlimit_as.rlim_max = RLIM_INFINITY; - mapcache->max_mcache_size = MCACHE_MAX_SIZE; + max_mcache_size = MCACHE_MAX_SIZE; } else { getrlimit(RLIMIT_AS, &rlimit_as); rlimit_as.rlim_cur = rlimit_as.rlim_max; @@ -119,24 +140,14 @@ void xen_map_cache_init(phys_offset_to_gaddr_t f, void *opaque) " memory is not infinity"); } if (rlimit_as.rlim_max < MCACHE_MAX_SIZE + NON_MCACHE_MEMORY_SIZE) { - mapcache->max_mcache_size = rlimit_as.rlim_max - - NON_MCACHE_MEMORY_SIZE; + max_mcache_size = rlimit_as.rlim_max - NON_MCACHE_MEMORY_SIZE; } else { - mapcache->max_mcache_size = MCACHE_MAX_SIZE; + max_mcache_size = MCACHE_MAX_SIZE; } } + mapcache = xen_map_cache_init_single(f, opaque, max_mcache_size); setrlimit(RLIMIT_AS, &rlimit_as); - - mapcache->nr_buckets = - (((mapcache->max_mcache_size >> XC_PAGE_SHIFT) + - (1UL << (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT)) - 1) >> - (MCACHE_BUCKET_SHIFT - XC_PAGE_SHIFT)); - - size = mapcache->nr_buckets * sizeof (MapCacheEntry); - size = (size + XC_PAGE_SIZE - 1) & ~(XC_PAGE_SIZE - 1); - trace_xen_map_cache_init(mapcache->nr_buckets, size); - mapcache->entry = g_malloc0(size); } static void xen_remap_bucket(MapCache *mc, From patchwork Mon May 6 12:37:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13655401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F458C10F16 for ; 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Mon, 06 May 2024 05:40:26 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id g4-20020a5d5404000000b0034ca136f0e9sm10608838wrv.88.2024.05.06.05.40.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:40:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Stefano Stabellini , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Peter Xu , David Hildenbrand Subject: [PULL 26/28] softmmu: Pass RAM MemoryRegion and is_write in xen_map_cache() Date: Mon, 6 May 2024 14:37:26 +0200 Message-ID: <20240506123728.65278-27-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "Edgar E. Iglesias" Propagate MR and is_write to xen_map_cache(). This is in preparation for adding support for grant mappings. No functional change. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini Reviewed-by: Philippe Mathieu-Daudé Acked-by: Peter Xu Reviewed-by: David Hildenbrand Message-ID: <20240430164939.925307-14-edgar.iglesias@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/xen-mapcache.h | 11 +++++++---- hw/xen/xen-mapcache.c | 10 ++++++---- system/physmem.c | 31 +++++++++++++++++++++++-------- 3 files changed, 36 insertions(+), 16 deletions(-) diff --git a/include/sysemu/xen-mapcache.h b/include/sysemu/xen-mapcache.h index 10c2e3082a..1ec9e66752 100644 --- a/include/sysemu/xen-mapcache.h +++ b/include/sysemu/xen-mapcache.h @@ -18,8 +18,9 @@ typedef hwaddr (*phys_offset_to_gaddr_t)(hwaddr phys_offset, void xen_map_cache_init(phys_offset_to_gaddr_t f, void *opaque); -uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size, - uint8_t lock, bool dma); +uint8_t *xen_map_cache(MemoryRegion *mr, hwaddr phys_addr, hwaddr size, + uint8_t lock, bool dma, + bool is_write); ram_addr_t xen_ram_addr_from_mapcache(void *ptr); void xen_invalidate_map_cache_entry(uint8_t *buffer); void xen_invalidate_map_cache(void); @@ -33,10 +34,12 @@ static inline void xen_map_cache_init(phys_offset_to_gaddr_t f, { } -static inline uint8_t *xen_map_cache(hwaddr phys_addr, +static inline uint8_t *xen_map_cache(MemoryRegion *mr, + hwaddr phys_addr, hwaddr size, uint8_t lock, - bool dma) + bool dma, + bool is_write) { abort(); } diff --git a/hw/xen/xen-mapcache.c b/hw/xen/xen-mapcache.c index 6fb2db2612..fa6813b1ad 100644 --- a/hw/xen/xen-mapcache.c +++ b/hw/xen/xen-mapcache.c @@ -254,7 +254,7 @@ static void xen_remap_bucket(MapCache *mc, static uint8_t *xen_map_cache_unlocked(MapCache *mc, hwaddr phys_addr, hwaddr size, - uint8_t lock, bool dma) + uint8_t lock, bool dma, bool is_write) { MapCacheEntry *entry, *pentry = NULL, *free_entry = NULL, *free_pentry = NULL; @@ -377,13 +377,15 @@ tryagain: return mc->last_entry->vaddr_base + address_offset; } -uint8_t *xen_map_cache(hwaddr phys_addr, hwaddr size, - uint8_t lock, bool dma) +uint8_t *xen_map_cache(MemoryRegion *mr, + hwaddr phys_addr, hwaddr size, + uint8_t lock, bool dma, + bool is_write) { uint8_t *p; mapcache_lock(mapcache); - p = xen_map_cache_unlocked(mapcache, phys_addr, size, lock, dma); + p = xen_map_cache_unlocked(mapcache, phys_addr, size, lock, dma, is_write); mapcache_unlock(mapcache); return p; } diff --git a/system/physmem.c b/system/physmem.c index 8278e31c1a..79d46054c5 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -2191,11 +2191,22 @@ void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) /* * Return a host pointer to guest's ram. + * For Xen, foreign mappings get created if they don't already exist. + * + * @block: block for the RAM to lookup (optional and may be NULL). + * @addr: address within the memory region. + * @size: pointer to requested size (optional and may be NULL). + * size may get modified and return a value smaller than + * what was requested. + * @lock: wether to lock the mapping in xen-mapcache until invalidated. + * @is_write: hint wether to map RW or RO in the xen-mapcache. + * (optional and may always be set to true). * * Called within RCU critical section. */ static void *qemu_ram_ptr_length(RAMBlock *block, ram_addr_t addr, - hwaddr *size, bool lock) + hwaddr *size, bool lock, + bool is_write) { hwaddr len = 0; @@ -2218,10 +2229,13 @@ static void *qemu_ram_ptr_length(RAMBlock *block, ram_addr_t addr, * In that case just map the requested area. */ if (block->offset == 0) { - return xen_map_cache(addr, len, lock, lock); + return xen_map_cache(block->mr, addr, len, lock, lock, + is_write); } - block->host = xen_map_cache(block->offset, block->max_length, 1, lock); + block->host = xen_map_cache(block->mr, block->offset, + block->max_length, 1, + lock, is_write); } return ramblock_ptr(block, addr); @@ -2237,7 +2251,7 @@ static void *qemu_ram_ptr_length(RAMBlock *block, ram_addr_t addr, */ void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) { - return qemu_ram_ptr_length(ram_block, addr, NULL, false); + return qemu_ram_ptr_length(ram_block, addr, NULL, false, true); } /* Return the offset of a hostpointer within a ramblock */ @@ -2747,7 +2761,7 @@ static MemTxResult flatview_write_continue_step(MemTxAttrs attrs, } else { /* RAM case */ uint8_t *ram_ptr = qemu_ram_ptr_length(mr->ram_block, mr_addr, l, - false); + false, true); memmove(ram_ptr, buf, *l); invalidate_and_set_dirty(mr, mr_addr, *l); @@ -2840,7 +2854,7 @@ static MemTxResult flatview_read_continue_step(MemTxAttrs attrs, uint8_t *buf, } else { /* RAM case */ uint8_t *ram_ptr = qemu_ram_ptr_length(mr->ram_block, mr_addr, l, - false); + false, false); memcpy(buf, ram_ptr, *l); @@ -3234,7 +3248,7 @@ void *address_space_map(AddressSpace *as, *plen = flatview_extend_translation(fv, addr, len, mr, xlat, l, is_write, attrs); fuzz_dma_read_cb(addr, *plen, mr); - return qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); + return qemu_ram_ptr_length(mr->ram_block, xlat, plen, true, is_write); } /* Unmaps a memory region previously mapped by address_space_map(). @@ -3330,7 +3344,8 @@ int64_t address_space_cache_init(MemoryRegionCache *cache, l = flatview_extend_translation(cache->fv, addr, len, mr, cache->xlat, l, is_write, MEMTXATTRS_UNSPECIFIED); - cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true); + cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true, + is_write); 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Mon, 06 May 2024 05:40:32 -0700 (PDT) Received: from m1x-phil.lan ([176.187.211.4]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0041abdaf8c6asm19693892wmo.13.2024.05.06.05.40.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 May 2024 05:40:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PULL 27/28] MAINTAINERS: Update Aleksandar Rikalo email Date: Mon, 6 May 2024 14:37:27 +0200 Message-ID: <20240506123728.65278-28-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philmd@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Aleksandar Rikalo Syrmia LLC has been acquired recently and the syrmia.com domain will disappear soon, so updating my email in the MAINTAINERS file. Signed-off-by: Aleksandar Rikalo Message-ID: <20240209062147.62453-1-aleksandar.rikalo@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 595808fc96..63ada48bb4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -285,7 +285,7 @@ MIPS TCG CPUs M: Philippe Mathieu-Daudé R: Aurelien Jarno R: Jiaxun Yang -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Odd Fixes F: target/mips/ F: disas/*mips.c @@ -1335,7 +1335,7 @@ F: include/hw/mips/ Jazz M: Hervé Poussineau -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Maintained F: hw/mips/jazz.c F: hw/display/g364fb.c @@ -1357,7 +1357,7 @@ F: tests/avocado/linux_ssh_mips_malta.py F: tests/avocado/machine_mips_malta.py Mipssim -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Orphan F: hw/mips/mipssim.c F: hw/net/mipsnet.c @@ -1385,7 +1385,7 @@ F: tests/avocado/machine_mips_loongson3v.py Boston M: Paul Burton -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Odd Fixes F: hw/core/loader-fit.c F: hw/mips/boston.c @@ -3762,7 +3762,7 @@ M: Philippe Mathieu-Daudé R: Aurelien Jarno R: Huacai Chen R: Jiaxun Yang -R: Aleksandar Rikalo +R: Aleksandar Rikalo S: Odd Fixes F: tcg/mips/ From patchwork Mon May 6 12:37:28 2024 Content-Type: text/plain; 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Mon, 06 May 2024 05:40:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Bin Meng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 28/28] MAINTAINERS: Update my email address Date: Mon, 6 May 2024 14:37:28 +0200 Message-ID: <20240506123728.65278-29-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240506123728.65278-1-philmd@linaro.org> References: <20240506123728.65278-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bin Meng The old Wind River email address (bin.meng@windriver.com) is no longer available due to an internal infrastructure change within the company. While a new email address (bin.meng.cn@windriver.com) has been assigned to me, I am unable to find a way to send this patch directly from the new address. Presumably, the basic authentication with client submission (SMTP AUTH) [1] has been disabled by the company's IT. Switch to use my personal email address instead. Signed-off-by: Bin Meng Signed-off-by: Bin Meng [1] https://learn.microsoft.com/en-us/exchange/mail-flow-best-practices/how-to-set-up-a-multifunction-device-or-application-to-send-email-using-microsoft-365-or-office-365 Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240505072312.2776074-1-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 63ada48bb4..84391777db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -320,7 +320,7 @@ F: tests/tcg/ppc*/* RISC-V TCG CPUs M: Palmer Dabbelt M: Alistair Francis -M: Bin Meng +M: Bin Meng R: Weiwei Li R: Daniel Henrique Barboza R: Liu Zhiwei @@ -1603,7 +1603,7 @@ F: include/hw/riscv/opentitan.h F: include/hw/*/ibex_*.h Microchip PolarFire SoC Icicle Kit -M: Bin Meng +M: Bin Meng L: qemu-riscv@nongnu.org S: Supported F: docs/system/riscv/microchip-icicle-kit.rst @@ -1630,7 +1630,7 @@ F: include/hw/char/shakti_uart.h SiFive Machines M: Alistair Francis -M: Bin Meng +M: Bin Meng M: Palmer Dabbelt L: qemu-riscv@nongnu.org S: Supported @@ -2126,7 +2126,7 @@ F: hw/ssi/xilinx_* SD (Secure Card) M: Philippe Mathieu-Daudé -M: Bin Meng +M: Bin Meng L: qemu-block@nongnu.org S: Odd Fixes F: include/hw/sd/sd*