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Tue, 7 May 2024 05:01:51 -0400 (EDT) From: Jiaxun Yang Date: Tue, 07 May 2024 10:01:49 +0100 Subject: [PATCH 1/5] MIPS: generic: Do __dt_setup_arch in prom_init Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-cm_probe-v1-1-11dbfd598f3c@flygoat.com> References: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> In-Reply-To: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> To: Paul Burton , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1100; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=EgYZHI74g5P3QvmuzwztTxZvJrgG/TaQMR9K1Fjgx+s=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjTLt/8rOvT2nfHeNE1kY9HMFzPTuXaqOl8Okzi0f9lt8 /OrOXZt6ChlYRDjYJAVU2QJEVDq29B4ccH1B1l/YOawMoEMYeDiFICJdMgyMhz9z+OxxMry9tuK uGhtV+ZXG3f/DIydFlB4tMckzl75xiOG/zWZnAH/pXeWGj1Z7Tqxz+bKuuQfhaJJ+bc7ha9o7JD 8zQMA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 We want fdt parse functions to be available as early as possible, thus do __dt_setup_arch immediately after we get fdt address in prom_init. Signed-off-by: Jiaxun Yang --- arch/mips/generic/init.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c index 1d712eac1617..9fd09061de78 100644 --- a/arch/mips/generic/init.c +++ b/arch/mips/generic/init.c @@ -26,8 +26,12 @@ static __initconst const void *mach_match_data; void __init prom_init(void) { + fw_init_cmdline(); plat_get_fdt(); BUG_ON(!fdt); + if (mach && mach->fixup_fdt) + fdt = mach->fixup_fdt(fdt, mach_match_data); + __dt_setup_arch((void *)fdt); } void __init *plat_get_fdt(void) @@ -101,11 +105,6 @@ void __init plat_fdt_relocated(void *new_location) void __init plat_mem_setup(void) { - if (mach && mach->fixup_fdt) - fdt = mach->fixup_fdt(fdt, mach_match_data); - - fw_init_cmdline(); - __dt_setup_arch((void *)fdt); } void __init device_tree_init(void) From patchwork Tue May 7 09:01:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13656431 Received: from fout8-smtp.messagingengine.com (fout8-smtp.messagingengine.com [103.168.172.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0B0014D458; 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Tue, 7 May 2024 05:01:53 -0400 (EDT) From: Jiaxun Yang Date: Tue, 07 May 2024 10:01:50 +0100 Subject: [PATCH 2/5] MIPS: cm: Prefix probe functions with __init Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-cm_probe-v1-2-11dbfd598f3c@flygoat.com> References: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> In-Reply-To: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> To: Paul Burton , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2498; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=SLgeVPAUIVYffojO40aOD2FkVjz1kvjwA4zqDsv9YXo=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjTLt/879SpaDhjy57Cr8bNKrrRfcsLQzVh4Tde5wOZ/9 zXPuFt2lLIwiHEwyIopsoQIKPVtaLy44PqDrD8wc1iZQIYwcHEKwEQ2LWJk2Nt6utjdSyU+ZtX3 FPWrzwLKneclqbxxvvXvgKST4AGvewy/WY2VJixl5Jp9xfBty882MdXy1INV9R2r+99GnbcNFTT iAwA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Those functions are only used at boot time. Prefix them with __init so they can be discarded after boot. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mips-cm.h | 4 ++-- arch/mips/kernel/mips-cm.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index c2930a75b7e4..5292b516d60b 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -30,7 +30,7 @@ extern void __iomem *mips_cm_l2sync_base; * and may be overridden by platforms which determine this address in a * different way by defining a function with the same prototype. */ -extern phys_addr_t mips_cm_phys_base(void); +extern phys_addr_t __init mips_cm_phys_base(void); /** * mips_cm_l2sync_phys_base - retrieve the physical base address of the CM @@ -43,7 +43,7 @@ extern phys_addr_t mips_cm_phys_base(void); * determine this address in a different way by defining a function with the * same prototype. */ -extern phys_addr_t mips_cm_l2sync_phys_base(void); +extern phys_addr_t __init mips_cm_l2sync_phys_base(void); /* * mips_cm_is64 - determine CM register width diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 3a115fab5573..dddc9428fe58 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -179,7 +179,7 @@ static char *cm3_causes[32] = { static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock); static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags); -phys_addr_t __weak mips_cm_phys_base(void) +phys_addr_t __init __weak mips_cm_phys_base(void) { unsigned long cmgcr; @@ -198,7 +198,7 @@ phys_addr_t __weak mips_cm_phys_base(void) return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); } -phys_addr_t __weak mips_cm_l2sync_phys_base(void) +phys_addr_t __init __weak mips_cm_l2sync_phys_base(void) { u32 base_reg; @@ -214,7 +214,7 @@ phys_addr_t __weak mips_cm_l2sync_phys_base(void) return mips_cm_phys_base() + MIPS_CM_GCR_SIZE; } -static void mips_cm_probe_l2sync(void) +static void __init mips_cm_probe_l2sync(void) { unsigned major_rev; phys_addr_t addr; @@ -237,7 +237,7 @@ static void mips_cm_probe_l2sync(void) mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE); } -int mips_cm_probe(void) +int __init mips_cm_probe(void) { phys_addr_t addr; u32 base_reg; From patchwork Tue May 7 09:01:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13656432 Received: from fhigh4-smtp.messagingengine.com (fhigh4-smtp.messagingengine.com [103.168.172.155]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B06014D6FA; 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Tue, 7 May 2024 05:01:54 -0400 (EDT) From: Jiaxun Yang Date: Tue, 07 May 2024 10:01:51 +0100 Subject: [PATCH 3/5] MIPS: Move mips_cm_probe after prom_init Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-cm_probe-v1-3-11dbfd598f3c@flygoat.com> References: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> In-Reply-To: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> To: Paul Burton , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=983; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=/VhFjeCllbEn45e0h4OgjSs8v3tfHTymSKkW07Ck+7g=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjTLt//nTL2zKDP+/xfmtr7GXwe0yjWOWSccs/WZxbvss tb818lTOkpZGMQ4GGTFFFlCBJT6NjReXHD9QdYfmDmsTCBDGLg4BWAiZu2MDE/7ndknT3+712VJ 9bvoTJGX129z7kk7J//N4ZTIWZ4228MMv1nd7me82T2Zbab9SrYbims3zTilqSbS7XDaz/Rj9dY 1/xkA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Move mips_cm_probe after prom_init so we can use fdt functions in mips_cm_probe to obtain essential information. Impat for all systems that may have CM in system: - geneirc: Adjusted code to accommodate this change - Lantiq: No impact, CM configuration won't be changed at all - ralink: Called mips_cm_probe on it's own, in prom_init->prom_soc_init - malta: No impact, CM address comes from CP0_CMGCR Signed-off-by: Jiaxun Yang --- arch/mips/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 12a1a4ffb602..732579c8f4f8 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -773,8 +773,8 @@ static void __init setup_rng_seed(void) void __init setup_arch(char **cmdline_p) { cpu_probe(); - mips_cm_probe(); prom_init(); + mips_cm_probe(); setup_early_fdc_console(); #ifdef CONFIG_EARLY_PRINTK From patchwork Tue May 7 09:01:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13656433 Received: from fout8-smtp.messagingengine.com (fout8-smtp.messagingengine.com [103.168.172.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C246B14E2C0; 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Tue, 7 May 2024 05:01:56 -0400 (EDT) From: Jiaxun Yang Date: Tue, 07 May 2024 10:01:52 +0100 Subject: [PATCH 4/5] dt-bindings: mips: Document mti,mips-cm Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-cm_probe-v1-4-11dbfd598f3c@flygoat.com> References: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> In-Reply-To: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> To: Paul Burton , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1338; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=BYd0z4w2P6361HK8XCnk63d1hg9xPM/ibgUD+fCXqh8=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjTLt/9PvYjtyrwTlmXEtUWy6pZfacGiP7K5145m57GYf Zn1Xj2+o5SFQYyDQVZMkSVEQKlvQ+PFBdcfZP2BmcPKBDKEgYtTACayN5/hr7Ddn+sOSYfLs/Tn drwN3ZHhcePgxa98vm/aYoqlZi8s4mZk+Pn4+vGD8t532K4nnmS7xTTXtn127JNSo91L5M/yCYk +YAYA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Add devicetree binding documentation for MIPS Coherence Manager. Signed-off-by: Jiaxun Yang --- .../devicetree/bindings/mips/mips-cm.yaml | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/mips-cm.yaml b/Documentation/devicetree/bindings/mips/mips-cm.yaml new file mode 100644 index 000000000000..b92b008d7758 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mips-cm.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mips-cm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Coherence Manager + +description: | + Defines a location of the MIPS Coherence Manager registers. + +maintainers: + - Jiaxun Yang + +properties: + compatible: + const: mti,mips-cm + + reg: + description: | + Base address and size of an unoccupied memory region, which will be + used to map the MIPS CM registers block. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cm@1fbf8000 { + compatible = "mti,mips-cm"; + reg = <0x1bde8000 0x8000>; + }; +... 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Tue, 7 May 2024 05:01:57 -0400 (EDT) From: Jiaxun Yang Date: Tue, 07 May 2024 10:01:53 +0100 Subject: [PATCH 5/5] MIPS: cm: Probe GCR address from DeviceTree Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240507-cm_probe-v1-5-11dbfd598f3c@flygoat.com> References: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> In-Reply-To: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> To: Paul Burton , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2951; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=4EfRyQXq3a/gP4GGGVwHML+S7nX0DpMKT8K0KyhTHVI=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjTLt/85r9+dvsBAqmGKLJf55oiN83aKbbS4wBW6y150l dkSQz3XjlIWBjEOBlkxRZYQAaW+DY0XF1x/kPUHZg4rE8gQBi5OAZiIqB7DX/n0b0HvE9bv/bSn Nevs+3fiSnJlU3a+9YifzX39bFSAjyfDf+eyZ8u4u72iw8ULViYVyO4WuWwyZ54qq1zX4rbYe7O ucAIA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Traditionally, CM GCR address can be probed from CP0_CMGCRBase. However there are chips in wild that do have CM GCR but CP0_CMGCRBase is not available from CPU point of view. Thus we need to be able to probe GCR address from DeviceTree. It is implemented as: - If only CP0_CMGCRBase present, trust CP0_CMGCRBase - If only mti,mips-cm node present, trust mti,mips-cm reg prop - If both present, remap address space to address specified in dt Signed-off-by: Jiaxun Yang --- arch/mips/kernel/mips-cm.c | 58 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 52 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index dddc9428fe58..9563fc1ad438 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -5,6 +5,8 @@ */ #include +#include +#include #include #include @@ -179,23 +181,67 @@ static char *cm3_causes[32] = { static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock); static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags); +static int __init mips_cm_fdt_scan(unsigned long node, const char *uname, + int depth, void *data) +{ + unsigned long *cmgcr = data; + + if (!of_flat_dt_is_compatible(node, "mti,mips-cm")) + return 0; + + *cmgcr = of_flat_dt_translate_address(node); + if (*cmgcr == OF_BAD_ADDR) + *cmgcr = 0; + + return 0; +} + phys_addr_t __init __weak mips_cm_phys_base(void) { - unsigned long cmgcr; + unsigned long gcr_reg = 0, gcr_dt = 0; + + if (of_have_populated_dt()) { + int err; + struct resource res; + struct device_node *cm_node; + + cm_node = of_find_compatible_node(of_root, NULL, "mti,mips-cm"); + if (cm_node) { + err = of_address_to_resource(cm_node, 0, &res); + of_node_put(cm_node); + if (!err) + gcr_dt = res.start; + } + } else { + of_scan_flat_dt(mips_cm_fdt_scan, &gcr_dt); + } /* Check the CMGCRBase register is implemented */ if (!(read_c0_config() & MIPS_CONF_M)) - return 0; + return gcr_dt; if (!(read_c0_config2() & MIPS_CONF_M)) - return 0; + return gcr_dt; if (!(read_c0_config3() & MIPS_CONF3_CMGCR)) - return 0; + return gcr_dt; /* Read the address from CMGCRBase */ - cmgcr = read_c0_cmgcrbase(); - return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); + gcr_reg = read_c0_cmgcrbase(); + gcr_reg = (gcr_reg & MIPS_CMGCRF_BASE) << (36 - 32); + + /* If no of node, return straight away */ + if (!gcr_dt) + return gcr_reg; + + /* If the CMGCRBase mismatches with dt, remap it */ + if (gcr_reg != gcr_dt) { + pr_info("Remapping CMGCRBase from 0x%08lx to 0x%08lx\n", + gcr_reg, gcr_dt); + change_gcr_base(CM_GCR_BASE_GCRBASE, gcr_dt); + } + + return gcr_dt; } phys_addr_t __init __weak mips_cm_l2sync_phys_base(void)