From patchwork Wed May 8 13:13:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658719 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF5D178C96; Wed, 8 May 2024 13:13:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174024; cv=none; b=gc3lo2oShaY2il/rrtRps/lFyFxRLdWRxVeebCWFDBKr6EZ5DKjQQovUH4U/l13c9ZGPVfL09XYMx4z7jVDxjE25PxCmYyQkBaM89QfWI16ihfAcd5eU+7TfmaZoAC7XvpH1/JpA8aHJXWot2OULXGfuotmJO9k6QAFTrTa3mEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174024; c=relaxed/simple; bh=2auuQGe9uHpx39X2DRGeyL4wn09dTQhuOpMdAqllMYs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Acq7NJseUWNiISk1XjCFJuVIT1JEYWyq8u1nyRDTj19/QR1/+qM4A7V90aXSQmjVcw1hZvkDrPD5WHd0A9ZpNJV1Jy5NtifK+Al07ikWy3PyJCUzjKXP2vhAV9KDW2bXECPrzi1Ium8rbMaD16/1XFne0h4skZtXfdeIZdDTsJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CwzkjClH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CwzkjClH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 850E0C4DDE1; Wed, 8 May 2024 13:13:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174024; bh=2auuQGe9uHpx39X2DRGeyL4wn09dTQhuOpMdAqllMYs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CwzkjClHXS2d5QhMsgppKR03OvIWFg6CYCTxUtnhwTKezY+02/nsfs8bmhmla11dh d4gEEbHyM6ZXJGmNDks7II0mndljxHVEnTr6HCidUXkl6nM6Lz5ZYkZzQvGGyJlfTD 7i9n3lf/+6/Z/LlMtOiLaD1I4doW3NXchQYRggLfA//1jEo/6r1/2BKahV6bkOrlAT cbKtGeuI2+xRBUFNyxUw8Q6xomU4amA0QtYlElmXRnimDwI8ylVNpIazj1rfL8R+Km lKxIY9f2ZW5Gl/y+K0G/ogK/I5Nu8LU30WV3t0A9VUJNHIUjY3Kkh7QUh2G98ZQBfR Etav7CZT8cOug== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:32 +0200 Subject: [PATCH v3 01/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-1-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1296; i=cassel@kernel.org; h=from:subject:message-id; bh=2auuQGe9uHpx39X2DRGeyL4wn09dTQhuOpMdAqllMYs=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+qbmYu0U7pFd1ryXK+TFfFnf80WoVmu5MG7zXdG6 OY8NZaOUhYGMS4GWTFFFt8fLvuLu92nHFe8YwMzh5UJZAgDF6cATGSROCPDlV1Cc/acU5qcL7nt sHPMvjU3pidxyd5QKVO/F78jN+2xNsP/6HL9ouqjLV8WKM5a3+RisuuIvVjWkpJzT2/bnpqVkHm JBwA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the reg-name "apb" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use a different reg-name when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "apb" is already defined in snps,dw-pcie.yaml, add it also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index bbdb01d22848..00dec01f1f73 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -100,7 +100,7 @@ properties: for new bindings. oneOf: - description: See native 'elbi/app' CSR region for details. - enum: [ link, appl ] + enum: [ apb, link, appl ] - description: See native 'atu' CSR region for details. enum: [ atu_dma ] allOf: From patchwork Wed May 8 13:13:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658720 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECD8779DDB; Wed, 8 May 2024 13:13:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174029; cv=none; b=OzZrqHswlRTBIIYW2bjioQKqRtFbM/Ls9ejfKy91XiZ8yfXdtov5S6uocNF7H2qqADzyFo/cinAqtZCgknyztTFulsKvOlBl5TFo+R0M6B6qFGWQQISLAUx5vBT5sUA8k4k6WwwHHqEMicbLZDk57Zn3h10UaAZCLDK1WMEDnWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174029; c=relaxed/simple; bh=dazCN/iT/MHdY+ckymlAcfBjUpa3OmMTl+4+NDKJR2A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FzkjWZA3anDX9rImBsx8xHOFPyweRiZjJSRdOGnGmtIsPyxsyFMrv3UrY2+63jKIvXXG9g4CjYiyMwRET1ghElDZLLL/tbyCL6A3suK1gtc7nrydD+6PkROODW7GxsJh0buMw/CzfRFgEXX01fV5PRDPi7srJTGD8Av3gK0nw9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Pi4E4VIC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Pi4E4VIC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD70BC4AF67; Wed, 8 May 2024 13:13:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174028; bh=dazCN/iT/MHdY+ckymlAcfBjUpa3OmMTl+4+NDKJR2A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Pi4E4VIC6PlUKiRfH02y9WHAKtBRzIOB1Z33gdIKcmkXVBfeVoaoRHuyxHrGcSA7V k+cEWHlV7ewtslwfMtDB/n7uajEAwcdpJp64e67nh/QJUyvMncSd+RMOrs9JfefYcm WvoByh6cYGJilhWkPqkYLiLc+GjWGaBIiG9Yh7ibdrP2G68YsWI9yH90pAfqH7w8a+ nRW+0shdXXyo4+qf7IlqKyhJyqdeC5Z9V8uMxfmfBPoNGHjxB3WPwATDNc5YVc8nYj IYpeCHi7NTu/4iHcIeCGM53sOTg35BVgM3e2GHYB4SfsOHNxNO0bHtYYlyRbidcPrM 3+QFCTc1+BPdA== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:33 +0200 Subject: [PATCH v3 02/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-2-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1267; i=cassel@kernel.org; h=from:subject:message-id; bh=dazCN/iT/MHdY+ckymlAcfBjUpa3OmMTl+4+NDKJR2A=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+pXvTt3YIdE5EqO0pe37rbctkmxdruwZq+k01HHE 1tj7Ev0OkpZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjAROW5Ghj0ttxwYolOlU1Zc ZXv4xe67enyLR3/bg/lnJWd6bO7+Vs7IcKtAa8esN0HaHG9mKV4wTsnZ8WjSVCXx/Qc1NpyL9O9 UZAMA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the interrupt-names "sys", "pmc", "msg", "err" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use different interrupt-names when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "sys", "pmc", "msg", "err" are already defined in snps,dw-pcie.yaml, add them also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index 00dec01f1f73..f5f12cbc2cb3 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -156,7 +156,7 @@ properties: for new bindings. oneOf: - description: See native "app" IRQ for details - enum: [ intr ] + enum: [ intr, sys, pmc, msg, err ] max-functions: maximum: 32 From patchwork Wed May 8 13:13:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658721 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CDE678C93; Wed, 8 May 2024 13:13:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174033; cv=none; b=nPRKQd1G54aP/2rllf0xqKzkpJ0ERla982JwkVflNk0tTFAUpf5ScY/clcRNF+cr8jb2IQmQHcQ9R4e8NCyK3mGKqWZxmpjS6uv0hTXezbnwWNkJP2SNeCftS6cGMBdPe84mhIpRu0fzoSbzRm2fQ9nGEKYyHQR6xBIIhA212Vc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174033; c=relaxed/simple; bh=MgvdOL0gkl34L22gpJGsJpktQEWaY6MRdjg4t+pKTZ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hhN728Cb1FxV5OAYYRJ+gkFBiwhatLZypm080FB3giJJpBP1VBh5xR+6ou8vsGokDMMwdNeZ3WW9/NWU1mkHrqkRhW0KeNPLH0T8v1Ff48jpv+tA6Lq207mAHZP4oAJEiK06rsFF/X6ymrT2hyTNX/s4FqWvbEw/+c9PKxM02sY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MWp/ga5o; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MWp/ga5o" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 02497C4AF17; Wed, 8 May 2024 13:13:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174032; bh=MgvdOL0gkl34L22gpJGsJpktQEWaY6MRdjg4t+pKTZ4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MWp/ga5oYYhuhUuKZDoLkl/rFYoZag8NsD/mXlXNRnohf6K4fLhjIv2ZwEEMcZehI Hq28Y/GVHu0r1Y12YNx2w140fGNKW++aPLiEN5JgnFji+erhABO0be7JiPP7mtn11R TBog3YXMbmq+ku7tCuUIgc9T5eD2Nze3suHv63bW5juJwmc3bqBTKsdJ1Dl2c5CTCP A3fu6403yxPBLFTj8NktiRmTYa/OBMN2PbIlIQEOo1l2+J4buWab491QPMlv0Fpqj2 075dcTnI4mjXH1iswEoF200gjtcizHkHfaEZObi6xIPNPvOEGbHeH8jRYrfgTrJjl+ A3lQmGhIHUe+g== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:34 +0200 Subject: [PATCH v3 03/13] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-3-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1672; i=cassel@kernel.org; h=from:subject:message-id; bh=MgvdOL0gkl34L22gpJGsJpktQEWaY6MRdjg4t+pKTZ4=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+q7TFws30Rt9nm8izPnqOVq3SmGvZ3f1ylKb9l9M effPDbdjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEzkynJGhkn6x7VVf4avFxBJ nbaDa9ma1ueHuVfOuHfxhOke3tBIuceMDL9aP8+u3797x/x/rawf7wn/lti778z790s45RUmxsZ PusMHAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd that are triggered when the PCIe controller (when running in Endpoint mode) has sent an Assert_INTA Message to the upstream device. Some DWC controllers have these interrupt in a combined interrupt signal. Add the description of these interrupts to the device tree binding. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index f5f12cbc2cb3..f474b9e3fc7e 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -151,6 +151,15 @@ properties: Application-specific IRQ raised depending on the vendor-specific events basis. const: app + - description: + Interrupts triggered when the controller itself (in Endpoint mode) + has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to + the upstream device. + pattern: "^tx_int(a|b|c|d)$" + - description: + Combined interrupt signal raised when the controller has sent an + Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details. + const: legacy - description: Vendor-specific IRQ names. Consider using the generic names above for new bindings. From patchwork Wed May 8 13:13:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658722 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 257C778C93; Wed, 8 May 2024 13:13:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174037; cv=none; b=Cwwel2vaois1JcvTANh18dz8od91mfd55chEQG0J3oQoSGwgRvHsLWJuOHRFvg0C8ClnFMasrmaKYim0EBgBF+d6lMHG8cnVGhKfsSO2S0SvpgVeU/9/LVvWzIIQl3mAl9Qcce1Aze3DhkL1jrI7CuzimXXY4+CmjaGLrg33yZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174037; c=relaxed/simple; bh=wJEqN/IGNju/BykODknHNNFeERj3ha42TqllslHk/H0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JA89g+uPPjuPoHxlo/AHPazeXFMrBm/cZOHVyZq9RSnsguJyggZcOFigLWIbvOE6qHjuqpXgaIf07d+R1qerenP8N9rdZnUGDzwa37MlYAVB3WzzzlsKX/8JczVzzpu8RsiEUZqL1i0onKUHL6sPkLmBcFvfgxPamshjjKgGebA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D0hNHpR4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D0hNHpR4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3CA09C4DDE0; Wed, 8 May 2024 13:13:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174037; bh=wJEqN/IGNju/BykODknHNNFeERj3ha42TqllslHk/H0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=D0hNHpR4aVX8YWJs/eZNO9Xk5ktGrBbUpmaJMBr1mcU20yH5O65n8aB2rsfek5QmS l7+rAddnuzZGVFK9iwHaH99RlBp+97Z666harhIHLgPjhCsw5HeSwETcjxHRRrB1pw ezfFe/0xGS4w+TPm8ngHme3PjHPlc5j/TF7Ra6MqitCxgGOsqk+htNcc4/NpGDqOSJ d6w9KbtxC0qx+dU5ioRAdZ+Fnh8vrFHXGQLTFVnzbwwtercJG9g7mOA62wHY+ROEyD +hO43NdRb123E3+iFnwVvjs1NVwnFEF4gGmBqPoBAPQ/lspXQrpvhoH9AqK7s+7QIG f4wyJ5iZvRdKA== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:35 +0200 Subject: [PATCH v3 04/13] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-4-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8069; i=cassel@kernel.org; h=from:subject:message-id; bh=wJEqN/IGNju/BykODknHNNFeERj3ha42TqllslHk/H0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+qXc+zMv/qQKZzB/pL+rzyuedJ/495+Kr5R/VtY3 tEnyWxRRykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACbiEc7I0CodY7FHz7mtuNR+ W4O5ztLJZ6QnBlm+aJF+dvstp6tSO8P/4kkM88rm+b4xM/eKPMpgLbJ/u+6xwN2xsybaMpn0GFk wAgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Refactor the rockchip-dw-pcie binding to move generic properties to a new rockchip-dw-pcie-common binding that can be shared by both RC and EP mode. No functional change intended. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 111 +++++++++++++++++++++ .../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 93 +---------------- 2 files changed, 114 insertions(+), 90 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml new file mode 100644 index 000000000000..60d190a77580 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe RC/EP controller on Rockchip SoCs + +maintainers: + - Shawn Lin + - Simon Xue + - Heiko Stuebner + +description: |+ + Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip + SoCs. + +properties: + clocks: + minItems: 5 + items: + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + - description: AHB clock for PCIe dbi + - description: APB clock for PCIe + - description: Auxiliary clock for PCIe + - description: PIPE clock + - description: Reference clock for PCIe + + clock-names: + minItems: 5 + items: + - const: aclk_mst + - const: aclk_slv + - const: aclk_dbi + - const: pclk + - const: aux + - const: pipe + - const: ref + + interrupts: + items: + - description: + Combined system interrupt, which is used to signal the following + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app + - description: + Combined PM interrupt, which is used to signal the following + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, + linkst_out_l0s, pm_dstate_update + - description: + Combined message interrupt, which is used to signal the following + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active + - description: + Combined legacy interrupt, which is used to signal the following + interrupts - inta, intb, intc, intd + - description: + Combined error interrupt, which is used to signal the following + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, + nf_err_rx, f_err_rx, radm_qoverflow + + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + oneOf: + - const: pipe + - items: + - const: pwr + - const: pipe + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - num-lanes + - phys + - phy-names + - power-domains + - resets + - reset-names + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 5f719218c472..550d8a684af3 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: DesignWare based PCIe controller on Rockchip SoCs +title: DesignWare based PCIe Root Complex controller on Rockchip SoCs maintainers: - Shawn Lin @@ -12,12 +12,13 @@ maintainers: - Heiko Stuebner description: |+ - RK3568 SoC PCIe host controller is based on the Synopsys DesignWare + RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# properties: compatible: @@ -40,61 +41,6 @@ properties: - const: apb - const: config - clocks: - minItems: 5 - items: - - description: AHB clock for PCIe master - - description: AHB clock for PCIe slave - - description: AHB clock for PCIe dbi - - description: APB clock for PCIe - - description: Auxiliary clock for PCIe - - description: PIPE clock - - description: Reference clock for PCIe - - clock-names: - minItems: 5 - items: - - const: aclk_mst - - const: aclk_slv - - const: aclk_dbi - - const: pclk - - const: aux - - const: pipe - - const: ref - - interrupts: - items: - - description: - Combined system interrupt, which is used to signal the following - interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, - hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, - edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app - - description: - Combined PM interrupt, which is used to signal the following - interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, - linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, - linkst_out_l0s, pm_dstate_update - - description: - Combined message interrupt, which is used to signal the following - interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, - pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - - description: - Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd - - description: - Combined error interrupt, which is used to signal the following - interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, - tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, - nf_err_rx, f_err_rx, radm_qoverflow - - interrupt-names: - items: - - const: sys - - const: pmc - - const: msg - - const: legacy - - const: err - legacy-interrupt-controller: description: Interrupt controller node for handling legacy PCI interrupts. type: object @@ -119,47 +65,14 @@ properties: msi-map: true - num-lanes: true - - phys: - maxItems: 1 - - phy-names: - const: pcie-phy - - power-domains: - maxItems: 1 - ranges: minItems: 2 maxItems: 3 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - oneOf: - - const: pipe - - items: - - const: pwr - - const: pipe - vpcie3v3-supply: true required: - - compatible - - reg - - reg-names - - clocks - - clock-names - msi-map - - num-lanes - - phys - - phy-names - - power-domains - - resets - - reset-names unevaluatedProperties: false From patchwork Wed May 8 13:13:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658723 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB6397CF1D; Wed, 8 May 2024 13:14:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174041; cv=none; b=kKSGeN8UTbR9KYQDi0dEn2/cmzCwY+jCspEL6jKlnydwBxL9IiwjRrI+l/kM+9MMYb8Xn9ljR0Oqx9w3eZdXgQMosqASjDArMCLdY6jxA92b2kyzp3WL6Hr+nfRmnT77hX2fM3BNT4Rg2A1Fh7G9lFGFZtTYE2hjBIO2a9atNpE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174041; c=relaxed/simple; bh=YpLt9USx5MURRWMvfXQdjc9NJxoYWfsGJds9NsR6Umk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZrINFViXnaNaUMtARwwPY7MI+shROtl3C+8nS+PuG0YSClia7UVexJ6E4J28PrXRxvzBKtqVfE+CpTr0dj8vqfZLmKo25KRmgQm5WjDAXQKmkM9UHAfXmvh+CX+qGVr7G3rRP11Mxc3ZT+GqFTm2/deVmkQsjJ3w9rgIIkoBxlc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=H0wYh7Ka; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="H0wYh7Ka" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7493FC4DDE4; Wed, 8 May 2024 13:13:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174041; bh=YpLt9USx5MURRWMvfXQdjc9NJxoYWfsGJds9NsR6Umk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=H0wYh7KaCRrAG+cKWahvCLwp79Q2AGVnlROAOVO2eyLg9sENMMfpgUZGOD2Zy2EZb HBnkgjcXNZmZo8wifh+dBMte4SP61q+yvbn0IpX5GVlblmNkXl2Zxi/3M+EshVLCND rnKHXcvWiy8gVDYbqrk0xKFV/EhjaV8smNaQOCTd/4fNABVaMxkJZAQU9cpkgbadGE lVrzahZ1wNtMDo9UlcKurlT+v/CxUdscIxFres0grmzIQn39uwSOGy2BTVgaZWrYIK eoVU+o8vAN/QPSO6qi7sSqvwKV16rVCdqp0tJdlCB3WPxTDvyteEhGcQL58lnDKjSw J9yFaadk8wHOg== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:36 +0200 Subject: [PATCH v3 05/13] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-5-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1950; i=cassel@kernel.org; h=from:subject:message-id; bh=YpLt9USx5MURRWMvfXQdjc9NJxoYWfsGJds9NsR6Umk=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+r99xff/v4yIuJXplz1RMOjJesWS6wu8r6i0DU3b E3N8ds2HSUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZjI63SG747LeL5oWlZdNjZd N/eI5dIHgg/WZPodDVtz2tlgl4rRVkaGF8Epy/UNDV41itmF/W7xmdT3b++rPqbVE/OOJ5c5Chx gBQA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The descriptions of the combined interrupt signals (level1) mention all the lower interrupt signals (level2) for each combined interrupt, regardless if the lower (level2) signal is RC or EP specific. E.g. the description of "Combined system interrupt" includes rbar_update, which is EP specific, and the description of "Combined message interrupt" includes obff_idle, obff_obff, obff_cpu_active, which are all EP specific. The only exception is the "Combined legacy interrupt", which for some reason does not provide an exhaustive list of the lower (level2) signals. Add the missing lower interrupt signals: tx_inta, tx_intb, tx_intc, and tx_intd for the "Combined legacy interrupt", as per the rk3568 and rk3588 Technical Reference Manuals, such that the descriptions of the combined interrupt signals are consistent. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index 60d190a77580..ec5e6a3d048e 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -56,7 +56,8 @@ properties: pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - description: Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd + interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc, + tx_intd - description: Combined error interrupt, which is used to signal the following interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, From patchwork Wed May 8 13:13:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658724 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA8D678C93; Wed, 8 May 2024 13:14:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174046; cv=none; b=IejmYEDcWt98O9Vb7gtoFXR64EH2hQ8342a1skEPLFfwVu0xW10b/cKDX+cPMwupbb4GmlvHUy6UPK9OQtt84kBpW3nbkFK7yTohi6gIIbtx3SnMKFsdPJ9WDkRxRsULc2h+xEBS+AHzu7J1BmlsVn+WpnJt5HQJQWUNRZvL6yI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174046; c=relaxed/simple; bh=a8pOODpzbTzj+peyc7fdoQaLOJmTFE1MbIu3A7gppK0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xec+1ZtjoxtbXip+n9/5QZHi2pVBLztj15lFxveNgFurmmIfomiEEsE7XWj75DOhF4f1aZC1JcCBmI9LqOZDQ4FeOEeJ8DrFG8VU3hotVYUNTQzG8uhUziqfgkp63A9zQQihakS/YhB6L7O2SsaNxCCDRNJAHkxoNGColGCPVxk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vktt/yrI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vktt/yrI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AD9DBC113CC; Wed, 8 May 2024 13:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174045; bh=a8pOODpzbTzj+peyc7fdoQaLOJmTFE1MbIu3A7gppK0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Vktt/yrIRb+w57yK1TOUCi7rIqMxLAswuWCuG3RJnyldv4h96z9XngR9eERN3JQZp zCrpHzgBY2neE82YwYP9yUUoK+HzLjS3ueVGwCgBvF3430D8gDDGeJ3u1V192GXpw6 gRH4JNa3tHlFkOQddcxlpSFtjsJqAzfAriSbFHhNBeT5bUQkVI9yGDRJR9sOYay/NF Zmm5OxiFEZJLft/G98hra3gH3wQRi3K8y9pwOtbuXCQhjiMFdt0WLntupadfAgYEJj SsFEzKgyOxiion42kYtWE+vLsXlPVWrg/8D0NrMqh82ffEhFvXDoJI9TabuFpj6zJH FGiyXZjCkARvQ== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:37 +0200 Subject: [PATCH v3 06/13] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-6-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5534; i=cassel@kernel.org; h=from:subject:message-id; bh=a8pOODpzbTzj+peyc7fdoQaLOJmTFE1MbIu3A7gppK0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+oLEl/zvyoO0X82l3l9eXNTq1Qf04fcrxuilorod K1YJ23WUcrCIMbFICumyOL7w2V/cbf7lOOKd2xg5rAygQxh4OIUgImwX2D4n7sw92bTqRxmibIi 82erDXgO5n74OkdgWUZMJeeWE7/aYxgZtn56e61Lf8YjtSX8TlsWn/+3bpHxe5euDu20gPYztz/ 7MgMA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 14 ++++ .../bindings/pci/rockchip-dw-pcie-ep.yaml | 95 ++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index ec5e6a3d048e..cc9adfc7611c 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -39,6 +39,7 @@ properties: - const: ref interrupts: + minItems: 5 items: - description: Combined system interrupt, which is used to signal the following @@ -63,14 +64,27 @@ properties: interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow + - description: + eDMA write channel 0 interrupt + - description: + eDMA write channel 1 interrupt + - description: + eDMA read channel 0 interrupt + - description: + eDMA read channel 1 interrupt interrupt-names: + minItems: 5 items: - const: sys - const: pmc - const: msg - const: legacy - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 num-lanes: true diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml new file mode 100644 index 000000000000..e0c8668afc01 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe Endpoint controller on Rockchip SoCs + +maintainers: + - Niklas Cassel + +description: |+ + RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# + +properties: + compatible: + enum: + - rockchip,rk3568-pcie-ep + - rockchip,rk3588-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Data Bus Interface (DBI) shadow registers + - description: Rockchip designed configuration registers + - description: Memory region used to map remote RC address space + - description: Address Translation Unit (ATU) registers + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: apb + - const: addr_space + - const: atu + +required: + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + }; + }; +... From patchwork Wed May 8 13:13:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658725 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FC6E6A338; Wed, 8 May 2024 13:14:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174050; cv=none; b=beblYFGcyiizsI8mkSPHyGdhGYO3YedfSE2cbPyu3Q5jW2sjDv69nvRDy/fkCvcaNhgWmYBehyBbuBR0uG2AX3c7XYZc8pIsscKFzfn20EH9TrLFOyPg8UycJE7bEkV1qYHoMxXKuiBwLYSCzS8qwFreDY/i6pMFW/rbHCtcx9Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174050; c=relaxed/simple; bh=zij3IqGLZejzZqkbvWLGGDEZbugER7QuKFOEIkUZjb0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YZgKYnszX20CNMfSQCb4gHuB6dVXghw6KCVVGOo+EHqSkXFHjYFuSx74WKHkrWPh+nFYXtCfgGJrYuOY/8Y1dBlTVUajkjazkoAXLz3utK7pf3bKkjDyFcnwIMJ36n62s+Pzxk1xdpcYOj7zEdS38h7jlTN5m0diF30Pnh3GKvo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GLprvzBP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GLprvzBP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E61B0C3277B; Wed, 8 May 2024 13:14:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174049; bh=zij3IqGLZejzZqkbvWLGGDEZbugER7QuKFOEIkUZjb0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GLprvzBPoV0oAu11Is8QP+AZVk2wFkQF8KHhN2jPTqLr0FcnWQ3Pqf4tU+K4urzOD +LBVD+VhEPxCWVD53avw/BqIz6o0x5cwMo3cVoeYVZdTLIU6shElCrbhcpAGJ4JVMh 8vFVlOqW+aT0ix5LtEaWx/lzIQTOnaxg3ViI7ClPBCPihBO9e/se2E/BFTV3+OzjBF Ji5WEhep+OAdeERMYbJLokborErGlsTWmv+ZMOe4eTGiWDMtLKfDGFggTH4fax85Te 2hR26C7xcCg0VR7kB2PBku2YmXURnmvJe0LYRZmak5/tlGtxDvY+FatHf+oWyAOSZn qRLG0heB/eEWg== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:38 +0200 Subject: [PATCH v3 07/13] PCI: dw-rockchip: Fix weird indentation Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-7-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1187; i=cassel@kernel.org; h=from:subject:message-id; bh=zij3IqGLZejzZqkbvWLGGDEZbugER7QuKFOEIkUZjb0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+onGig/ebujIUVOotn2Q756Tgd7/5fbUz4J8VzLO HGnlzOyo5SFQYyLQVZMkcX3h8v+4m73KccV79jAzGFlAhnCwMUpABPprWNkaHetORKhryt4yXe7 zQTOFMWYexkqRm6XK4sUb65feczpNyPDjsux0nH97Zdt727xmiuYaXtFW2bRqpnzHeNLJi4Xu5L DCQA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Fix the indentation of rockchip_pcie_{readl,writel}_apb() parameters to match the opening parenthesis. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index d6842141d384..1993c430b90c 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -60,14 +60,13 @@ struct rockchip_pcie { struct irq_domain *irq_domain; }; -static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, - u32 reg) +static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg) { return readl_relaxed(rockchip->apb_base + reg); } -static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, - u32 val, u32 reg) +static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val, + u32 reg) { writel_relaxed(val, rockchip->apb_base + reg); } From patchwork Wed May 8 13:13:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658726 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E5116A8A6; Wed, 8 May 2024 13:14:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174054; cv=none; b=FQQPMXchinh71CCyDARvVpBfQAn2zKzOBzbQFDlel2AVkYqzn+3/YAp5cB2FVUM6H/w4Hx6zpidsitid/OB55ZLimAb3ibf/qGPDFtGGHsz6cuLEBMz46hFIMRL2hMonWYSyeib9AZrTZrvW1MOndY8v9HM24eSVYqyW6C+2PEg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174054; c=relaxed/simple; bh=KjWl1JIkPYpwTbCHiK+X6uD304vyVCxgjTUQh/FZ8VQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KSPYPEz+0DMMXziDWyiQ1v/+5KDpONebOFkcFMLsPqMV1SDIEWy7+CiVkpgzajLuflqrMn4q9NOelfryUGbFu0d2WIC/uHOzkfRqBWWbSkVASL2eU9ybYSPoSiTWrVZ53V/ZIy8ZV6B6QnajrW/ISaMZteJVjqnXWjlaK+LLDTo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IHn57ocs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IHn57ocs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2A1E2C4AF18; Wed, 8 May 2024 13:14:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174053; bh=KjWl1JIkPYpwTbCHiK+X6uD304vyVCxgjTUQh/FZ8VQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=IHn57ocstpd54cLclBPMY39ZzBo8WFq6ybv73maNAwKmjY5aAKpT71jkYnqEKeQvK iUwUJ0E/brCpqBpIDDE8znwSfQfbQwBmKorNhJ3SVdmp3RB7kmwOylJDDSTUKpNCp8 e16QK/vXLNWD96ChzJB9Pz6DKDxFRDB4yJJTNb9DltRPLXUfaEE81Va+ijUAdDjoU/ gNfgdZw5PXrJn8MHOiLkkI70t6M/A/U2X7+8K/iNJfQFke6TABfeI/KLLO3CcztO+r JAK81eLq34aqETle8tv5K1Jg11X9EOJ8hBB5ZDZCI8q6MIr3ruCL3lmdtqnoqAig0t 6VlWYY6nayMiA== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:39 +0200 Subject: [PATCH v3 08/13] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-8-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1426; i=cassel@kernel.org; h=from:subject:message-id; bh=KjWl1JIkPYpwTbCHiK+X6uD304vyVCxgjTUQh/FZ8VQ=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+pf3pnzwPfPLnl9845TN/a2dP5Rnyzr437mcFe7s 5S7S9qijlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEyk8AHD/8B9+j5cp3oM4755 +sVufHEn07xav1RSMCEg9S6DQq/HG0aGF6s3/LnzvGNG8NTyci9POwOJOY0Jh+d2nYjXTd/xpEC eFQA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add a rockchip_pcie_ltssm() helper function that reads the LTSSM status. This helper will be used in additional places in follow-up commits. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 1993c430b90c..2a70326cc0bc 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -143,6 +143,11 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) return 0; } +static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip) +{ + return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS); +} + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, @@ -152,7 +157,7 @@ static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) static int rockchip_pcie_link_up(struct dw_pcie *pci) { struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); - u32 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS); + u32 val = rockchip_pcie_get_ltssm(rockchip); if ((val & PCIE_LINKUP) == PCIE_LINKUP && (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY) From patchwork Wed May 8 13:13:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658727 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 452BD59158; Wed, 8 May 2024 13:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174058; cv=none; b=hiDvUU8u5lL+ncs3OfaoAtdXcsu3bySEsOV1UQt4AOZogBH3hSogW7fZRtX7g87pl4w8jNw6qWOG+WiDedCfqVnr9CmnMFPziMHnzkCvMIpjCgmUTH86q+SsYqK+/9qzdpgk4s8OQ12N0TilLc6FGsmkL5iy5scRq0JspiEUO+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174058; c=relaxed/simple; bh=59kFpa6ALdPCnEsQbbSRjoY4cwSouyaqunrcUlCZnSs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sD6dEtK88mtSM9K6/4y9VmF7iel0ntLNXC55mqIGM8vOsH/X0BVZ+FL2Sra7GLCtENyvaRqIdzv3pytPd9pE03jkuPnZUztJReJTG53V0l7z0PBqz64A0CqREKiYQ8eN2TbErfALJEgrO47bJvluj1mWTvrfs064sMxW5yRbLmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LJNvrddb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LJNvrddb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61C96C113CC; Wed, 8 May 2024 13:14:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174058; bh=59kFpa6ALdPCnEsQbbSRjoY4cwSouyaqunrcUlCZnSs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LJNvrddbW3WjR20oW37Vi2I9PS/0PPHvqa3ludqYvGCvJj9QSdSehfXcKcQrb37my BFICMtH8A9SwCbJbXyVYGHB7ejDXCCydvqhSI1gA81YHt37CeUvUqUmlf7dn5d0jUS wtZNUgv7U1WeLQy48EZqSoxiHGYEGWCI1tm1LPO3UqwsCPGYZ2R4Vla0Itu2Jp7OEf GJUybLzOiaeLYdmtbuxf/tTButy9lfhyOJl0O5vGbf+1NYDx/Dhrp7YW9GqzIERBAq Q2EoZxDVYXfDGJ7EF9AGysQdtRV499MsRMcvgrvr/lP/JFVUvZ48mhAIIpv0VU081k g2sPF45FbJ4bA== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:40 +0200 Subject: [PATCH v3 09/13] PCI: dw-rockchip: Refactor the driver to prepare for EP mode Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-9-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4770; i=cassel@kernel.org; h=from:subject:message-id; bh=59kFpa6ALdPCnEsQbbSRjoY4cwSouyaqunrcUlCZnSs=; b=kA0DAAoWyWQxo5nGTXIByyZiAGY7en+h5bfUWCxs6quy4NoAF8nr8mDGpzKJVKFiuiMqzeYKi Yh1BAAWCgAdFiEETfhEv3OLR5THIdw8yWQxo5nGTXIFAmY7en8ACgkQyWQxo5nGTXLE4AD+KKy9 bsBL4dMFp1VbGzwBKAeqcY5dYaWBSVM91slqJC8BAIz6tZANn/Vjwd1IvbTtcYVn1socgobMoEd xwTTdqt4N X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA This refactors the driver to prepare for EP mode. Add of-match data to the existing compatible, and explicitly define it as DW_PCIE_RC_TYPE. This way, we will be able to add EP mode in a follow-up commit in a much less intrusive way, which makes the follup-up commit much easier to review. No functional change intended. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 84 +++++++++++++++++++-------- 1 file changed, 60 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 2a70326cc0bc..3c2e012e3e91 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -49,15 +49,20 @@ #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) struct rockchip_pcie { - struct dw_pcie pci; - void __iomem *apb_base; - struct phy *phy; - struct clk_bulk_data *clks; - unsigned int clk_cnt; - struct reset_control *rst; - struct gpio_desc *rst_gpio; - struct regulator *vpcie3v3; - struct irq_domain *irq_domain; + struct dw_pcie pci; + void __iomem *apb_base; + struct phy *phy; + struct clk_bulk_data *clks; + unsigned int clk_cnt; + struct reset_control *rst; + struct gpio_desc *rst_gpio; + struct regulator *vpcie3v3; + struct irq_domain *irq_domain; + const struct rockchip_pcie_of_data *data; +}; + +struct rockchip_pcie_of_data { + enum dw_pcie_device_mode mode; }; static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg) @@ -195,7 +200,6 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); struct device *dev = rockchip->pci.dev; - u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); int irq, ret; irq = of_irq_get_byname(dev->of_node, "legacy"); @@ -209,12 +213,6 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler, rockchip); - /* LTSSM enable control mode */ - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); - - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, - PCIE_CLIENT_GENERAL_CONTROL); - return 0; } @@ -288,13 +286,35 @@ static const struct dw_pcie_ops dw_pcie_ops = { .start_link = rockchip_pcie_start_link, }; +static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip) +{ + struct dw_pcie_rp *pp; + u32 val; + + /* LTSSM enable control mode */ + val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, + PCIE_CLIENT_GENERAL_CONTROL); + + pp = &rockchip->pci.pp; + pp->ops = &rockchip_pcie_host_ops; + + return dw_pcie_host_init(pp); +} + static int rockchip_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct rockchip_pcie *rockchip; - struct dw_pcie_rp *pp; + const struct rockchip_pcie_of_data *data; int ret; + data = of_device_get_match_data(dev); + if (!data) + return -EINVAL; + rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL); if (!rockchip) return -ENOMEM; @@ -303,9 +323,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev) rockchip->pci.dev = dev; rockchip->pci.ops = &dw_pcie_ops; - - pp = &rockchip->pci.pp; - pp->ops = &rockchip_pcie_host_ops; + rockchip->data = data; ret = rockchip_pcie_resource_get(pdev, rockchip); if (ret) @@ -342,10 +360,21 @@ static int rockchip_pcie_probe(struct platform_device *pdev) if (ret) goto deinit_phy; - ret = dw_pcie_host_init(pp); - if (!ret) - return 0; + switch (data->mode) { + case DW_PCIE_RC_TYPE: + ret = rockchip_pcie_configure_rc(rockchip); + if (ret) + goto deinit_clk; + break; + default: + dev_err(dev, "INVALID device type %d\n", data->mode); + ret = -EINVAL; + goto deinit_clk; + } + + return 0; +deinit_clk: clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); deinit_phy: rockchip_pcie_phy_deinit(rockchip); @@ -356,8 +385,15 @@ static int rockchip_pcie_probe(struct platform_device *pdev) return ret; } +static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = { + .mode = DW_PCIE_RC_TYPE, +}; + static const struct of_device_id rockchip_pcie_of_match[] = { - { .compatible = "rockchip,rk3568-pcie", }, + { + .compatible = "rockchip,rk3568-pcie", + .data = &rockchip_pcie_rc_of_data_rk3568, + }, {}, }; From patchwork Wed May 8 13:13:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658728 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D09B48286F; Wed, 8 May 2024 13:14:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174062; cv=none; b=E5LtvO2soX5gVHFq9mDZQUOdkfFXWNuudeLmEujtSmqqDF88ZADDAKb1jv9kmyvMBD8VyUgAnG/8VjQUdgWP07WMiWz/tFg9TBJSd4uQW3A3NolYm9x4WSbFdohvhKl87yqbavcyf0tywBIFIkg5lH/t/T0NqhKc+PiZJY3r7B8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174062; c=relaxed/simple; bh=QYrAlRFQl9OfrVkr1R4fFgfw/9cDmg0C//OE6N9TnD4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YG+FpzFWjlwaehGzr8QQg6JU+A0oXPphjm5ccTQaf2UgPvhlTFpVUxWgqzy5V3Wpxu3RBWzovBS1UXTXrf43OepaTRi2m6I2OX4Onv+KnU9aeF0261v++SbMwcc3uw3Avi9vGvjNqUGxoWdy0VAZ0X6FU9AXcSrtR9NQsnUzONs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F78Gc4rc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F78Gc4rc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99B58C4AF66; Wed, 8 May 2024 13:14:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174062; bh=QYrAlRFQl9OfrVkr1R4fFgfw/9cDmg0C//OE6N9TnD4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=F78Gc4rcOyHaXUu5PvEF9BGRksFxDBuIyOzq37Pqus4nPER/m70j0d/qZfvxHKSFS v4uzNFSJPdyWGVLWm15TlY39XckCeKZ3o0sysrKQ333Zh41WxFIosUqcsuGNIR8LJk NutgkSsQIbmfAfKI4Nq4FtCAQ4kNBrrBZ2c6jsdroIq+qAR9jtpG0hVRBGzNgkEYTf HN+YxryqrdhqA5q/5jEpe2zl++C9I9FBWqsaV6qc160U4ABHsv79hQdeBszQ+iclCs NfTpCC792Mdb1OmNNowS5isry6mUe3MNBRUEMePkXAQjp5SqphuSnv5OO1DzYz9hPB EUCoV/nDr9aIA== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:41 +0200 Subject: [PATCH v3 10/13] PCI: dw-rockchip: Add endpoint mode support Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-10-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11300; i=cassel@kernel.org; h=from:subject:message-id; bh=QYrAlRFQl9OfrVkr1R4fFgfw/9cDmg0C//OE6N9TnD4=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+qjJx64fsNlwcy2BL97v4M+rv/Oxn6veUXtkh11E mxTMthndpSyMIhxMciKKbL4/nDZX9ztPuW44h0bmDmsTCBDGLg4BWAiG/4xMiwr4HMoXZy5LGbh Cy9HVz/WUwmX5RcdTd0/a/HL2xsbGCoZGT4rPfj+7N+Gr/vyucWi7h5xiDnVvHR+wuk9TFads93 7AxkA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The PCIe controller in rk3568 and rk3588 can operate in endpoint mode. This endpoint mode support heavily leverages the existing code in pcie-designware-ep.c. Add support for endpoint mode to the existing pcie-dw-rockchip glue driver. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/Kconfig | 17 ++- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 210 ++++++++++++++++++++++++++ 2 files changed, 224 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 8afacc90c63b..9fae0d977271 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -311,16 +311,27 @@ config PCIE_RCAR_GEN4_EP SoCs. To compile this driver as a module, choose M here: the module will be called pcie-rcar-gen4.ko. This uses the DesignWare core. +config PCIE_ROCKCHIP_DW + bool + config PCIE_ROCKCHIP_DW_HOST - bool "Rockchip DesignWare PCIe controller" - select PCIE_DW + bool "Rockchip DesignWare PCIe controller (host mode)" select PCIE_DW_HOST depends on PCI_MSI depends on ARCH_ROCKCHIP || COMPILE_TEST depends on OF help Enables support for the DesignWare PCIe controller in the - Rockchip SoC except RK3399. + Rockchip SoC (except RK3399) to work in host mode. + +config PCIE_ROCKCHIP_DW_EP + bool "Rockchip DesignWare PCIe controller (endpoint mode)" + select PCIE_DW_EP + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on OF + help + Enables support for the DesignWare PCIe controller in the + Rockchip SoC (except RK3399) to work in endpoint mode. config PCI_EXYNOS tristate "Samsung Exynos PCIe controller" diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 3c2e012e3e91..c93c620f8b28 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -34,10 +34,16 @@ #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) #define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) #define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) +#define PCIE_CLIENT_INTR_STATUS_MISC 0x10 +#define PCIE_CLIENT_INTR_MASK_MISC 0x24 #define PCIE_SMLH_LINKUP BIT(16) #define PCIE_RDLH_LINKUP BIT(17) #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) #define PCIE_L0S_ENTRY 0x11 #define PCIE_CLIENT_GENERAL_CONTROL 0x0 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 @@ -63,6 +69,7 @@ struct rockchip_pcie { struct rockchip_pcie_of_data { enum dw_pcie_device_mode mode; + const struct pci_epc_features *epc_features; }; static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg) @@ -159,6 +166,12 @@ static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) PCIE_CLIENT_GENERAL_CONTROL); } +static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip) +{ + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM, + PCIE_CLIENT_GENERAL_CONTROL); +} + static int rockchip_pcie_link_up(struct dw_pcie *pci) { struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); @@ -195,6 +208,13 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci) return 0; } +static void rockchip_pcie_stop_link(struct dw_pcie *pci) +{ + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + + rockchip_pcie_disable_ltssm(rockchip); +} + static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -220,6 +240,82 @@ static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { .init = rockchip_pcie_host_init, }; +static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar; + + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) + dw_pcie_ep_reset_bar(pci, bar); +}; + +static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + unsigned int type, u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_IRQ_INTX: + return dw_pcie_ep_raise_intx_irq(ep, func_no); + case PCI_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + case PCI_IRQ_MSIX: + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + } + + return 0; +} + +static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = { + .linkup_notifier = true, + .msi_capable = true, + .msix_capable = true, + .align = SZ_64K, + .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, +}; + +/* + * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of + * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver, + * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by + * default.) If the host could write to BAR4, the iATU settings (for all other + * BARs) would be overwritten, resulting in (all other BARs) no longer working. + */ +static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { + .linkup_notifier = true, + .msi_capable = true, + .msix_capable = true, + .align = SZ_64K, + .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_4] = { .type = BAR_RESERVED, }, + .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, +}; + +static const struct pci_epc_features * +rockchip_pcie_get_features(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + + return rockchip->data->epc_features; +} + +static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = { + .init = rockchip_pcie_ep_init, + .raise_irq = rockchip_pcie_raise_irq, + .get_features = rockchip_pcie_get_features, +}; + static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->pci.dev; @@ -284,13 +380,47 @@ static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip) static const struct dw_pcie_ops dw_pcie_ops = { .link_up = rockchip_pcie_link_up, .start_link = rockchip_pcie_start_link, + .stop_link = rockchip_pcie_stop_link, }; +static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg) +{ + struct rockchip_pcie *rockchip = arg; + struct dw_pcie *pci = &rockchip->pci; + struct device *dev = pci->dev; + u32 reg, val; + + reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); + + dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg); + dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip)); + + if (reg & PCIE_LINK_REQ_RST_NOT_INT) { + dev_dbg(dev, "hot reset or link-down reset\n"); + dw_pcie_ep_linkdown(&pci->ep); + } + + if (reg & PCIE_RDLH_LINK_UP_CHGED) { + val = rockchip_pcie_get_ltssm(rockchip); + if ((val & PCIE_LINKUP) == PCIE_LINKUP) { + dev_dbg(dev, "link up\n"); + dw_pcie_ep_linkup(&pci->ep); + } + } + + rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); + + return IRQ_HANDLED; +} + static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip) { struct dw_pcie_rp *pp; u32 val; + if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST)) + return -ENODEV; + /* LTSSM enable control mode */ val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); @@ -304,6 +434,63 @@ static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip) return dw_pcie_host_init(pp); } +static int rockchip_pcie_configure_ep(struct platform_device *pdev, + struct rockchip_pcie *rockchip) +{ + struct device *dev = &pdev->dev; + int irq, ret; + u32 val; + + if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP)) + return -ENODEV; + + irq = platform_get_irq_byname(pdev, "sys"); + if (irq < 0) { + dev_err(dev, "missing sys IRQ resource\n"); + return irq; + } + + ret = devm_request_threaded_irq(dev, irq, NULL, + rockchip_pcie_ep_sys_irq_thread, + IRQF_ONESHOT, "pcie-sys", rockchip); + if (ret) { + dev_err(dev, "failed to request PCIe sys IRQ\n"); + return ret; + } + + /* LTSSM enable control mode */ + val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE, + PCIE_CLIENT_GENERAL_CONTROL); + + rockchip->pci.ep.ops = &rockchip_pcie_ep_ops; + rockchip->pci.ep.page_size = SZ_64K; + + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + + ret = dw_pcie_ep_init(&rockchip->pci.ep); + if (ret) { + dev_err(dev, "failed to initialize endpoint\n"); + return ret; + } + + ret = dw_pcie_ep_init_registers(&rockchip->pci.ep); + if (ret) { + dev_err(dev, "failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(&rockchip->pci.ep); + return ret; + } + + dw_pcie_ep_init_notify(&rockchip->pci.ep); + + /* unmask DLL up/down indicator and hot reset/link-down reset */ + rockchip_pcie_writel_apb(rockchip, 0x60000, PCIE_CLIENT_INTR_MASK_MISC); + + return ret; +} + static int rockchip_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -366,6 +553,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev) if (ret) goto deinit_clk; break; + case DW_PCIE_EP_TYPE: + ret = rockchip_pcie_configure_ep(pdev, rockchip); + if (ret) + goto deinit_clk; + break; default: dev_err(dev, "INVALID device type %d\n", data->mode); ret = -EINVAL; @@ -389,11 +581,29 @@ static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = { .mode = DW_PCIE_RC_TYPE, }; +static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = { + .mode = DW_PCIE_EP_TYPE, + .epc_features = &rockchip_pcie_epc_features_rk3568, +}; + +static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = { + .mode = DW_PCIE_EP_TYPE, + .epc_features = &rockchip_pcie_epc_features_rk3588, +}; + static const struct of_device_id rockchip_pcie_of_match[] = { { .compatible = "rockchip,rk3568-pcie", .data = &rockchip_pcie_rc_of_data_rk3568, }, + { + .compatible = "rockchip,rk3568-pcie-ep", + .data = &rockchip_pcie_ep_of_data_rk3568, + }, + { + .compatible = "rockchip,rk3588-pcie-ep", + .data = &rockchip_pcie_ep_of_data_rk3588, + }, {}, }; From patchwork Wed May 8 13:13:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658729 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 151FE6FE2A; Wed, 8 May 2024 13:14:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174067; cv=none; b=SnVZUqtL5woS6xdHbHV81yaobCmseaudxzbsHfVqU/ZcyaaFiV6WBcVckCI/vlkQYGcckI1vCMnKXKEp+N29+j/TwRH0/9pzUTgDOfsDjc0Mt3PkI3++Cg8fhSG/UluXMo+Gry492FBFzkSJB5A+1AUHgp4lQDGqOKW1zpZf4d0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174067; c=relaxed/simple; bh=C4BXtDtnPo3XQ7NV1y/rceBvVT8N7ly3fImlpXG2wtA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kMk62vvBMSlpr9TYqWxvxGbD9SNbuTUmNa+W6646l1R+5oQB/+LA/ac6KjNcfDSqgoBbpCVSvf3So40dpnbrhdWrNPy9lRjGASuZS9HqQ2bpYaoDnSNC7Vs9i6gKxc/fzDaTh0D/hUPShsbHYcQafBe64GOmAHDclJxiO7P/xHY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JE8G/vSj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JE8G/vSj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2073C4AF17; Wed, 8 May 2024 13:14:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174066; bh=C4BXtDtnPo3XQ7NV1y/rceBvVT8N7ly3fImlpXG2wtA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JE8G/vSj4VJEpp4n0d/Z7Cq8kp35Ap2uimu1wOTNgIUeTWuMsWOjZouuGK0muqUbL yJ8xVXx1iMrHSXn3V5ByH2MMA5q//7JebvOb2A0x0w/cJVKdOJFQQ5fCht7F+it2TY M5+CZSo7v8K5au3t1cfZfU6UE9UNiGyhJDWV0XP8/+xIEm5dGm8p4Qdb4s/FSRgvvN lmD4dxLeLbydbV+UTacIwktDnZHSbMzYShgBB407xogu0h7tqF5+eZndOyMZBnIKrL IwARebg15bHkx4v0p2D064KlbdwUrJ11/YvgHE59v3LJIflvKivo6qao0Nz8k50Vil 6UYYaKLRUUD2w== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:42 +0200 Subject: [PATCH v3 11/13] misc: pci_endpoint_test: Add support for rockchip rk3588 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-11-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2357; i=cassel@kernel.org; h=from:subject:message-id; bh=C4BXtDtnPo3XQ7NV1y/rceBvVT8N7ly3fImlpXG2wtA=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+pbP8heOhh5LsXQMUviX4jrTdvEuzs6D8W9TC97N V9O78zJjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEzkeTrDX4Hl7a3b9KfzuSpw HRPV+f227dCW0H1ZKl9rn93ydnaeYsvI0LNpi8x1ztlJSo5WGS6nTwbMNPIR3Rx1N7jp4DyXqyJ N/AA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Rockchip rk3588 requires 64k alignment. While there is an existing device_id:vendor_id in the driver with 64k alignment, that device_id:vendor_id is am654, which uses BAR2 instead of BAR0 as the test_reg_bar, and also has special is_am654_pci_dev() checks in the driver to disallow BAR0. In order to allow testing all BARs, add a new rk3588 entry in the driver. We intentionally do not add the vendor id to pci_ids.h, since the policy for that file is that the vendor id has to be used by multiple drivers. Hopefully, this new entry will be short-lived, as there is a series on the mailing list which intends to move the address alignment restrictions from this driver to the endpoint side. Add a new entry for rk3588 in order to allow us to test all BARs. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/misc/pci_endpoint_test.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index c38a6083f0a7..a7f593b4e3b3 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -84,6 +84,9 @@ #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025 #define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031 +#define PCI_VENDOR_ID_ROCKCHIP 0x1d87 +#define PCI_DEVICE_ID_ROCKCHIP_RK3588 0x3588 + static DEFINE_IDA(pci_endpoint_test_ida); #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ @@ -980,6 +983,11 @@ static const struct pci_endpoint_test_data j721e_data = { .irq_type = IRQ_TYPE_MSI, }; +static const struct pci_endpoint_test_data rk3588_data = { + .alignment = SZ_64K, + .irq_type = IRQ_TYPE_MSI, +}; + static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x), .driver_data = (kernel_ulong_t)&default_data, @@ -1017,6 +1025,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721S2), .driver_data = (kernel_ulong_t)&j721e_data, }, + { PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588), + .driver_data = (kernel_ulong_t)&rk3588_data, + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); From patchwork Wed May 8 13:13:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658730 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B0616BFC5; Wed, 8 May 2024 13:14:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174071; cv=none; b=o07dyBSUnTXuQjqNxCpQlz2NEHqx9fK26QqmB4eO18KkE0c/1x9HYUm6sYj0tKKMF79vBTwG4RlRVZ3A1b7RafhSnjPtz4Tvu0sBHbQXxZO0SoGFdW8hgA/Z6k1WnMmjRxCzagQYMdJupAtkxR6ps+pvGZFNrzUUAPICFFWhvNY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715174071; c=relaxed/simple; bh=zV5QDNN0Jd7t4ZstveDXwSQbOhLYZJYhoixvLN8ii44=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RKgPWSLU20BZBih9AG3fEMYblVWCLIzJNUhZTGVtwe3qwkAJfafX7rGHJjttBMEsb703b2tFKQ6mH/ksVL62JU+gt7J5G+Hu+DzY0evwQu1idYGIxXVKtvqbBRYqcknntX+No/FKhlZmyiN7F95NIMBctWpJ/yFDbsV6T6PAZBw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fBFG0Tl2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fBFG0Tl2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 15D02C3277B; Wed, 8 May 2024 13:14:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174070; bh=zV5QDNN0Jd7t4ZstveDXwSQbOhLYZJYhoixvLN8ii44=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fBFG0Tl207Es9jMIQMTVUytr1QIkFHM6h5fpRHFiZLDTEwn17nn95dUGLB4FVBiJj S0Cg2Fq2xVM0Brebwubo9Sfjfq+3UkWkfczO6H7tmv0mNtLazZipq6ElfjE7e6XZ56 KkBOyikoSRQJJhIni6czWklduns73hwoxyVAUKiysd4XOoXfs6YWLV6fZ11qbUsDrd AqfyagKXuOAPMDBLW7/IVPsp+qz0t0MTDJunUoy/3oGofk5WbGhP+bxq02gXGLF4kK sJtZ2zQ6FD15eWmJPG+rNLJDww+H7Rz84qtuGQSo3fkNxAHpCAlcRUvVMubt6BQ+sr 8IIkkjyi8FArw== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:43 +0200 Subject: [PATCH v3 12/13] arm64: dts: rockchip: Add PCIe endpoint mode support Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-12-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2324; i=cassel@kernel.org; h=from:subject:message-id; bh=zV5QDNN0Jd7t4ZstveDXwSQbOhLYZJYhoixvLN8ii44=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKsq+o7xZ9f5FrNW2OrMelt6wuWiXvuOZteLcw6furgE X3uALEtHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZjIPSOG/0l38jpr+jcemX+l 2C52Q/VcQfFfVdU9j9fbGz7bXZl6Wo/hr8RBDZ/ajdmrch6yl7KsW6F6z8zx7iK7GQbMxbfTtY6 1cAEA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add a device tree node representing PCIe endpoint mode. The controller can either be configured to run in Root Complex or Endpoint node. If a user wants to run the controller in endpoint mode, the user has to disable the pcie3x4 node and enable the pcie3x4_ep node. Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 5519c1430cb7..09a06e8c43b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -136,6 +136,41 @@ pcie3x4_intc: legacy-interrupt-controller { }; }; + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + }; + pcie3x2: pcie@fe160000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; From patchwork Wed May 8 13:13:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658731 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F87585C5D; Wed, 8 May 2024 13:14:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 8 May 2024 13:14:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174075; bh=4qN66Ir2UFp9Lf/FY4N/yTmNKplsIfb7tfx/17jEJAs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=H3vDS/ZMSu2jc/jka1+zMAJzWeo1JXgkRQQskyMCMxX62PRtYTOIOhHu8i9X81GAm +Z5zN3lTn2Qph8nyMUcuQIeDOdnvsUhxp4eE3VGA6cgYAEN3uS4kSBWff686u+u+f+ Zerrus9eC4o6EwKFHsTKCMtwGupLE1wl+G2TezU4rwJ+w3hvnbGFtUgBZYVDHrwJuT Tm03m0GYeON5ewFn3k/Jco3d6+bUQ2GrHFwL+bXbd3VK8Ead/a8wX6imIl79hdi0U2 09z1rpAp4/ffp8Oou0axIxtDb2RjKy7KkvSXhec+GQpNbKdktGoRo1wMb4wco7/wY5 pAp3XxYloP1xQ== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:44 +0200 Subject: [PATCH v3 13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-13-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3453; i=cassel@kernel.org; h=from:subject:message-id; bh=4qN66Ir2UFp9Lf/FY4N/yTmNKplsIfb7tfx/17jEJAs=; b=kA0DAAoWyWQxo5nGTXIByyZiAGY7en+iU336wmdzkB6v5qlNz4tNEY6beo6f2OZq/+SyqI20f Ih1BAAWCgAdFiEETfhEv3OLR5THIdw8yWQxo5nGTXIFAmY7en8ACgkQyWQxo5nGTXK7XQD+PmFy Ydn/rF0xGmAkuXJHReuOBaNrXhf01lI4aa6pweUA/iVGALA3enh08RohJX+udFsce2YzMIbCO4t VB3hVI8kK X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add rock5b overlays for PCIe endpoint mode support. If using the rock5b as an endpoint against a normal PC, only the rk3588-rock-5b-pcie-ep.dtbo needs to be applied. If using two rock5b:s, with one board as EP and the other board as RC, rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to be applied to the respective boards. Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/Makefile | 5 +++++ .../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++ .../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f906a868b71a..d827432d5111 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -117,6 +117,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb @@ -127,3 +129,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb + +# Enable support for device-tree overlays +DTC_FLAGS_rk3588-rock-5b += -@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso new file mode 100644 index 000000000000..672d748fcc67 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode + * in the SRNS (Separate Reference Clock No Spread) configuration. + * + * NOTE: If using a setup with two ROCK 5B:s, with one board running in + * RC mode and the other board running in EP mode, see also the device + * tree overlay: rk3588-rock-5b-pcie-srns.dtso. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&pcie3x4_ep { + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso new file mode 100644 index 000000000000..1a0f1af65c43 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex + * mode in the SRNS (Separate Reference Clock No Spread) configuration. + * + * This device tree overlay is only needed (on the RC side) when running + * a setup with two ROCK 5B:s, with one board running in RC mode and the + * other board running in EP mode. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +};