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AJvYcCUoBzMNC1dPUX4te+iLaLzxqsvfcd6rITfw/O203v56hsuNU8ayN3HWgXV1hFjii55nBgGP25BWju7p+Oxqyn1byqK/919PGMnHgFXjREWrO1XQvgwmlvj8lIS7eds0dt7tP67Wi1KduGWe5gOD9kj4UP6Gpuq+QGA= X-Gm-Message-State: AOJu0Yx4JSH8cpDvUOD2GOnB+m8zEUonP+oB+oVpnAaZZgHVXaF6wn5F jgiiJYFsxG3UIS5qJlTymsw3VJh/rgc6UokTi4xiJPi6+Ls9HPQ= X-Google-Smtp-Source: AGHT+IHTG1IHRUpJsEvbfsclIDD11n/Cn0Dv06smo6eYHnW+6ah5dzq6AfYFQdIT1VKgAJhmoFvavg== X-Received: by 2002:a05:600c:5128:b0:418:2b26:47a3 with SMTP id 5b1f17b1804b1-41f71ecb1fcmr44191365e9.32.1715256442507; Thu, 09 May 2024 05:07:22 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccce1912sm24112005e9.11.2024.05.09.05.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 05:07:22 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v2 1/7] dt-bindings: display: rockchip,dw-mipi-dsi: Document RK3128 DSI Date: Thu, 9 May 2024 14:07:09 +0200 Message-ID: <20240509120715.86694-2-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240509120715.86694-1-knaerzche@gmail.com> References: <20240509120715.86694-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240509_050729_786899_E9F6720D X-CRM114-Status: GOOD ( 10.40 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Document the MIPI DSI controller for Rockchip RK3128. The integration is very similar to PX30, but it has an additional AHB clock. Signed-off-by: Alex Bee --- changes since v1: - added ahb clock .../rockchip/rockchip,dw-mipi-dsi.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index ccf79e738fa1..fdd1c8ad6045 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -15,6 +15,7 @@ properties: items: - enum: - rockchip,px30-mipi-dsi + - rockchip,rk3128-mipi-dsi - rockchip,rk3288-mipi-dsi - rockchip,rk3399-mipi-dsi - rockchip,rk3568-mipi-dsi @@ -36,7 +37,10 @@ properties: - const: pclk - const: phy_cfg - const: grf - - const: pclk + - minItems: 1 + items: + - const: pclk + - const: ahb rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -120,6 +124,25 @@ allOf: clock-names: minItems: 4 + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3128-mipi-dsi + + then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + required: + - phys + - phy-names + unevaluatedProperties: false examples: From patchwork Thu May 9 12:07:10 2024 Content-Type: text/plain; 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X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The DPHY's APB clock is required to be exposed in order to be able to enable it and access the phy's registers. Signed-off-by: Alex Bee Acked-by: Conor Dooley --- changes since v1: - none include/dt-bindings/clock/rk3128-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index 6a47825dac5d..1be455ba4985 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -116,6 +116,7 @@ #define PCLK_GMAC 367 #define PCLK_PMU_PRE 368 #define PCLK_SIM_CARD 369 +#define PCLK_MIPIPHY 370 /* hclk gates */ #define HCLK_SPDIF 440 From patchwork Thu May 9 12:07:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Bee X-Patchwork-Id: 13659681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B484EC10F1A for ; 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Thu, 09 May 2024 05:07:24 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccce1912sm24112005e9.11.2024.05.09.05.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 05:07:23 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v2 3/7] clk: rockchip: rk3128: Export PCLK_MIPIPHY Date: Thu, 9 May 2024 14:07:11 +0200 Message-ID: <20240509120715.86694-4-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240509120715.86694-1-knaerzche@gmail.com> References: <20240509120715.86694-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240509_050729_724220_9009B726 X-CRM114-Status: GOOD ( 12.63 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Export the D-DHY's APB clock for usage in the DT. Also drop the CLK_IGNORE_UNUSED-flag, as the clock will be enabled on demand. Signed-off-by: Alex Bee --- changes since v1: - reword commit message drivers/clk/rockchip/clk-rk3128.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index 75071e0cd321..a20d1fd25e2a 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -526,7 +526,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS), GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), - GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS), + GATE(PCLK_MIPIPHY, "pclk_mipiphy", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS), GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS), From patchwork Thu May 9 12:07:12 2024 Content-Type: text/plain; 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Add support for it as an optional clock. Signed-off-by: Alex Bee --- changes since v1: - new patch .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 4cc8ed8f4fbd..6ed64cc35275 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -265,6 +265,7 @@ struct dw_mipi_dsi_rockchip { struct clk *pllref_clk; struct clk *grf_clk; struct clk *phy_cfg_clk; + struct clk *ahb_clk; /* dual-channel */ bool is_slave; @@ -1153,7 +1154,15 @@ static int dw_mipi_dsi_dphy_init(struct phy *phy) goto err_init; } + ret = clk_prepare_enable(dsi->ahb_clk); + if (ret) { + clk_disable_unprepare(dsi->grf_clk); + clk_disable_unprepare(dsi->pclk); + goto err_init; + } + ret = dsi->cdata->dphy_rx_init(phy); + clk_disable_unprepare(dsi->ahb_clk); clk_disable_unprepare(dsi->grf_clk); clk_disable_unprepare(dsi->pclk); if (ret < 0) @@ -1240,6 +1249,12 @@ static int dw_mipi_dsi_dphy_power_on(struct phy *phy) goto err_phy_cfg_clk; } + ret = clk_prepare_enable(dsi->ahb_clk); + if (ret) { + DRM_DEV_ERROR(dsi->dev, "Failed to enable ahb_clk: %d\n", ret); + goto err_ahb_clk; + } + /* do soc-variant specific init */ if (dsi->cdata->dphy_rx_power_on) { ret = dsi->cdata->dphy_rx_power_on(phy); @@ -1269,6 +1284,8 @@ static int dw_mipi_dsi_dphy_power_on(struct phy *phy) return ret; err_pwr_on: + clk_disable_unprepare(dsi->ahb_clk); +err_ahb_clk: clk_disable_unprepare(dsi->phy_cfg_clk); err_phy_cfg_clk: clk_disable_unprepare(dsi->grf_clk); @@ -1296,6 +1313,7 @@ static int dw_mipi_dsi_dphy_power_off(struct phy *phy) DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); } + clk_disable_unprepare(dsi->ahb_clk); clk_disable_unprepare(dsi->grf_clk); clk_disable_unprepare(dsi->pclk); @@ -1429,6 +1447,13 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) } } + dsi->ahb_clk = devm_clk_get_optional(dev, "ahb"); + if (IS_ERR(dsi->ahb_clk)) { + ret = PTR_ERR(dsi->ahb_clk); + DRM_DEV_ERROR(dev, "Unable to get ahb_clk: %d\n", ret); + return ret; + } + dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); if (IS_ERR(dsi->grf_regmap)) { DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); From patchwork Thu May 9 12:07:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Bee X-Patchwork-Id: 13659677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95911C25B4F for ; Thu, 9 May 2024 12:07:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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AJvYcCXARPq16M7brqm3ip2PGRV0OxH2FLAr84d9LotksYbK2eqb8+A8hLA3T0Gsu4/TbcYnPQQ40SLZBLWwq7JD0pAMkmL6AVRT+qIvXoHvk2btxfPpdc+i4nK7ful7gk+nnbEJifkWYoF34DTL7i3cy8nC0d+UPhbcmbE= X-Gm-Message-State: AOJu0Yx6i02e8rb/D8f/jgaapHYibmqtLbZ2z9VZSL6mDZJxp5t2YJ6p flwFRh0QQNDeZkISnngL8ZhkmIyJx0LTwLVLTNPXkjnI+Btuxy4= X-Google-Smtp-Source: AGHT+IHtoArrqD0dnvqLAhLONFA8xc0foDIiP2c2dDm/g4xMVPSUsPLYrXXxqeAb6C9ioPtRQlXv6w== X-Received: by 2002:a05:600c:354a:b0:41b:f24a:b590 with SMTP id 5b1f17b1804b1-41fbc91f3e4mr21505645e9.3.1715256446176; Thu, 09 May 2024 05:07:26 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccce1912sm24112005e9.11.2024.05.09.05.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 05:07:25 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v2 5/7] drm/rockchip: dsi: Add support for RK3128 Date: Thu, 9 May 2024 14:07:13 +0200 Message-ID: <20240509120715.86694-6-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240509120715.86694-1-knaerzche@gmail.com> References: <20240509120715.86694-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240509_050728_298817_690BFA4C X-CRM114-Status: GOOD ( 13.09 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The DesignWare MIPI DSI controller found RK3128 SoCs supports up to 4 DSI data lanes. Similar to PX30/RK356x/RV1126 it uses an external D-PHY. Signed-off-by: Alex Bee --- changes since v1: - none .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 6ed64cc35275..17fd5260218a 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -153,6 +153,11 @@ #define PX30_DSI_TURNDISABLE BIT(5) #define PX30_DSI_LCDC_SEL BIT(0) +#define RK3128_GRF_LVDS_CON0 0x0150 +#define RK3128_DSI_FORCETXSTOPMODE GENMASK(13, 10) +#define RK3128_DSI_FORCERXMODE BIT(9) +#define RK3128_DSI_TURNDISABLE BIT(8) + #define RK3288_GRF_SOC_CON6 0x025c #define RK3288_DSI0_LCDC_SEL BIT(6) #define RK3288_DSI1_LCDC_SEL BIT(9) @@ -1518,6 +1523,18 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = { + { + .reg = 0x10110000, + .lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0, + .lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE | + RK3128_DSI_FORCERXMODE | + RK3128_DSI_FORCETXSTOPMODE), + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { { .reg = 0xff960000, @@ -1695,6 +1712,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { { .compatible = "rockchip,px30-mipi-dsi", .data = &px30_chip_data, + }, { + .compatible = "rockchip,rk3128-mipi-dsi", + .data = &rk3128_chip_data, }, { .compatible = "rockchip,rk3288-mipi-dsi", .data = &rk3288_chip_data, From patchwork Thu May 9 12:07:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Bee X-Patchwork-Id: 13659679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F3CDC25B10 for ; Thu, 9 May 2024 12:07:58 +0000 (UTC) DKIM-Signature: v=1; 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Thu, 09 May 2024 05:07:26 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v2 6/7] ARM: dts: rockchip: Add D-PHY for RK3128 Date: Thu, 9 May 2024 14:07:14 +0200 Message-ID: <20240509120715.86694-7-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240509120715.86694-1-knaerzche@gmail.com> References: <20240509120715.86694-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240509_050729_499098_3FAF4FF0 X-CRM114-Status: GOOD ( 11.52 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The InnoSilicon D-PHY found in RK3128 SoCs supports DSI/LVDS/TTL with a maximum transfer rate of 1 Gbps per lane. While adding it, also add it's clocks to RK3128_PD_VIO powerdomain as the phy is part of it. Signed-off-by: Alex Bee --- changes since v1: - also added SCLK_MIPI_24M to powerdomain - reword commit message arch/arm/boot/dts/rockchip/rk3128.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index fb98873fd94e..fbd95bb08cd3 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -216,6 +216,8 @@ power-domain@RK3128_PD_VIO { <&cru ACLK_LCDC0>, <&cru HCLK_LCDC0>, <&cru PCLK_MIPI>, + <&cru PCLK_MIPIPHY>, + <&cru SCLK_MIPI_24M>, <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru ACLK_VIO0>, @@ -496,6 +498,18 @@ hdmi_out: port@1 { }; }; + dphy: phy@20038000 { + compatible = "rockchip,rk3128-dsi-dphy"; + reg = <0x20038000 0x4000>; + clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; + clock-names = "ref", "pclk"; + resets = <&cru SRST_MIPIPHY_P>; + reset-names = "apb"; + power-domains = <&power RK3128_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; 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AJvYcCUnUKnNQ426hUdYoFoNXq27JYmgf4ceg/iL8ctbRutUExdbHuknXRjQVONv4v3LuN+RHFit9YazWTWAd2Umn1agKzzqS6B++6gcsDndff7N5JSx6hYsaz5X5rmu9/JA4Pfn0zUiJ6I5WOF8U3zuG8EGv97UqWjjLpA= X-Gm-Message-State: AOJu0YwTxLx8lgsb61RI4gx1yjdgBvZj/WjX75qKvS0/gNxJ7C99NOs4 UUdK1ePzxM5vF+DZWt/LyaVU3mmowwrua0IrcSLEUcoX19LpwDo= X-Google-Smtp-Source: AGHT+IEOGVpnlxc4D9Jfg4bzT5yUTxC5Nb1l7o9iKNsaxhKiAZ+w5GYZsS4D630ujkwBJ9hHrRUsqA== X-Received: by 2002:a2e:4602:0:b0:2e0:3132:94d4 with SMTP id 38308e7fff4ca-2e446f7c72amr28137541fa.16.1715256447777; Thu, 09 May 2024 05:07:27 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:b44:d8c3:6fa8:c46f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccce1912sm24112005e9.11.2024.05.09.05.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 05:07:27 -0700 (PDT) From: Alex Bee To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v2 7/7] ARM: dts: rockchip: Add DSI for RK3128 Date: Thu, 9 May 2024 14:07:15 +0200 Message-ID: <20240509120715.86694-8-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240509120715.86694-1-knaerzche@gmail.com> References: <20240509120715.86694-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240509_050732_047133_3C009591 X-CRM114-Status: GOOD ( 10.83 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add the Designware MIPI DSI controller and it's port nodes. Signed-off-by: Alex Bee --- changes since v1: - added HCLK_VIO_H2P as ahb clock arch/arm/boot/dts/rockchip/rk3128.dtsi | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index fbd95bb08cd3..1ed4436549ee 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -277,6 +277,42 @@ vop_out_hdmi: endpoint@0 { reg = <0>; remote-endpoint = <&hdmi_in_vop>; }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vop>; + }; + }; + }; + + dsi: dsi@10110000 { + compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x10110000 0x4000>; + interrupts = ; + clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>; + clock-names = "pclk", "ahb"; + phys = <&dphy>; + phy-names = "dphy"; + resets = <&cru SRST_VIO_MIPI_DSI>; + reset-names = "apb"; + rockchip,grf = <&grf>; + power-domains = <&power RK3128_PD_VIO>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + dsi_in_vop: endpoint { + remote-endpoint = <&vop_out_dsi>; + }; + }; + + dsi_out: port@1 { + reg = <1>; + }; }; };