From patchwork Thu May 9 17:00:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3847C10F1A for ; Thu, 9 May 2024 17:01:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s578Z-0002D0-U1; Thu, 09 May 2024 13:00:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578Y-0002Bu-2t for qemu-devel@nongnu.org; Thu, 09 May 2024 13:00:54 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578V-0003UR-P6 for qemu-devel@nongnu.org; Thu, 09 May 2024 13:00:53 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274051; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CSdbbijnqqu6Q0jIu+Qkk/Gmy2abee1VL3NL5PRrhBA=; b=LmOsU/dOeHaBGR6KF1+Vzn135yS0WVs/Xa+C002GCVhvUDLu3G79VwPIgoLHBilvQVMBtb 5oHwXE3WS3z8GpJDc6fSr5knc70MbfPKUbSnR7ppsog3Exir1h0oPdOjGNT+RHih6V9bI1 QdCcPjkT7U+hqia1wY9arBH+4ncf2Hg= Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-477-XQXVVISGMwGRnXM6zyidXA-1; Thu, 09 May 2024 13:00:49 -0400 X-MC-Unique: XQXVVISGMwGRnXM6zyidXA-1 Received: by mail-ej1-f70.google.com with SMTP id a640c23a62f3a-a5966e85bf6so191860666b.0 for ; Thu, 09 May 2024 10:00:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274047; x=1715878847; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CSdbbijnqqu6Q0jIu+Qkk/Gmy2abee1VL3NL5PRrhBA=; b=EjK5W5WZwABhwOKcZKkHA/iPPqIz2YodlQOcSaXZo2pUR8L1a1fWm5O4Bt1TUNpw0M RKyafDMR0gMROMNSXHu9ItPB7EzFJPXJPbfjJhSo0YoyKfKXJfVfdOxCP8IjCoVTm54P Ow0bd9bbF92zbdI6RFuHS6Ah6JHUnXpwXblesHAjpfKr9cpzCJCsnMmt8DHhZaDdvSVx ZnebBgiYILvdL2O4yAYytJ84dtIxVAOr5nY6YOx5sxMjO/SLCwFlQoatAoE4AaqKg4Si nXnREX7Evi1ek0+mTKI97HbSwK+sRbJE4PJsT+06LrikV3FwgDp/WcPnxR+bH79OBeln yadw== X-Gm-Message-State: AOJu0YxmrGE4JCFRis0OXfX4HG1+Jg1YJXG/voqS9jPnNZ/qya2EVlU4 iZVz7d+GA9ZQKb81phnpEodRGayigqdsxd6feD+apf5hh46LOw/3GrLoxd+7X03hlv1qUiFuA2g kagVwAHcDxUg85mrt9RUXz6QYJuNBd3RwVeGZOYYqKges19NJFcDSg+mhgwcUf4ZYRON1ryIC9i KiOBpc/u7IM7YwwLmWP19chz5S/cPaNVcvAqOm X-Received: by 2002:a17:906:308b:b0:a58:9a67:967b with SMTP id a640c23a62f3a-a5a11844720mr261523066b.27.1715274047016; Thu, 09 May 2024 10:00:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH9w7WUbqsGUYP9TFk+LYI8lDiO+u2ZSHR2NmcOcxtMBWkBS8hpZkMnI/0Qf3m6oIbjlQ/R8w== X-Received: by 2002:a17:906:308b:b0:a58:9a67:967b with SMTP id a640c23a62f3a-a5a11844720mr261519966b.27.1715274046408; Thu, 09 May 2024 10:00:46 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a1781cd90sm92868066b.20.2024.05.09.10.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:00:46 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 01/13] s390x: move s390_cpu_addr2state to target/s390x/sigp.c Date: Thu, 9 May 2024 19:00:32 +0200 Message-ID: <20240509170044.190795-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This function has no dependency on the virtio-ccw machine type, though it assumes that the CPU address corresponds to the core_id and the index. If there is any need of something different or more fancy (unlikely) S390 can include a MachineClass subclass and implement it there. For now, move it to sigp.c for simplicity. Signed-off-by: Paolo Bonzini Reviewed-by: Thomas Huth --- hw/s390x/s390-virtio-ccw.c | 16 ---------------- target/s390x/sigp.c | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 16 deletions(-) diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 4dcc2138200..feabc173eb3 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -50,22 +50,6 @@ static Error *pv_mig_blocker; -S390CPU *s390_cpu_addr2state(uint16_t cpu_addr) -{ - static MachineState *ms; - - if (!ms) { - ms = MACHINE(qdev_get_machine()); - g_assert(ms->possible_cpus); - } - - /* CPU address corresponds to the core_id and the index */ - if (cpu_addr >= ms->possible_cpus->len) { - return NULL; - } - return S390_CPU(ms->possible_cpus->cpus[cpu_addr].cpu); -} - static S390CPU *s390x_new_cpu(const char *typename, uint32_t core_id, Error **errp) { diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index 9dd977349ab..ad0ad61177d 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "s390x-internal.h" +#include "hw/boards.h" #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" #include "exec/address-spaces.h" @@ -435,6 +436,22 @@ static int sigp_set_architecture(S390CPU *cpu, uint32_t param, return SIGP_CC_STATUS_STORED; } +S390CPU *s390_cpu_addr2state(uint16_t cpu_addr) +{ + static MachineState *ms; + + if (!ms) { + ms = MACHINE(qdev_get_machine()); + g_assert(ms->possible_cpus); + } + + /* CPU address corresponds to the core_id and the index */ + if (cpu_addr >= ms->possible_cpus->len) { + return NULL; + } + return S390_CPU(ms->possible_cpus->cpus[cpu_addr].cpu); +} + int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3) { uint64_t *status_reg = &env->regs[r1]; From patchwork Thu May 9 17:00:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35409C25B74 for ; Thu, 9 May 2024 17:02:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s578a-0002DI-Iz; Thu, 09 May 2024 13:00:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578Z-0002Cv-MX for qemu-devel@nongnu.org; Thu, 09 May 2024 13:00:55 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578X-0003Uv-UE for qemu-devel@nongnu.org; Thu, 09 May 2024 13:00:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274053; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0LrJYd46GHGKVcNYX3wgLHzt987Ipk3AVpa7I+rUYDY=; b=R8m8OAL0f24r/PkU3LkbT2aplPa/Ay2OZWtsDHmNuc6Bkwtz1Ezo0jwWj2D7+tTguqy5mg 6RwGyd7z0d5icuenfPi9RAKK2AIoqzVeUBkj4DWXuko3Q8EECuzgH7/Ai68iqqb27yfMNU a/nOOBg2dY/g5RkOr1n9E91ZdqRH3SI= Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-157-j6ZPJ_ZSN82cs3Sh86Y2Uw-1; Thu, 09 May 2024 13:00:51 -0400 X-MC-Unique: j6ZPJ_ZSN82cs3Sh86Y2Uw-1 Received: by mail-ej1-f70.google.com with SMTP id a640c23a62f3a-a59a5b06802so63539666b.1 for ; Thu, 09 May 2024 10:00:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274050; x=1715878850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0LrJYd46GHGKVcNYX3wgLHzt987Ipk3AVpa7I+rUYDY=; b=NjX9ba0KiBTlKfRvlyIuwsRFlJR0OtlhnRoQV2A29GKaLQHI83DJOnXWQD4IJ1BTIF C+u3kmVlnLN4Q3WcO78f1363Aix3HWS1f3FxKyIjA9EMuZoywb8A94xlIGKA7sr318pX y0o5zUA22o4Jf5DgTSOy4vRhD8/60urylIc4SxBGyGRV9p+hwcjoFQLNAB7m3Vj3pOqn B7/3UMwO8t+OV+m7oALWYsh5LVVsgz5Zr2Q/OcC9/xCT4LVeZiOL0zZlBphxf+LNAeyX bo5i41hK4JcrALwAilc1mzDKkqc0fxpZzbY1KJVLAUavDlqdTKVhngDFonvv44GSd6y7 Ql3g== X-Gm-Message-State: AOJu0YyoSd9BkEtygbu3mhjIGWOxwwSP0f63dpk73iEMl3eaJ+Y/UtpO pQoc/2+IAz4ftNwnguO08LUQ4oL3dGwNcXcvl1iWWuVJ3WTH0WC8vYXIDLr9Zm9WDToBt3tjBW0 4Z3VH987gJhY69yYMlDLNycYlgbXoBp57m3ojx0PYV6G3TfALkdUd7b4wk6xUrG/KN8w1PJZNRI r+ndtP66IRgf+5f0BuReYMdBIt3ICPLgF7GObF X-Received: by 2002:a17:906:f6ca:b0:a54:c130:21fd with SMTP id a640c23a62f3a-a5a2d53ade1mr13736966b.13.1715274050031; Thu, 09 May 2024 10:00:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHreuDCtL1B1aeAW4RUhdRt9SuJ2I7vlx4l7CrAcCke/aTgNgWMXoblpJ29V45D4UCHJJUHgQ== X-Received: by 2002:a17:906:f6ca:b0:a54:c130:21fd with SMTP id a640c23a62f3a-a5a2d53ade1mr13735266b.13.1715274049704; Thu, 09 May 2024 10:00:49 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a17b17cc5sm91389566b.205.2024.05.09.10.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:00:47 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 02/13] s390_flic: add migration-enabled property Date: Thu, 9 May 2024 19:00:33 +0200 Message-ID: <20240509170044.190795-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of mucking with css_migration_enabled(), add a property specific to the FLIC device, similar to what is done for TYPE_S390_STATTRIB. Signed-off-by: Paolo Bonzini Reviewed-by: Thomas Huth --- include/hw/s390x/s390_flic.h | 1 + hw/intc/s390_flic.c | 6 +++++- hw/s390x/s390-virtio-ccw.c | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/hw/s390x/s390_flic.h b/include/hw/s390x/s390_flic.h index 3907a13d076..bcb081def58 100644 --- a/include/hw/s390x/s390_flic.h +++ b/include/hw/s390x/s390_flic.h @@ -47,6 +47,7 @@ struct S390FLICState { /* to limit AdapterRoutes.num_routes for compat */ uint32_t adapter_routes_max_batch; bool ais_supported; + bool migration_enabled; }; diff --git a/hw/intc/s390_flic.c b/hw/intc/s390_flic.c index f4a848460b8..7f930800877 100644 --- a/hw/intc/s390_flic.c +++ b/hw/intc/s390_flic.c @@ -405,6 +405,8 @@ static void qemu_s390_flic_class_init(ObjectClass *oc, void *data) static Property s390_flic_common_properties[] = { DEFINE_PROP_UINT32("adapter_routes_max_batch", S390FLICState, adapter_routes_max_batch, ADAPTER_ROUTES_MAX_GSI), + DEFINE_PROP_BOOL("migration-enabled", S390FLICState, + migration_enabled, true), DEFINE_PROP_END_OF_LIST(), }; @@ -457,7 +459,9 @@ type_init(qemu_s390_flic_register_types) static bool adapter_info_so_needed(void *opaque) { - return css_migration_enabled(); + S390FLICState *fs = S390_FLIC_COMMON(opaque); + + return fs->migration_enabled; } const VMStateDescription vmstate_adapter_info_so = { diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index feabc173eb3..1383e47eeb5 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -1174,6 +1174,7 @@ static void ccw_machine_2_9_class_options(MachineClass *mc) S390CcwMachineClass *s390mc = S390_CCW_MACHINE_CLASS(mc); static GlobalProperty compat[] = { { TYPE_S390_STATTRIB, "migration-enabled", "off", }, + { TYPE_S390_FLIC_COMMON, "migration-enabled", "off", }, }; ccw_machine_2_10_class_options(mc); From patchwork Thu May 9 17:00:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C99A5C10F1A for ; Thu, 9 May 2024 17:02:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s578e-0002E7-Al; Thu, 09 May 2024 13:01:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578c-0002Ds-C4 for qemu-devel@nongnu.org; Thu, 09 May 2024 13:00:58 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578a-0003Vq-LI for qemu-devel@nongnu.org; Thu, 09 May 2024 13:00:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274055; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WgP6NyhcsWgkUVzyE952+E9Mx6cg42Kmy5V3+u1tIFU=; b=bQDZzE0eDjxbdSr3wqmfGivjvwQrXTiE0eZfEeepzyHng/t7j0ygW8hAeHh2hZ1Eoe4IL3 lLVPUGasN4l8MUPqDSpZw1bk7DzyLXxz2opAHACHyb9+x+dylxMSIeG2LgznjRPjia4Oh/ SqVhR/0UVPwITc5V6Mn5cw6lFcaBXn8= Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-468-oRqA5oshOauvBB-FFNQdqQ-1; Thu, 09 May 2024 13:00:54 -0400 X-MC-Unique: oRqA5oshOauvBB-FFNQdqQ-1 Received: by mail-ed1-f69.google.com with SMTP id 4fb4d7f45d1cf-5725715b9beso1095414a12.1 for ; Thu, 09 May 2024 10:00:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274052; x=1715878852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WgP6NyhcsWgkUVzyE952+E9Mx6cg42Kmy5V3+u1tIFU=; b=gpLPCJsYiDsyvOEAxxzQYgqvxcojN9CE62nUxd8/0oSgajlfxM9sxvGJy79P6vVkNL 5LQMmQrPif0PzIh80YuM+W+f2Z/UMlE5RhmdWOMa4R2IDU3iZBDQ2698TmbNzBJy7YWO JWmD7A/s2CZpYjq91GX6lo+0xSWmy5+g/qtgAjijtG8zHpwuOkmfmYj+BlzWvPL8Mr8K qBoLFl8VnBECZQrsGZEdADB1YsJVCTV0zWyzxDRIIH53UixmMvlYvIPI6zBKlfoJ1Xcb MR5DSy+8D8MbAoo/Xt3+CQxOary0OnAy7EUsOG00fcIT/KgPTFkTQ/n3M50RvTTRXquC kiMA== X-Gm-Message-State: AOJu0YzMdktXwAPoIP4aFf9B5Sevt/T/c6hiI+BllrqdsX6/wIr1c+Ci cL3y+AvgWZ1Pt5naoIKfE7KOx8TKW8qZ7mO5FTurAXEtcNvt4ykWvoZWSuK57egAemeCiyItkFr 3ZCbnX+vnvoBQkV1F6ZZbzbO8y8NWTQUZnSb8AdnJg5mehhnLaSM0M3GX0zGDe9RuUICbxZLEVU GVtVoS18/F6X7Q3pIlJnLat5v+s4UWycNGEmLa X-Received: by 2002:aa7:c992:0:b0:572:b0a8:65fd with SMTP id 4fb4d7f45d1cf-573326eddfemr2325095a12.6.1715274052306; Thu, 09 May 2024 10:00:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFLuhCxXYfgVg4UNoInB+G70igMmMs6E5mXCATPm8gie2OBVKaF78hm2Hh7bifBvgNNL7wzlA== X-Received: by 2002:aa7:c992:0:b0:572:b0a8:65fd with SMTP id 4fb4d7f45d1cf-573326eddfemr2325081a12.6.1715274051796; Thu, 09 May 2024 10:00:51 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733c2c7dd9sm852739a12.69.2024.05.09.10.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:00:50 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 03/13] s390: move css_migration_enabled from machine to css.c Date: Thu, 9 May 2024 19:00:34 +0200 Message-ID: <20240509170044.190795-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The CSS subsystem uses global variables, just face the truth and use a variable also for whether the CSS vmstate is in use; remove the indirection of fetching it from the machine type, which makes the TCG code depend unnecessarily on the virtio-ccw machine. Signed-off-by: Paolo Bonzini --- include/hw/s390x/css.h | 6 ++++++ include/hw/s390x/s390-virtio-ccw.h | 7 ------- hw/s390x/css.c | 10 +++++++--- hw/s390x/s390-virtio-ccw.c | 15 +++------------ 4 files changed, 16 insertions(+), 22 deletions(-) diff --git a/include/hw/s390x/css.h b/include/hw/s390x/css.h index ba72ee3dd20..8289e458370 100644 --- a/include/hw/s390x/css.h +++ b/include/hw/s390x/css.h @@ -333,4 +333,10 @@ static inline int ccw_dstream_read_buf(CcwDataStream *cds, void *buff, int len) #define ccw_dstream_read(cds, v) ccw_dstream_read_buf((cds), &(v), sizeof(v)) #define ccw_dstream_write(cds, v) ccw_dstream_write_buf((cds), &(v), sizeof(v)) +/** + * true if (vmstate based) migration of the channel subsystem + * is enabled, false if it is disabled. + */ +extern bool css_migration_enabled; + #endif diff --git a/include/hw/s390x/s390-virtio-ccw.h b/include/hw/s390x/s390-virtio-ccw.h index c1d46e78af8..c0494e511cb 100644 --- a/include/hw/s390x/s390-virtio-ccw.h +++ b/include/hw/s390x/s390-virtio-ccw.h @@ -43,7 +43,6 @@ struct S390CcwMachineClass { /*< public >*/ bool ri_allowed; bool cpu_model_allowed; - bool css_migration_enabled; bool hpage_1m_allowed; int max_threads; }; @@ -55,10 +54,4 @@ bool cpu_model_allowed(void); /* 1M huge page mappings allowed by the machine */ bool hpage_1m_allowed(void); -/** - * Returns true if (vmstate based) migration of the channel subsystem - * is enabled, false if it is disabled. - */ -bool css_migration_enabled(void); - #endif diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 295530963a6..b2d5327dbf4 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -23,6 +23,8 @@ #include "hw/s390x/s390-virtio-ccw.h" #include "hw/s390x/s390-ccw.h" +bool css_migration_enabled = true; + typedef struct CrwContainer { CRW crw; QTAILQ_ENTRY(CrwContainer) sibling; @@ -180,7 +182,7 @@ static const VMStateDescription vmstate_orb = { static bool vmstate_schdev_orb_needed(void *opaque) { - return css_migration_enabled(); + return css_migration_enabled; } static const VMStateDescription vmstate_schdev_orb = { @@ -388,7 +390,7 @@ static int subch_dev_post_load(void *opaque, int version_id) css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s); } - if (css_migration_enabled()) { + if (css_migration_enabled) { /* No compat voodoo to do ;) */ return 0; } @@ -412,7 +414,9 @@ static int subch_dev_post_load(void *opaque, int version_id) void css_register_vmstate(void) { - vmstate_register(NULL, 0, &vmstate_css, &channel_subsys); + if (css_migration_enabled) { + vmstate_register(NULL, 0, &vmstate_css, &channel_subsys); + } } IndAddr *get_indicator(hwaddr ind_addr, int len) diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 1383e47eeb5..aa90703d518 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -275,11 +275,9 @@ static void ccw_init(MachineState *machine) s390_enable_css_support(s390_cpu_addr2state(0)); ret = css_create_css_image(VIRTUAL_CSSID, true); - assert(ret == 0); - if (css_migration_enabled()) { - css_register_vmstate(); - } + + css_register_vmstate(); /* Create VirtIO network adapters */ s390_create_virtio_net(BUS(css_bus), mc->default_nic); @@ -741,7 +739,6 @@ static void ccw_machine_class_init(ObjectClass *oc, void *data) s390mc->ri_allowed = true; s390mc->cpu_model_allowed = true; - s390mc->css_migration_enabled = true; s390mc->hpage_1m_allowed = true; s390mc->max_threads = 1; mc->init = ccw_init; @@ -811,11 +808,6 @@ static const TypeInfo ccw_machine_info = { }, }; -bool css_migration_enabled(void) -{ - return get_machine_class()->css_migration_enabled; -} - #define DEFINE_CCW_MACHINE(suffix, verstr, latest) \ static void ccw_machine_##suffix##_class_init(ObjectClass *oc, \ void *data) \ @@ -1171,7 +1163,6 @@ static void ccw_machine_2_9_instance_options(MachineState *machine) static void ccw_machine_2_9_class_options(MachineClass *mc) { - S390CcwMachineClass *s390mc = S390_CCW_MACHINE_CLASS(mc); static GlobalProperty compat[] = { { TYPE_S390_STATTRIB, "migration-enabled", "off", }, { TYPE_S390_FLIC_COMMON, "migration-enabled", "off", }, @@ -1180,7 +1171,7 @@ static void ccw_machine_2_9_class_options(MachineClass *mc) ccw_machine_2_10_class_options(mc); compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); - s390mc->css_migration_enabled = false; + css_migration_enabled = false; } DEFINE_CCW_MACHINE(2_9, "2.9", false); From patchwork Thu May 9 17:00:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B24EDC10F1A for ; Thu, 9 May 2024 17:02:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s578g-0002Ey-HG; Thu, 09 May 2024 13:01:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578e-0002EJ-Q7 for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:00 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578d-0003WK-D2 for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274058; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RkXh8iMmEX+Na8Ja+pj2VTtRvHtCubEpo1ctt3O6Hhs=; b=MhZhVEKFENSX81rsDoUr20BlQmJm3qseJA8PsprX1XvFs+1EbLhAjRmsaTIBgMYVsL6qBE vo1BkIPw5QzOVmh6ORm0ZpY6VQlvRRRwuoArXCje/oJqwRjwXR2X/eulrIosuGtxl1B/cF 5MU9ldEkNoX7SwiR0p6WDdgPhAnDQLk= Received: from mail-lf1-f70.google.com (mail-lf1-f70.google.com [209.85.167.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-44-DAoRk-L0MS6RuFU3c2C5iQ-1; Thu, 09 May 2024 13:00:56 -0400 X-MC-Unique: DAoRk-L0MS6RuFU3c2C5iQ-1 Received: by mail-lf1-f70.google.com with SMTP id 2adb3069b0e04-51f7d5c8500so938447e87.0 for ; Thu, 09 May 2024 10:00:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274054; x=1715878854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RkXh8iMmEX+Na8Ja+pj2VTtRvHtCubEpo1ctt3O6Hhs=; b=SJYiYHGbWXn86fEd5kszBO/XjKndFrM68admGI+tJI4OJL9JLnMwwfkE5xSNnu44Qd pntWFCx2kbK5+BjklY3wTvMQkZNEK3Gs0Zky0/YH1/JHfXqUV1jMsYkC7GhOaDNP91je bK3QsPfveEUZtOj6Uy6a2vaTaUIplNax0ZCvtUCF+SAnOtEuCBW0OLbnxtUCSoLIfKC/ ItZxNvrNlaIrlzRqZO05ZEYa169ZZdqFx6x/kyC9DCgh9hq9ZDuG3fRWmnbJJX9ysECr XYvV4/mzjngsKQ/qyZuRtV5T27lA9/Tvxql2FzOXKVQTLnjP3Qk8GCi0dUqOZx+pJODr 9dGw== X-Gm-Message-State: AOJu0YwdMdm9apVhpHQoE9qzEg0B1AX6czqP/4z2YjCIgNQ6YT4JCCD2 jIh9uTo+dcOM6wRebcIF1vDEVmgToziesgs6hEqY+qwX5wYvxFbTv6sscS7kUDZrgr1vahxAlhS SjzYsIBCZ1//EYwVJjfxRx2FHBUQ5u2VlCwlv0KfQLr4xezt74J82ZisvaArlMalXusVx+ZVOh3 t5OqY2DwOp7mzQQLqVX9mzkddcDptZdN9oaYB7 X-Received: by 2002:ac2:53a4:0:b0:521:9963:3896 with SMTP id 2adb3069b0e04-5220fc6da32mr65961e87.41.1715274054609; Thu, 09 May 2024 10:00:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEENc/FoJpG8UOOXW9YEZx7vKcipAwsHN2AvdF1eKk+cE/YqVjHav1fnTel9hnfnQpBxj1Y7A== X-Received: by 2002:ac2:53a4:0:b0:521:9963:3896 with SMTP id 2adb3069b0e04-5220fc6da32mr65949e87.41.1715274054109; Thu, 09 May 2024 10:00:54 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733c350d9asm866698a12.97.2024.05.09.10.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:00:52 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 04/13] s390x: select correct components for no-board build Date: Thu, 9 May 2024 19:00:35 +0200 Message-ID: <20240509170044.190795-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Paolo Bonzini Reviewed-by: Thomas Huth --- .gitlab-ci.d/buildtest.yml | 4 ++-- target/s390x/Kconfig | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 13afd0df1f0..f8502905203 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -650,7 +650,7 @@ build-tci: # Check our reduced build configurations # requires libfdt: aarch64, arm, i386, loongarch64, microblaze, microblazeel, # mips64el, or1k, ppc, ppc64, riscv32, riscv64, rx, x86_64 -# does not build without boards: i386, s390x, x86_64 +# does not build without boards: i386, x86_64 build-without-defaults: extends: .native_build_job_template needs: @@ -666,7 +666,7 @@ build-without-defaults: --disable-strip TARGETS: alpha-softmmu avr-softmmu cris-softmmu hppa-softmmu m68k-softmmu mips-softmmu mips64-softmmu mipsel-softmmu - sh4-softmmu sh4eb-softmmu sparc-softmmu + s390x-softmmu sh4-softmmu sh4eb-softmmu sparc-softmmu sparc64-softmmu tricore-softmmu xtensa-softmmu xtensaeb-softmmu hexagon-linux-user i386-linux-user s390x-linux-user MAKE_CHECK_ARGS: check diff --git a/target/s390x/Kconfig b/target/s390x/Kconfig index 72da48136c6..d886be48b47 100644 --- a/target/s390x/Kconfig +++ b/target/s390x/Kconfig @@ -1,2 +1,4 @@ config S390X bool + select PCI + select S390_FLIC From patchwork Thu May 9 17:00:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24181C10F1A for ; Thu, 9 May 2024 17:03:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s579K-0002Ut-Lf; Thu, 09 May 2024 13:01:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s579E-0002Tt-9g for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:41 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s5799-0003d1-NW for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:36 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274091; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tfwFcUpcowXHmSd2Ge81kDPkuiKnyaodHB6RPGeDEk8=; b=ZuvsuOH9DtLPvLZRzl7pNuBctAKNV0AsLYEjzVVMf67/FEQJmnEiS+0d4A2QK6n721S8Qr Nnl2qK5NdQuCIZsUVXYq8a8BiurzuTqgQpsGzqojKQHRR5ZxTR3U4cdTyEwaFdQYCtPLgr 60xf99GlNNMPM9gh2pUvEBI5hIClTkc= Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-426-QEbgvFLNNCenoEE-bZjfbw-1; Thu, 09 May 2024 13:00:58 -0400 X-MC-Unique: QEbgvFLNNCenoEE-bZjfbw-1 Received: by mail-ej1-f71.google.com with SMTP id a640c23a62f3a-a599dbd2b6aso58964166b.2 for ; Thu, 09 May 2024 10:00:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274056; x=1715878856; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tfwFcUpcowXHmSd2Ge81kDPkuiKnyaodHB6RPGeDEk8=; b=sGta77f6rwL5wt9/AYgjEFH1TkD6G0EB0deOEGltiW9cBqs1zjdDu8MOfLfpUobbPs YRv4y8GXkIDpUYKwNr0Aa0fRasxuJhlOC/v2QtxT/CSLUDzcaeCK9yd9EyJLnzOaaQCZ zfjdKNDaRe6fU3YKcJKWhX8VBg9Dsv6NWR7m9c8xVHlmh4ckKklZa3+tEo2lb8IgJlok XrNcEHR395MdD179VuxB2nPdXc2Ypz3+uIAf/jjVciLHVJ/GL9Dq2fopPunp+782xmCG LZnp3GQAUu3/K3Wds8Hea6T7H505kD0Tq1ztH+c0aSqf2ra6WAqDmYLFn98fiO8tu6zc Ia1g== X-Gm-Message-State: AOJu0YzM5aQjAJ/B7xGjPiA9mnVqoZSeaM6zFdFhWunLmFTlo7n7jEqI hW+SSRt2OKtihANw7xZ3eChVts8E/oc1lVcCtJ+9tTXqdBCA08K0EXD7pzFnJ90/gal5exTsGHC GIjNNsHSARb1i++nn0NOQMvvCdC9Zii6i3N4MFHe9hXMNunmEZQjh4x+aEI9ggLTiSR917mWBo6 rfpoJiOd37JOoUd6/9v1xCXJFZdff5xjNfa72O X-Received: by 2002:a17:907:7da3:b0:a59:d063:f5f3 with SMTP id a640c23a62f3a-a5a2d673401mr16521966b.63.1715274056446; Thu, 09 May 2024 10:00:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE9LZyJu+Hm3YRCK3W7zrnGKvxq2cylzn9xsCzrd2jeQC1+YO5WhwNzZsClGWl6H0UwHXXAUw== X-Received: by 2002:a17:907:7da3:b0:a59:d063:f5f3 with SMTP id a640c23a62f3a-a5a2d673401mr16520666b.63.1715274056114; Thu, 09 May 2024 10:00:56 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c7ebcsm91884466b.117.2024.05.09.10.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:00:54 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 05/13] tests/qtest: s390x: fix operation in a build without any boards or devices Date: Thu, 9 May 2024 19:00:36 +0200 Message-ID: <20240509170044.190795-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Do the bare minimum to ensure that at least a vanilla --without-default-devices build works for all targets except i386, x86_64 and ppc64. In particular this fixes s390x-softmmu; i386 and x86_64 have about a dozen failing tests that do not pass -M and therefore require a default machine type; ppc64 has the same issue, though only with numa-test. If we can for now ignore the cases where boards and devices are picked by hand, drive_del-test however can be fixed easily; almost all tests check for the virtio-blk or virtio-scsi device that they use, and are already skipped. Only one didn't get the memo; plus another one does not need a machine at all and can be run with -M none. Signed-off-by: Paolo Bonzini Reviewed-by: Thomas Huth --- tests/qtest/drive_del-test.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/qtest/drive_del-test.c b/tests/qtest/drive_del-test.c index 8a6f3ac963d..7b67a4bbee4 100644 --- a/tests/qtest/drive_del-test.c +++ b/tests/qtest/drive_del-test.c @@ -173,7 +173,7 @@ static void test_drive_without_dev(void) QTestState *qts; /* Start with an empty drive */ - qts = qtest_init("-drive if=none,id=drive0"); + qts = qtest_init("-drive if=none,id=drive0 -M none"); /* Delete the drive */ drive_del(qts); @@ -192,6 +192,11 @@ static void test_after_failed_device_add(void) QDict *response; QTestState *qts; + if (!has_device_builtin("virtio-blk")) { + g_test_skip("Device virtio-blk is not available"); + return; + } + snprintf(driver, sizeof(driver), "virtio-blk-%s", qvirtio_get_dev_type()); From patchwork Thu May 9 17:00:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CC61C41513 for ; Thu, 9 May 2024 17:02:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s5790-0002M2-Uz; Thu, 09 May 2024 13:01:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578w-0002KP-Dh for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:18 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578h-0003XB-Rt for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274062; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6WAHTvAaE6sY6xhH4JOpgzSpMmfvt1RmbHZ80hmJ/+E=; b=VEBlLBivj9FjRlOb1jKgJvV+teJ5aK4HnONALqcp2C8M6FubMw9P9AXjytko1w1DqxeRkH z8UnTiDP29Vp7f8qBiQmJJrrcSMiS6Rj94xbeHcMe2fjiBjjLTZ/WdBZc2YhXwQt3L2Vsa FjJLBZLJuiSqo7KIsjEyCK7tf5JBaFc= Received: from mail-lf1-f70.google.com (mail-lf1-f70.google.com [209.85.167.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-653-hdMl6wfLPwG1Mo2gagOh7Q-1; Thu, 09 May 2024 13:01:01 -0400 X-MC-Unique: hdMl6wfLPwG1Mo2gagOh7Q-1 Received: by mail-lf1-f70.google.com with SMTP id 2adb3069b0e04-51f98fc5a80so952136e87.1 for ; Thu, 09 May 2024 10:01:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274059; x=1715878859; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6WAHTvAaE6sY6xhH4JOpgzSpMmfvt1RmbHZ80hmJ/+E=; b=SlUzMSII4ViYEFcmQjxomAa7mJY4GUEgyYh5lMGVpsTP8T8TAOBw5TcaT2+gt7FN5b Q9UDKpup8qmUTAoYQv8Zv89kF4qDj8UpwUoqNGKwHmJ2b630W0q9OKIY6nF/bc/Pwjbd nhX/AqLSV+rFrrmInT3PRySEfGXdDJzz5dVxUcIvw6jIHJsNHp7xnpDHJp7IQneuiluz WzJhkD7P96tfXMDs8jpfKQdPpOsFqOg4jShpNnT486HeydNIeXXDRp8xSVP8njX7ZUsa /xbG0MqsacpDA9l5bVoYCu59zq/UfNJC+iV5QdYyHFXJrJChikI1JMzKRHgjU4GbMtR4 54jg== X-Gm-Message-State: AOJu0YykGnhScE4CUsp3IzDtGnzVxc48HL4t7Y0126DohDJaVY+Ip4Pn sez0HF2mm5bjOiCRoLdDwAyS7UxPQF95rkFSFvhuLifpbVb1DOfQeIDnPg39qjgM3TjrbzZHFDc Mm7t4X57EwR8fvWjs/wwAZVJ0X4VRCkLNM6iRzf0Io7e9+HIp6mD+RF57CgFldUncwGrl5nIszF b64GxSYCrj2xkdXAKKauFpc+1EvKkRDjnXfqlT X-Received: by 2002:a05:6512:e81:b0:51b:6ed6:af3f with SMTP id 2adb3069b0e04-5221006e630mr82583e87.16.1715274058822; Thu, 09 May 2024 10:00:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IERzlguJhi1uTwj2+3mHaHADh5DS+tmJn6GHgD9UDre8mMOfIWMRii+3e2JZ5PaXFxTmqi71w== X-Received: by 2002:a05:6512:e81:b0:51b:6ed6:af3f with SMTP id 2adb3069b0e04-5221006e630mr82562e87.16.1715274058295; Thu, 09 May 2024 10:00:58 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a1781d342sm92958566b.6.2024.05.09.10.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:00:56 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 06/13] xen: initialize legacy backends from xen_bus_init() Date: Thu, 9 May 2024 19:00:37 +0200 Message-ID: <20240509170044.190795-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Prepare for moving the calls to xen_be_register() under the control of xen_bus_init(), using the normal xen_backend_init() method that is used by the "modern" backends. This requires the xenstore global variable to be initialized, which is done by xen_be_init(). To ensure that everything is ready at the time the xen_backend_init() functions are called, remove the xen_be_init() function from all the boards and place it directly in xen_bus_init(). Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé --- hw/i386/pc.c | 1 - hw/xen/xen-bus.c | 4 ++++ hw/xen/xen-hvm-common.c | 2 -- hw/xenpv/xen_machine_pv.c | 5 +---- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 505ea750f4d..19f21953b4a 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1250,7 +1250,6 @@ void pc_basic_device_init(struct PCMachineState *pcms, pci_create_simple(pcms->pcibus, -1, "xen-platform"); } xen_bus_init(); - xen_be_init(); } #endif diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c index fb82cc33e48..95b207ac8b4 100644 --- a/hw/xen/xen-bus.c +++ b/hw/xen/xen-bus.c @@ -13,6 +13,7 @@ #include "hw/sysbus.h" #include "hw/xen/xen.h" #include "hw/xen/xen-backend.h" +#include "hw/xen/xen-legacy-backend.h" /* xen_be_init() */ #include "hw/xen/xen-bus.h" #include "hw/xen/xen-bus-helper.h" #include "monitor/monitor.h" @@ -329,6 +330,9 @@ static void xen_bus_realize(BusState *bus, Error **errp) goto fail; } + /* Initialize legacy backend core & drivers */ + xen_be_init(); + if (xs_node_scanf(xenbus->xsh, XBT_NULL, "", /* domain root node */ "domid", NULL, "%u", &domid) == 1) { xenbus->backend_id = domid; diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hvm-common.c index 1627da73982..2d1b0321214 100644 --- a/hw/xen/xen-hvm-common.c +++ b/hw/xen/xen-hvm-common.c @@ -872,8 +872,6 @@ void xen_register_ioreq(XenIOState *state, unsigned int max_cpus, xen_bus_init(); - xen_be_init(); - return; err: diff --git a/hw/xenpv/xen_machine_pv.c b/hw/xenpv/xen_machine_pv.c index 1130d1a1479..b500ce09891 100644 --- a/hw/xenpv/xen_machine_pv.c +++ b/hw/xenpv/xen_machine_pv.c @@ -34,8 +34,7 @@ static void xen_init_pv(MachineState *machine) { setup_xen_backend_ops(); - /* Initialize backend core & drivers */ - xen_be_init(); + xen_bus_init(); switch (xen_mode) { case XEN_ATTACH: @@ -60,8 +59,6 @@ static void xen_init_pv(MachineState *machine) vga_interface_created = true; } - xen_bus_init(); - /* config cleanup hook */ atexit(xen_config_cleanup); } From patchwork Thu May 9 17:00:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC6AEC25B74 for ; Thu, 9 May 2024 17:03:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s578q-0002Gu-8z; Thu, 09 May 2024 13:01:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578o-0002GF-8i for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:10 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578m-0003Xk-6V for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274065; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yfht/8nDL9dNmoJdt0AfWcd+ja7bm3XnHVnoXh9KG24=; b=R2KldbKm3mfdHlncOiYoR/5Npcg1oxKS585huPlNi1yUeyjIe6Bg64mSjQ0sNjwW8M/BX9 6gvRsvP+pUIAU3A8lmdHuTVI6Li0xaEL5SrgQVE2jbFcde4zoYI2k05oQv7aSL+nIIVom0 RRTJ7hKetdIrdImn+xrayNcdrcTItY0= Received: from mail-lf1-f69.google.com (mail-lf1-f69.google.com [209.85.167.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-445-Q25JQfYrOnmY29JYexrn2g-1; Thu, 09 May 2024 13:01:04 -0400 X-MC-Unique: Q25JQfYrOnmY29JYexrn2g-1 Received: by mail-lf1-f69.google.com with SMTP id 2adb3069b0e04-51ffd1181e4so1148849e87.2 for ; Thu, 09 May 2024 10:01:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274062; x=1715878862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yfht/8nDL9dNmoJdt0AfWcd+ja7bm3XnHVnoXh9KG24=; b=Mxey30h84Cgk/9Tw6idPDTM16XXkwja6xP+kjFzYTf+QvqtxaCWIaEgSczMzRqWn6r a4hz5UtixrSu2dpBk5Z1YyD8jYbBjOFHk2g/h0y/q1V3BRwugIxeWOLNjGtKcHSkQjyA QK58/cCDjkddDFWZVXrsk3pvaP/iT1v06bnXK1in9wSHWPq+PyxDEAhmQ7ONhwfU0zdu BfeHJ6hy5je/3rVeZJvWjSoZOcVOPDVA5JzViqxjHoUnsceLOQjc3/44mWpS2/Y8SeqB oLCTjeLpjr32i7hvjCnGo5olzlnKnJue85KVFWTc/2O9S58duIm3fBCVjJdjZju51jfc iwnw== X-Gm-Message-State: AOJu0Yw34NDSciBopBLfkQ+bdOrsr1m5BBUWgCskf9vvQNjsfS8oUubc AVAxx5m8hP6rOOidbQ+tExONwpdA3BAUr0oGZ6qRBjsiQi4S9kPrrdXXaUQ8OTedFUryuf96Xwf Zk+BhFajNMH7dXNYLV0L5DWY3p5nn/F0cuIJxwwPiMaegmefiWo64S8j8Auex+avxu80OVWJV9r uGecIcjWZ7hKe0LD3VUwHqq91v39/4BXApmMeu X-Received: by 2002:a05:6512:3f20:b0:51d:4383:9e59 with SMTP id 2adb3069b0e04-5220f86c902mr140668e87.0.1715274061674; Thu, 09 May 2024 10:01:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHnvI2p0M3PxeHQAPpxwPMeRQ4GavaRnF8Fj08jaaeJbRuWyShBlEDzg7q+Zg4Bv+N9hTTTLg== X-Received: by 2002:a05:6512:3f20:b0:51d:4383:9e59 with SMTP id 2adb3069b0e04-5220f86c902mr140603e87.0.1715274060298; Thu, 09 May 2024 10:01:00 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a178a9d9csm91480766b.74.2024.05.09.10.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:00:59 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 07/13] xen: register legacy backends via xen_backend_init Date: Thu, 9 May 2024 19:00:38 +0200 Message-ID: <20240509170044.190795-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org It is okay to register legacy backends in the middle of xen_bus_init(). All that the registration does is record the existence of the backend in xenstore. This makes it possible to remove them from the build without introducing undefined symbols in xen_be_init(). It also removes the need for the backend_register callback, whose only purpose is to avoid registering nonfunctional backends. Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé --- include/hw/xen/xen-legacy-backend.h | 14 ++------------ include/hw/xen/xen_pvdev.h | 1 - hw/9pfs/xen-9p-backend.c | 8 +++++++- hw/display/xenfb.c | 8 +++++++- hw/usb/xen-usb.c | 14 ++++---------- hw/xen/xen-legacy-backend.c | 16 ---------------- 6 files changed, 20 insertions(+), 41 deletions(-) diff --git a/include/hw/xen/xen-legacy-backend.h b/include/hw/xen/xen-legacy-backend.h index 2cca1747786..979c4ea04c5 100644 --- a/include/hw/xen/xen-legacy-backend.h +++ b/include/hw/xen/xen-legacy-backend.h @@ -66,18 +66,8 @@ static inline void xen_be_unmap_grant_ref(struct XenLegacyDevice *xendev, return xen_be_unmap_grant_refs(xendev, ptr, &ref, 1); } -/* actual backend drivers */ -extern struct XenDevOps xen_console_ops; /* xen_console.c */ -extern struct XenDevOps xen_kbdmouse_ops; /* xen_framebuffer.c */ -extern struct XenDevOps xen_framebuffer_ops; /* xen_framebuffer.c */ -extern struct XenDevOps xen_blkdev_ops; /* xen_disk.c */ -#ifdef CONFIG_VIRTFS -extern struct XenDevOps xen_9pfs_ops; /* xen-9p-backend.c */ -#endif -extern struct XenDevOps xen_netdev_ops; /* xen_nic.c */ -#ifdef CONFIG_USB_LIBUSB -extern struct XenDevOps xen_usb_ops; /* xen-usb.c */ -#endif +/* backend drivers not included in all machines */ +extern struct XenDevOps xen_framebuffer_ops; /* xenfb.c */ /* configuration (aka xenbus setup) */ void xen_config_cleanup(void); diff --git a/include/hw/xen/xen_pvdev.h b/include/hw/xen/xen_pvdev.h index ddad4b9f36a..fdf84f47af1 100644 --- a/include/hw/xen/xen_pvdev.h +++ b/include/hw/xen/xen_pvdev.h @@ -29,7 +29,6 @@ struct XenDevOps { const char *node); void (*frontend_changed)(struct XenLegacyDevice *xendev, const char *node); - int (*backend_register)(void); }; struct XenLegacyDevice { diff --git a/hw/9pfs/xen-9p-backend.c b/hw/9pfs/xen-9p-backend.c index 4aa9c8c736d..a3ac53f989e 100644 --- a/hw/9pfs/xen-9p-backend.c +++ b/hw/9pfs/xen-9p-backend.c @@ -513,7 +513,7 @@ static void xen_9pfs_alloc(struct XenLegacyDevice *xendev) xenstore_write_be_int(xendev, "max-ring-page-order", MAX_RING_ORDER); } -struct XenDevOps xen_9pfs_ops = { +static struct XenDevOps xen_9pfs_ops = { .size = sizeof(Xen9pfsDev), .flags = DEVOPS_FLAG_NEED_GNTDEV, .alloc = xen_9pfs_alloc, @@ -522,3 +522,9 @@ struct XenDevOps xen_9pfs_ops = { .disconnect = xen_9pfs_disconnect, .free = xen_9pfs_free, }; + +static void xen_9pfs_register_backend(void) +{ + xen_be_register("9pfs", &xen_9pfs_ops); +} +xen_backend_init(xen_9pfs_register_backend); diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c index b2130a0d700..27536bfce0c 100644 --- a/hw/display/xenfb.c +++ b/hw/display/xenfb.c @@ -972,7 +972,7 @@ static void fb_event(struct XenLegacyDevice *xendev) /* -------------------------------------------------------------------- */ -struct XenDevOps xen_kbdmouse_ops = { +static struct XenDevOps xen_kbdmouse_ops = { .size = sizeof(struct XenInput), .init = input_init, .initialise = input_initialise, @@ -995,3 +995,9 @@ static const GraphicHwOps xenfb_ops = { .gfx_update = xenfb_update, .ui_info = xenfb_ui_info, }; + +static void xen_vkbd_register_backend(void) +{ + xen_be_register("vkbd", &xen_kbdmouse_ops); +} +xen_backend_init(xen_vkbd_register_backend); diff --git a/hw/usb/xen-usb.c b/hw/usb/xen-usb.c index 09ec326aeae..416623f956a 100644 --- a/hw/usb/xen-usb.c +++ b/hw/usb/xen-usb.c @@ -1083,7 +1083,7 @@ static void usbback_event(struct XenLegacyDevice *xendev) qemu_bh_schedule(usbif->bh); } -struct XenDevOps xen_usb_ops = { +static struct XenDevOps xen_usb_ops = { .size = sizeof(struct usbback_info), .flags = DEVOPS_FLAG_NEED_GNTDEV, .init = usbback_init, @@ -1095,15 +1095,9 @@ struct XenDevOps xen_usb_ops = { .event = usbback_event, }; -#else /* USBIF_SHORT_NOT_OK */ - -static int usbback_not_supported(void) +static void xen_usb_register_backend(void) { - return -EINVAL; + xen_be_register("qusb", &xen_usb_ops); } - -struct XenDevOps xen_usb_ops = { - .backend_register = usbback_not_supported, -}; - +xen_backend_init(xen_usb_register_backend); #endif diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c index 124dd5f3d68..6f0b300a421 100644 --- a/hw/xen/xen-legacy-backend.c +++ b/hw/xen/xen-legacy-backend.c @@ -622,27 +622,11 @@ void xen_be_init(void) qbus_set_bus_hotplug_handler(xen_sysbus); xen_set_dynamic_sysbus(); - - xen_be_register("vkbd", &xen_kbdmouse_ops); -#ifdef CONFIG_VIRTFS - xen_be_register("9pfs", &xen_9pfs_ops); -#endif -#ifdef CONFIG_USB_LIBUSB - xen_be_register("qusb", &xen_usb_ops); -#endif } int xen_be_register(const char *type, struct XenDevOps *ops) { char path[50]; - int rc; - - if (ops->backend_register) { - rc = ops->backend_register(); - if (rc) { - return rc; - } - } snprintf(path, sizeof(path), "device-model/%u/backends/%s", xen_domid, type); From patchwork Thu May 9 17:00:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2415C10F1A for ; Thu, 9 May 2024 17:02:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s578s-0002Hb-WB; Thu, 09 May 2024 13:01:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578p-0002GS-0b for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:11 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578m-0003YB-Vs for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274068; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lgqJCblTtWKOGjneOII9w24G3R5kWdUK9+a6Wm03r3E=; b=hu7qxq05qbpYlws5ewprlkip9E5a6RvU1X/1y/6QCHqYk4+H6ZKs+lDy+3NCvZcnZJ5o/b HpnYpPxU/6dasUQEK+ErboANg3h5yrPyO8vOcbjo+rmQPTRq15l24mhy2ir11Sk/jcGj2F vaYNk3wXodo4cF9HE25T8+xqIq7PnhE= Received: from mail-lf1-f69.google.com (mail-lf1-f69.google.com [209.85.167.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-392-Dw_GSiN-N12x3ZK0erYOQg-1; Thu, 09 May 2024 13:01:06 -0400 X-MC-Unique: Dw_GSiN-N12x3ZK0erYOQg-1 Received: by mail-lf1-f69.google.com with SMTP id 2adb3069b0e04-5206ef0d6fdso961255e87.3 for ; Thu, 09 May 2024 10:01:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274064; x=1715878864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lgqJCblTtWKOGjneOII9w24G3R5kWdUK9+a6Wm03r3E=; b=u1rqKT/oTJAGwepCxnkDICLZTnsw/uwIv8Q5GPn1IdigO86RSIuGaExRdxWc1BovwP eME2HIab7ZVGlTzLfnNuhPr1tmeIyur0y2WHsRXOeRLc+4oVuWrhwcSPSkufOQp61PEB UM2sK/zALK/+ig+RfDU2mqRc3LlJkAnyFBNRAkO3/4qe8FKJGGVKYxd7bW0mXCqwK/ng tqualg0fl04TooYZLoVfYYD5d0TGpjlkmijJQCNmbvdAERwqgoMfrB7ks3eitzlu2xy6 B9hUeLqYpq+0NOwFBagXyRu0hKGhF9RiqWjDGMGXhFPaSGGynWWCt1kNv+6csg321iJK dk5w== X-Gm-Message-State: AOJu0Yy79M1ND6z6k3Mm6Y5ykBRameWw1jVFiJ62GocA4nrSe8BbN0aO 6Q9rMcZrJGcuwVrf0AjGu6UAqns92XJS5FiW0giaofDhWXn+NH0m07Gk0gwoJ0X1LG8Bj6O+b1U 6C6ESOSGsl9lE6e1UQktPcieH7KwjiySq4AEXdwSzC2ZDT/nb4Vjw2/+JGWV1OzuyYVnBk0Jdam kthOMUN9vbxlpMUiG/ZMv3kZUJVpiBWC5dfZFp X-Received: by 2002:a19:e043:0:b0:51d:2529:7c4d with SMTP id 2adb3069b0e04-5220f646013mr98117e87.0.1715274063955; Thu, 09 May 2024 10:01:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFBNPmqz2/dhBivLLDbKihMa1v+CFAs1PRZ6MxFKeBXvgFcB0GX88zY4XFkXUWqcloEYjz5Lw== X-Received: by 2002:a19:e043:0:b0:51d:2529:7c4d with SMTP id 2adb3069b0e04-5220f646013mr98108e87.0.1715274063596; Thu, 09 May 2024 10:01:03 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a17b18110sm92085866b.225.2024.05.09.10.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:01:02 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 08/13] i386: correctly select code in hw/i386 that depends on other components Date: Thu, 9 May 2024 19:00:39 +0200 Message-ID: <20240509170044.190795-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org fw_cfg.c and vapic.c are currently included unconditionally but depend on other components. vapic.c depends on the local APIC, while fw_cfg.c includes a piece of AML builder code that depends on CONFIG_ACPI. Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- hw/i386/fw_cfg.c | 2 ++ hw/i386/meson.build | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index d802d2787f0..6e0d9945d07 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -203,6 +203,7 @@ void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); } +#ifdef CONFIG_ACPI void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) { /* @@ -229,3 +230,4 @@ void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg) aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); } +#endif diff --git a/hw/i386/meson.build b/hw/i386/meson.build index d8b70ef3e9c..d9da676038c 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -1,12 +1,12 @@ i386_ss = ss.source_set() i386_ss.add(files( 'fw_cfg.c', - 'vapic.c', 'e820_memory_layout.c', 'multiboot.c', 'x86.c', )) +i386_ss.add(when: 'CONFIG_APIC', if_true: files('vapic.c')) i386_ss.add(when: 'CONFIG_X86_IOMMU', if_true: files('x86-iommu.c'), if_false: files('x86-iommu-stub.c')) i386_ss.add(when: 'CONFIG_AMD_IOMMU', if_true: files('amd_iommu.c'), From patchwork Thu May 9 17:00:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6CF68C25B10 for ; Thu, 9 May 2024 17:03:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s578t-0002He-0h; Thu, 09 May 2024 13:01:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578q-0002H0-Ii for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:12 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578o-0003YX-QY for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274069; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LVIFiD89QhCcDd/5PLOQqXkqJ//w22v0cKCzdxBuTYI=; b=Fz5yOeZm/bgHlt67vJ6CK3Z0zcN5GzIAjj84e8R/BvCBOxWtgoaOSbbtoW0Crx2d5N7hxZ FW2kuj60o8FJPGibvWMzQFxonwDfnYFfEV1OiHu6cLNFXJXOgyuE432gvuK+zv1edAA0GS YKc/FibNUxW8rcWqdycR7t/bzR2qX+o= Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-345-lp0BVV2tOQGQgNbJ8A2kTA-1; Thu, 09 May 2024 13:01:08 -0400 X-MC-Unique: lp0BVV2tOQGQgNbJ8A2kTA-1 Received: by mail-ed1-f71.google.com with SMTP id 4fb4d7f45d1cf-572cbbdb450so552937a12.1 for ; Thu, 09 May 2024 10:01:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274066; x=1715878866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LVIFiD89QhCcDd/5PLOQqXkqJ//w22v0cKCzdxBuTYI=; b=qeLUIehD5oiLnMefOQHNIjK97AKY9oCogK6GzmIkJSmZOk6LXvhEQ0wtq7mzX7ZD0+ MXE+3YWvIoeItiYsh6ww2luedIKm0Tf+7fZHvo2n+iXsHAUUn2FVNFk9+ivpKWp8CKlQ dzdsGSsbHPzintnpgEfwXoGwr1pMuAgVZh8eRRC05npBkM9OCl3c5rxKEeiNP53l33i3 2rmNPuTB8weZr6iZhw2lkqp1YZ93iXHj8LpK7Z64CypucO0H/bMfLFoVtRx7r4HXrRmd jLA9nQf1OiJ/Tl57qbzy1SuWDy8LpTx+txv/HeeYlFQOw3772xUZ4b5pfMcnw3RjwJHT nbXg== X-Gm-Message-State: AOJu0Ywxc7OvWgchsP3Zy3ywT1Zrg44GRJvHI3Ld7gG0r5cDNFRTxdnt uGyRwrsh/D6/K/DoCxRxnBQ7VjKlaDRQzF2cz8ihy/yPcmr6nSNcG3pESI7He8+FParIGZgYtsB QFKwhYxMnmmmiiKV+zzNtgzXhTTUMNPXlUj2Yo24P8qRhK72CxITW8JRu/iJYvgGkVRNEB6ITTm kYapcVpxJt72tCibteCgx66celP/C90VsxmnQF X-Received: by 2002:a50:ab05:0:b0:570:5b3d:91f with SMTP id 4fb4d7f45d1cf-5734d5ceb5emr197384a12.23.1715274066206; Thu, 09 May 2024 10:01:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFb8A6sgQ+MbhQHdnzOlhWhAhzTxAFxIX9acXMl9AuIGc2QA5bXTpO3yKD+XUoHTB/N9MMblQ== X-Received: by 2002:a50:ab05:0:b0:570:5b3d:91f with SMTP id 4fb4d7f45d1cf-5734d5ceb5emr197366a12.23.1715274065865; Thu, 09 May 2024 10:01:05 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733bbbfcfesm891663a12.0.2024.05.09.10.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:01:04 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 09/13] i386: pc: remove unnecessary MachineClass overrides Date: Thu, 9 May 2024 19:00:40 +0200 Message-ID: <20240509170044.190795-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There is no need to override these fields of MachineClass because they are already set to the right value in the superclass. Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- include/hw/i386/x86.h | 4 ---- hw/i386/pc.c | 3 --- hw/i386/x86.c | 6 +++--- 3 files changed, 3 insertions(+), 10 deletions(-) diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index d7b7d3f3ce0..c2062db13f5 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -114,10 +114,6 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms, void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp); void x86_cpus_init(X86MachineState *pcms, int default_cpu_version); -CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms, - unsigned cpu_index); -int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx); -const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms); CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx); void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count); void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 19f21953b4a..bfb46e9b548 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1826,9 +1826,6 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) assert(!mc->get_hotplug_handler); mc->get_hotplug_handler = pc_get_hotplug_handler; mc->hotplug_allowed = pc_hotplug_allowed; - mc->cpu_index_to_instance_props = x86_cpu_index_to_props; - mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; - mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; mc->auto_enable_numa_with_memhp = true; mc->auto_enable_numa_with_memdev = true; mc->has_hotpluggable_cpus = true; diff --git a/hw/i386/x86.c b/hw/i386/x86.c index c61f4ebfa6a..fcef652c1e3 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -443,7 +443,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, numa_cpu_pre_plug(cpu_slot, dev, errp); } -CpuInstanceProperties +static CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) { MachineClass *mc = MACHINE_GET_CLASS(ms); @@ -453,7 +453,7 @@ x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) return possible_cpus->cpus[cpu_index].props; } -int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) +static int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) { X86CPUTopoIDs topo_ids; X86MachineState *x86ms = X86_MACHINE(ms); @@ -467,7 +467,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) return topo_ids.pkg_id % ms->numa_state->num_nodes; } -const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) +static const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) { X86MachineState *x86ms = X86_MACHINE(ms); unsigned int max_cpus = ms->smp.max_cpus; From patchwork Thu May 9 17:00:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5CF9C10F1A for ; Thu, 9 May 2024 17:02:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s5798-0002R9-PC; Thu, 09 May 2024 13:01:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s5794-0002Pa-Se for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:27 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578z-0003aj-V9 for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274079; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TDpGr/IvbLSmpeSvpHUhFYvgrYYZWU4FFB6JgViCNhc=; b=Yrdj3VqabB/9QTeQDzYYTJYXtEKzQ1WpTG5FUw6yEoKJzMf3XhZ90OjHKA/ioKB1pzDDLk +JV0y1EmiYmdoZ7bRjbChr78/9XpLmEjL1iL94FW0L91sCl7fT1KzncTyW91gYiWkauEj7 c0GZ9RairnGi/eygRRajOBuTGhXIq8M= Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-154-gESthRvPM7KG4fbYLXTjdQ-1; Thu, 09 May 2024 13:01:14 -0400 X-MC-Unique: gESthRvPM7KG4fbYLXTjdQ-1 Received: by mail-ej1-f69.google.com with SMTP id a640c23a62f3a-a51fdbd06c8so75413666b.3 for ; Thu, 09 May 2024 10:01:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274071; x=1715878871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TDpGr/IvbLSmpeSvpHUhFYvgrYYZWU4FFB6JgViCNhc=; b=StJzXD8bv/mmAmHCRYDDJ8kcZBry5wgiHiiZltAVjl70zUDBxxpEqefWxlhbCbw3bR p5o95XZFWWhSV/+oVnNILczl5Fbona2Y1gF42lzR0HlQnN8P4ZmGKASeq2xjwqWK2Qof 6AUoNfEacp+JNcWton1wUYgyqE19zCEydFmGy9FR4l+WvBGTtVDBRKKsjk5wf1h3mIaC VPM392Y73pT+qn5kIAfKr+qA7/K50vcAtsbmZtZDyHk88nnJgcXqyoW4ZLb5mR4tvtBE 0QYDmzGvQ9eYSiLxNzDENNV1VVuVG+pxK4lh3JYKvw0R7ZiYOBX/L8a5/0aH0VKMwvCI Fk4g== X-Gm-Message-State: AOJu0YzfXwoa/WnnyGAud4bNVOTwZYOpeMWqHJrbwamp6+mpG1ADtOCp 9hsxvOHdSbFE5R6YtVmhxPFbG2iPGASNVXks7aS5V5RvnJbwimZPk3lr4Iqjj2SBGsSX8gf7Upx 5rJDmK+N9gbw7IALKHOQ7nccV+iEQXa+rjV9uvN9Dba2e52NEHv5aGmsiVvTo2t8T6lXq5sxLvF ocBKaHfqm5gbcOuE896cwd0XyzfeXIeSy4HN/0 X-Received: by 2002:a17:907:1118:b0:a59:c5c2:a320 with SMTP id a640c23a62f3a-a5a2d581b19mr15032666b.23.1715274069952; Thu, 09 May 2024 10:01:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGv+bwtzbFPKMoVJ1QqwWeWeeTOF5faDgGol3DXZXghlDqQJspCl79lcGpiRLPUKWtgjO/QMA== X-Received: by 2002:a17:907:1118:b0:a59:c5c2:a320 with SMTP id a640c23a62f3a-a5a2d581b19mr15028166b.23.1715274068730; Thu, 09 May 2024 10:01:08 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a1789247csm91575566b.82.2024.05.09.10.01.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:01:07 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 10/13] hw/i386: split x86.c in multiple parts Date: Thu, 9 May 2024 19:00:41 +0200 Message-ID: <20240509170044.190795-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Keep the basic X86MachineState definition in x86.c. Move out functions that are only needed by other files: x86-common.c for the pc and microvm machines, x86-cpu.c for those used by accelerator code. Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- include/hw/i386/x86.h | 6 +- hw/i386/x86-common.c | 1007 +++++++++++++++++++++++++++++++++++++++ hw/i386/x86-cpu.c | 97 ++++ hw/i386/x86.c | 1052 +---------------------------------------- hw/i386/meson.build | 4 +- 5 files changed, 1113 insertions(+), 1053 deletions(-) create mode 100644 hw/i386/x86-common.c create mode 100644 hw/i386/x86-cpu.c diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index c2062db13f5..b006f16b8d3 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -21,6 +21,7 @@ #include "exec/memory.h" #include "hw/boards.h" +#include "hw/i386/topology.h" #include "hw/intc/ioapic.h" #include "hw/isa/isa.h" #include "qom/object.h" @@ -109,12 +110,11 @@ struct X86MachineState { #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86") OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE) -uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms, +void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms); +uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, unsigned int cpu_index); -void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp); void x86_cpus_init(X86MachineState *pcms, int default_cpu_version); -CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx); void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count); void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c new file mode 100644 index 00000000000..67b03c913a5 --- /dev/null +++ b/hw/i386/x86-common.c @@ -0,0 +1,1007 @@ +/* + * Copyright (c) 2003-2004 Fabrice Bellard + * Copyright (c) 2019, 2024 Red Hat, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qemu/cutils.h" +#include "qemu/units.h" +#include "qemu/datadir.h" +#include "qapi/error.h" +#include "sysemu/numa.h" +#include "sysemu/sysemu.h" +#include "sysemu/xen.h" +#include "trace.h" + +#include "hw/i386/x86.h" +#include "target/i386/cpu.h" +#include "hw/rtc/mc146818rtc.h" +#include "target/i386/sev.h" + +#include "hw/acpi/cpu_hotplug.h" +#include "hw/irq.h" +#include "hw/loader.h" +#include "multiboot.h" +#include "elf.h" +#include "standard-headers/asm-x86/bootparam.h" +#include CONFIG_DEVICES +#include "kvm/kvm_i386.h" + +#ifdef CONFIG_XEN_EMU +#include "hw/xen/xen.h" +#include "hw/i386/kvm/xen_evtchn.h" +#endif + +/* Physical Address of PVH entry point read from kernel ELF NOTE */ +static size_t pvh_start_addr; + +static void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp) +{ + Object *cpu = object_new(MACHINE(x86ms)->cpu_type); + + if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) { + goto out; + } + qdev_realize(DEVICE(cpu), NULL, errp); + +out: + object_unref(cpu); +} + +void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) +{ + int i; + const CPUArchIdList *possible_cpus; + MachineState *ms = MACHINE(x86ms); + MachineClass *mc = MACHINE_GET_CLASS(x86ms); + + x86_cpu_set_default_version(default_cpu_version); + + /* + * Calculates the limit to CPU APIC ID values + * + * Limit for the APIC ID value, so that all + * CPU APIC IDs are < x86ms->apic_id_limit. + * + * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). + */ + x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms, + ms->smp.max_cpus - 1) + 1; + + /* + * Can we support APIC ID 255 or higher? With KVM, that requires + * both in-kernel lapic and X2APIC userspace API. + * + * kvm_enabled() must go first to ensure that kvm_* references are + * not emitted for the linker to consume (kvm_enabled() is + * a literal `0` in configurations where kvm_* aren't defined) + */ + if (kvm_enabled() && x86ms->apic_id_limit > 255 && + kvm_irqchip_in_kernel() && !kvm_enable_x2apic()) { + error_report("current -smp configuration requires kernel " + "irqchip and X2APIC API support."); + exit(EXIT_FAILURE); + } + + if (kvm_enabled()) { + kvm_set_max_apic_id(x86ms->apic_id_limit); + } + + if (!kvm_irqchip_in_kernel()) { + apic_set_max_apic_id(x86ms->apic_id_limit); + } + + possible_cpus = mc->possible_cpu_arch_ids(ms); + for (i = 0; i < ms->smp.cpus; i++) { + x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); + } +} + +void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus_count) +{ + MC146818RtcState *rtc = MC146818_RTC(s); + + if (cpus_count > 0xff) { + /* + * If the number of CPUs can't be represented in 8 bits, the + * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just + * to make old BIOSes fail more predictably. + */ + mc146818rtc_set_cmos_data(rtc, 0x5f, 0); + } else { + mc146818rtc_set_cmos_data(rtc, 0x5f, cpus_count - 1); + } +} + +static int x86_apic_cmp(const void *a, const void *b) +{ + CPUArchId *apic_a = (CPUArchId *)a; + CPUArchId *apic_b = (CPUArchId *)b; + + return apic_a->arch_id - apic_b->arch_id; +} + +/* + * returns pointer to CPUArchId descriptor that matches CPU's apic_id + * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no + * entry corresponding to CPU's apic_id returns NULL. + */ +static CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) +{ + CPUArchId apic_id, *found_cpu; + + apic_id.arch_id = id; + found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, + ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), + x86_apic_cmp); + if (found_cpu && idx) { + *idx = found_cpu - ms->possible_cpus->cpus; + } + return found_cpu; +} + +void x86_cpu_plug(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + CPUArchId *found_cpu; + Error *local_err = NULL; + X86CPU *cpu = X86_CPU(dev); + X86MachineState *x86ms = X86_MACHINE(hotplug_dev); + + if (x86ms->acpi_dev) { + hotplug_handler_plug(x86ms->acpi_dev, dev, &local_err); + if (local_err) { + goto out; + } + } + + /* increment the number of CPUs */ + x86ms->boot_cpus++; + if (x86ms->rtc) { + x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); + } + if (x86ms->fw_cfg) { + fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); + } + + found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); + found_cpu->cpu = CPU(dev); +out: + error_propagate(errp, local_err); +} + +void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + int idx = -1; + X86CPU *cpu = X86_CPU(dev); + X86MachineState *x86ms = X86_MACHINE(hotplug_dev); + + if (!x86ms->acpi_dev) { + error_setg(errp, "CPU hot unplug not supported without ACPI"); + return; + } + + x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); + assert(idx != -1); + if (idx == 0) { + error_setg(errp, "Boot CPU is unpluggable"); + return; + } + + hotplug_handler_unplug_request(x86ms->acpi_dev, dev, + errp); +} + +void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + CPUArchId *found_cpu; + Error *local_err = NULL; + X86CPU *cpu = X86_CPU(dev); + X86MachineState *x86ms = X86_MACHINE(hotplug_dev); + + hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); + if (local_err) { + goto out; + } + + found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); + found_cpu->cpu = NULL; + qdev_unrealize(dev); + + /* decrement the number of CPUs */ + x86ms->boot_cpus--; + /* Update the number of CPUs in CMOS */ + x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); + fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); + out: + error_propagate(errp, local_err); +} + +void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + int idx; + CPUState *cs; + CPUArchId *cpu_slot; + X86CPUTopoIDs topo_ids; + X86CPU *cpu = X86_CPU(dev); + CPUX86State *env = &cpu->env; + MachineState *ms = MACHINE(hotplug_dev); + X86MachineState *x86ms = X86_MACHINE(hotplug_dev); + unsigned int smp_cores = ms->smp.cores; + unsigned int smp_threads = ms->smp.threads; + X86CPUTopoInfo topo_info; + + if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { + error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", + ms->cpu_type); + return; + } + + if (x86ms->acpi_dev) { + Error *local_err = NULL; + + hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev, + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + } + + init_topo_info(&topo_info, x86ms); + + env->nr_dies = ms->smp.dies; + + /* + * If APIC ID is not set, + * set it based on socket/die/core/thread properties. + */ + if (cpu->apic_id == UNASSIGNED_APIC_ID) { + int max_socket = (ms->smp.max_cpus - 1) / + smp_threads / smp_cores / ms->smp.dies; + + /* + * die-id was optional in QEMU 4.0 and older, so keep it optional + * if there's only one die per socket. + */ + if (cpu->die_id < 0 && ms->smp.dies == 1) { + cpu->die_id = 0; + } + + if (cpu->socket_id < 0) { + error_setg(errp, "CPU socket-id is not set"); + return; + } else if (cpu->socket_id > max_socket) { + error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", + cpu->socket_id, max_socket); + return; + } + if (cpu->die_id < 0) { + error_setg(errp, "CPU die-id is not set"); + return; + } else if (cpu->die_id > ms->smp.dies - 1) { + error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", + cpu->die_id, ms->smp.dies - 1); + return; + } + if (cpu->core_id < 0) { + error_setg(errp, "CPU core-id is not set"); + return; + } else if (cpu->core_id > (smp_cores - 1)) { + error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", + cpu->core_id, smp_cores - 1); + return; + } + if (cpu->thread_id < 0) { + error_setg(errp, "CPU thread-id is not set"); + return; + } else if (cpu->thread_id > (smp_threads - 1)) { + error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", + cpu->thread_id, smp_threads - 1); + return; + } + + topo_ids.pkg_id = cpu->socket_id; + topo_ids.die_id = cpu->die_id; + topo_ids.core_id = cpu->core_id; + topo_ids.smt_id = cpu->thread_id; + cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); + } + + cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); + if (!cpu_slot) { + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + error_setg(errp, + "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" + " APIC ID %" PRIu32 ", valid index range 0:%d", + topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, + cpu->apic_id, ms->possible_cpus->len - 1); + return; + } + + if (cpu_slot->cpu) { + error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", + idx, cpu->apic_id); + return; + } + + /* if 'address' properties socket-id/core-id/thread-id are not set, set them + * so that machine_query_hotpluggable_cpus would show correct values + */ + /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() + * once -smp refactoring is complete and there will be CPU private + * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { + error_setg(errp, "property socket-id: %u doesn't match set apic-id:" + " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, + topo_ids.pkg_id); + return; + } + cpu->socket_id = topo_ids.pkg_id; + + if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { + error_setg(errp, "property die-id: %u doesn't match set apic-id:" + " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); + return; + } + cpu->die_id = topo_ids.die_id; + + if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { + error_setg(errp, "property core-id: %u doesn't match set apic-id:" + " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, + topo_ids.core_id); + return; + } + cpu->core_id = topo_ids.core_id; + + if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { + error_setg(errp, "property thread-id: %u doesn't match set apic-id:" + " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, + topo_ids.smt_id); + return; + } + cpu->thread_id = topo_ids.smt_id; + + /* + * kvm_enabled() must go first to ensure that kvm_* references are + * not emitted for the linker to consume (kvm_enabled() is + * a literal `0` in configurations where kvm_* aren't defined) + */ + if (kvm_enabled() && hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && + !kvm_hv_vpindex_settable()) { + error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); + return; + } + + cs = CPU(cpu); + cs->cpu_index = idx; + + numa_cpu_pre_plug(cpu_slot, dev, errp); +} + +static long get_file_size(FILE *f) +{ + long where, size; + + /* XXX: on Unix systems, using fstat() probably makes more sense */ + + where = ftell(f); + fseek(f, 0, SEEK_END); + size = ftell(f); + fseek(f, where, SEEK_SET); + + return size; +} + +void gsi_handler(void *opaque, int n, int level) +{ + GSIState *s = opaque; + + trace_x86_gsi_interrupt(n, level); + switch (n) { + case 0 ... ISA_NUM_IRQS - 1: + if (s->i8259_irq[n]) { + /* Under KVM, Kernel will forward to both PIC and IOAPIC */ + qemu_set_irq(s->i8259_irq[n], level); + } + /* fall through */ + case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: +#ifdef CONFIG_XEN_EMU + /* + * Xen delivers the GSI to the Legacy PIC (not that Legacy PIC + * routing actually works properly under Xen). And then to + * *either* the PIRQ handling or the I/OAPIC depending on + * whether the former wants it. + */ + if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) { + break; + } +#endif + qemu_set_irq(s->ioapic_irq[n], level); + break; + case IO_APIC_SECONDARY_IRQBASE + ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: + qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); + break; + } +} + +void ioapic_init_gsi(GSIState *gsi_state, Object *parent) +{ + DeviceState *dev; + SysBusDevice *d; + unsigned int i; + + assert(parent); + if (kvm_ioapic_in_kernel()) { + dev = qdev_new(TYPE_KVM_IOAPIC); + } else { + dev = qdev_new(TYPE_IOAPIC); + } + object_property_add_child(parent, "ioapic", OBJECT(dev)); + d = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(d, &error_fatal); + sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); + + for (i = 0; i < IOAPIC_NUM_PINS; i++) { + gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); + } +} + +DeviceState *ioapic_init_secondary(GSIState *gsi_state) +{ + DeviceState *dev; + SysBusDevice *d; + unsigned int i; + + dev = qdev_new(TYPE_IOAPIC); + d = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(d, &error_fatal); + sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); + + for (i = 0; i < IOAPIC_NUM_PINS; i++) { + gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i); + } + return dev; +} + +/* + * The entry point into the kernel for PVH boot is different from + * the native entry point. The PVH entry is defined by the x86/HVM + * direct boot ABI and is available in an ELFNOTE in the kernel binary. + * + * This function is passed to load_elf() when it is called from + * load_elfboot() which then additionally checks for an ELF Note of + * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to + * parse the PVH entry address from the ELF Note. + * + * Due to trickery in elf_opts.h, load_elf() is actually available as + * load_elf32() or load_elf64() and this routine needs to be able + * to deal with being called as 32 or 64 bit. + * + * The address of the PVH entry point is saved to the 'pvh_start_addr' + * global variable. (although the entry point is 32-bit, the kernel + * binary can be either 32-bit or 64-bit). + */ +static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) +{ + size_t *elf_note_data_addr; + + /* Check if ELF Note header passed in is valid */ + if (arg1 == NULL) { + return 0; + } + + if (is64) { + struct elf64_note *nhdr64 = (struct elf64_note *)arg1; + uint64_t nhdr_size64 = sizeof(struct elf64_note); + uint64_t phdr_align = *(uint64_t *)arg2; + uint64_t nhdr_namesz = nhdr64->n_namesz; + + elf_note_data_addr = + ((void *)nhdr64) + nhdr_size64 + + QEMU_ALIGN_UP(nhdr_namesz, phdr_align); + + pvh_start_addr = *elf_note_data_addr; + } else { + struct elf32_note *nhdr32 = (struct elf32_note *)arg1; + uint32_t nhdr_size32 = sizeof(struct elf32_note); + uint32_t phdr_align = *(uint32_t *)arg2; + uint32_t nhdr_namesz = nhdr32->n_namesz; + + elf_note_data_addr = + ((void *)nhdr32) + nhdr_size32 + + QEMU_ALIGN_UP(nhdr_namesz, phdr_align); + + pvh_start_addr = *(uint32_t *)elf_note_data_addr; + } + + return pvh_start_addr; +} + +static bool load_elfboot(const char *kernel_filename, + int kernel_file_size, + uint8_t *header, + size_t pvh_xen_start_addr, + FWCfgState *fw_cfg) +{ + uint32_t flags = 0; + uint32_t mh_load_addr = 0; + uint32_t elf_kernel_size = 0; + uint64_t elf_entry; + uint64_t elf_low, elf_high; + int kernel_size; + + if (ldl_p(header) != 0x464c457f) { + return false; /* no elfboot */ + } + + bool elf_is64 = header[EI_CLASS] == ELFCLASS64; + flags = elf_is64 ? + ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; + + if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ + error_report("elfboot unsupported flags = %x", flags); + exit(1); + } + + uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; + kernel_size = load_elf(kernel_filename, read_pvh_start_addr, + NULL, &elf_note_type, &elf_entry, + &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE, + 0, 0); + + if (kernel_size < 0) { + error_report("Error while loading elf kernel"); + exit(1); + } + mh_load_addr = elf_low; + elf_kernel_size = elf_high - elf_low; + + if (pvh_start_addr == 0) { + error_report("Error loading uncompressed kernel without PVH ELF Note"); + exit(1); + } + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); + + return true; +} + +void x86_load_linux(X86MachineState *x86ms, + FWCfgState *fw_cfg, + int acpi_data_size, + bool pvh_enabled) +{ + bool linuxboot_dma_enabled = X86_MACHINE_GET_CLASS(x86ms)->fwcfg_dma_enabled; + uint16_t protocol; + int setup_size, kernel_size, cmdline_size; + int dtb_size, setup_data_offset; + uint32_t initrd_max; + uint8_t header[8192], *setup, *kernel; + hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; + FILE *f; + char *vmode; + MachineState *machine = MACHINE(x86ms); + struct setup_data *setup_data; + const char *kernel_filename = machine->kernel_filename; + const char *initrd_filename = machine->initrd_filename; + const char *dtb_filename = machine->dtb; + const char *kernel_cmdline = machine->kernel_cmdline; + SevKernelLoaderContext sev_load_ctx = {}; + + /* Align to 16 bytes as a paranoia measure */ + cmdline_size = (strlen(kernel_cmdline) + 16) & ~15; + + /* load the kernel header */ + f = fopen(kernel_filename, "rb"); + if (!f) { + fprintf(stderr, "qemu: could not open kernel file '%s': %s\n", + kernel_filename, strerror(errno)); + exit(1); + } + + kernel_size = get_file_size(f); + if (!kernel_size || + fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != + MIN(ARRAY_SIZE(header), kernel_size)) { + fprintf(stderr, "qemu: could not load kernel '%s': %s\n", + kernel_filename, strerror(errno)); + exit(1); + } + + /* kernel protocol version */ + if (ldl_p(header + 0x202) == 0x53726448) { + protocol = lduw_p(header + 0x206); + } else { + /* + * This could be a multiboot kernel. If it is, let's stop treating it + * like a Linux kernel. + * Note: some multiboot images could be in the ELF format (the same of + * PVH), so we try multiboot first since we check the multiboot magic + * header before to load it. + */ + if (load_multiboot(x86ms, fw_cfg, f, kernel_filename, initrd_filename, + kernel_cmdline, kernel_size, header)) { + return; + } + /* + * Check if the file is an uncompressed kernel file (ELF) and load it, + * saving the PVH entry point used by the x86/HVM direct boot ABI. + * If load_elfboot() is successful, populate the fw_cfg info. + */ + if (pvh_enabled && + load_elfboot(kernel_filename, kernel_size, + header, pvh_start_addr, fw_cfg)) { + fclose(f); + + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, + strlen(kernel_cmdline) + 1); + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); + + fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); + fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, + header, sizeof(header)); + + /* load initrd */ + if (initrd_filename) { + GMappedFile *mapped_file; + gsize initrd_size; + gchar *initrd_data; + GError *gerr = NULL; + + mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); + if (!mapped_file) { + fprintf(stderr, "qemu: error reading initrd %s: %s\n", + initrd_filename, gerr->message); + exit(1); + } + x86ms->initrd_mapped_file = mapped_file; + + initrd_data = g_mapped_file_get_contents(mapped_file); + initrd_size = g_mapped_file_get_length(mapped_file); + initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; + if (initrd_size >= initrd_max) { + fprintf(stderr, "qemu: initrd is too large, cannot support." + "(max: %"PRIu32", need %"PRId64")\n", + initrd_max, (uint64_t)initrd_size); + exit(1); + } + + initrd_addr = (initrd_max - initrd_size) & ~4095; + + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, + initrd_size); + } + + option_rom[nb_option_roms].bootindex = 0; + option_rom[nb_option_roms].name = "pvh.bin"; + nb_option_roms++; + + return; + } + protocol = 0; + } + + if (protocol < 0x200 || !(header[0x211] & 0x01)) { + /* Low kernel */ + real_addr = 0x90000; + cmdline_addr = 0x9a000 - cmdline_size; + prot_addr = 0x10000; + } else if (protocol < 0x202) { + /* High but ancient kernel */ + real_addr = 0x90000; + cmdline_addr = 0x9a000 - cmdline_size; + prot_addr = 0x100000; + } else { + /* High and recent kernel */ + real_addr = 0x10000; + cmdline_addr = 0x20000; + prot_addr = 0x100000; + } + + /* highest address for loading the initrd */ + if (protocol >= 0x20c && + lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { + /* + * Linux has supported initrd up to 4 GB for a very long time (2007, + * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), + * though it only sets initrd_max to 2 GB to "work around bootloader + * bugs". Luckily, QEMU firmware(which does something like bootloader) + * has supported this. + * + * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can + * be loaded into any address. + * + * In addition, initrd_max is uint32_t simply because QEMU doesn't + * support the 64-bit boot protocol (specifically the ext_ramdisk_image + * field). + * + * Therefore here just limit initrd_max to UINT32_MAX simply as well. + */ + initrd_max = UINT32_MAX; + } else if (protocol >= 0x203) { + initrd_max = ldl_p(header + 0x22c); + } else { + initrd_max = 0x37ffffff; + } + + if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) { + initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; + } + + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1); + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); + sev_load_ctx.cmdline_data = (char *)kernel_cmdline; + sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1; + + if (protocol >= 0x202) { + stl_p(header + 0x228, cmdline_addr); + } else { + stw_p(header + 0x20, 0xA33F); + stw_p(header + 0x22, cmdline_addr - real_addr); + } + + /* handle vga= parameter */ + vmode = strstr(kernel_cmdline, "vga="); + if (vmode) { + unsigned int video_mode; + const char *end; + int ret; + /* skip "vga=" */ + vmode += 4; + if (!strncmp(vmode, "normal", 6)) { + video_mode = 0xffff; + } else if (!strncmp(vmode, "ext", 3)) { + video_mode = 0xfffe; + } else if (!strncmp(vmode, "ask", 3)) { + video_mode = 0xfffd; + } else { + ret = qemu_strtoui(vmode, &end, 0, &video_mode); + if (ret != 0 || (*end && *end != ' ')) { + fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n"); + exit(1); + } + } + stw_p(header + 0x1fa, video_mode); + } + + /* loader type */ + /* + * High nybble = B reserved for QEMU; low nybble is revision number. + * If this code is substantially changed, you may want to consider + * incrementing the revision. + */ + if (protocol >= 0x200) { + header[0x210] = 0xB0; + } + /* heap */ + if (protocol >= 0x201) { + header[0x211] |= 0x80; /* CAN_USE_HEAP */ + stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); + } + + /* load initrd */ + if (initrd_filename) { + GMappedFile *mapped_file; + gsize initrd_size; + gchar *initrd_data; + GError *gerr = NULL; + + if (protocol < 0x200) { + fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); + exit(1); + } + + mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); + if (!mapped_file) { + fprintf(stderr, "qemu: error reading initrd %s: %s\n", + initrd_filename, gerr->message); + exit(1); + } + x86ms->initrd_mapped_file = mapped_file; + + initrd_data = g_mapped_file_get_contents(mapped_file); + initrd_size = g_mapped_file_get_length(mapped_file); + if (initrd_size >= initrd_max) { + fprintf(stderr, "qemu: initrd is too large, cannot support." + "(max: %"PRIu32", need %"PRId64")\n", + initrd_max, (uint64_t)initrd_size); + exit(1); + } + + initrd_addr = (initrd_max - initrd_size) & ~4095; + + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); + fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); + sev_load_ctx.initrd_data = initrd_data; + sev_load_ctx.initrd_size = initrd_size; + + stl_p(header + 0x218, initrd_addr); + stl_p(header + 0x21c, initrd_size); + } + + /* load kernel and setup */ + setup_size = header[0x1f1]; + if (setup_size == 0) { + setup_size = 4; + } + setup_size = (setup_size + 1) * 512; + if (setup_size > kernel_size) { + fprintf(stderr, "qemu: invalid kernel header\n"); + exit(1); + } + kernel_size -= setup_size; + + setup = g_malloc(setup_size); + kernel = g_malloc(kernel_size); + fseek(f, 0, SEEK_SET); + if (fread(setup, 1, setup_size, f) != setup_size) { + fprintf(stderr, "fread() failed\n"); + exit(1); + } + if (fread(kernel, 1, kernel_size, f) != kernel_size) { + fprintf(stderr, "fread() failed\n"); + exit(1); + } + fclose(f); + + /* append dtb to kernel */ + if (dtb_filename) { + if (protocol < 0x209) { + fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); + exit(1); + } + + dtb_size = get_image_size(dtb_filename); + if (dtb_size <= 0) { + fprintf(stderr, "qemu: error reading dtb %s: %s\n", + dtb_filename, strerror(errno)); + exit(1); + } + + setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); + kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; + kernel = g_realloc(kernel, kernel_size); + + stq_p(header + 0x250, prot_addr + setup_data_offset); + + setup_data = (struct setup_data *)(kernel + setup_data_offset); + setup_data->next = 0; + setup_data->type = cpu_to_le32(SETUP_DTB); + setup_data->len = cpu_to_le32(dtb_size); + + load_image_size(dtb_filename, setup_data->data, dtb_size); + } + + /* + * If we're starting an encrypted VM, it will be OVMF based, which uses the + * efi stub for booting and doesn't require any values to be placed in the + * kernel header. We therefore don't update the header so the hash of the + * kernel on the other side of the fw_cfg interface matches the hash of the + * file the user passed in. + */ + if (!sev_enabled()) { + memcpy(setup, header, MIN(sizeof(header), setup_size)); + } + + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); + fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); + sev_load_ctx.kernel_data = (char *)kernel; + sev_load_ctx.kernel_size = kernel_size; + + fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); + fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); + sev_load_ctx.setup_data = (char *)setup; + sev_load_ctx.setup_size = setup_size; + + if (sev_enabled()) { + sev_add_kernel_loader_hashes(&sev_load_ctx, &error_fatal); + } + + option_rom[nb_option_roms].bootindex = 0; + option_rom[nb_option_roms].name = "linuxboot.bin"; + if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { + option_rom[nb_option_roms].name = "linuxboot_dma.bin"; + } + nb_option_roms++; +} + +void x86_isa_bios_init(MemoryRegion *isa_bios, MemoryRegion *isa_memory, + MemoryRegion *bios, bool read_only) +{ + uint64_t bios_size = memory_region_size(bios); + uint64_t isa_bios_size = MIN(bios_size, 128 * KiB); + + memory_region_init_alias(isa_bios, NULL, "isa-bios", bios, + bios_size - isa_bios_size, isa_bios_size); + memory_region_add_subregion_overlap(isa_memory, 1 * MiB - isa_bios_size, + isa_bios, 1); + memory_region_set_readonly(isa_bios, read_only); +} + +void x86_bios_rom_init(X86MachineState *x86ms, const char *default_firmware, + MemoryRegion *rom_memory, bool isapc_ram_fw) +{ + const char *bios_name; + char *filename; + int bios_size; + ssize_t ret; + + /* BIOS load */ + bios_name = MACHINE(x86ms)->firmware ?: default_firmware; + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (filename) { + bios_size = get_image_size(filename); + } else { + bios_size = -1; + } + if (bios_size <= 0 || + (bios_size % 65536) != 0) { + goto bios_error; + } + memory_region_init_ram(&x86ms->bios, NULL, "pc.bios", bios_size, + &error_fatal); + if (sev_enabled()) { + /* + * The concept of a "reset" simply doesn't exist for + * confidential computing guests, we have to destroy and + * re-launch them instead. So there is no need to register + * the firmware as rom to properly re-initialize on reset. + * Just go for a straight file load instead. + */ + void *ptr = memory_region_get_ram_ptr(&x86ms->bios); + load_image_size(filename, ptr, bios_size); + x86_firmware_configure(ptr, bios_size); + } else { + memory_region_set_readonly(&x86ms->bios, !isapc_ram_fw); + ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); + if (ret != 0) { + goto bios_error; + } + } + g_free(filename); + + /* map the last 128KB of the BIOS in ISA space */ + x86_isa_bios_init(&x86ms->isa_bios, rom_memory, &x86ms->bios, + !isapc_ram_fw); + + /* map all the bios at the top of memory */ + memory_region_add_subregion(rom_memory, + (uint32_t)(-bios_size), + &x86ms->bios); + return; + +bios_error: + fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); + exit(1); +} diff --git a/hw/i386/x86-cpu.c b/hw/i386/x86-cpu.c new file mode 100644 index 00000000000..ab2920522d1 --- /dev/null +++ b/hw/i386/x86-cpu.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2003-2004 Fabrice Bellard + * Copyright (c) 2019, 2024 Red Hat, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "sysemu/whpx.h" +#include "sysemu/cpu-timers.h" +#include "trace.h" + +#include "hw/i386/x86.h" +#include "target/i386/cpu.h" +#include "hw/intc/i8259.h" +#include "hw/irq.h" +#include "sysemu/kvm.h" + +/* TSC handling */ +uint64_t cpu_get_tsc(CPUX86State *env) +{ + return cpus_get_elapsed_ticks(); +} + +/* IRQ handling */ +static void pic_irq_request(void *opaque, int irq, int level) +{ + CPUState *cs = first_cpu; + X86CPU *cpu = X86_CPU(cs); + + trace_x86_pic_interrupt(irq, level); + if (cpu_is_apic_enabled(cpu->apic_state) && !kvm_irqchip_in_kernel() && + !whpx_apic_in_platform()) { + CPU_FOREACH(cs) { + cpu = X86_CPU(cs); + if (apic_accept_pic_intr(cpu->apic_state)) { + apic_deliver_pic_intr(cpu->apic_state, level); + } + } + } else { + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } + } +} + +qemu_irq x86_allocate_cpu_irq(void) +{ + return qemu_allocate_irq(pic_irq_request, NULL, 0); +} + +int cpu_get_pic_interrupt(CPUX86State *env) +{ + X86CPU *cpu = env_archcpu(env); + int intno; + + if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { + intno = apic_get_interrupt(cpu->apic_state); + if (intno >= 0) { + return intno; + } + /* read the irq from the PIC */ + if (!apic_accept_pic_intr(cpu->apic_state)) { + return -1; + } + } + + intno = pic_read_irq(isa_pic); + return intno; +} + +DeviceState *cpu_get_current_apic(void) +{ + if (current_cpu) { + X86CPU *cpu = X86_CPU(current_cpu); + return cpu->apic_state; + } else { + return NULL; + } +} diff --git a/hw/i386/x86.c b/hw/i386/x86.c index fcef652c1e3..0b5cc599566 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -22,52 +22,25 @@ */ #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "qemu/option.h" -#include "qemu/cutils.h" #include "qemu/units.h" -#include "qemu/datadir.h" #include "qapi/error.h" #include "qapi/qapi-visit-common.h" -#include "qapi/clone-visitor.h" #include "qapi/qapi-visit-machine.h" #include "qapi/visitor.h" #include "sysemu/qtest.h" -#include "sysemu/whpx.h" #include "sysemu/numa.h" -#include "sysemu/replay.h" -#include "sysemu/sysemu.h" -#include "sysemu/cpu-timers.h" -#include "sysemu/xen.h" #include "trace.h" +#include "hw/acpi/aml-build.h" #include "hw/i386/x86.h" -#include "target/i386/cpu.h" #include "hw/i386/topology.h" -#include "hw/i386/fw_cfg.h" -#include "hw/intc/i8259.h" -#include "hw/rtc/mc146818rtc.h" -#include "target/i386/sev.h" -#include "hw/acpi/cpu_hotplug.h" -#include "hw/irq.h" #include "hw/nmi.h" -#include "hw/loader.h" -#include "multiboot.h" -#include "elf.h" -#include "standard-headers/asm-x86/bootparam.h" -#include CONFIG_DEVICES #include "kvm/kvm_i386.h" -#ifdef CONFIG_XEN_EMU -#include "hw/xen/xen.h" -#include "hw/i386/kvm/xen_evtchn.h" -#endif -/* Physical Address of PVH entry point read from kernel ELF NOTE */ -static size_t pvh_start_addr; - -static void init_topo_info(X86CPUTopoInfo *topo_info, - const X86MachineState *x86ms) +void init_topo_info(X86CPUTopoInfo *topo_info, + const X86MachineState *x86ms) { MachineState *ms = MACHINE(x86ms); @@ -94,355 +67,6 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, return x86_apicid_from_cpu_idx(&topo_info, cpu_index); } - -void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id, Error **errp) -{ - Object *cpu = object_new(MACHINE(x86ms)->cpu_type); - - if (!object_property_set_uint(cpu, "apic-id", apic_id, errp)) { - goto out; - } - qdev_realize(DEVICE(cpu), NULL, errp); - -out: - object_unref(cpu); -} - -void x86_cpus_init(X86MachineState *x86ms, int default_cpu_version) -{ - int i; - const CPUArchIdList *possible_cpus; - MachineState *ms = MACHINE(x86ms); - MachineClass *mc = MACHINE_GET_CLASS(x86ms); - - x86_cpu_set_default_version(default_cpu_version); - - /* - * Calculates the limit to CPU APIC ID values - * - * Limit for the APIC ID value, so that all - * CPU APIC IDs are < x86ms->apic_id_limit. - * - * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). - */ - x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms, - ms->smp.max_cpus - 1) + 1; - - /* - * Can we support APIC ID 255 or higher? With KVM, that requires - * both in-kernel lapic and X2APIC userspace API. - * - * kvm_enabled() must go first to ensure that kvm_* references are - * not emitted for the linker to consume (kvm_enabled() is - * a literal `0` in configurations where kvm_* aren't defined) - */ - if (kvm_enabled() && x86ms->apic_id_limit > 255 && - kvm_irqchip_in_kernel() && !kvm_enable_x2apic()) { - error_report("current -smp configuration requires kernel " - "irqchip and X2APIC API support."); - exit(EXIT_FAILURE); - } - - if (kvm_enabled()) { - kvm_set_max_apic_id(x86ms->apic_id_limit); - } - - if (!kvm_irqchip_in_kernel()) { - apic_set_max_apic_id(x86ms->apic_id_limit); - } - - possible_cpus = mc->possible_cpu_arch_ids(ms); - for (i = 0; i < ms->smp.cpus; i++) { - x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); - } -} - -void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus_count) -{ - MC146818RtcState *rtc = MC146818_RTC(s); - - if (cpus_count > 0xff) { - /* - * If the number of CPUs can't be represented in 8 bits, the - * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just - * to make old BIOSes fail more predictably. - */ - mc146818rtc_set_cmos_data(rtc, 0x5f, 0); - } else { - mc146818rtc_set_cmos_data(rtc, 0x5f, cpus_count - 1); - } -} - -static int x86_apic_cmp(const void *a, const void *b) -{ - CPUArchId *apic_a = (CPUArchId *)a; - CPUArchId *apic_b = (CPUArchId *)b; - - return apic_a->arch_id - apic_b->arch_id; -} - -/* - * returns pointer to CPUArchId descriptor that matches CPU's apic_id - * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no - * entry corresponding to CPU's apic_id returns NULL. - */ -CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) -{ - CPUArchId apic_id, *found_cpu; - - apic_id.arch_id = id; - found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, - ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), - x86_apic_cmp); - if (found_cpu && idx) { - *idx = found_cpu - ms->possible_cpus->cpus; - } - return found_cpu; -} - -void x86_cpu_plug(HotplugHandler *hotplug_dev, - DeviceState *dev, Error **errp) -{ - CPUArchId *found_cpu; - Error *local_err = NULL; - X86CPU *cpu = X86_CPU(dev); - X86MachineState *x86ms = X86_MACHINE(hotplug_dev); - - if (x86ms->acpi_dev) { - hotplug_handler_plug(x86ms->acpi_dev, dev, &local_err); - if (local_err) { - goto out; - } - } - - /* increment the number of CPUs */ - x86ms->boot_cpus++; - if (x86ms->rtc) { - x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); - } - if (x86ms->fw_cfg) { - fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); - } - - found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); - found_cpu->cpu = CPU(dev); -out: - error_propagate(errp, local_err); -} - -void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, - DeviceState *dev, Error **errp) -{ - int idx = -1; - X86CPU *cpu = X86_CPU(dev); - X86MachineState *x86ms = X86_MACHINE(hotplug_dev); - - if (!x86ms->acpi_dev) { - error_setg(errp, "CPU hot unplug not supported without ACPI"); - return; - } - - x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); - assert(idx != -1); - if (idx == 0) { - error_setg(errp, "Boot CPU is unpluggable"); - return; - } - - hotplug_handler_unplug_request(x86ms->acpi_dev, dev, - errp); -} - -void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, - DeviceState *dev, Error **errp) -{ - CPUArchId *found_cpu; - Error *local_err = NULL; - X86CPU *cpu = X86_CPU(dev); - X86MachineState *x86ms = X86_MACHINE(hotplug_dev); - - hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); - if (local_err) { - goto out; - } - - found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); - found_cpu->cpu = NULL; - qdev_unrealize(dev); - - /* decrement the number of CPUs */ - x86ms->boot_cpus--; - /* Update the number of CPUs in CMOS */ - x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); - fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); - out: - error_propagate(errp, local_err); -} - -void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, - DeviceState *dev, Error **errp) -{ - int idx; - CPUState *cs; - CPUArchId *cpu_slot; - X86CPUTopoIDs topo_ids; - X86CPU *cpu = X86_CPU(dev); - CPUX86State *env = &cpu->env; - MachineState *ms = MACHINE(hotplug_dev); - X86MachineState *x86ms = X86_MACHINE(hotplug_dev); - unsigned int smp_cores = ms->smp.cores; - unsigned int smp_threads = ms->smp.threads; - X86CPUTopoInfo topo_info; - - if (!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { - error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", - ms->cpu_type); - return; - } - - if (x86ms->acpi_dev) { - Error *local_err = NULL; - - hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev, - &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - } - - init_topo_info(&topo_info, x86ms); - - env->nr_dies = ms->smp.dies; - - /* - * If APIC ID is not set, - * set it based on socket/die/core/thread properties. - */ - if (cpu->apic_id == UNASSIGNED_APIC_ID) { - int max_socket = (ms->smp.max_cpus - 1) / - smp_threads / smp_cores / ms->smp.dies; - - /* - * die-id was optional in QEMU 4.0 and older, so keep it optional - * if there's only one die per socket. - */ - if (cpu->die_id < 0 && ms->smp.dies == 1) { - cpu->die_id = 0; - } - - if (cpu->socket_id < 0) { - error_setg(errp, "CPU socket-id is not set"); - return; - } else if (cpu->socket_id > max_socket) { - error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", - cpu->socket_id, max_socket); - return; - } - if (cpu->die_id < 0) { - error_setg(errp, "CPU die-id is not set"); - return; - } else if (cpu->die_id > ms->smp.dies - 1) { - error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", - cpu->die_id, ms->smp.dies - 1); - return; - } - if (cpu->core_id < 0) { - error_setg(errp, "CPU core-id is not set"); - return; - } else if (cpu->core_id > (smp_cores - 1)) { - error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", - cpu->core_id, smp_cores - 1); - return; - } - if (cpu->thread_id < 0) { - error_setg(errp, "CPU thread-id is not set"); - return; - } else if (cpu->thread_id > (smp_threads - 1)) { - error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", - cpu->thread_id, smp_threads - 1); - return; - } - - topo_ids.pkg_id = cpu->socket_id; - topo_ids.die_id = cpu->die_id; - topo_ids.core_id = cpu->core_id; - topo_ids.smt_id = cpu->thread_id; - cpu->apic_id = x86_apicid_from_topo_ids(&topo_info, &topo_ids); - } - - cpu_slot = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, &idx); - if (!cpu_slot) { - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); - error_setg(errp, - "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" - " APIC ID %" PRIu32 ", valid index range 0:%d", - topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id, - cpu->apic_id, ms->possible_cpus->len - 1); - return; - } - - if (cpu_slot->cpu) { - error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", - idx, cpu->apic_id); - return; - } - - /* if 'address' properties socket-id/core-id/thread-id are not set, set them - * so that machine_query_hotpluggable_cpus would show correct values - */ - /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() - * once -smp refactoring is complete and there will be CPU private - * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); - if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) { - error_setg(errp, "property socket-id: %u doesn't match set apic-id:" - " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, - topo_ids.pkg_id); - return; - } - cpu->socket_id = topo_ids.pkg_id; - - if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) { - error_setg(errp, "property die-id: %u doesn't match set apic-id:" - " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id); - return; - } - cpu->die_id = topo_ids.die_id; - - if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { - error_setg(errp, "property core-id: %u doesn't match set apic-id:" - " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, - topo_ids.core_id); - return; - } - cpu->core_id = topo_ids.core_id; - - if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) { - error_setg(errp, "property thread-id: %u doesn't match set apic-id:" - " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, - topo_ids.smt_id); - return; - } - cpu->thread_id = topo_ids.smt_id; - - /* - * kvm_enabled() must go first to ensure that kvm_* references are - * not emitted for the linker to consume (kvm_enabled() is - * a literal `0` in configurations where kvm_* aren't defined) - */ - if (kvm_enabled() && hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && - !kvm_hv_vpindex_settable()) { - error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); - return; - } - - cs = CPU(cpu); - cs->cpu_index = idx; - - numa_cpu_pre_plug(cpu_slot, dev, errp); -} - static CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms, unsigned cpu_index) { @@ -528,676 +152,6 @@ static void x86_nmi(NMIState *n, int cpu_index, Error **errp) } } -static long get_file_size(FILE *f) -{ - long where, size; - - /* XXX: on Unix systems, using fstat() probably makes more sense */ - - where = ftell(f); - fseek(f, 0, SEEK_END); - size = ftell(f); - fseek(f, where, SEEK_SET); - - return size; -} - -/* TSC handling */ -uint64_t cpu_get_tsc(CPUX86State *env) -{ - return cpus_get_elapsed_ticks(); -} - -/* IRQ handling */ -static void pic_irq_request(void *opaque, int irq, int level) -{ - CPUState *cs = first_cpu; - X86CPU *cpu = X86_CPU(cs); - - trace_x86_pic_interrupt(irq, level); - if (cpu_is_apic_enabled(cpu->apic_state) && !kvm_irqchip_in_kernel() && - !whpx_apic_in_platform()) { - CPU_FOREACH(cs) { - cpu = X86_CPU(cs); - if (apic_accept_pic_intr(cpu->apic_state)) { - apic_deliver_pic_intr(cpu->apic_state, level); - } - } - } else { - if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } - } -} - -qemu_irq x86_allocate_cpu_irq(void) -{ - return qemu_allocate_irq(pic_irq_request, NULL, 0); -} - -int cpu_get_pic_interrupt(CPUX86State *env) -{ - X86CPU *cpu = env_archcpu(env); - int intno; - - if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { - intno = apic_get_interrupt(cpu->apic_state); - if (intno >= 0) { - return intno; - } - /* read the irq from the PIC */ - if (!apic_accept_pic_intr(cpu->apic_state)) { - return -1; - } - } - - intno = pic_read_irq(isa_pic); - return intno; -} - -DeviceState *cpu_get_current_apic(void) -{ - if (current_cpu) { - X86CPU *cpu = X86_CPU(current_cpu); - return cpu->apic_state; - } else { - return NULL; - } -} - -void gsi_handler(void *opaque, int n, int level) -{ - GSIState *s = opaque; - - trace_x86_gsi_interrupt(n, level); - switch (n) { - case 0 ... ISA_NUM_IRQS - 1: - if (s->i8259_irq[n]) { - /* Under KVM, Kernel will forward to both PIC and IOAPIC */ - qemu_set_irq(s->i8259_irq[n], level); - } - /* fall through */ - case ISA_NUM_IRQS ... IOAPIC_NUM_PINS - 1: -#ifdef CONFIG_XEN_EMU - /* - * Xen delivers the GSI to the Legacy PIC (not that Legacy PIC - * routing actually works properly under Xen). And then to - * *either* the PIRQ handling or the I/OAPIC depending on - * whether the former wants it. - */ - if (xen_mode == XEN_EMULATE && xen_evtchn_set_gsi(n, level)) { - break; - } -#endif - qemu_set_irq(s->ioapic_irq[n], level); - break; - case IO_APIC_SECONDARY_IRQBASE - ... IO_APIC_SECONDARY_IRQBASE + IOAPIC_NUM_PINS - 1: - qemu_set_irq(s->ioapic2_irq[n - IO_APIC_SECONDARY_IRQBASE], level); - break; - } -} - -void ioapic_init_gsi(GSIState *gsi_state, Object *parent) -{ - DeviceState *dev; - SysBusDevice *d; - unsigned int i; - - assert(parent); - if (kvm_ioapic_in_kernel()) { - dev = qdev_new(TYPE_KVM_IOAPIC); - } else { - dev = qdev_new(TYPE_IOAPIC); - } - object_property_add_child(parent, "ioapic", OBJECT(dev)); - d = SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(d, &error_fatal); - sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); - - for (i = 0; i < IOAPIC_NUM_PINS; i++) { - gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); - } -} - -DeviceState *ioapic_init_secondary(GSIState *gsi_state) -{ - DeviceState *dev; - SysBusDevice *d; - unsigned int i; - - dev = qdev_new(TYPE_IOAPIC); - d = SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(d, &error_fatal); - sysbus_mmio_map(d, 0, IO_APIC_SECONDARY_ADDRESS); - - for (i = 0; i < IOAPIC_NUM_PINS; i++) { - gsi_state->ioapic2_irq[i] = qdev_get_gpio_in(dev, i); - } - return dev; -} - -/* - * The entry point into the kernel for PVH boot is different from - * the native entry point. The PVH entry is defined by the x86/HVM - * direct boot ABI and is available in an ELFNOTE in the kernel binary. - * - * This function is passed to load_elf() when it is called from - * load_elfboot() which then additionally checks for an ELF Note of - * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to - * parse the PVH entry address from the ELF Note. - * - * Due to trickery in elf_opts.h, load_elf() is actually available as - * load_elf32() or load_elf64() and this routine needs to be able - * to deal with being called as 32 or 64 bit. - * - * The address of the PVH entry point is saved to the 'pvh_start_addr' - * global variable. (although the entry point is 32-bit, the kernel - * binary can be either 32-bit or 64-bit). - */ -static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) -{ - size_t *elf_note_data_addr; - - /* Check if ELF Note header passed in is valid */ - if (arg1 == NULL) { - return 0; - } - - if (is64) { - struct elf64_note *nhdr64 = (struct elf64_note *)arg1; - uint64_t nhdr_size64 = sizeof(struct elf64_note); - uint64_t phdr_align = *(uint64_t *)arg2; - uint64_t nhdr_namesz = nhdr64->n_namesz; - - elf_note_data_addr = - ((void *)nhdr64) + nhdr_size64 + - QEMU_ALIGN_UP(nhdr_namesz, phdr_align); - - pvh_start_addr = *elf_note_data_addr; - } else { - struct elf32_note *nhdr32 = (struct elf32_note *)arg1; - uint32_t nhdr_size32 = sizeof(struct elf32_note); - uint32_t phdr_align = *(uint32_t *)arg2; - uint32_t nhdr_namesz = nhdr32->n_namesz; - - elf_note_data_addr = - ((void *)nhdr32) + nhdr_size32 + - QEMU_ALIGN_UP(nhdr_namesz, phdr_align); - - pvh_start_addr = *(uint32_t *)elf_note_data_addr; - } - - return pvh_start_addr; -} - -static bool load_elfboot(const char *kernel_filename, - int kernel_file_size, - uint8_t *header, - size_t pvh_xen_start_addr, - FWCfgState *fw_cfg) -{ - uint32_t flags = 0; - uint32_t mh_load_addr = 0; - uint32_t elf_kernel_size = 0; - uint64_t elf_entry; - uint64_t elf_low, elf_high; - int kernel_size; - - if (ldl_p(header) != 0x464c457f) { - return false; /* no elfboot */ - } - - bool elf_is64 = header[EI_CLASS] == ELFCLASS64; - flags = elf_is64 ? - ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; - - if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ - error_report("elfboot unsupported flags = %x", flags); - exit(1); - } - - uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; - kernel_size = load_elf(kernel_filename, read_pvh_start_addr, - NULL, &elf_note_type, &elf_entry, - &elf_low, &elf_high, NULL, 0, I386_ELF_MACHINE, - 0, 0); - - if (kernel_size < 0) { - error_report("Error while loading elf kernel"); - exit(1); - } - mh_load_addr = elf_low; - elf_kernel_size = elf_high - elf_low; - - if (pvh_start_addr == 0) { - error_report("Error loading uncompressed kernel without PVH ELF Note"); - exit(1); - } - fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); - fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); - fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); - - return true; -} - -void x86_load_linux(X86MachineState *x86ms, - FWCfgState *fw_cfg, - int acpi_data_size, - bool pvh_enabled) -{ - bool linuxboot_dma_enabled = X86_MACHINE_GET_CLASS(x86ms)->fwcfg_dma_enabled; - uint16_t protocol; - int setup_size, kernel_size, cmdline_size; - int dtb_size, setup_data_offset; - uint32_t initrd_max; - uint8_t header[8192], *setup, *kernel; - hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; - FILE *f; - char *vmode; - MachineState *machine = MACHINE(x86ms); - struct setup_data *setup_data; - const char *kernel_filename = machine->kernel_filename; - const char *initrd_filename = machine->initrd_filename; - const char *dtb_filename = machine->dtb; - const char *kernel_cmdline = machine->kernel_cmdline; - SevKernelLoaderContext sev_load_ctx = {}; - - /* Align to 16 bytes as a paranoia measure */ - cmdline_size = (strlen(kernel_cmdline) + 16) & ~15; - - /* load the kernel header */ - f = fopen(kernel_filename, "rb"); - if (!f) { - fprintf(stderr, "qemu: could not open kernel file '%s': %s\n", - kernel_filename, strerror(errno)); - exit(1); - } - - kernel_size = get_file_size(f); - if (!kernel_size || - fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != - MIN(ARRAY_SIZE(header), kernel_size)) { - fprintf(stderr, "qemu: could not load kernel '%s': %s\n", - kernel_filename, strerror(errno)); - exit(1); - } - - /* kernel protocol version */ - if (ldl_p(header + 0x202) == 0x53726448) { - protocol = lduw_p(header + 0x206); - } else { - /* - * This could be a multiboot kernel. If it is, let's stop treating it - * like a Linux kernel. - * Note: some multiboot images could be in the ELF format (the same of - * PVH), so we try multiboot first since we check the multiboot magic - * header before to load it. - */ - if (load_multiboot(x86ms, fw_cfg, f, kernel_filename, initrd_filename, - kernel_cmdline, kernel_size, header)) { - return; - } - /* - * Check if the file is an uncompressed kernel file (ELF) and load it, - * saving the PVH entry point used by the x86/HVM direct boot ABI. - * If load_elfboot() is successful, populate the fw_cfg info. - */ - if (pvh_enabled && - load_elfboot(kernel_filename, kernel_size, - header, pvh_start_addr, fw_cfg)) { - fclose(f); - - fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, - strlen(kernel_cmdline) + 1); - fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); - - fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); - fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, - header, sizeof(header)); - - /* load initrd */ - if (initrd_filename) { - GMappedFile *mapped_file; - gsize initrd_size; - gchar *initrd_data; - GError *gerr = NULL; - - mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); - if (!mapped_file) { - fprintf(stderr, "qemu: error reading initrd %s: %s\n", - initrd_filename, gerr->message); - exit(1); - } - x86ms->initrd_mapped_file = mapped_file; - - initrd_data = g_mapped_file_get_contents(mapped_file); - initrd_size = g_mapped_file_get_length(mapped_file); - initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; - if (initrd_size >= initrd_max) { - fprintf(stderr, "qemu: initrd is too large, cannot support." - "(max: %"PRIu32", need %"PRId64")\n", - initrd_max, (uint64_t)initrd_size); - exit(1); - } - - initrd_addr = (initrd_max - initrd_size) & ~4095; - - fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); - fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); - fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, - initrd_size); - } - - option_rom[nb_option_roms].bootindex = 0; - option_rom[nb_option_roms].name = "pvh.bin"; - nb_option_roms++; - - return; - } - protocol = 0; - } - - if (protocol < 0x200 || !(header[0x211] & 0x01)) { - /* Low kernel */ - real_addr = 0x90000; - cmdline_addr = 0x9a000 - cmdline_size; - prot_addr = 0x10000; - } else if (protocol < 0x202) { - /* High but ancient kernel */ - real_addr = 0x90000; - cmdline_addr = 0x9a000 - cmdline_size; - prot_addr = 0x100000; - } else { - /* High and recent kernel */ - real_addr = 0x10000; - cmdline_addr = 0x20000; - prot_addr = 0x100000; - } - - /* highest address for loading the initrd */ - if (protocol >= 0x20c && - lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { - /* - * Linux has supported initrd up to 4 GB for a very long time (2007, - * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), - * though it only sets initrd_max to 2 GB to "work around bootloader - * bugs". Luckily, QEMU firmware(which does something like bootloader) - * has supported this. - * - * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can - * be loaded into any address. - * - * In addition, initrd_max is uint32_t simply because QEMU doesn't - * support the 64-bit boot protocol (specifically the ext_ramdisk_image - * field). - * - * Therefore here just limit initrd_max to UINT32_MAX simply as well. - */ - initrd_max = UINT32_MAX; - } else if (protocol >= 0x203) { - initrd_max = ldl_p(header + 0x22c); - } else { - initrd_max = 0x37ffffff; - } - - if (initrd_max >= x86ms->below_4g_mem_size - acpi_data_size) { - initrd_max = x86ms->below_4g_mem_size - acpi_data_size - 1; - } - - fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); - fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline) + 1); - fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); - sev_load_ctx.cmdline_data = (char *)kernel_cmdline; - sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1; - - if (protocol >= 0x202) { - stl_p(header + 0x228, cmdline_addr); - } else { - stw_p(header + 0x20, 0xA33F); - stw_p(header + 0x22, cmdline_addr - real_addr); - } - - /* handle vga= parameter */ - vmode = strstr(kernel_cmdline, "vga="); - if (vmode) { - unsigned int video_mode; - const char *end; - int ret; - /* skip "vga=" */ - vmode += 4; - if (!strncmp(vmode, "normal", 6)) { - video_mode = 0xffff; - } else if (!strncmp(vmode, "ext", 3)) { - video_mode = 0xfffe; - } else if (!strncmp(vmode, "ask", 3)) { - video_mode = 0xfffd; - } else { - ret = qemu_strtoui(vmode, &end, 0, &video_mode); - if (ret != 0 || (*end && *end != ' ')) { - fprintf(stderr, "qemu: invalid 'vga=' kernel parameter.\n"); - exit(1); - } - } - stw_p(header + 0x1fa, video_mode); - } - - /* loader type */ - /* - * High nybble = B reserved for QEMU; low nybble is revision number. - * If this code is substantially changed, you may want to consider - * incrementing the revision. - */ - if (protocol >= 0x200) { - header[0x210] = 0xB0; - } - /* heap */ - if (protocol >= 0x201) { - header[0x211] |= 0x80; /* CAN_USE_HEAP */ - stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); - } - - /* load initrd */ - if (initrd_filename) { - GMappedFile *mapped_file; - gsize initrd_size; - gchar *initrd_data; - GError *gerr = NULL; - - if (protocol < 0x200) { - fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); - exit(1); - } - - mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); - if (!mapped_file) { - fprintf(stderr, "qemu: error reading initrd %s: %s\n", - initrd_filename, gerr->message); - exit(1); - } - x86ms->initrd_mapped_file = mapped_file; - - initrd_data = g_mapped_file_get_contents(mapped_file); - initrd_size = g_mapped_file_get_length(mapped_file); - if (initrd_size >= initrd_max) { - fprintf(stderr, "qemu: initrd is too large, cannot support." - "(max: %"PRIu32", need %"PRId64")\n", - initrd_max, (uint64_t)initrd_size); - exit(1); - } - - initrd_addr = (initrd_max - initrd_size) & ~4095; - - fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); - fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); - fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); - sev_load_ctx.initrd_data = initrd_data; - sev_load_ctx.initrd_size = initrd_size; - - stl_p(header + 0x218, initrd_addr); - stl_p(header + 0x21c, initrd_size); - } - - /* load kernel and setup */ - setup_size = header[0x1f1]; - if (setup_size == 0) { - setup_size = 4; - } - setup_size = (setup_size + 1) * 512; - if (setup_size > kernel_size) { - fprintf(stderr, "qemu: invalid kernel header\n"); - exit(1); - } - kernel_size -= setup_size; - - setup = g_malloc(setup_size); - kernel = g_malloc(kernel_size); - fseek(f, 0, SEEK_SET); - if (fread(setup, 1, setup_size, f) != setup_size) { - fprintf(stderr, "fread() failed\n"); - exit(1); - } - if (fread(kernel, 1, kernel_size, f) != kernel_size) { - fprintf(stderr, "fread() failed\n"); - exit(1); - } - fclose(f); - - /* append dtb to kernel */ - if (dtb_filename) { - if (protocol < 0x209) { - fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); - exit(1); - } - - dtb_size = get_image_size(dtb_filename); - if (dtb_size <= 0) { - fprintf(stderr, "qemu: error reading dtb %s: %s\n", - dtb_filename, strerror(errno)); - exit(1); - } - - setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); - kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; - kernel = g_realloc(kernel, kernel_size); - - stq_p(header + 0x250, prot_addr + setup_data_offset); - - setup_data = (struct setup_data *)(kernel + setup_data_offset); - setup_data->next = 0; - setup_data->type = cpu_to_le32(SETUP_DTB); - setup_data->len = cpu_to_le32(dtb_size); - - load_image_size(dtb_filename, setup_data->data, dtb_size); - } - - /* - * If we're starting an encrypted VM, it will be OVMF based, which uses the - * efi stub for booting and doesn't require any values to be placed in the - * kernel header. We therefore don't update the header so the hash of the - * kernel on the other side of the fw_cfg interface matches the hash of the - * file the user passed in. - */ - if (!sev_enabled()) { - memcpy(setup, header, MIN(sizeof(header), setup_size)); - } - - fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); - fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); - fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); - sev_load_ctx.kernel_data = (char *)kernel; - sev_load_ctx.kernel_size = kernel_size; - - fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); - fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); - fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); - sev_load_ctx.setup_data = (char *)setup; - sev_load_ctx.setup_size = setup_size; - - if (sev_enabled()) { - sev_add_kernel_loader_hashes(&sev_load_ctx, &error_fatal); - } - - option_rom[nb_option_roms].bootindex = 0; - option_rom[nb_option_roms].name = "linuxboot.bin"; - if (linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { - option_rom[nb_option_roms].name = "linuxboot_dma.bin"; - } - nb_option_roms++; -} - -void x86_isa_bios_init(MemoryRegion *isa_bios, MemoryRegion *isa_memory, - MemoryRegion *bios, bool read_only) -{ - uint64_t bios_size = memory_region_size(bios); - uint64_t isa_bios_size = MIN(bios_size, 128 * KiB); - - memory_region_init_alias(isa_bios, NULL, "isa-bios", bios, - bios_size - isa_bios_size, isa_bios_size); - memory_region_add_subregion_overlap(isa_memory, 1 * MiB - isa_bios_size, - isa_bios, 1); - memory_region_set_readonly(isa_bios, read_only); -} - -void x86_bios_rom_init(X86MachineState *x86ms, const char *default_firmware, - MemoryRegion *rom_memory, bool isapc_ram_fw) -{ - const char *bios_name; - char *filename; - int bios_size; - ssize_t ret; - - /* BIOS load */ - bios_name = MACHINE(x86ms)->firmware ?: default_firmware; - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); - if (filename) { - bios_size = get_image_size(filename); - } else { - bios_size = -1; - } - if (bios_size <= 0 || - (bios_size % 65536) != 0) { - goto bios_error; - } - memory_region_init_ram(&x86ms->bios, NULL, "pc.bios", bios_size, - &error_fatal); - if (sev_enabled()) { - /* - * The concept of a "reset" simply doesn't exist for - * confidential computing guests, we have to destroy and - * re-launch them instead. So there is no need to register - * the firmware as rom to properly re-initialize on reset. - * Just go for a straight file load instead. - */ - void *ptr = memory_region_get_ram_ptr(&x86ms->bios); - load_image_size(filename, ptr, bios_size); - x86_firmware_configure(ptr, bios_size); - } else { - memory_region_set_readonly(&x86ms->bios, !isapc_ram_fw); - ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1); - if (ret != 0) { - goto bios_error; - } - } - g_free(filename); - - /* map the last 128KB of the BIOS in ISA space */ - x86_isa_bios_init(&x86ms->isa_bios, rom_memory, &x86ms->bios, - !isapc_ram_fw); - - /* map all the bios at the top of memory */ - memory_region_add_subregion(rom_memory, - (uint32_t)(-bios_size), - &x86ms->bios); - return; - -bios_error: - fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); - exit(1); -} - bool x86_machine_is_smm_enabled(const X86MachineState *x86ms) { bool smm_available = false; diff --git a/hw/i386/meson.build b/hw/i386/meson.build index d9da676038c..3437da0aad1 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -4,6 +4,7 @@ i386_ss.add(files( 'e820_memory_layout.c', 'multiboot.c', 'x86.c', + 'x86-cpu.c', )) i386_ss.add(when: 'CONFIG_APIC', if_true: files('vapic.c')) @@ -12,7 +13,7 @@ i386_ss.add(when: 'CONFIG_X86_IOMMU', if_true: files('x86-iommu.c'), i386_ss.add(when: 'CONFIG_AMD_IOMMU', if_true: files('amd_iommu.c'), if_false: files('amd_iommu-stub.c')) i386_ss.add(when: 'CONFIG_I440FX', if_true: files('pc_piix.c')) -i386_ss.add(when: 'CONFIG_MICROVM', if_true: files('microvm.c', 'acpi-microvm.c', 'microvm-dt.c')) +i386_ss.add(when: 'CONFIG_MICROVM', if_true: files('x86-common.c', 'microvm.c', 'acpi-microvm.c', 'microvm-dt.c')) i386_ss.add(when: 'CONFIG_Q35', if_true: files('pc_q35.c')) i386_ss.add(when: 'CONFIG_VMMOUSE', if_true: files('vmmouse.c')) i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport.c')) @@ -22,6 +23,7 @@ i386_ss.add(when: 'CONFIG_SGX', if_true: files('sgx-epc.c','sgx.c'), i386_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-common.c')) i386_ss.add(when: 'CONFIG_PC', if_true: files( + 'x86-common.c', 'pc.c', 'pc_sysfw.c', 'acpi-build.c', From patchwork Thu May 9 17:00:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6CC35C25B74 for ; Thu, 9 May 2024 17:01:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s578x-0002Kx-PX; Thu, 09 May 2024 13:01:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578v-0002Je-Cy for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:18 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s578s-0003ZV-Ly for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274074; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fwfrX5iNrX5LjziOh1abTyopnwgbwoodYNJhfUqWXtg=; b=Ha0sYl826d+sm8GEXgB2upB2qsQBPwPjHrAr2+Xlx9sojFPwJb5da/zjEDFZfyOJ85ij4N NncT43OIDql1beOVgsGg6tpmoULphzOpLl4S6tf0L3yh0i35+C0XrsDrdhkeTSFax5EXmi B3SXEsQjrvdGGnXvb4AiVMRAuEiIeSE= Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-511-g070jOb6N5yBaZwlWBLLoQ-1; Thu, 09 May 2024 13:01:12 -0400 X-MC-Unique: g070jOb6N5yBaZwlWBLLoQ-1 Received: by mail-ed1-f69.google.com with SMTP id 4fb4d7f45d1cf-572a203c05dso650085a12.0 for ; Thu, 09 May 2024 10:01:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274070; x=1715878870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fwfrX5iNrX5LjziOh1abTyopnwgbwoodYNJhfUqWXtg=; b=jq6vFsVPrFNaBCjUTlxLN0Z+JObmPMse2kLilE6D/WYWWjR8hPZOCj3sVUtMcwE7uK CKkduuPlUf4ZsHeh/GkhMkqkUz7qPdWA4vSnK8a8kqJlept07ShNYxxZk3GE/ugF5Xwn 0p1lFk16HKTTBdhCws4XYTJSdbX/BNGIo21N2K/w1CRtIRcVrRImvP+7urUz8gbz+Eun iIk0l/ZiYc7M1vIBbSjGuTZjPX0m4wbBgn8OUaI5F3jTVqo2Iug8u/VSottrHuEZa8dh oFks5JtOub282PF0V/4WbL+7dsAI8bFOIJS6V8mU7Q2JpyVXUHROwo0j4nn3B+kEQ9tY wrhg== X-Gm-Message-State: AOJu0Yy7yHtaG5NGJLVfrJRUAudgo/n+iBXnHScf8Hgw1mqCJ2p6C7Pk 7jibjqRo2JID6gQr0aoUvjnMkzsm/+psoXByHKgmlNPxTmP/K1r6dDLLMrUNvB61AbuV9p6tCu6 WCOiUwWUM8EK65+9C/bwceCE6R3R/WRCu98YQwNiuQ1LdKS0GqWidvhl4ZiXIQWhmM6zT/Myujg 1ey2G/pKvsXYTCVPx1l3LF8sYep0y0r1RlxwjZ X-Received: by 2002:a50:d503:0:b0:56e:215b:75c2 with SMTP id 4fb4d7f45d1cf-5734d5c137amr195830a12.17.1715274070740; Thu, 09 May 2024 10:01:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHuyDFUhwHoku1yoYmYcumNHRkiRzP2CH4HGjIYCJ20G0msQfFbPjf/fDOUhKZ1ULrAnVyJww== X-Received: by 2002:a50:d503:0:b0:56e:215b:75c2 with SMTP id 4fb4d7f45d1cf-5734d5c137amr195820a12.17.1715274070446; Thu, 09 May 2024 10:01:10 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5734d4cf324sm96876a12.24.2024.05.09.10.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:01:10 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 11/13] hw/i386: move rtc-reset-reinjection command out of hw/rtc Date: Thu, 9 May 2024 19:00:42 +0200 Message-ID: <20240509170044.190795-12-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The rtc-reset-reinjection QMP command is specific to x86, other boards do not have the ACK tracking functionality that is needed for RTC interrupt reinjection. Therefore the QMP command is only included in x86, but qmp_rtc_reset_reinjection() is implemented by hw/rtc/mc146818rtc.c and requires tracking of all created RTC devices. Move the implementation to hw/i386, so that 1) it is available even if no RTC device exist 2) the only RTC that exists is easily found in x86ms->rtc. Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- include/hw/rtc/mc146818rtc.h | 2 +- hw/i386/monitor.c | 46 ++++++++++++++++++++++++++++++++++++ hw/rtc/mc146818rtc.c | 12 ++-------- hw/i386/meson.build | 1 + 4 files changed, 50 insertions(+), 11 deletions(-) create mode 100644 hw/i386/monitor.c diff --git a/include/hw/rtc/mc146818rtc.h b/include/hw/rtc/mc146818rtc.h index 97cec0b3e84..64893be1515 100644 --- a/include/hw/rtc/mc146818rtc.h +++ b/include/hw/rtc/mc146818rtc.h @@ -55,6 +55,6 @@ MC146818RtcState *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq); void mc146818rtc_set_cmos_data(MC146818RtcState *s, int addr, int val); int mc146818rtc_get_cmos_data(MC146818RtcState *s, int addr); -void qmp_rtc_reset_reinjection(Error **errp); +void rtc_reset_reinjection(MC146818RtcState *rtc); #endif /* HW_RTC_MC146818RTC_H */ diff --git a/hw/i386/monitor.c b/hw/i386/monitor.c new file mode 100644 index 00000000000..1ebd3564bf2 --- /dev/null +++ b/hw/i386/monitor.c @@ -0,0 +1,46 @@ +/* + * QEMU monitor + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "monitor/monitor.h" +#include "qapi/qmp/qdict.h" +#include "qapi/error.h" +#include "qapi/qapi-commands-misc-target.h" +#include "hw/i386/x86.h" +#include "hw/rtc/mc146818rtc.h" + +#include CONFIG_DEVICES + +void qmp_rtc_reset_reinjection(Error **errp) +{ + X86MachineState *x86ms = X86_MACHINE(qdev_get_machine()); + +#ifdef CONFIG_MC146818RTC + if (x86ms->rtc) { + rtc_reset_reinjection(MC146818_RTC(x86ms->rtc)); + } +#else + assert(!x86ms->rtc); +#endif +} diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index 3379f92748b..8ccee9a385d 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -104,16 +104,9 @@ static void rtc_coalesced_timer_update(MC146818RtcState *s) } } -static QLIST_HEAD(, MC146818RtcState) rtc_devices = - QLIST_HEAD_INITIALIZER(rtc_devices); - -void qmp_rtc_reset_reinjection(Error **errp) +void rtc_reset_reinjection(MC146818RtcState *rtc) { - MC146818RtcState *s; - - QLIST_FOREACH(s, &rtc_devices, link) { - s->irq_coalesced = 0; - } + rtc->irq_coalesced = 0; } static bool rtc_policy_slew_deliver_irq(MC146818RtcState *s) @@ -941,7 +934,6 @@ static void rtc_realizefn(DeviceState *dev, Error **errp) object_property_add_tm(OBJECT(s), "date", rtc_get_date); qdev_init_gpio_out(dev, &s->irq, 1); - QLIST_INSERT_HEAD(&rtc_devices, s, link); } MC146818RtcState *mc146818_rtc_init(ISABus *bus, int base_year, diff --git a/hw/i386/meson.build b/hw/i386/meson.build index 3437da0aad1..03aad10df7a 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -2,6 +2,7 @@ i386_ss = ss.source_set() i386_ss.add(files( 'fw_cfg.c', 'e820_memory_layout.c', + 'monitor.c', 'multiboot.c', 'x86.c', 'x86-cpu.c', From patchwork Thu May 9 17:00:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659960 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52347C10F1A for ; Thu, 9 May 2024 17:03:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s5797-0002Qa-7n; Thu, 09 May 2024 13:01:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s5794-0002PH-5x for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:27 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s5791-0003b5-PZ for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274081; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fwuKd3xDQi5jqV7bVmAt6zG3iu3oNv9dZi8phhwclTk=; b=MYjfxszpUl9XXK0mukPWVayDE/AFn/U4dvwd6/ASuHNsjYOlEpHf9UC+6whoe68it0xJnq Lc0XzQNOoHgTDZLWXd7404GCvQUcAPiMnbl9BMChjT/YVY5kLS53FQ8tjI9+YS0+vuIiPq 1F3n+TSPXhvJbJPD8/JWckdkNJIjIDs= Received: from mail-lf1-f71.google.com (mail-lf1-f71.google.com [209.85.167.71]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-548-ltratU-dMjSEbkIlui_Qng-1; Thu, 09 May 2024 13:01:16 -0400 X-MC-Unique: ltratU-dMjSEbkIlui_Qng-1 Received: by mail-lf1-f71.google.com with SMTP id 2adb3069b0e04-51fa40244f6so1025572e87.1 for ; Thu, 09 May 2024 10:01:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274073; x=1715878873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fwuKd3xDQi5jqV7bVmAt6zG3iu3oNv9dZi8phhwclTk=; b=FmjHOTymRd3NYwcrQvGIliEfPMhf8qHY8QOhA8MLAUPpfVVkhTSmGbg4wc4Ig/MWp0 /MWMXvjqhm+CouNV69m9V27YMORwsIxTOu1if1b1ntlOc4lJkYAypYoIspDO+YkoS9Ne vSXcLsrR0s0RboCUElvfjgcsuC9bLGNZgjb9oo+JIGmIthnfqlSn5po+noc643WjYs86 VT5AmJpfTzDKdQA+1rL7ccNgz4CV1heeLS2wH4+KVTu4AVCgDzBnzCTf5nqQYgdo3lNf 2a7j/j1jQIw6Q23aAdvsGZBCHk+8D3wdYfCiWUMRbijMg3HvQ9QNE/58/yG9Sbzk2Tq4 hZlQ== X-Gm-Message-State: AOJu0YwhNl4mqSHAnH9TwUsSSokH65l0URKT25lT0bhtqO7YIZSV0tOc 0OJVbnClQePhM1H5YU35obBY5Hjw6iZABv2MlrqRyq3vA/GpEkmxFz9xyPoQrofVcH98C50++r5 uwhRTxpA5YwpakM69aGfKWOWQAklJkxOSrtglWqBaTGAbPKHPPDykzQ+rq7UaJ0boRPFNi4Dq9b iLJqyhOz7Op7PC6+R7ltC3ogeP1UwkDicn/NXd X-Received: by 2002:a05:6512:10c9:b0:51e:ef7f:4e89 with SMTP id 2adb3069b0e04-5220fb76884mr102864e87.6.1715274073420; Thu, 09 May 2024 10:01:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG+FRMeRZq1nvhsAjfLlfh8C25qyukNK0bbj5du0KKSnjG3G7MPmDDt9iw3+QmGWhALp4bOog== X-Received: by 2002:a05:6512:10c9:b0:51e:ef7f:4e89 with SMTP id 2adb3069b0e04-5220fb76884mr102842e87.6.1715274073045; Thu, 09 May 2024 10:01:13 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a17922159sm93336666b.97.2024.05.09.10.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:01:11 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 12/13] i386: select correct components for no-board build Date: Thu, 9 May 2024 19:00:43 +0200 Message-ID: <20240509170044.190795-13-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The local APIC is a part of the CPU and has callbacks that are invoked from multiple accelerators. The IOAPIC on the other hand is optional, but ioapic_eoi_broadcast is used by common x86 code to implement the IOAPIC's implicit EOI mode. Add a stub in case the IOAPIC device is not included but the APIC is. Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- hw/intc/ioapic-stub.c | 29 +++++++++++++++++++++++++++++ .gitlab-ci.d/buildtest.yml | 2 +- hw/intc/meson.build | 2 +- target/i386/Kconfig | 1 + 4 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 hw/intc/ioapic-stub.c diff --git a/hw/intc/ioapic-stub.c b/hw/intc/ioapic-stub.c new file mode 100644 index 00000000000..4dcd86248da --- /dev/null +++ b/hw/intc/ioapic-stub.c @@ -0,0 +1,29 @@ +/* + * ioapic.c IOAPIC emulation logic + * + * Copyright (c) 2004-2005 Fabrice Bellard + * + * Split the ioapic logic from apic.c + * Xiantao Zhang + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/intc/ioapic.h" + +void ioapic_eoi_broadcast(int vector) +{ +} diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index f8502905203..62616157206 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -650,7 +650,7 @@ build-tci: # Check our reduced build configurations # requires libfdt: aarch64, arm, i386, loongarch64, microblaze, microblazeel, # mips64el, or1k, ppc, ppc64, riscv32, riscv64, rx, x86_64 -# does not build without boards: i386, x86_64 +# fails qtest without boards: i386, x86_64 build-without-defaults: extends: .native_build_job_template needs: diff --git a/hw/intc/meson.build b/hw/intc/meson.build index f4b540e6a8b..0d1b7d0a432 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -20,7 +20,7 @@ system_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c')) system_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c')) system_ss.add(when: 'CONFIG_I8259', if_true: files('i8259_common.c', 'i8259.c')) system_ss.add(when: 'CONFIG_IMX', if_true: files('imx_avic.c', 'imx_gpcv2.c')) -system_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic_common.c')) +system_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic_common.c'), if_false: files('ioapic-stub.c')) system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c')) system_ss.add(when: 'CONFIG_OPENPIC', if_true: files('openpic.c')) system_ss.add(when: 'CONFIG_PL190', if_true: files('pl190.c')) diff --git a/target/i386/Kconfig b/target/i386/Kconfig index ad9291d3b8f..6b0feef0299 100644 --- a/target/i386/Kconfig +++ b/target/i386/Kconfig @@ -1,5 +1,6 @@ config I386 bool + select APIC # kvm_arch_fixup_msi_route() needs to access PCIDevice select PCI if KVM From patchwork Thu May 9 17:00:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 13659957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB314C10F1A for ; Thu, 9 May 2024 17:03:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s5798-0002Ql-0j; Thu, 09 May 2024 13:01:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s5794-0002PF-4f for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:27 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s5790-0003ax-5G for qemu-devel@nongnu.org; Thu, 09 May 2024 13:01:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1715274081; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1hcm1IKa8Lax1aQxNeVEkxaMcKmsJIcXMqbmtbDBUs4=; b=G1xoXpT2HHfG7+630ZxmN6DAtjZtKKTKHNKRwqLlgCHxAA7et5yfjqWdrOa2o93cGWyLXc XRbFTFoikzLiCLVLJAey+pzYocawMSmVr1AYqHNnfeQRITcWCvAEBOPVmNwyzePV8S+93G p4i4ACxL2IibyCXLKBg83wZpli9ZcwI= Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-487-3A3bRGTbNyyAAm5GD7kJSA-1; Thu, 09 May 2024 13:01:17 -0400 X-MC-Unique: 3A3bRGTbNyyAAm5GD7kJSA-1 Received: by mail-ed1-f70.google.com with SMTP id 4fb4d7f45d1cf-572146eeed3so525443a12.2 for ; Thu, 09 May 2024 10:01:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715274076; x=1715878876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1hcm1IKa8Lax1aQxNeVEkxaMcKmsJIcXMqbmtbDBUs4=; b=Ia7fjbUJkpw4ZeicBHOwOVcNNFkpTlu9rBau1rozlfvbmkNktbaCIa5dWSYxxMUnBN q57Yk3eLby4aZ5q7IosQaKsO0cF1pzyOes5ZfRokDJssoWI/0wz2cA0GJhyOudYJOt1E o/QqWV2pG6qphvYb4/beW5GTF+fth+9hPIMZyXyHioeOnFpztXKaGCTsbgk0X446+YvD wEMD1gYSt8mq5UBbnIz+yBDyR6rlKBj0PIi31WnjYAFNt2b8Td8Sf7XEexny7a6aYCnl f2oaEW4UedtGSExQVNlBAYtp5LQC2Fb/e82q5Lcl62wFPm1ZQIk2j1v+vx/jUJaFqbNv NMwA== X-Gm-Message-State: AOJu0Ywn/YfOlDPKDbvgFHRHpVWdjCnbjiUNvE8P4x/Sluqh69QNxnc7 lT4AZ4Q+AWn43X24fUniRFIK4hr8ST9Ebw5Osapxw3QrcO4QDRDLXEaGxfXXdlUC4SalLXjdRPs XhLA+9A6TuVa9Pa6cef4qtZGnnGjFSeTBRJrwRYEtKpztjo8Qt/U1ci+h7QmL3qrjT6hWckKmO3 fyuB+Vq8gAvkcQ00lxmWRzGmGMR26MsEL+/PVL X-Received: by 2002:a50:870d:0:b0:572:5fff:accd with SMTP id 4fb4d7f45d1cf-5734d590348mr230616a12.6.1715274076032; Thu, 09 May 2024 10:01:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGm9+FqysnC6/VwSzSZ14Ys8hBrm8NopkBaatfbB6POVSgRGtxAQjSM8OVv6l9TDMSvhi+dcg== X-Received: by 2002:a50:870d:0:b0:572:5fff:accd with SMTP id 4fb4d7f45d1cf-5734d590348mr230600a12.6.1715274075691; Thu, 09 May 2024 10:01:15 -0700 (PDT) Received: from avogadro.local ([151.95.155.52]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733c2c7d6esm880328a12.72.2024.05.09.10.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 10:01:13 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: thuth@redhat.com Subject: [PATCH 13/13] tests/qtest: arm: fix operation in a build without any boards or devices Date: Thu, 9 May 2024 19:00:44 +0200 Message-ID: <20240509170044.190795-14-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240509170044.190795-1-pbonzini@redhat.com> References: <20240509170044.190795-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.581, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org ARM/aarch64 are easy to fix because they already have to pass a machine type by hand. Just guard the tests with a check that the machine actually exists. Signed-off-by: Paolo Bonzini Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- tests/qtest/arm-cpu-features.c | 4 ++++ tests/qtest/migration-test.c | 6 ++++++ tests/qtest/numa-test.c | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 9d6e6190d55..966c65d5c3e 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -632,6 +632,10 @@ int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); + if (!qtest_has_machine("virt")) { + goto out; + } + if (qtest_has_accel("tcg")) { qtest_add_data_func("/arm/query-cpu-model-expansion", NULL, test_query_cpu_model_expansion); diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c index 5d6d8cd6343..31045b69fa7 100644 --- a/tests/qtest/migration-test.c +++ b/tests/qtest/migration-test.c @@ -813,6 +813,12 @@ static int test_migrate_start(QTestState **from, QTestState **to, kvm_opts = ",dirty-ring-size=4096"; } + if (!qtest_has_machine(machine_alias)) { + g_autofree char *msg = g_strdup_printf("machine %s not supported", machine_alias); + g_test_skip(msg); + return -1; + } + machine = resolve_machine_version(machine_alias, QEMU_ENV_SRC, QEMU_ENV_DST); diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c index 4f4404a4b14..7aa262dbb99 100644 --- a/tests/qtest/numa-test.c +++ b/tests/qtest/numa-test.c @@ -558,6 +558,9 @@ int main(int argc, char **argv) } if (g_str_equal(arch, "aarch64")) { + if (!qtest_has_machine("virt")) { + goto out; + } g_string_append(args, " -machine virt"); } @@ -590,5 +593,6 @@ int main(int argc, char **argv) aarch64_numa_cpu); } +out: return g_test_run(); }