From patchwork Fri May 10 11:04:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TElBTktVTiBZQU5HICjmnajov57lnaQp?= X-Patchwork-Id: 13661322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B291C25B5F for ; Fri, 10 May 2024 11:05:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E904410E8F6; Fri, 10 May 2024 11:05:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="SwirdxV2"; dkim-atps=neutral Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id E0BB910E8F3 for ; Fri, 10 May 2024 11:05:37 +0000 (UTC) X-UUID: 37a82f700ebd11ef8065b7b53f7091ad-20240510 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=tGYdTrBFfpb9eyzoW0iXytY9VmA09b1t9jreY07jxjA=; b=SwirdxV2yb/ioStg0g2/gkoG5tfI425yf9jydDL8YcYMrxxVfrU+CcTA+ygdIcmsQDCkGd1JC+lHjG7fSf2yBHmsPxKMDavQ6RNDrCeRzlJcwuSHulEnCL0csVfZAShd+EpOpbECI3bI9ZUmSkAUDO2xms6koMASD/nP+oiraio=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.38, REQID:72aa8e58-bad5-464f-ba0c-ed3ee568eb83, IP:0, U RL:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:-50 X-CID-META: VersionHash:82c5f88, CLOUDID:3113effb-ed05-4274-9204-014369d201e8, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:1,IP:nil,UR L:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,S PR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 37a82f700ebd11ef8065b7b53f7091ad-20240510 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 617051973; Fri, 10 May 2024 19:05:31 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 10 May 2024 04:05:30 -0700 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 10 May 2024 19:05:30 +0800 From: Liankun Yang To: , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 1/2] Add write DP phyd register from parse dts Date: Fri, 10 May 2024 19:04:14 +0800 Message-ID: <20240510110523.12524-2-liankun.yang@mediatek.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240510110523.12524-1-liankun.yang@mediatek.com> References: <20240510110523.12524-1-liankun.yang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" During the testing phase, screen flickering is observed when using displayport for screen casting. Relevant SSC register parameters are set in dts to address the screen flickering issue effectively and improve compatibility with different devices by adjusting the SSC gear. Obtaining the DPTX node, parsing the dts to obtain PHY register address and value can adapt to settings of different manufacturers projects. Changeds in v2: - Optimized method of writing to DP PHY register https://patchwork.kernel.org/project/linux-mediatek/patch/ 20240403040517.3279-1-liankun.yang@mediatek.com/ Signed-off-by: Liankun Yang --- drivers/phy/mediatek/phy-mtk-dp.c | 37 +++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c index d7024a144335..ce78112d5938 100644 --- a/drivers/phy/mediatek/phy-mtk-dp.c +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -28,6 +28,10 @@ #define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38) #define DP_GLB_SW_RST_PHYD BIT(0) +#define MTK_DP_PHY_DIG_GLB_DA_REG_14 (PHY_OFFSET + 0xD8) +#define XTP_GLB_TXPLL_SSC_DELTA_RBR_DEFAULT GENMASK(15, 0) +#define XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT GENMASK(31, 16) + #define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138) #define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238) #define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338) @@ -78,10 +82,39 @@ #define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) +#define SSC_SETTING "dp-ssc-setting" +#define RG_XTP_GLB_TXPLL_SSC_DELTA_HBR "ssc-delta-hbr" + struct mtk_dp_phy { struct regmap *regs; + struct device *dev; }; +static int mtk_dp_set_ssc_config(struct phy *phy, struct mtk_dp_phy *dp_phy) +{ + int ret; + u32 read_value = 0, reg_mask = 0; + struct device_node *ssc_node = NULL; + + ssc_node = of_find_node_by_name(dp_phy->dev->of_node, SSC_SETTING); + if (!ssc_node) { + dev_err(&phy->dev, "SSC node is NULL\n"); + return -ENODEV; + } + + ret = of_property_read_u32(ssc_node, RG_XTP_GLB_TXPLL_SSC_DELTA_HBR, &read_value); + if (ret < 0 || !read_value) { + dev_err(&phy->dev, "Read SSC vlaue fail!\n"); + return -EINVAL; + } + read_value |= read_value << 16; + reg_mask |= XTP_GLB_TXPLL_SSC_DELTA_HBR_DEFAULT; + + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_GLB_DA_REG_14, reg_mask, read_value); + + return 0; +} + static int mtk_dp_phy_init(struct phy *phy) { struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); @@ -137,6 +170,8 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); + mtk_dp_set_ssc_config(phy, dp_phy); + return 0; } @@ -186,6 +221,8 @@ static int mtk_dp_phy_probe(struct platform_device *pdev) if (!dev->of_node) phy_create_lookup(phy, "dp", dev_name(dev)); + dp_phy->dev = dev; + return 0; } From patchwork Fri May 10 11:04:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TElBTktVTiBZQU5HICjmnajov57lnaQp?= X-Patchwork-Id: 13661321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D4F4C25B10 for ; Fri, 10 May 2024 11:05:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 11CEC10E8E1; Fri, 10 May 2024 11:05:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="pvhpW5hj"; dkim-atps=neutral Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id B110310E8E1 for ; Fri, 10 May 2024 11:05:37 +0000 (UTC) X-UUID: 3858353c0ebd11ef8065b7b53f7091ad-20240510 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=kpRLxFp1HniKMgGxgeGEPO0SSPqHobCE+LsRmF4NMto=; b=pvhpW5hj2YNG0F4cXbOQvaxS1Kh8OHJ89wIUS55tbsOURE77hW3bpD8q0M3SRPeOMY4SBAVk8PdaPM1dBLePN8vH5hH9SMuUbpAMUd06ViL0vSyXO6MSm7Ji4wNBlXxa/WQJ8oebGbwsg2WxHgDt/n7lapHdOoWQNRF1f9c0z8Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.38, REQID:c9705c32-425e-4ca0-b8c8-2e5db76f7ddf, IP:0, U RL:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:20 X-CID-META: VersionHash:82c5f88, CLOUDID:1bcb3287-8d4f-477b-89d2-1e3bdbef96d1, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: 3858353c0ebd11ef8065b7b53f7091ad-20240510 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1906352426; Fri, 10 May 2024 19:05:32 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 10 May 2024 19:05:31 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 10 May 2024 19:05:30 +0800 From: Liankun Yang To: , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 2/2] Add dp PHY dt-bindings Date: Fri, 10 May 2024 19:04:15 +0800 Message-ID: <20240510110523.12524-3-liankun.yang@mediatek.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240510110523.12524-1-liankun.yang@mediatek.com> References: <20240510110523.12524-1-liankun.yang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add dp PHY dt-bindings. Changeds in v2: - Add dp PHY dt-bindings. https://patchwork.kernel.org/project/linux-mediatek/patch/ 20240403040517.3279-1-liankun.yang@mediatek.com/ Signed-off-by: Liankun Yang --- .../display/mediatek/mediatek.phy-dp.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml index 000000000000..476bc329363f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek.phy-dp.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,phy-dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Port Controller + +maintainers: + - Mac shen + - Liankun yang + +description: | + Special settings need to be configured by MediaTek DP based on the actual + hardware situation. For example, when using a certain brand's docking + station for display projection, garbage may appear. Adjusting the specific + ssc value can resolve this issue. + +properties: + status: disabled + description: | + Since the DP driver has already registered the DP PHY device + through mtk_dp_register_phy(), so the status is disabled. + + dp-ssc-setting: + - ssc-delta-hbr + description: Specific values are set based on the actual HW situation. + +required: + - status + - dp-ssc-setting + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy-dp@1c600000 { + status = "disabled"; + dp-ssc-setting { + ssc-delta-hbr = <0x01fe>; + } + }; + };