From patchwork Sun May 12 08:28:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 13662619 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E07112E71; Sun, 12 May 2024 08:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715502564; cv=none; b=OWTqSgwo+DngU/3T3E0tNne7dTxTj1zQCcoR7tZlNOLfkaupZcwKpode9y0ECv4KC+mdW+vaGKBb69JVeT7dIbeZX8XGde8EHZRTKvBczN+RDHpRgvEWZ9x+wO88oGHXjv1XhsJiiauzxrTO2YFiv/TJUoA9N8b6Fxxdf+Y6AsU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715502564; c=relaxed/simple; bh=hkRcLNpi4Lp6ijSDG6LJlaGMQFI9QGMsz7AEzoplLvQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QY0yk4pvD6lOEvrqsrWt8pwIGj9y3YpjCUp1rz70qW5yPYEreAh3ogsESD2L1mEBkMfMZOD1fmFtClFS1cN9urQsdzSBv8hEpkn1VSs8E5Frwagw4GwhoOOVLbZqpR4eR357rHSQPbqkt5BXKA4fuyrRAa0LW8Q/zUcn+Wa5Ekk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=fwxA5AuE; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="fwxA5AuE" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 44C6wAgA017175; Sun, 12 May 2024 08:29:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=qcppdkim1; bh=9grXqED j9b6Vod/joeuSG+eZOG7oD6vV6i9bV40dO2A=; b=fwxA5AuEAJPXh6Y8OSUwGEv D1wQYSxB0MN9vTsoiZOUtM9P38dFChYs4JamBu+W0VUz1ydU7cd9KGZ7JhvjFqrU Ggvy12oxuPJSqVFl8vyz/5yLVWredxA9sTX3tLbBu30MUZ6j6EQSqwbL8qTD9qDj 7y7gczKWiIGfD+VtVNpFOmTjBBFvQFCMG0+CZ3zipbHpg8dCQwoC+fEDt5hPT+6Q 6yaY5jFgBZ4A9VRvaFcFNuzYyLCrtywAYchVBuvAHrtn/fWGaMIOKgXEOgQ5GEwi 3o03RRVsvtmy4xbfT/xT0Ricub2kBZDRy8nI+RYH5Y1ws+91KgMXFC/DUe0f17g= = Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3y208vshdh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 12 May 2024 08:29:02 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 44C8Sxn0009791; Sun, 12 May 2024 08:28:59 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3y21rkna3f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 12 May 2024 08:28:59 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 44C8SxbD009761; Sun, 12 May 2024 08:28:59 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-devipriy-blr.qualcomm.com [10.131.37.37]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 44C8Sw6i009755 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 12 May 2024 08:28:59 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 4059087) id 1065A41042; Sun, 12 May 2024 13:58:58 +0530 (+0530) From: devi priya To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, manivannan.sadhasivam@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: quic_devipriy@quicinc.com Subject: [PATCH V5 1/6] Add PCIe pipe clock definitions for IPQ9574 SoC. Date: Sun, 12 May 2024 13:58:53 +0530 Message-Id: <20240512082858.1806694-2-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240512082858.1806694-1-quic_devipriy@quicinc.com> References: <20240512082858.1806694-1-quic_devipriy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nV2XN6COcDa1D59cfnw-ocsatfbB5Nkw X-Proofpoint-GUID: nV2XN6COcDa1D59cfnw-ocsatfbB5Nkw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-12_05,2024-05-10_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 suspectscore=0 priorityscore=1501 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405120061 Acked-by: Stephen Boyd Acked-by: Krzysztof Kozlowski Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: devi priya --- Changes in V5: - No changes include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 08fd3a37acaa..52123c5a09fa 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -216,4 +216,8 @@ #define GCC_CRYPTO_AHB_CLK 207 #define GCC_USB0_PIPE_CLK 208 #define GCC_USB0_SLEEP_CLK 209 +#define GCC_PCIE0_PIPE_CLK 210 +#define GCC_PCIE1_PIPE_CLK 211 +#define GCC_PCIE2_PIPE_CLK 212 +#define GCC_PCIE3_PIPE_CLK 213 #endif From patchwork Sun May 12 08:28:54 2024 Content-Type: text/plain; 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Sun, 12 May 2024 08:28:59 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 44C8Sxrr009760; Sun, 12 May 2024 08:28:59 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-devipriy-blr.qualcomm.com [10.131.37.37]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 44C8SwMw009756 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 12 May 2024 08:28:59 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 4059087) id 13C6C41970; Sun, 12 May 2024 13:58:58 +0530 (+0530) From: devi priya To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, manivannan.sadhasivam@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: quic_devipriy@quicinc.com Subject: [PATCH V5 2/6] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Date: Sun, 12 May 2024 13:58:54 +0530 Message-Id: <20240512082858.1806694-3-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240512082858.1806694-1-quic_devipriy@quicinc.com> References: <20240512082858.1806694-1-quic_devipriy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: S1w_IeEndSfpfwlgC9q8MvBE8BsvTfP2 X-Proofpoint-ORIG-GUID: S1w_IeEndSfpfwlgC9q8MvBE8BsvTfP2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-12_05,2024-05-10_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 mlxscore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405120063 Add the PCIe pipe clocks needed for enabling PCIe in IPQ9574. Acked-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: devi priya --- Changes in V5: - No changes drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 3738f92c6f9c..7d1b9d2468e6 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -1572,6 +1572,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie0_pipe_clk = { + .halt_reg = 0x28044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x28044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { .reg = 0x29064, .clkr = { @@ -1586,6 +1604,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie1_pipe_clk = { + .halt_reg = 0x29044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x29044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie1_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { .reg = 0x2a064, .clkr = { @@ -1600,6 +1636,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie2_pipe_clk = { + .halt_reg = 0x2a044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2a044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie2_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie2_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { .reg = 0x2b064, .clkr = { @@ -1614,6 +1668,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie3_pipe_clk = { + .halt_reg = 0x2b044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2b044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_pcie3_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie3_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(100000000, P_GPLL0, 8, 0, 0), @@ -4007,9 +4079,13 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr, [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr, [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr, + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr, + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr, + [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr, + [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, From patchwork Sun May 12 08:28:55 2024 Content-Type: text/plain; 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Signed-off-by: devi priya --- Changes in V5: - Dropped msi-parent for pcie node, as it is handled by "msi" IRQ .../devicetree/bindings/pci/qcom,pcie.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index cf9a6910b542..65d4c0c0bcd0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -26,6 +26,7 @@ properties: - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 + - qcom,pcie-ipq9574 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sdm845 @@ -161,6 +162,7 @@ allOf: enum: - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 + - qcom,pcie-ipq9574 then: properties: reg: @@ -397,6 +399,39 @@ allOf: - const: axi_m_sticky # AXI Master Sticky reset - const: axi_s_sticky # AXI Slave Sticky reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq9574 + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: ahb # AHB clock + - const: aux # Auxiliary clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: axi_bridge # AXI bridge clock + - const: rchng + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sticky # Core Sticky reset + - const: axi_s_sticky # AXI Slave Sticky reset + - const: axi_s # AXI Slave reset + - const: axi_m_sticky # AXI Master Sticky reset + - const: axi_m # AXI Master reset + - const: aux # AUX Reset + - const: ahb # AHB Reset + - if: properties: compatible: @@ -507,6 +542,7 @@ allOf: - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 + - qcom,pcie-ipq9574 - qcom,pcie-qcs404 then: required: @@ -566,6 +602,7 @@ allOf: - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 + - qcom,pcie-ipq9574 - qcom,pcie-qcs404 then: properties: From patchwork Sun May 12 08:28:56 2024 Content-Type: text/plain; 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Sun, 12 May 2024 08:28:59 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 44C8SxVK009762; Sun, 12 May 2024 08:28:59 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-devipriy-blr.qualcomm.com [10.131.37.37]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 44C8SwpM009757 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 12 May 2024 08:28:59 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 4059087) id 1C47A4198A; Sun, 12 May 2024 13:58:58 +0530 (+0530) From: devi priya To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, manivannan.sadhasivam@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: quic_devipriy@quicinc.com Subject: [PATCH V5 4/6] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes Date: Sun, 12 May 2024 13:58:56 +0530 Message-Id: <20240512082858.1806694-5-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240512082858.1806694-1-quic_devipriy@quicinc.com> References: <20240512082858.1806694-1-quic_devipriy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: DFxju643ej2s4xi7k5_j69ck04fJBPbI X-Proofpoint-ORIG-GUID: DFxju643ej2s4xi7k5_j69ck04fJBPbI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-12_05,2024-05-10_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 phishscore=0 malwarescore=0 suspectscore=0 impostorscore=0 clxscore=1015 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405120063 Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3 host whereas PCIe2 & PCIe3 are 2-lane Gen3 host. Signed-off-by: devi priya --- Changes in V5: - Dropped anoc and snoc lane clocks from Phy nodes and enabled them via interconnect. - Dropped msi-parent as it is handled via msi IRQ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 365 +++++++++++++++++++++++++- 1 file changed, 361 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 5b3e69379b1f..da6418c9d52b 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -226,6 +226,52 @@ rpm_msg_ram: sram@60000 { reg = <0x00060000 0x6000>; }; + pcie0_phy: phy@84000 { + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; + reg = <0x00084000 0x1000>; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "pipe"; + + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + + pcie2_phy: phy@8c000 { + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x0008c000 0x2000>; + + clocks = <&gcc GCC_PCIE2_AUX_CLK>, + <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_PCIE2_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "pipe"; + + assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE2_PHY_BCR>, + <&gcc GCC_PCIE2PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie2_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; @@ -233,6 +279,52 @@ rng: rng@e3000 { clock-names = "core"; }; + pcie3_phy: phy@f4000 { + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x000f4000 0x2000>; + + clocks = <&gcc GCC_PCIE3_AUX_CLK>, + <&gcc GCC_PCIE3_AHB_CLK>, + <&gcc GCC_PCIE3_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "pipe"; + + assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE3_PHY_BCR>, + <&gcc GCC_PCIE3PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie3_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + + pcie1_phy: phy@fc000 { + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; + reg = <0x000fc000 0x1000>; + + clocks = <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "pipe"; + + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie1_pipe_clk_src"; + + #phy-cells = <0>; + status = "disabled"; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x5a1>; @@ -299,10 +391,10 @@ gcc: clock-controller@1800000 { clocks = <&xo_board_clk>, <&sleep_clk>, <0>, - <0>, - <0>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, + <&pcie2_phy>, + <&pcie3_phy>, <0>; #clock-cells = <1>; #reset-cells = <1>; @@ -747,6 +839,271 @@ frame@b128000 { status = "disabled"; }; }; + + pcie1: pci@10000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x10000000 0xf1d>, + <0x10000F20 0xa8>, + <0x10001000 0x1000>, + <0x000F8000 0x4000>, + <0x10100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>, /* I/O */ + <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>; /* MEM */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + /* clocks and clock-names are used to enable the clock in CBCR */ + clocks = <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE1_RCHNG_CLK>; + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_S_ARES>, + <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_M_ARES>, + <&gcc GCC_PCIE1_AUX_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, + <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; + interconnect-names = "pcie-mem", "cpu-pcie"; + status = "disabled"; + }; + + pcie3: pci@18000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x18000000 0xf1d>, + <0x18000F20 0xa8>, + <0x18001000 0x1000>, + <0x000F0000 0x4000>, + <0x18100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <4>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, /* I/O */ + <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; /* MEM */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + /* clocks and clock-names are used to enable the clock in CBCR */ + clocks = <&gcc GCC_PCIE3_AHB_CLK>, + <&gcc GCC_PCIE3_AUX_CLK>, + <&gcc GCC_PCIE3_AXI_M_CLK>, + <&gcc GCC_PCIE3_AXI_S_CLK>, + <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3_RCHNG_CLK>; + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE3_PIPE_ARES>, + <&gcc GCC_PCIE3_CORE_STICKY_ARES>, + <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE3_AXI_S_ARES>, + <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE3_AXI_M_ARES>, + <&gcc GCC_PCIE3_AUX_ARES>, + <&gcc GCC_PCIE3_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie3_phy>; + phy-names = "pciephy"; + interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, + <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>; + interconnect-names = "pcie-mem", "cpu-pcie"; + status = "disabled"; + }; + + pcie2: pci@20000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x20000000 0xf1d>, + <0x20000F20 0xa8>, + <0x20001000 0x1000>, + <0x00088000 0x4000>, + <0x20100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <3>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>, /* I/O */ + <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>; /* MEM */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + /* clocks and clock-names are used to enable the clock in CBCR */ + clocks = <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_PCIE2_AUX_CLK>, + <&gcc GCC_PCIE2_AXI_M_CLK>, + <&gcc GCC_PCIE2_AXI_S_CLK>, + <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE2_RCHNG_CLK>; + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE2_PIPE_ARES>, + <&gcc GCC_PCIE2_CORE_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_S_ARES>, + <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_M_ARES>, + <&gcc GCC_PCIE2_AUX_ARES>, + <&gcc GCC_PCIE2_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie2_phy>; + phy-names = "pciephy"; + interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, + <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>; + interconnect-names = "pcie-mem", "cpu-pcie"; + status = "disabled"; + }; + + pcie0: pci@28000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x28000000 0xf1d>, + <0x28000F20 0xa8>, + <0x28001000 0x1000>, + <0x00080000 0x4000>, + <0x28100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>, /* I/O */ + <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>; /* MEM */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + /* clocks and clock-names are used to enable the clock in CBCR */ + clocks = <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>; + clock-names = "ahb", + "aux", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_S_ARES>, + <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_M_ARES>, + <&gcc GCC_PCIE0_AUX_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, + <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + status = "disabled"; + }; + }; thermal-zones { From patchwork Sun May 12 08:28:57 2024 Content-Type: text/plain; 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Sun, 12 May 2024 08:29:00 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 44C8PgI6005071; Sun, 12 May 2024 08:29:00 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-devipriy-blr.qualcomm.com [10.131.37.37]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 44C8T0qN009817 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 12 May 2024 08:29:00 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 4059087) id 1FA6E4198E; Sun, 12 May 2024 13:58:58 +0530 (+0530) From: devi priya To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, manivannan.sadhasivam@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: quic_devipriy@quicinc.com Subject: [PATCH V5 5/6] arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllers Date: Sun, 12 May 2024 13:58:57 +0530 Message-Id: <20240512082858.1806694-6-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240512082858.1806694-1-quic_devipriy@quicinc.com> References: <20240512082858.1806694-1-quic_devipriy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rfBmmQ0BCHr85qnnIjOWZb476pwGGbYQ X-Proofpoint-ORIG-GUID: rfBmmQ0BCHr85qnnIjOWZb476pwGGbYQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-12_05,2024-05-10_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405120063 Enable the PCIe controller and PHY nodes corresponding to RDP 433. Signed-off-by: devi priya --- Changes in V5: - No change arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 113 ++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 1bb8d96c9a82..f4b6d540612c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include #include "ipq9574-rdp-common.dtsi" / { @@ -15,6 +16,45 @@ / { compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; }; +&pcie1_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default>; + + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie2_phy { + status = "okay"; +}; + +&pcie2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_default>; + + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie3_phy { + status = "okay"; +}; + +&pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_default>; + + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; @@ -28,6 +68,79 @@ &sdhc_1 { }; &tlmm { + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio25"; + function = "pcie1_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins = "gpio27"; + function = "pcie1_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie2_default: pcie2-default-state { + clkreq-n-pins { + pins = "gpio28"; + function = "pcie2_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio29"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins = "gpio30"; + function = "pcie2_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio31"; + function = "pcie3_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio32"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio33"; + function = "pcie3_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio5"; From patchwork Sun May 12 08:28:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 13662621 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D56FC14286; Sun, 12 May 2024 08:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 12 May 2024 08:29:04 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 44C8Sx5R009796; Sun, 12 May 2024 08:29:00 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3y21rkna3y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 12 May 2024 08:29:00 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 44C8Sxnw009763; Sun, 12 May 2024 08:29:00 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-devipriy-blr.qualcomm.com [10.131.37.37]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 44C8T0wx009816 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 12 May 2024 08:29:00 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 4059087) id 22D794199E; Sun, 12 May 2024 13:58:58 +0530 (+0530) From: devi priya To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, manivannan.sadhasivam@linaro.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: quic_devipriy@quicinc.com Subject: [PATCH V5 6/6] PCI: qcom: Add support for IPQ9574 Date: Sun, 12 May 2024 13:58:58 +0530 Message-Id: <20240512082858.1806694-7-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240512082858.1806694-1-quic_devipriy@quicinc.com> References: <20240512082858.1806694-1-quic_devipriy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xHUAt-wAPY5e1AxWjXLJQ_L5P6vQPpFo X-Proofpoint-ORIG-GUID: xHUAt-wAPY5e1AxWjXLJQ_L5P6vQPpFo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-12_05,2024-05-10_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 malwarescore=0 phishscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405120063 The IPQ9574 platform has 4 Gen3 PCIe controllers: two single-lane and two dual-lane based on SNPS core 5.70a The Qcom IP rev is 1.27.0 and Synopsys IP rev is 5.80a Added a new compatible 'qcom,pcie-ipq9574' and 'ops_1_27_0' which reuses all the members of 'ops_2_9_0' except for the post_init as the SLV_ADDR_SPACE_SIZE configuration differs between 2_9_0 and 1_27_0. Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: devi priya --- Changes in V5: - Rebased on top of the below series which adds support for fetching clocks from the device tree https://lore.kernel.org/linux-pci/20240417-pci-qcom-clk-bulk-v1-1-52ca19b3d6b2@linaro.org/ drivers/pci/controller/dwc/pcie-qcom.c | 36 +++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 3d2eeff9a876..af36a29c092e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -106,6 +106,7 @@ /* PARF_SLV_ADDR_SPACE_SIZE register value */ #define SLV_ADDR_SPACE_SZ 0x10000000 +#define SLV_ADDR_SPACE_SZ_1_27_0 0x08000000 /* PARF_MHI_CLOCK_RESET_CTRL register fields */ #define AHB_CLK_EN BIT(0) @@ -1095,16 +1096,13 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) return clk_bulk_prepare_enable(res->num_clks, res->clks); } -static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) +static int qcom_pcie_post_init(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; int i; - writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); - val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); @@ -1144,6 +1142,22 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) return 0; } +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) +{ + writel(SLV_ADDR_SPACE_SZ_1_27_0, + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); + + return qcom_pcie_post_init(pcie); +} + +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) +{ + writel(SLV_ADDR_SPACE_SZ, + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); + + return qcom_pcie_post_init(pcie); +} + static int qcom_pcie_link_up(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -1297,6 +1311,15 @@ static const struct qcom_pcie_ops ops_2_9_0 = { .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; +/* Qcom IP rev.: 1.27.0 Synopsys IP rev.: 5.80a */ +static const struct qcom_pcie_ops ops_1_27_0 = { + .get_resources = qcom_pcie_get_resources_2_9_0, + .init = qcom_pcie_init_2_9_0, + .post_init = qcom_pcie_post_init_1_27_0, + .deinit = qcom_pcie_deinit_2_9_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 = { .ops = &ops_1_0_0, }; @@ -1334,6 +1357,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { .no_l0s = true, }; +static const struct qcom_pcie_cfg cfg_1_27_0 = { + .ops = &ops_1_27_0, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, @@ -1603,6 +1630,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_1_27_0 }, { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },