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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Shay Drory , Mark Bloch , Tariq Toukan Subject: [PATCH net-next 1/3] net/mlx5: Enable 8 ports LAG Date: Sun, 12 May 2024 15:43:03 +0300 Message-ID: <20240512124306.740898-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240512124306.740898-1-tariqt@nvidia.com> References: <20240512124306.740898-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|PH7PR12MB8428:EE_ X-MS-Office365-Filtering-Correlation-Id: dde0d0e5-a209-460f-b852-08dc72813a9d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: F5OJ1Q4/EPKPs8XYWq5tLjeLZAWnz3eYnH60aH761BuVZ5cTiuaBQKMr//g4adjVeriT4IcaU4Z4K4TmKL40rG3qTO7y42YkIasmXg3WDO/cWFtzpGGG6IlpvHDDLuVgKldOZpKZgHN7l/HF155ktGZcphxe1/J1EqmNyyliEByWEaXsK/gsQ3KHPtqJUNtrtbJgnachl0Y88LPEP2YNfH5FZ9A07Rsu6fZCo0yfkeZ+2qI5M9OaqW40ZOVFm1NdB8+r6lNwIXu5IBvegIV9AeLhTmMpN/REBBf+IOaU/XWpAQBh1caY0SIxQ59o6QSF4EvOj+gJFzVG+CDtMucIQaCM4jRaFRA+TE2KP2RLkZ9mRYE+ChbKkUz2ewXbh1wJ3dPAH+8YD2cS096wAWbrN/l6gVwkpbSgv79HpJBXUlqg1BMwiEYvUu9hQpHpz0k9bX8hlTdrdNEHYsTjZhGNtTcu2n/QVcTNpoCIsmCqfaK+VxvJaJdqbnd/ZHqRw+zG5lpNyDPlxheenQLLyUhZ5Jcp8Y3ffzzlzHhpHpkF7R3Ey+YE+VhgeeRRJ9ej0upLrzR4wzkQSnpom84VHi4X3g+2sqGWWKKF7f495bkA3BPwWUMEbWP5goCuv2NsrOAjauE1yRoOryBPksu82yKtRbuWIsbm9mA6VF4VZvU7gddl7DLJEoQvZur3fTcDx8qF/eEP/m40IT7NJ9wB5TOiQ2EQ3gJpC9nTGib1641PN+wI71jm+RIqamfO6narUNM9YLebBL4gzQZHUoCv4c8QudMjHmRWDh3C7nbxCNDt45D+9k+JwTnj6oqZwe6nB6Bm39ExXsnIT7I0O3vdaVUjgu+ehXcWg/0IylYwJJEypxY0Z0f2kEJ0RQ/btvDNfBmaZj0byt86rmmUzEIcHXHNzHjz8ThaRNKydgnahcyLkVGbqIUk0JahYv9WLaus9PU/7m8ntQBVKuBHyiP1gY5W2c4sU+gwinXeHxbW3I186tXkYGA8F0GvQA47VpVR8mt+IDkuqs47fzo863iCWYk1S40Vuywo3DxLrAvjVFUvi9fe1YU82+5YajRRs8rHsEeNngEYCvf80MiSm1UNPVHnqnmjH9wuvhTiTEzR1rhkOM0YgRgqAUcHEiExV7to5BrVXuclCR4gNLBpCa3fGD0XogQ6HpEHvhNDuesWOR1CJKd/JMb+/gaDRtrAijeqzmSHPQCPUtGaGaWaPg4UFPvbNbdVEAp1xAWbGjhlgNBJ9xMY+EU/VEEvQC0QvXr8rT2HuQo096Rd/n1VZSK5zB8aiwc2CVVKfjvczKz+7hnYmIOQ/IOPAGGZqIHb8v5coo80NUdWBz20OvcvK4UI2Q6UTyRv8/s2dRi6vPyD+/GHv+k= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(36860700004)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2024 12:44:13.7967 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dde0d0e5-a209-460f-b852-08dc72813a9d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8428 X-Patchwork-Delegate: kuba@kernel.org From: Shay Drory This patch adds to mlx5 drivers support for 8 ports HCAs. Starting with ConnectX-8 HCAs with 8 ports are possible. As most driver parts aren't affected by such configuration most driver code is unchanged. Specially the only affected areas are: - Lag - Multiport E-Switch - Single FDB E-Switch All of the above are already factored in generic way, and LAG and VF LAG are tested, so all that left is to change a #define and remove checks which are no longer needed. However, Multiport E-Switch is not tested yet, so it is left untouched. This patch will allow to create hardware LAG/VF LAG when all 8 ports are added to the same bond device. for example, In order to activate the hardware lag a user can execute the following: ip link add bond0 type bond ip link set bond0 type bond miimon 100 mode 2 ip link set eth2 master bond0 ip link set eth3 master bond0 ip link set eth4 master bond0 ip link set eth5 master bond0 ip link set eth6 master bond0 ip link set eth7 master bond0 ip link set eth8 master bond0 ip link set eth9 master bond0 Where eth2, eth3, eth4, eth5, eth6, eth7, eth8 and eth9 are the PFs of the same HCA. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 3 --- include/linux/mlx5/driver.h | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index 69d482f7c5a2..5e2171ff0a89 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -713,7 +713,6 @@ int mlx5_deactivate_lag(struct mlx5_lag *ldev) return 0; } -#define MLX5_LAG_OFFLOADS_SUPPORTED_PORTS 4 bool mlx5_lag_check_prereq(struct mlx5_lag *ldev) { #ifdef CONFIG_MLX5_ESWITCH @@ -739,8 +738,6 @@ bool mlx5_lag_check_prereq(struct mlx5_lag *ldev) if (mlx5_eswitch_mode(ldev->pf[i].dev) != mode) return false; - if (mode == MLX5_ESWITCH_OFFLOADS && ldev->ports > MLX5_LAG_OFFLOADS_SUPPORTED_PORTS) - return false; #else for (i = 0; i < ldev->ports; i++) if (mlx5_sriov_is_enabled(ldev->pf[i].dev)) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index bf9324a31ae9..8218588688b5 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -85,7 +85,7 @@ enum mlx5_sqp_t { }; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Carolina Jubran , Tariq Toukan Subject: [PATCH net-next 2/3] net/mlx5e: Modifying channels number and updating TX queues Date: Sun, 12 May 2024 15:43:04 +0300 Message-ID: <20240512124306.740898-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240512124306.740898-1-tariqt@nvidia.com> References: <20240512124306.740898-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AE:EE_|DM4PR12MB7646:EE_ X-MS-Office365-Filtering-Correlation-Id: d6e449c1-ee69-4196-b579-08dc72813bcf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|82310400017|1800799015; X-Microsoft-Antispam-Message-Info: TuA7zalNQnluLombki07TwSRkHSMTi8jwwuNEruuXZLjYnqDlC8MO3rFNEs0Zd4tl+Vw1YVB+nskaTm0wkzVg8BJddi72xrohspSOSZXRrPt8vPVyKYTbunoSEG+05BjvxeJZJkh998PTff1hn5trJz7Qf5/3DXJrg3J6/pU4kT8SrWeD8IZjykf9HqYEhqlr2K15LxvUuX/0x/Jslhj3JrKo9z3fpS1W2wUHJEMVP7aE+xLDS05Ut7c/kVzbm85FSO8g4dc+GlRwK/CX2YOt9YZCiScX1RstVkD32rsgL+SR/mNchU6A0aOtoipsHd8KDnjS6akfp6z4+DsrcRRFoq8ALkKBONPre116v41N8GhJAJkAE1hhqCBC4O0Xy7fFhivpvwvxhkkLQwZeB2vLT6JTlIg1/FOxqzjpxFPDgMQJlZ5DB7X7hq8wcVynUUrLyaGQs0ZYx50u0wVU/ioWljyeqwT3a77JAzpVoQ4iAQDjaHfNO3hq7LNmWLy7LEZw0v4sxLsTSXFkzu0hp8Gwgt4hBfTl8ACe0W+lFGnil+x69IvANDndMpmSNgjjVmKxjpNXvIljXMpgj6q2QNrbkWETOYWykh3eVB6po+h5m4iGL5jaulcRmAKJeK9setmRrePbvY9zJIzDCOn0qKWByTBue5VBIataZA9vXzKFNK8uzb0lvh2GT37sIvrKRIdaozdl3HzejQWb6symiaiTJyEf54Wp7ZdpMav4Ail/3r7RexvYZWByZvC3HKuyLq3Gsa3BzPOAQtxKbGpt6vufBKFcaD4tlO8EcZGpB1fVtQ0s2YiZU10u/HIPyxzBIWzENAGKVyoWY3g+HwQ2u9JxYw4oP+urwmUXEPImnqegHONovtwqR7nYCW5wd3GurZLNKwnLiB96HuXCqNDq8PGwBwzK/rXhX0Xiu/7lNEDDrtaw6ERZsVYtxmevl69q/89c8o90uXPyNohnHeE2SIBg9A2tTLqe3BzOqO5kdH06ApX31I0a7XqB5DsoJ+bhIBw3i4bU3eSeL8ssj/3vr+ORUyiO7OYgeOvLSSNNKIbxQQEjnki0mPP2YecoWZPltTm9LYMRi+kjsc54SLsdlhsZS1NyiPuba1Sd0vQ+OZ1krGpwzujKrAWsrQCwFv3sxfflZhOAKhU2hVQgSZRb8DBAcKyC4XqdXSpGRN9kqTblzrwHBe7eLywsH04Xr1/assNDfqmeRYIj9MZFytkiAVbAnKD7KgtxgHuowZRVLFDpMpwREf9cazJHCQBzmjFRgrODpNnzWhepR8Z4435Ht25aM+zDPXUmsNCU1yOAptBDIymCrhDm2XOKZoKDq3+q1D61gdyUnpragPPSnVmFbQRiPLKp6CPVsVNvEUgLeQBsS39HqeIvBknAkb0UVt9G6Wb X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(36860700004)(82310400017)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2024 12:44:15.8177 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6e449c1-ee69-4196-b579-08dc72813bcf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7646 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran It is not appropriate for the mlx5e_num_channels_changed function to be called solely for updating the TX queues, even if the channels number has not been changed. Move the code responsible for updating the TC and TX queues from mlx5e_num_channels_changed and produce a new function called mlx5e_update_tc_and_tx_queues. This new function should only be called when the channels number remains unchanged. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + .../ethernet/mellanox/mlx5/core/en_ethtool.c | 2 +- .../net/ethernet/mellanox/mlx5/core/en_main.c | 95 +++++++++---------- 3 files changed, 47 insertions(+), 51 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index f8bd9dbf59cd..e85fb71bf0b4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -1102,6 +1102,7 @@ int mlx5e_safe_switch_params(struct mlx5e_priv *priv, void *context, bool reset); int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); +int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context); void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 1eb3a712930b..3320f12ba2db 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -2292,7 +2292,7 @@ static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable) */ err = mlx5e_safe_switch_params(priv, &new_params, - mlx5e_num_channels_changed_ctx, NULL, true); + mlx5e_update_tc_and_tx_queues_ctx, NULL, true); if (!err) priv->tx_ptp_opened = true; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index ffe8919494d5..0a3d1999ede5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -3002,7 +3002,28 @@ int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv) return err; } -static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv) +static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv, + struct mlx5e_params *params) +{ + struct mlx5_core_dev *mdev = priv->mdev; + int num_comp_vectors, ix, irq; + + num_comp_vectors = mlx5_comp_vectors_max(mdev); + + for (ix = 0; ix < params->num_channels; ix++) { + cpumask_clear(priv->scratchpad.cpumask); + + for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) { + int cpu = mlx5_comp_vector_get_cpu(mdev, irq); + + cpumask_set_cpu(cpu, priv->scratchpad.cpumask); + } + + netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix); + } +} + +static int mlx5e_update_tc_and_tx_queues(struct mlx5e_priv *priv) { struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq; struct net_device *netdev = priv->netdev; @@ -3026,22 +3047,10 @@ static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv) err = mlx5e_update_tx_netdev_queues(priv); if (err) goto err_tcs; - err = netif_set_real_num_rx_queues(netdev, nch); - if (err) { - netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err); - goto err_txqs; - } + mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params); return 0; -err_txqs: - /* netif_set_real_num_rx_queues could fail only when nch increased. Only - * one of nch and ntc is changed in this function. That means, the call - * to netif_set_real_num_tx_queues below should not fail, because it - * decreases the number of TX queues. - */ - WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs)); - err_tcs: WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc, old_tc_to_txq)); @@ -3049,42 +3058,32 @@ static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv) return err; } -static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues); - -static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv, - struct mlx5e_params *params) -{ - int ix; - - for (ix = 0; ix < params->num_channels; ix++) { - int num_comp_vectors, irq, vec_ix; - struct mlx5_core_dev *mdev; - - mdev = mlx5_sd_ch_ix_get_dev(priv->mdev, ix); - num_comp_vectors = mlx5_comp_vectors_max(mdev); - cpumask_clear(priv->scratchpad.cpumask); - vec_ix = mlx5_sd_ch_ix_get_vec_ix(mdev, ix); - - for (irq = vec_ix; irq < num_comp_vectors; irq += params->num_channels) { - int cpu = mlx5_comp_vector_get_cpu(mdev, irq); - - cpumask_set_cpu(cpu, priv->scratchpad.cpumask); - } - - netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix); - } -} +MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_tc_and_tx_queues); static int mlx5e_num_channels_changed(struct mlx5e_priv *priv) { u16 count = priv->channels.params.num_channels; + struct net_device *netdev = priv->netdev; + int old_num_rxqs; int err; - err = mlx5e_update_netdev_queues(priv); - if (err) + old_num_rxqs = netdev->real_num_rx_queues; + err = netif_set_real_num_rx_queues(netdev, count); + if (err) { + netdev_warn(netdev, "%s: netif_set_real_num_rx_queues failed, %d\n", + __func__, err); return err; - - mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params); + } + err = mlx5e_update_tc_and_tx_queues(priv); + if (err) { + /* mlx5e_update_tc_and_tx_queues can fail if channels or TCs number increases. + * Since channel number changed, it increased. That means, the call to + * netif_set_real_num_rx_queues below should not fail, because it + * decreases the number of RX queues. + */ + WARN_ON_ONCE(netif_set_real_num_rx_queues(netdev, old_num_rxqs)); + return err; + } /* This function may be called on attach, before priv->rx_res is created. */ if (priv->rx_res) { @@ -3617,7 +3616,7 @@ static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv, mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1); err = mlx5e_safe_switch_params(priv, &new_params, - mlx5e_num_channels_changed_ctx, NULL, true); + mlx5e_update_tc_and_tx_queues_ctx, NULL, true); if (!err && priv->mqprio_rl) { mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); @@ -3718,10 +3717,8 @@ static struct mlx5e_mqprio_rl *mlx5e_mqprio_rl_create(struct mlx5_core_dev *mdev static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv, struct tc_mqprio_qopt_offload *mqprio) { - mlx5e_fp_preactivate preactivate; struct mlx5e_params new_params; struct mlx5e_mqprio_rl *rl; - bool nch_changed; int err; err = mlx5e_mqprio_channel_validate(priv, mqprio); @@ -3735,10 +3732,8 @@ static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv, new_params = priv->channels.params; mlx5e_params_mqprio_channel_set(&new_params, mqprio, rl); - nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1; - preactivate = nch_changed ? mlx5e_num_channels_changed_ctx : - mlx5e_update_netdev_queues_ctx; - err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true); + err = mlx5e_safe_switch_params(priv, &new_params, + mlx5e_update_tc_and_tx_queues_ctx, NULL, true); if (err) { if (rl) { mlx5e_mqprio_rl_cleanup(rl); From patchwork Sun May 12 12:43:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13662726 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2086.outbound.protection.outlook.com [40.107.237.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14797210E4 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Parav Pandit , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 3/3] net/mlx5: Remove unused msix related exported APIs Date: Sun, 12 May 2024 15:43:05 +0300 Message-ID: <20240512124306.740898-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240512124306.740898-1-tariqt@nvidia.com> References: <20240512124306.740898-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B3:EE_|MN2PR12MB4440:EE_ X-MS-Office365-Filtering-Correlation-Id: ed2ff29f-4bf0-4ac4-c4a7-08dc72813cda X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|376005|82310400017|1800799015; X-Microsoft-Antispam-Message-Info: CPc6r+o8iAuzfQRpkgDheQmKcmJsjS+fz2ooHXlx5EWAwmuE3965ZvwDHAwYwmrjtC28i98o22K3FM17pXCOwyOYvr2e3c7rpz/fAhyLzgUauZgZGm4/DXqU3+FixO1SUE7Gpq/qdVqgapcqZuL4ru6D4pru4Xdc3Biju22GXPym6vmHEP7z/sV5QkvbEHMiwdUuW+2H9t95JeZt749UnPfBB8ZBlydMno4k9XnnDkfKZcbStHQkJ4Z7OSXtc1ZFr4s5Oow7ZfPK6/V1fyTk173Xc6RmklLLfoy1a4prdEVwzHa0m5NbL0pB5BBGVEA1G6nQ1sgUa7faAtg99tgl8JoUX0WH24mvL3sQH7csPC2aMRtFsO/wiEcLJrkYpIeLIuoX6nqTRqCrV5FJmx89incVsJEGRoZJ6mQeXZFDka7oSghWnBvjLif2zKA7P+X2WpRKRnMGN/051IKQzL/8pC+cmbNiIqJ3Uvh7WsmAphqfwdXgXwC0opwNlvT0xyArUGAh6A34VNgRAdiHs4PEluI6+HW/c0Zdq9sVeOO0jNkPyIQ21blXCXjbsB78F8BshDHxkxD4hE2udONClfFp+O9975yAPqO14CNWhL0Gn8t3L6+Q36AoPy1/AY0NuitWwTaDrTVsr3QRuAQ9E9oWFfdR89nDvhd3NBuDuED0U9qcAeuwR/YLoW/T25wjmRTnRbLmhJyWvrD1rjSawKhlKSNnXE8BUQnDBXH/86uWi3zDOMEYA+DluT43RIznfL10CzZe/iw9npavbTFk2qV7hImH2Hgb7L5yNNh+ca0DjGJrTcj7xPLWItXZ/5+hwwxLNAfp7SAhhpHgEc5y5eNX0bWX0T4Q7iZVrrAvr1yfrdDZqzxC+lkhk9HCS78nYmYK1ITeRXlNhvr27fw+hggzxSZXba1KAxfZe9iNaMCq3OHaViE0UuNw/LgxoVTATFprscdKjImwze0LwHhpODHwQ+GCVuzuwtlC/el9yJQC6PK52IhosUDeme7E/sfFcNYQAECupo6zWvaIhYpHd/9ElpbDsdMcXOohinX7v9XU89QnSEHO/oJt/9/BJ4Dh67yTWqPTLHnlwRNauJMS9kuLrMZHwsf8kSzVq9vfHGmx110Mp6zTwq7+qGbzor0/johc4AW1nJtM5pT2gDH6q6ZxnqwAqAfZ9dQ5fyCRd6RupdAaX1tjJEXbcK4BJyTA8zqR67ZuhWggYEPi3pNfGIHRT3BZU0VVJUMTc+KqTsaouD5N7aces8NcPna80qvocEMxIGS84iv39e/3WgNWnXRnXhanEO7PN7TpeOhW8dIVQpgHnaS4+jYTglN0JjDvDDUVWm10QHDCky0ueyW/JuBXdfxMHYoq9Hsnp6YN31P9334PAsOW006GcSEMy6PQq6bA X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(376005)(82310400017)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2024 12:44:17.5523 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed2ff29f-4bf0-4ac4-c4a7-08dc72813cda X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4440 X-Patchwork-Delegate: kuba@kernel.org From: Parav Pandit MSIX irq allocation and free APIs are no longer in use. Hence, remove the dead code. Signed-off-by: Parav Pandit Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman Reviewed-by: Kalesh AP --- .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 52 ------------------- include/linux/mlx5/driver.h | 7 --- 2 files changed, 59 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c index 6bac8ad70ba6..fb8787e30d3f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -507,58 +507,6 @@ struct mlx5_irq *mlx5_irq_request(struct mlx5_core_dev *dev, u16 vecidx, return irq; } -/** - * mlx5_msix_alloc - allocate msix interrupt - * @dev: mlx5 device from which to request - * @handler: interrupt handler - * @affdesc: affinity descriptor - * @name: interrupt name - * - * Returns: struct msi_map with result encoded. - * Note: the caller must make sure to release the irq by calling - * mlx5_msix_free() if shutdown was initiated. - */ -struct msi_map mlx5_msix_alloc(struct mlx5_core_dev *dev, - irqreturn_t (*handler)(int, void *), - const struct irq_affinity_desc *affdesc, - const char *name) -{ - struct msi_map map; - int err; - - if (!dev->pdev) { - map.virq = 0; - map.index = -EINVAL; - return map; - } - - map = pci_msix_alloc_irq_at(dev->pdev, MSI_ANY_INDEX, affdesc); - if (!map.virq) - return map; - - err = request_irq(map.virq, handler, 0, name, NULL); - if (err) { - mlx5_core_warn(dev, "err %d\n", err); - pci_msix_free_irq(dev->pdev, map); - map.virq = 0; - map.index = -ENOMEM; - } - return map; -} -EXPORT_SYMBOL(mlx5_msix_alloc); - -/** - * mlx5_msix_free - free a previously allocated msix interrupt - * @dev: mlx5 device associated with interrupt - * @map: map previously returned by mlx5_msix_alloc() - */ -void mlx5_msix_free(struct mlx5_core_dev *dev, struct msi_map map) -{ - free_irq(map.virq, NULL); - pci_msix_free_irq(dev->pdev, map); -} -EXPORT_SYMBOL(mlx5_msix_free); - /** * mlx5_irq_release_vector - release one IRQ back to the system. * @irq: the irq to release. diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 8218588688b5..0aa15cac0308 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1374,11 +1374,4 @@ static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev) enum { MLX5_OCTWORD = 16, }; - -struct msi_map mlx5_msix_alloc(struct mlx5_core_dev *dev, - irqreturn_t (*handler)(int, void *), - const struct irq_affinity_desc *affdesc, - const char *name); -void mlx5_msix_free(struct mlx5_core_dev *dev, struct msi_map map); - #endif /* MLX5_DRIVER_H */