From patchwork Mon May 13 07:46:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 641B4C25B74 for ; Mon, 13 May 2024 07:49:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPC-0002mP-4g; Mon, 13 May 2024 03:47:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QP6-0002js-Ut for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:25 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QP4-0001JS-0l for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:24 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-420104e5336so8096025e9.1 for ; Mon, 13 May 2024 00:47:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586440; x=1716191240; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eUEXDe4PCMsFe4DA4mYg1FIK58I7QokH1/RCklBXYEQ=; b=pLH1zIaDc9P8rE9vv0YKAjGi5YiH15l2aAvqnOSu/Ltm5F6r7kRka6idvNPuPb3mSy ebO4CjKSVgUJkNPpKOpCyLFHWAwy8rouSZEvBC2/j1zlVSMGjE/Xbi3eOsF55mKAXPAd Gx1VS6FGMmHg3+ecWyq9sX2vKO8lUGUVc/gjm6S6Mvn6VVp/hq5Mr7+Usmb/OzsX8Hz0 Uy4Y8Hv2dOGXXRD1u/I0Z3BQ34z8ynGmr5NvMjNn2z3CKOaz/SvpzZXuEamyhE6tabNE FUytLZmj6DaIoz1a+sLpDRaRFcg5n8uoeuV7rl60wJwHPjGZBXRITmNwLK5JHfLqS2Xp P5rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586440; x=1716191240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eUEXDe4PCMsFe4DA4mYg1FIK58I7QokH1/RCklBXYEQ=; b=SQ8BrwCvaVzsk48BC/v4wvMZM42Sehv3dIB71zyYsFFXqjxVMoxfVia/9OOrGoB2Cx 7YtcnDvSDk44o47uiv2R1aEdvtqC38CgyWTbY+BRgSmlKXUJ4AvssJEAFMVX0gIe1OE+ FzD4eORECobxYjYX4rIRvbKTGeH5RLEnU9B5tPFtw2RdWcxGOHqC1F6rwfBoZ2+IAgu0 suTcJPDMsb0M9rtK4wNrBHdW86/9Zsm5gYwdEBGGDnRWPd+C5WVGLcub2cntaEnkZ+kh j9Alnb5QabB+zdy/8A6rDGHAF1H4jC0arY6GVquiohIsVQKs/LwnSXWG4BEeOH4XY7en Bksg== X-Gm-Message-State: AOJu0YzowRNdkh43BV/bzeR25XATJjUkDLn5eMQYavplp8bu2fzs5tUN TA5NmcKpiFrBAH6gmPZtVXzLkq5ae9bCjA2598nPAg2fFxjVb2R+laTDyK+SDdQBf7UcemN8EoW MqmI= X-Google-Smtp-Source: AGHT+IEZLzEwwa9i3/2iW6KJtd9IJTESLn48CFGTWL22gABI2u1nauODrPeuy5s9SM91ITrdtUq9kg== X-Received: by 2002:a05:600c:3c83:b0:41b:8041:53c2 with SMTP id 5b1f17b1804b1-41feac51e04mr88420345e9.15.1715586439836; Mon, 13 May 2024 00:47:19 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 01/45] target/hppa: Move cpu_get_tb_cpu_state out of line Date: Mon, 13 May 2024 09:46:33 +0200 Message-Id: <20240513074717.130949-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 43 ++----------------------------------------- target/hppa/cpu.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 41 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fb2e4c4a98..61f1353133 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -314,47 +314,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 -static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - uint32_t flags = env->psw_n * PSW_N; - - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ -#ifdef CONFIG_USER_ONLY - *pc = env->iaoq_f & -4; - *cs_base = env->iaoq_b & -4; - flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#else - /* ??? E, T, H, L, B bits need to be here, when implemented. */ - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); - flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); - *cs_base = env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a page. - Failure is indicated by a zero difference. */ - if (env->iasq_f == env->iasq_b) { - target_long diff = env->iaoq_b - env->iaoq_f; - if (diff == (int32_t)diff) { - *cs_base |= (uint32_t)diff; - } - } - if ((env->sr[4] == env->sr[5]) - & (env->sr[4] == env->sr[6]) - & (env->sr[4] == env->sr[7])) { - flags |= TB_FLAG_SR_SAME; - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags); target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 393a81988d..582036b31e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -43,6 +43,48 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) return cpu->env.iaoq_f; } +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags = env->psw_n * PSW_N; + + /* TB lookup assumes that PC contains the complete virtual address. + If we leave space+offset separate, we'll get ITLB misses to an + incomplete virtual address. This also means that we must separate + out current cpu privilege from the low bits of IAOQ_F. */ +#ifdef CONFIG_USER_ONLY + *pc = env->iaoq_f & -4; + *cs_base = env->iaoq_b & -4; + flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#else + /* ??? E, T, H, L, B bits need to be here, when implemented. */ + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); + *cs_base = env->iasq_f; + + /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero + low 32-bits of CS_BASE. This will succeed for all direct branches, + which is the primary case we care about -- using goto_tb within a page. + Failure is indicated by a zero difference. */ + if (env->iasq_f == env->iasq_b) { + target_long diff = env->iaoq_b - env->iaoq_f; + if (diff == (int32_t)diff) { + *cs_base |= (uint32_t)diff; + } + } + if ((env->sr[4] == env->sr[5]) + & (env->sr[4] == env->sr[6]) + & (env->sr[4] == env->sr[7])) { + flags |= TB_FLAG_SR_SAME; + } +#endif + + *pflags = flags; +} + static void hppa_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { From patchwork Mon May 13 07:46:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E94EEC25B10 for ; Mon, 13 May 2024 07:54:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPU-0002v3-4k; Mon, 13 May 2024 03:47:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPE-0002nE-AL for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:33 -0400 Received: from mail-lj1-x231.google.com ([2a00:1450:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QP4-0001Jm-J7 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:32 -0400 Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2e43c481b53so50102431fa.2 for ; Mon, 13 May 2024 00:47:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586441; x=1716191241; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+9boudcCOGEVYkNrscgu8HWtkLEddppv4wDb4lWwH3M=; b=THxqmqN/EmdmzAsZggy5Yy5EsG3gfyPi4QfcDX+iOWx8fX/+SwXCaU7WlyYh3CsQ15 B8TCM+Phly6xRjuOUIhWMebqEKdA4UdJ0Syf+ZEEEUCY7KQgWLcfuDm57hDR84kDvtxj f7sXmuQ60gyeiTCiPd/nAV8PvW5/zbNB+5tZi2vTnxc/Ms286txvQ2z6xsyAMuteJ4kb xP4g2UOLmrm3TowuA/LYQXLsV6M9p3Nr0cEvDHjNSFLnCX3Foty8FhMonB4Hs4ma5FTW ItAVM+5qZgsr1ZelRKttrkJweNuk5Zl5TPEKKsmAfBR3gfvVDpEwmhs9TyuWTFupEgjF yKCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586441; x=1716191241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+9boudcCOGEVYkNrscgu8HWtkLEddppv4wDb4lWwH3M=; b=wZb2TQSloOOIU/2E22cMbQchtVxdUna7jTW1e0krhLOLZO+toydC0XFRIRNcVE99JY QmHXDoxwV3eo71EkCoj1EUZ+i2zudZmkChmUdfMjQ26JkcovEtRrfIq8XoPWsx2v1ML5 M7hm4klVz5NOdBdisABdnFg7+WP/Mo9rKfL2xTtEhAXUfvLsVHwYxp4MMxzJTCee5/6a e3l8tf/3jYvFzMG6lb8nCssL+8oja4dZs5ymXmmhYMAhy+LxippG6iFrS4knSijLezAB hQGzDlMIdRn+C9Incarp7M/cswnB8wazeHI1YRIoC8Z7y3zN7zhfYs4otamKWnTqfs7Y 2Fag== X-Gm-Message-State: AOJu0Yz4uLX3O/n30j2pFBnj60VJosbcbGlILgCvkt1aT8aa8P+ppvW7 vqufOPeD/uDrAFWhl15kEfecqQj+9qliEpD38alb4wlYCwo1K877J3u5+sPzDEY0UTGsydJDef2 UKyY= X-Google-Smtp-Source: AGHT+IH+Vvm/I2rgO34Jclmma7qPq440dWyEREmjFlB+26uERjUq7JtIyp2GKkk0qzVtJ9Fd0xvdCg== X-Received: by 2002:a2e:8748:0:b0:2d8:a921:dfc1 with SMTP id 38308e7fff4ca-2e51fd4b3c2mr56017951fa.20.1715586440666; Mon, 13 May 2024 00:47:20 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 02/45] target/hppa: Use hppa_form_gva_psw in hppa_cpu_get_pc Date: Mon, 13 May 2024 09:46:34 +0200 Message-Id: <20240513074717.130949-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This function is for log_pc(), which needs to produce a similar result to cpu_get_tb_cpu_state(). Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 582036b31e..be8c558014 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -38,9 +38,10 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) static vaddr hppa_cpu_get_pc(CPUState *cs) { - HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = cpu_env(cs); - return cpu->env.iaoq_f; + return hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); } void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, @@ -61,8 +62,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); + *pc = hppa_cpu_get_pc(env_cpu(env)); *cs_base = env->iasq_f; /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero From patchwork Mon May 13 07:46:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4379FC25B10 for ; Mon, 13 May 2024 07:47:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPC-0002mi-It; Mon, 13 May 2024 03:47:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QP8-0002k5-8N for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:27 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QP4-0001Js-UM for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:25 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-34da35cd01cso3731035f8f.2 for ; Mon, 13 May 2024 00:47:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586441; x=1716191241; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DRvEbVFABG0rQ6mtoE7EPY1IsVsNamdAxtlX4BxsiVU=; b=ta4I31Tp79zrIyVXar2dtj8scpCYF3YIL5QHZef8T9S8EoC9L4bAQa5DW5Ykoy32c5 G7MngUMSdpjBxIdtHn2FR5JAwUpzFRk4YvDp/h2pLXkqfvR2lqdUrYyHhhmBq2KA5HfV IoUTwh9hzammJg4mrSfL56OY5FqqEpx/iWstJeCQvwO+bUzQbnCzzvAEoZPa1ve5ALN2 8I38yd1b8pQPWGN064AdbxQla6rPI1JVoxcWtXT+cbR3PPLF8HYaM/0E2ZxPd7wQkeyk VZKdZEB79SVtshwNpvIXptaS3EuaCidyeHDWhROOyd6Uo5Osfg5U9EzHGV4hIR2G3QL3 4dMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586441; x=1716191241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DRvEbVFABG0rQ6mtoE7EPY1IsVsNamdAxtlX4BxsiVU=; b=JL/yp9LX41jqK4EN8iuOBtiK3jGDAVSkURn1w0C+pZpP7DOwTQVQm7iFAyl1xyqnuw QsrThJbCqNJFPVUOiTEX6v+mJxFqQC34qdmhQeGYHt2FzAtVTrc+u1Lq+noQxeZz17Cr BuByqb1PswktebKp4pktr0vMjalNzMQBmS9rdLzljCBhWdiHhRoD1RPKFZMeGJLiME/d QSa9qMFOm/G7lokpSw2NPxdz2USt/C6torq+MeJxGOEIn+2LUiZk3g04cfGC8URt0tu1 bngLHuCdE9IqKpyJP8b7+J70FO/BoVfz4v/Aa+QjwDM+JiRrIMfjYkqvwew7buVKB0iz PRRQ== X-Gm-Message-State: AOJu0YzlSAtquiUfAGkDi+AGFJYaskqqHCmog2AveQt5Nf41AYYTsaH0 qN8y3ir7aBFyh4O9HHpPuYXYwd0crI7wLxRJ1qMQCvPerxmlylLyeMzEPypMXncJiIs054qoH4P 7Aiw= X-Google-Smtp-Source: AGHT+IFT6dh/6W19yMvg3Xn0bdjsyExHe/qmts3FM+WfAe4DB40oTXA2uNbmupm+bBfrK2EblaQ+cw== X-Received: by 2002:a5d:5262:0:b0:34d:b634:9033 with SMTP id ffacd0b85a97d-3504a9691acmr7570268f8f.51.1715586441498; Mon, 13 May 2024 00:47:21 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 03/45] target/hppa: Move constant destination check into use_goto_tb Date: Mon, 13 May 2024 09:46:35 +0200 Message-Id: <20240513074717.130949-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Share this check between gen_goto_tb and hppa_tr_translate_insn. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6d45611888..398803981c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -662,9 +662,10 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif -static bool use_goto_tb(DisasContext *ctx, uint64_t dest) +static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) { - return translator_use_goto_tb(&ctx->base, dest); + return (bofs != -1 && nofs != -1 && + translator_use_goto_tb(&ctx->base, bofs)); } /* If the next insn is to be nullified, and it's on the same page, @@ -678,16 +679,16 @@ static bool use_nullify_skip(DisasContext *ctx) } static void gen_goto_tb(DisasContext *ctx, int which, - uint64_t f, uint64_t b) + uint64_t b, uint64_t n) { - if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { + if (use_goto_tb(ctx, b, n)) { tcg_gen_goto_tb(which); - copy_iaoq_entry(ctx, cpu_iaoq_f, f, NULL); - copy_iaoq_entry(ctx, cpu_iaoq_b, b, NULL); + copy_iaoq_entry(ctx, cpu_iaoq_f, b, NULL); + copy_iaoq_entry(ctx, cpu_iaoq_b, n, NULL); tcg_gen_exit_tb(ctx->base.tb, which); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, f, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, b, ctx->iaoq_n_var); + copy_iaoq_entry(ctx, cpu_iaoq_f, b, cpu_iaoq_b); + copy_iaoq_entry(ctx, cpu_iaoq_b, n, ctx->iaoq_n_var); tcg_gen_lookup_and_goto_ptr(); } } @@ -4744,8 +4745,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { - if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 - && use_goto_tb(ctx, ctx->iaoq_b) + if (use_goto_tb(ctx, ctx->iaoq_b, ctx->iaoq_n) && (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); From patchwork Mon May 13 07:46:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A0D7C25B10 for ; Mon, 13 May 2024 07:54:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPK-0002rE-RW; Mon, 13 May 2024 03:47:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QP8-0002kQ-Dp for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:27 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QP6-0001K7-8y for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:26 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-41fe54cb0e3so24585415e9.2 for ; Mon, 13 May 2024 00:47:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586442; x=1716191242; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EF71oCEKPx9KffJ0nhQbR+6fCow0EB4c3hkf8VxLkbs=; b=MYpWRI/2Xf8UQ8dnUCdBm2fjM/mLe4wUep1V/aFN0zp4gUTbzwkAarDNM+FwO+muYJ IWvPZeRHWF/MnbtwHIRuQLb4C7MamnWBF3lij6I8PB+jr50E9T2GyUuyvnmSbxn5tYUR N3ZN6DDnEx2AwxLi1AEQpRkw03BfKXUgLjpIU4WMgikyN/HpPfNww/EtWaRzaUpQEvpR DZ35dFWkpErLR3CLTleC2jM6nLVVdHLf2q3lL4PtYYwO2HBffY0KsAVphWKzK6HcWUxh viQnhOqwkylmMRfRtoztUuhHzmZnIIENj75fULmKi2xkgdr32KHBHiVdSPhUjiPfjYHT +17g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586442; x=1716191242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EF71oCEKPx9KffJ0nhQbR+6fCow0EB4c3hkf8VxLkbs=; b=Nq+JNAb2ePynh+BO3Zg9kEQ2FK7i8Mx7Vx5rNKemMLnAzvctqiLcmv1TvzBh1GeBr0 2h6m9pC+fhTXeQRaK0NMsnrUeXay+X26JCgebMheE7Qj0BloAFAbVUX5Huzz4AuHFf+a 840DxGFAFFJUM2hUChpZf3ma2fzJfvl3l/WVxnovuLkky4yotPORAdu6Dfw4qVQPSMGI j1fFLW83QiKIPqMa23IUJozGM1pOMSruNHLdQvjGHaYBcGWLDZmFPG7c0GWvtoM6CYnG OEbyrs4YDfh39LV4n28V4Rxa7aG2UWB3ija9h7qObiE4Mv2PV5M6UVsxYxoNh0kNmo2K 9ajQ== X-Gm-Message-State: AOJu0YyLsx2fr+VW/0nJJAgVacJthxsQQLx7Mx4qYihGBJbUiTzyr9kj 7CGtRU2N41kLIzd+kQw3NToaDfhngzWnIxu80fzLH3bAp++h14eZQ7L74IztQCvBGjNnFtWL7wk XNGs= X-Google-Smtp-Source: AGHT+IH0MP3m7Lw4XERojhlCysB49zTKxNdd4hpNuj2kz3lKHqAdjeLRkhzZhMCXeJ5D67E+jJpaZA== X-Received: by 2002:a05:600c:1f93:b0:41e:dc7f:e2c with SMTP id 5b1f17b1804b1-41feac59cddmr61728755e9.30.1715586442305; Mon, 13 May 2024 00:47:22 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 04/45] target/hppa: Pass displacement to do_dbranch Date: Mon, 13 May 2024 09:46:36 +0200 Message-Id: <20240513074717.130949-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Pass a displacement instead of an absolute value. In trans_be, remove the user-only do_dbranch case. The branch we are attempting to optimize is to the zero page, which is perforce on a different page than the code currently executing, which means that we will *not* use a goto_tb. Use a plain indirect branch instead, which is what we got out of the attempted direct branch anyway. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 33 +++++++++------------------------ 1 file changed, 9 insertions(+), 24 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 398803981c..4c42b518c5 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1766,9 +1766,11 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static bool do_dbranch(DisasContext *ctx, uint64_t dest, +static bool do_dbranch(DisasContext *ctx, int64_t disp, unsigned link, bool is_n) { + uint64_t dest = iaoq_dest(ctx, disp); + if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { if (link != 0) { copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); @@ -1815,10 +1817,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, /* Handle TRUE and NEVER as direct branches. */ if (c == TCG_COND_ALWAYS) { - return do_dbranch(ctx, dest, 0, is_n && disp >= 0); - } - if (c == TCG_COND_NEVER) { - return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0); + return do_dbranch(ctx, disp, 0, is_n && disp >= 0); } taken = gen_new_label(); @@ -3914,22 +3913,6 @@ static bool trans_be(DisasContext *ctx, arg_be *a) { TCGv_i64 tmp; -#ifdef CONFIG_USER_ONLY - /* ??? It seems like there should be a good way of using - "be disp(sr2, r0)", the canonical gateway entry mechanism - to our advantage. But that appears to be inconvenient to - manage along side branch delay slots. Therefore we handle - entry into the gateway page via absolute address. */ - /* Since we don't implement spaces, just branch. Do notice the special - case of "be disp(*,r0)" using a direct branch to disp, so that we can - goto_tb to the TB containing the syscall. */ - if (a->b == 0) { - return do_dbranch(ctx, a->disp, a->l, a->n); - } -#else - nullify_over(ctx); -#endif - tmp = tcg_temp_new_i64(); tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); tmp = do_ibranch_priv(ctx, tmp); @@ -3939,6 +3922,8 @@ static bool trans_be(DisasContext *ctx, arg_be *a) #else TCGv_i64 new_spc = tcg_temp_new_i64(); + nullify_over(ctx); + load_spr(ctx, new_spc, a->sp); if (a->l) { copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); @@ -3968,7 +3953,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) static bool trans_bl(DisasContext *ctx, arg_bl *a) { - return do_dbranch(ctx, iaoq_dest(ctx, a->disp), a->l, a->n); + return do_dbranch(ctx, a->disp, a->l, a->n); } static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) @@ -4022,7 +4007,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) save_gpr(ctx, a->l, tmp); } - return do_dbranch(ctx, dest, 0, a->n); + return do_dbranch(ctx, dest - iaoq_dest(ctx, 0), 0, a->n); } static bool trans_blr(DisasContext *ctx, arg_blr *a) @@ -4035,7 +4020,7 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) return do_ibranch(ctx, tmp, a->l, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ - return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n); + return do_dbranch(ctx, 0, a->l, a->n); } } From patchwork Mon May 13 07:46:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8B49C25B10 for ; Mon, 13 May 2024 07:48:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QQ0-0003Sq-CZ; Mon, 13 May 2024 03:48:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QP8-0002kO-E9 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:27 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QP6-0001KB-Eh for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:26 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-420160f8f52so3882665e9.0 for ; Mon, 13 May 2024 00:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586443; x=1716191243; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CAJ+Dwjcdmii7teUjtvDvc6ZzqaDM6m0amLzUomnego=; b=v3lzTkxuSxj7vj1xcB9qRN/RLzA4eDXgY/MbIHo3Rzg8xd3Q1XhpKJYi8tEWQFUdof e0rAdrsG/i5Df/OdTOy3cvyQWsECXCVgL8sEnYkj992Zc0JzH+hpZdnGnVFCkQNK9dKt oRXQFmFt05upuafNPasdDqhAF4dkhiokO+bptDB7dI5X6xXdSGLjP3175triHPLDLgMO WYvPufoVHNcCRiXwakQE/7DOYU6gTIirh+VG6BcLQyyi/NStu3wGLPvnkUQ+WBHguSqm GJ/BUADrcwHOXwx1yCTwPWpyzMlQ4Ms2+xBrWah2BgSNoaKY03YUm3dfoF5X/T+vUqlc svuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586443; x=1716191243; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CAJ+Dwjcdmii7teUjtvDvc6ZzqaDM6m0amLzUomnego=; b=mSVw0VrIoSUWCBfOms6rSOho5Y4Loskmcfo+GJZNYDVzeuvlD3DQt7I0FyWyXXKY1F Ha4UHadQFFUCleBm9+GYpxUDX7qd6K0tD8y0cSLe0RsutSr9bN0wf3ghVUMFnvCcN8hr ibtJbB6F2OdWKDcfU5TRzl7KIKricyAXIlM9iI9YrjbhAYy7ujzrO8yVVj9epskDPdKL neuSlDH0DE2iIm9RkP/c5nrUPKmlpWwRug80ff5dg9JfpDkLNrpdewzF/OSYiFknFGmw DkW/E3/Ufm5nGUL/ya4Ck2WEAyz+wWaUhEu2HvgVqBHWUd1J04GB1fzUFNI/KG88oJVt cv8w== X-Gm-Message-State: AOJu0YwmLlPijLl75fqwFk9Vgw8lMfImw/rU57ho6ooNMTx8LuCMSS8I cThbdsBU8usP27vTgF4qix36c01KGxUR+mr8rT4TPAgpRh6a4KDVKVuYMQC7SUdMmy6fvGvdIBX oaq0= X-Google-Smtp-Source: AGHT+IHeXAtTzo5lqc0WugFUw/YdgYFXrwUftOL0hjE1SeD/MAfMz8dAIynCQkw0gRtGoAL3PNjPBw== X-Received: by 2002:a05:600c:4ed0:b0:41c:14a4:7b05 with SMTP id 5b1f17b1804b1-41fea93af8cmr57956215e9.8.1715586443027; Mon, 13 May 2024 00:47:23 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 05/45] target/hppa: Allow prior nullification in do_ibranch Date: Mon, 13 May 2024 09:46:37 +0200 Message-Id: <20240513074717.130949-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Simplify the function by not attempting a conditional move on the branch destination -- just use nullify_over normally. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 73 +++++++++++------------------------------ 1 file changed, 20 insertions(+), 53 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4c42b518c5..140dfb747a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1871,17 +1871,15 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, unsigned link, bool is_n) { - TCGv_i64 a0, a1, next, tmp; - TCGCond c; + TCGv_i64 next; - assert(ctx->null_lab == NULL); + if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { + next = tcg_temp_new_i64(); + tcg_gen_mov_i64(next, dest); - if (ctx->null_cond.c == TCG_COND_NEVER) { if (link != 0) { copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } - next = tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); if (is_n) { if (use_nullify_skip(ctx)) { copy_iaoq_entry(ctx, cpu_iaoq_f, -1, next); @@ -1895,60 +1893,29 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, } ctx->iaoq_n = -1; ctx->iaoq_n_var = next; - } else if (is_n && use_nullify_skip(ctx)) { - /* The (conditional) branch, B, nullifies the next insn, N, - and we're allowed to skip execution N (no single-step or - tracepoint in effect). Since the goto_ptr that we must use - for the indirect branch consumes no special resources, we - can (conditionally) skip B and continue execution. */ - /* The use_nullify_skip test implies we have a known control path. */ - tcg_debug_assert(ctx->iaoq_b != -1); - tcg_debug_assert(ctx->iaoq_n != -1); + return true; + } - /* We do have to handle the non-local temporary, DEST, before - branching. Since IOAQ_F is not really live at this point, we - can simply store DEST optimistically. Similarly with IAOQ_B. */ + nullify_over(ctx); + + if (is_n && use_nullify_skip(ctx)) { copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest); next = tcg_temp_new_i64(); tcg_gen_addi_i64(next, dest, 4); copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); - - nullify_over(ctx); - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } - tcg_gen_lookup_and_goto_ptr(); - return nullify_end(ctx); + nullify_set(ctx, 0); } else { - c = ctx->null_cond.c; - a0 = ctx->null_cond.a0; - a1 = ctx->null_cond.a1; - - tmp = tcg_temp_new_i64(); - next = tcg_temp_new_i64(); - - copy_iaoq_entry(ctx, tmp, ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest); - ctx->iaoq_n = -1; - ctx->iaoq_n_var = next; - - if (link != 0) { - tcg_gen_movcond_i64(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); - } - - if (is_n) { - /* The branch nullifies the next insn, which means the state of N - after the branch is the inverse of the state of N that applied - to the branch. */ - tcg_gen_setcond_i64(tcg_invert_cond(c), cpu_psw_n, a0, a1); - cond_free(&ctx->null_cond); - ctx->null_cond = cond_make_n(); - ctx->psw_n_nonzero = true; - } else { - cond_free(&ctx->null_cond); - } + copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); + nullify_set(ctx, is_n); } - return true; + if (link != 0) { + copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); + } + + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp = DISAS_NORETURN; + return nullify_end(ctx); } /* Implement From patchwork Mon May 13 07:46:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BE06C25B10 for ; Mon, 13 May 2024 07:49:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPH-0002pY-QT; Mon, 13 May 2024 03:47:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QP9-0002lS-LD for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:27 -0400 Received: from mail-lj1-x22d.google.com ([2a00:1450:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QP7-0001KG-4i for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:27 -0400 Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2e1fa824504so53159741fa.0 for ; Mon, 13 May 2024 00:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586443; x=1716191243; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5zJVPddiwqndhAfsv4bxEk5QwYGlyRAHKsQYLRbwnmM=; b=OoCip7xlwrYZrjYYUre61Koe9afdh0/69uJcTg0Bfii5PwyjvY9fYjuuoWaPSqDGxR m4vd9X1ol1kXBZHasglYVEqJCoZgWB8VgsarQaJ4Pkn7jRXdq6y5rrsVzvrSfh4y6BcH Zu7VR+4q0mg2JGmKIqunk7OgiWcGk7gvgQxK1Zzk1AWkKNIoQPXQZqDhgSawv306c/G5 Ot3MKaVvYOdxyTbpAyFJL53Wwon26+16mcKhyMhOanG0NA3zONnXeLS4ZGulrhWWgwn7 sRPvbh+BzifB3gh2CJ1VR5BniPnSBYws9z3Ams5lbrovRbNmIIiT3PMPBSrawq1KxVol HuBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586443; x=1716191243; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5zJVPddiwqndhAfsv4bxEk5QwYGlyRAHKsQYLRbwnmM=; b=tGVRLh2CY74y4zi3OBua5CMHZ8+ruITtXwQhWccMuzKr7Dd6WHVpqaxfsxPsZxgdSn lLuJTWDqLxlE4gVKXB0O2u+Y4kXWXDWme74cnATyw+p0hiaYu+DCUjN6SJwhBW9/e6Si KwZAS+RhuXvuUhT8QJexJLqvDXxSOyhKtnPOr0M/7GX36bxqCMhlzfu2C2jRszLmkpE/ KdXGkImNb1xS4tebspR4dIqU/CgydJeywvTjDcicinyEq3135fP+zKYEQPkpYjafwncC MTO6OuNoDti7XyMYfA0klRUr0PFPn7/augwTOkZCbf98+VmfVuzcqYIzvY/1pekLd3I3 KexA== X-Gm-Message-State: AOJu0YxfG5gRPH/EJB+RkqL4I1yaocRNQGxlYAmRjrLgvjX12Nw/9/CB stOcUm3VARq3jSZySxKYGm3fADPlCMjqmpZHpmqsoOx6p6o0gxtRy0QizZ9rVgQCm+XE9P3jiDt 72dU= X-Google-Smtp-Source: AGHT+IGxg8xzNZEDiGmSiZyAEAu6vEBI7aixr2Q8ixm0s0IRbtqU1aKbM9cyB4KdJmlhFpuhzyuQdw== X-Received: by 2002:a05:651c:1a21:b0:2e3:3eaa:ac92 with SMTP id 38308e7fff4ca-2e5205e6e08mr68402721fa.53.1715586443604; Mon, 13 May 2024 00:47:23 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 06/45] target/hppa: Use CF_BP_PAGE instead of cpu_breakpoint_test Date: Mon, 13 May 2024 09:46:38 +0200 Message-Id: <20240513074717.130949-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The generic tcg driver will have already checked for breakpoints. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 140dfb747a..d272be0e6e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -674,8 +674,9 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) executing a TB that merely branches to the next TB. */ static bool use_nullify_skip(DisasContext *ctx) { - return (((ctx->iaoq_b ^ ctx->iaoq_f) & TARGET_PAGE_MASK) == 0 - && !cpu_breakpoint_test(ctx->cs, ctx->iaoq_b, BP_ANY)); + return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) + && ctx->iaoq_b != -1 + && is_same_page(&ctx->base, ctx->iaoq_b)); } static void gen_goto_tb(DisasContext *ctx, int which, From patchwork Mon May 13 07:46:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2EB3AC41513 for ; Mon, 13 May 2024 07:50:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPR-0002uJ-ES; Mon, 13 May 2024 03:47:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPC-0002mh-EJ for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:30 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QP8-0001KN-IE for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:30 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-41fd5dc0480so24482445e9.1 for ; Mon, 13 May 2024 00:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586444; x=1716191244; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8fqWIFmvD9JUaraiZpom6kTf9G8T11TFsgyyJnV2gt8=; b=fmmoYJm9c17ifW+IYsemz3k9nPAIz7prekbEKqrL6VJm7zhX2VovsgHPwZR2p9ShgJ VQ7BRG5u9rxpJZLijz8cQk2BBUq60sZhzc1e6a34u6h9n9PdEDQ9Vv8gSFJIux0MZsgt i8urBqJPgTyqyD9OrdSeoPvZ0nUs56RZVhX8BBb/LbaqfVrvTiwpT9875oHeqn7a4DvO V6CwRYGefT7/w2KKoAUQ6YBhLyaDsijsWWE+Qn9bIBu5aBw8+NsXlG9R+kP43LeHmqjX eTqELheyKtIpjteSkUrMZitiSE2GV9zMvKND63OYiH49h0xK6jp88rITfPYy8PFhNStm Ey6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586444; x=1716191244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8fqWIFmvD9JUaraiZpom6kTf9G8T11TFsgyyJnV2gt8=; b=bddkLczLTGjOpU2eNMUpoidai/Sigrnh2sMxrZAZIqqZdwofiGEhhA2ZndbDUM3Kjs BrAwYMd2pU7frI8SqGqGLJ4n8Caxh0pKDiRGhno2G+9inu+K+6W8yu++kVyU2L08iG2Y 7foPtLErGrHmAvDC7Ttcy1NMv6D0lq0pPOvcr5tWdSiupuDZPL42/bXrM9nAw6835u9r 9n/apNwR89eXXh07L3eZLsHUFSnqcachSKXu8W1yOV2ZEjGoFVmrXbVgl5BCCBTTtyG8 87TWGtYt4T/sj7b23ebP1YIn9+Decyb4aCsk1fQ9nuT7fC+CYaodzKt7/09x7x1kMrgd N8Qw== X-Gm-Message-State: AOJu0YyaGneC5RnSBA3tEPuTSLI0ZIwqWn2qevgzzT716jaIk5AU7G7e sdspvqEG+CXGt04LrUtgqCIjea5i0LC8TGVDw+e6O4o4Y2foTIgOYDcCvzU8QK92n3WKuKCYWR4 8FTg= X-Google-Smtp-Source: AGHT+IGw+MUXyr+5kp/dkxVFfsZSEt+sfP3tmbGlr/fpWnExQUCyZHXmRlz0EzGEezYajqGCXz9iZw== X-Received: by 2002:a05:600c:4513:b0:41f:df08:5ef7 with SMTP id 5b1f17b1804b1-41feac5a4a7mr66401265e9.28.1715586444197; Mon, 13 May 2024 00:47:24 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 07/45] target/hppa: Add install_iaq_entries Date: Mon, 13 May 2024 09:46:39 +0200 Message-Id: <20240513074717.130949-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of two separate cpu_iaoq_entry calls, use one call to update both IAQ_Front and IAQ_Back. Simplify with an argument combination that automatically handles a simple increment from Front to Back. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 64 +++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 31 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d272be0e6e..08d5e2a4bc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -617,6 +617,23 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, } } +static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, + uint64_t ni, TCGv_i64 nv) +{ + copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); + + /* Allow ni variable, with nv null, to indicate a trivial advance. */ + if (ni != -1 || nv) { + copy_iaoq_entry(ctx, cpu_iaoq_b, ni, nv); + } else if (bi != -1) { + copy_iaoq_entry(ctx, cpu_iaoq_b, bi + 4, NULL); + } else { + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, + gva_offset_mask(ctx->tb_flags)); + } +} + static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) { return ctx->iaoq_f + disp + 8; @@ -629,8 +646,7 @@ static void gen_excp_1(int exception) static void gen_excp(DisasContext *ctx, int exception) { - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp = DISAS_NORETURN; @@ -684,12 +700,10 @@ static void gen_goto_tb(DisasContext *ctx, int which, { if (use_goto_tb(ctx, b, n)) { tcg_gen_goto_tb(which); - copy_iaoq_entry(ctx, cpu_iaoq_f, b, NULL); - copy_iaoq_entry(ctx, cpu_iaoq_b, n, NULL); + install_iaq_entries(ctx, b, NULL, n, NULL); tcg_gen_exit_tb(ctx->base.tb, which); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, b, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, n, ctx->iaoq_n_var); + install_iaq_entries(ctx, b, cpu_iaoq_b, n, ctx->iaoq_n_var); tcg_gen_lookup_and_goto_ptr(); } } @@ -1883,9 +1897,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, } if (is_n) { if (use_nullify_skip(ctx)) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, next); - tcg_gen_addi_i64(next, next, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); + install_iaq_entries(ctx, -1, next, -1, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; @@ -1900,14 +1912,10 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, nullify_over(ctx); if (is_n && use_nullify_skip(ctx)) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest); - next = tcg_temp_new_i64(); - tcg_gen_addi_i64(next, dest, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); + install_iaq_entries(ctx, -1, dest, -1, NULL); nullify_set(ctx, 0); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); nullify_set(ctx, is_n); } if (link != 0) { @@ -1998,9 +2006,7 @@ static void do_page_zero(DisasContext *ctx) tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); tmp = tcg_temp_new_i64(); tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); - tcg_gen_addi_i64(tmp, tmp, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); + install_iaq_entries(ctx, -1, tmp, -1, NULL); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; break; @@ -2744,8 +2750,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) nullify_over(ctx); /* Advance the instruction queue. */ - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, + ctx->iaoq_n, ctx->iaoq_n_var); nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3898,18 +3904,15 @@ static bool trans_be(DisasContext *ctx, arg_be *a) tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); } if (a->n && use_nullify_skip(ctx)) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); - tcg_gen_addi_i64(tmp, tmp, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); + install_iaq_entries(ctx, -1, tmp, -1, NULL); tcg_gen_mov_i64(cpu_iasq_f, new_spc); tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); nullify_set(ctx, 0); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp); if (ctx->iaoq_b == -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, a->n); } @@ -4018,11 +4021,10 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) nullify_over(ctx); dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); if (ctx->iaoq_b == -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); if (a->l) { copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); @@ -4721,8 +4723,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) case DISAS_IAQ_N_STALE: case DISAS_IAQ_N_STALE_EXIT: if (ctx->iaoq_f == -1) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + install_iaq_entries(ctx, -1, cpu_iaoq_b, + ctx->iaoq_n, ctx->iaoq_n_var); #ifndef CONFIG_USER_ONLY tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); #endif @@ -4751,8 +4753,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: case DISAS_IAQ_N_STALE_EXIT: - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, + ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); /* FALLTHRU */ case DISAS_IAQ_N_UPDATED: From patchwork Mon May 13 07:46:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 892E6C25B74 for ; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 08/45] target/hppa: Add install_link Date: Mon, 13 May 2024 09:46:40 +0200 Message-Id: <20240513074717.130949-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add a common routine for writing the return address. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 54 +++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 08d5e2a4bc..f816b337ee 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -634,6 +634,23 @@ static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, } } +static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) +{ + tcg_debug_assert(ctx->null_cond.c == TCG_COND_NEVER); + if (link) { + if (ctx->iaoq_b == -1) { + tcg_gen_addi_i64(cpu_gr[link], cpu_iaoq_b, 4); + } else { + tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_b + 4); + } +#ifndef CONFIG_USER_ONLY + if (with_sr0) { + tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); + } +#endif + } +} + static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) { return ctx->iaoq_f + disp + 8; @@ -1787,9 +1804,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, uint64_t dest = iaoq_dest(ctx, disp); if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } + install_link(ctx, link, false); ctx->iaoq_n = dest; if (is_n) { ctx->null_cond.c = TCG_COND_ALWAYS; @@ -1797,10 +1812,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, } else { nullify_over(ctx); - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } - + install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); gen_goto_tb(ctx, 0, dest, dest + 4); @@ -1892,9 +1904,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, next = tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } + install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { install_iaq_entries(ctx, -1, next, -1, NULL); @@ -1911,16 +1921,17 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, nullify_over(ctx); + next = tcg_temp_new_i64(); + tcg_gen_mov_i64(next, dest); + + install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, dest, -1, NULL); + install_iaq_entries(ctx, -1, next, -1, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, next); nullify_set(ctx, is_n); } - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; @@ -3899,10 +3910,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) nullify_over(ctx); load_spr(ctx, new_spc, a->sp); - if (a->l) { - copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); - } + install_link(ctx, a->l, true); if (a->n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, -1, tmp, -1, NULL); tcg_gen_mov_i64(cpu_iasq_f, new_spc); @@ -4019,16 +4027,16 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) return do_ibranch(ctx, dest, a->l, a->n); #else nullify_over(ctx); - dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); + dest = tcg_temp_new_i64(); + tcg_gen_mov_i64(dest, load_gpr(ctx, a->b)); + dest = do_ibranch_priv(ctx, dest); + install_link(ctx, a->l, false); install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); if (ctx->iaoq_b == -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); - if (a->l) { - copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); - } nullify_set(ctx, a->n); tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; From patchwork Mon May 13 07:46:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3EB2AC25B10 for ; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 09/45] target/hppa: Delay computation of IAQ_Next Date: Mon, 13 May 2024 09:46:41 +0200 Message-Id: <20240513074717.130949-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We no longer have to allocate a temp and perform an addition before translation of the rest of the insn. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f816b337ee..a9196050dc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1806,6 +1806,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); ctx->iaoq_n = dest; + ctx->iaoq_n_var = NULL; if (is_n) { ctx->null_cond.c = TCG_COND_ALWAYS; } @@ -1862,11 +1863,6 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, ctx->null_lab = NULL; } nullify_set(ctx, n); - if (ctx->iaoq_n == -1) { - /* The temporary iaoq_n_var died at the branch above. - Regenerate it here instead of saving it. */ - tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); - } gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); } @@ -4630,8 +4626,6 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); #endif - ctx->iaoq_n = -1; - ctx->iaoq_n_var = NULL; ctx->zero = tcg_constant_i64(0); @@ -4683,14 +4677,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ - if (ctx->iaoq_b == -1) { - ctx->iaoq_n = -1; - ctx->iaoq_n_var = tcg_temp_new_i64(); - tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); - } else { - ctx->iaoq_n = ctx->iaoq_b + 4; - ctx->iaoq_n_var = NULL; - } + ctx->iaoq_n_var = NULL; + ctx->iaoq_n = ctx->iaoq_b == -1 ? -1 : ctx->iaoq_b + 4; if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { ctx->null_cond.c = TCG_COND_NEVER; @@ -4741,7 +4729,13 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ? DISAS_EXIT : DISAS_IAQ_N_UPDATED); } else if (ctx->iaoq_b == -1) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); + if (ctx->iaoq_n_var) { + copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); + } else { + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); + tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, + gva_offset_mask(ctx->tb_flags)); + } } break; From patchwork Mon May 13 07:46:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663138 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6798CC25B74 for ; Mon, 13 May 2024 07:52:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QQ6-0003k2-Ua; Mon, 13 May 2024 03:48:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPE-0002nH-NC for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:33 -0400 Received: from mail-lj1-x233.google.com ([2a00:1450:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPA-0001LA-4A for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:32 -0400 Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2e538a264f7so36924351fa.0 for ; Mon, 13 May 2024 00:47:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586446; x=1716191246; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2VF6uhgMTXvCNMpmE9TGG3M5Ce9XJhasOpTWLXUhXUs=; b=to7oM5G24BtaTUdtK9pxsvaVdbime/xj0/94FS3BsXOTK9mbgeFC2VW0+gW2LH+a0P H9o22rCLxNOrbUfOABirSZvflEDQ21yW7XL5+gemBR+Sl0HQ8Vk6QN/qdu93UhdD8WUU GD6zuCDuur9EJFyKF7B/1VFB6uglEOLLaLP9x3EPe6+ayBRkQiCp4vato/doCnEog0oN mRTxCeIAuCPLnBG4Me68R1kAKaP1AFw77UXV+Dxx11gCOLgwHB4deo8clukrh+XWZSQb i/o7CC4oKMlnHNqwqNyXve6un8snW3lgLaAqgEwhF9Dg0rnqGG2efBq2klYkQnrkhgFC AghQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586446; x=1716191246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2VF6uhgMTXvCNMpmE9TGG3M5Ce9XJhasOpTWLXUhXUs=; b=bECxkDoBeZHuMuqor7Rt0QnRoR7wjMizsm6uOcq4oyKoRgfjhfag8roP7lK/dst3iM MoF0Yh4H2JaTHKGF5e5atR02A7MS1wKxHrmcmoyUz5LfMFoYqoEG6Xlh54YVZgIrJCvM OevC3e/6kKGT7gKMQPokTLm5iyTNfN8tu0l14pBQ9K4u75M1Mwm0t/jy9PcMbnHhtYG6 z8QIwGxnXdU8rUjA47GqrFh89HpckTJ/q46Ajxe5dS4s6hGSt37bzVrtvkgdd9rZXbnu 0pj8p1sw0lkySyTVsPgc0FuQYzJdAYgctWcncsVDBDsQMrZ0OK3AFBLkmLLvCwWJcrEN IlWw== X-Gm-Message-State: AOJu0Ywt1f145K7edK369TgeiBt3xwc3IyR/0t1DtnaJUdFBn98yehyB BhAFzqEnzJ2evZKGh5Yv2qfX/LS4fhUzSUnrOpTwL4Jxqxae6JGK94Vb8zCB/2ogy49DoskDN1o 8xgY= X-Google-Smtp-Source: AGHT+IE7OJEj23f1JpsbYCQLKloqFDRUyouRNsdIa8vd7zjTHaSfIjNBG9zb/9rG1En9Wc5KYp86Sg== X-Received: by 2002:a2e:b04b:0:b0:2e3:cba4:234 with SMTP id 38308e7fff4ca-2e51fd2dccbmr59550281fa.10.1715586446495; Mon, 13 May 2024 00:47:26 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 10/45] target/hppa: Skip nullified insns in unconditional dbranch path Date: Mon, 13 May 2024 09:46:42 +0200 Message-Id: <20240513074717.130949-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a9196050dc..ca979f4137 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1805,11 +1805,17 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); - ctx->iaoq_n = dest; - ctx->iaoq_n_var = NULL; if (is_n) { + if (use_nullify_skip(ctx)) { + nullify_set(ctx, 0); + gen_goto_tb(ctx, 0, dest, dest + 4); + ctx->base.is_jmp = DISAS_NORETURN; + return true; + } ctx->null_cond.c = TCG_COND_ALWAYS; } + ctx->iaoq_n = dest; + ctx->iaoq_n_var = NULL; } else { nullify_over(ctx); From patchwork Mon May 13 07:46:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4EEAC25B78 for ; Mon, 13 May 2024 07:54:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPU-0002v5-4v; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 11/45] target/hppa: Simplify TB end Date: Mon, 13 May 2024 09:46:43 +0200 Message-Id: <20240513074717.130949-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Minimize the amount of code in hppa_tr_translate_insn advancing the insn queue for the next insn. Move the goto_tb path to hppa_tr_tb_stop. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 109 +++++++++++++++++++++------------------- 1 file changed, 57 insertions(+), 52 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ca979f4137..13a48d1b6c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4699,54 +4699,31 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } } - /* Advance the insn queue. Note that this check also detects - a priority change within the instruction queue. */ - if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { - if (use_goto_tb(ctx, ctx->iaoq_b, ctx->iaoq_n) - && (ctx->null_cond.c == TCG_COND_NEVER - || ctx->null_cond.c == TCG_COND_ALWAYS)) { - nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); - gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); - ctx->base.is_jmp = ret = DISAS_NORETURN; - } else { - ctx->base.is_jmp = ret = DISAS_IAQ_N_STALE; - } + /* If the TranslationBlock must end, do so. */ + ctx->base.pc_next += 4; + if (ret != DISAS_NEXT) { + return; } + /* Note this also detects a priority change. */ + if (ctx->iaoq_b != ctx->iaoq_f + 4) { + ctx->base.is_jmp = DISAS_IAQ_N_STALE; + return; + } + + /* + * Advance the insn queue. + * The only exit now is DISAS_TOO_MANY from the translator loop. + */ ctx->iaoq_f = ctx->iaoq_b; ctx->iaoq_b = ctx->iaoq_n; - ctx->base.pc_next += 4; - - switch (ret) { - case DISAS_NORETURN: - case DISAS_IAQ_N_UPDATED: - break; - - case DISAS_NEXT: - case DISAS_IAQ_N_STALE: - case DISAS_IAQ_N_STALE_EXIT: - if (ctx->iaoq_f == -1) { - install_iaq_entries(ctx, -1, cpu_iaoq_b, - ctx->iaoq_n, ctx->iaoq_n_var); -#ifndef CONFIG_USER_ONLY - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); -#endif - nullify_save(ctx); - ctx->base.is_jmp = (ret == DISAS_IAQ_N_STALE_EXIT - ? DISAS_EXIT - : DISAS_IAQ_N_UPDATED); - } else if (ctx->iaoq_b == -1) { - if (ctx->iaoq_n_var) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); - } + if (ctx->iaoq_b == -1) { + if (ctx->iaoq_n_var) { + copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); + } else { + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); + tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, + gva_offset_mask(ctx->tb_flags)); } - break; - - default: - g_assert_not_reached(); } } @@ -4754,23 +4731,51 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasJumpType is_jmp = ctx->base.is_jmp; + uint64_t fi, bi; + TCGv_i64 fv, bv; + TCGv_i64 fs; + + /* Assume the insn queue has not been advanced. */ + fi = ctx->iaoq_b; + fv = cpu_iaoq_b; + fs = fi == -1 ? cpu_iasq_b : NULL; + bi = ctx->iaoq_n; + bv = ctx->iaoq_n_var; switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: - case DISAS_IAQ_N_STALE: - case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, - ctx->iaoq_b, cpu_iaoq_b); - nullify_save(ctx); + /* The insn queue has not been advanced. */ + bi = fi; + bv = fv; + fi = ctx->iaoq_f; + fv = NULL; + fs = NULL; /* FALLTHRU */ - case DISAS_IAQ_N_UPDATED: - if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { - tcg_gen_lookup_and_goto_ptr(); + case DISAS_IAQ_N_STALE: + if (use_goto_tb(ctx, fi, bi) + && (ctx->null_cond.c == TCG_COND_NEVER + || ctx->null_cond.c == TCG_COND_ALWAYS)) { + nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); + gen_goto_tb(ctx, 0, fi, bi); break; } /* FALLTHRU */ + case DISAS_IAQ_N_STALE_EXIT: + install_iaq_entries(ctx, fi, fv, bi, bv); + if (fs) { + tcg_gen_mov_i64(cpu_iasq_f, fs); + } + nullify_save(ctx); + if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { + tcg_gen_exit_tb(NULL, 0); + break; + } + /* FALLTHRU */ + case DISAS_IAQ_N_UPDATED: + tcg_gen_lookup_and_goto_ptr(); + break; case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; From patchwork Mon May 13 07:46:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80D30C25B10 for ; Mon, 13 May 2024 07:54:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPK-0002r5-6y; Mon, 13 May 2024 03:47:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPE-0002nF-Ah for qemu-devel@nongnu.org; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 12/45] target/hppa: Add IASQ entries to DisasContext Date: Mon, 13 May 2024 09:46:44 +0200 Message-Id: <20240513074717.130949-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add variable to track space changes to IAQ. So far, no such changes are introduced, but the new checks vs ctx->iasq_b may eliminate an unnecessary copy to cpu_iasq_f with e.g. BLR. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 13a48d1b6c..d24220c60f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -50,6 +50,13 @@ typedef struct DisasContext { uint64_t iaoq_b; uint64_t iaoq_n; TCGv_i64 iaoq_n_var; + /* + * Null when IASQ_Back unchanged from IASQ_Front, + * or cpu_iasq_b, when IASQ_Back has been changed. + */ + TCGv_i64 iasq_b; + /* Null when IASQ_Next unchanged from IASQ_Back, or set by branch. */ + TCGv_i64 iasq_n; DisasCond null_cond; TCGLabel *null_lab; @@ -3916,12 +3923,12 @@ static bool trans_be(DisasContext *ctx, arg_be *a) if (a->n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, -1, tmp, -1, NULL); tcg_gen_mov_i64(cpu_iasq_f, new_spc); - tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); + tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, 0); } else { install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp); - if (ctx->iaoq_b == -1) { - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + if (ctx->iasq_b) { + tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); } tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, a->n); @@ -4035,8 +4042,8 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) install_link(ctx, a->l, false); install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); - if (ctx->iaoq_b == -1) { - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + if (ctx->iasq_b) { + tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); } tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); nullify_set(ctx, a->n); @@ -4617,6 +4624,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; + ctx->iasq_b = NULL; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4631,6 +4639,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); + ctx->iasq_b = (diff ? NULL : cpu_iasq_b); #endif ctx->zero = tcg_constant_i64(0); @@ -4683,6 +4692,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ + ctx->iasq_n = NULL; ctx->iaoq_n_var = NULL; ctx->iaoq_n = ctx->iaoq_b == -1 ? -1 : ctx->iaoq_b + 4; @@ -4705,7 +4715,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } /* Note this also detects a priority change. */ - if (ctx->iaoq_b != ctx->iaoq_f + 4) { + if (ctx->iaoq_b != ctx->iaoq_f + 4 || ctx->iasq_b) { ctx->base.is_jmp = DISAS_IAQ_N_STALE; return; } @@ -4725,6 +4735,10 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) gva_offset_mask(ctx->tb_flags)); } } + if (ctx->iasq_n) { + tcg_gen_mov_i64(cpu_iasq_b, ctx->iasq_n); + ctx->iasq_b = cpu_iasq_b; + } } static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) @@ -4733,14 +4747,15 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) DisasJumpType is_jmp = ctx->base.is_jmp; uint64_t fi, bi; TCGv_i64 fv, bv; - TCGv_i64 fs; + TCGv_i64 fs, bs; /* Assume the insn queue has not been advanced. */ fi = ctx->iaoq_b; fv = cpu_iaoq_b; - fs = fi == -1 ? cpu_iasq_b : NULL; + fs = ctx->iasq_b; bi = ctx->iaoq_n; bv = ctx->iaoq_n_var; + bs = ctx->iasq_n; switch (is_jmp) { case DISAS_NORETURN: @@ -4749,12 +4764,15 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) /* The insn queue has not been advanced. */ bi = fi; bv = fv; + bs = fs; fi = ctx->iaoq_f; fv = NULL; fs = NULL; /* FALLTHRU */ case DISAS_IAQ_N_STALE: - if (use_goto_tb(ctx, fi, bi) + if (fs == NULL + && bs == NULL + && use_goto_tb(ctx, fi, bi) && (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); @@ -4767,6 +4785,9 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) if (fs) { tcg_gen_mov_i64(cpu_iasq_f, fs); } + if (bs) { + tcg_gen_mov_i64(cpu_iasq_b, bs); + } nullify_save(ctx); if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); From patchwork Mon May 13 07:46:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BEE1FC25B78 for ; Mon, 13 May 2024 07:49:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPR-0002uI-EW; Mon, 13 May 2024 03:47:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPE-0002nB-2g for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:33 -0400 Received: from mail-lj1-x231.google.com ([2a00:1450:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPC-0001Lm-7M for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:31 -0400 Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2e0a34b2899so60308591fa.3 for ; Mon, 13 May 2024 00:47:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586448; x=1716191248; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZeHTNmgl5VcWCzWyaGiTmj8h8z3iRV8Wt7l8INt8uKM=; b=r6vcA7G6u3edbGuZGtbaoutRGLTVSkuh2yhOV8PqR8OULVM4XCOrVZ81Lx/n1UOtUX ZVFUHxHBfii73bnVdNEX+vXe7Q/ZDYYbjjpUpnv8JGSxClo26S41EvXPPXJ+i1JXqqVE 5HcMwIx1xKRTjETfB463DKQgH9plC3pFklJX+XLXE3F8n7YPxN3Q9JKJwK3w/BKZpVCJ wHarEZDyaQjvAo8yHNLLVl0dDpbS57WRlNNk5DqkNPfgomoFVjQp22KL2jS+VMEihMmc mQiEkkhrP9u0+aV76uC10PVoW9olvBMEtoi+nSZwiLjZMpqmvmw3LhOxcph/Cr6hrYV8 akRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586448; x=1716191248; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZeHTNmgl5VcWCzWyaGiTmj8h8z3iRV8Wt7l8INt8uKM=; b=WcWQBpk5g9QHOG/omRBu8ZvOjYwL623o8rBHcEBl1gzbwF4FhN7BrNyEYbmAu7lW5g uYfPJ/riNkfacMvbztkMZdEemXeP41hFg5kM2Iw9EyZw4ksy1h0Mx6So5vKWvfbK5uH+ bxoIdTThstX2uiJicz6lrDhT/WcXlv8b9aFgQbD43K+OxnEnYY209XXHjIynoPzqDM9C N+i/f9VjfHcppQ4m8u0lBgYJPZqyxpFfylqvoxhDLHPFRwhB9fGScWfPdLCi0NLkTp/g x+id7xJpsp5NesRplxus/+apSGUCaHF0jUBQKNi1tAUHQ33Y6QTFZmDNCFzdRCF8eyhe N/bQ== X-Gm-Message-State: AOJu0Yyn7xey0C/MoKZPa1i3K9oJoKb8oK+LSEcLzR1nryXZ+NNgquh5 dvWsHL9tJuc2zoODvryWihIjMoGE5MZ+81CrwLXGABnlN8g8A8f09rLDuNiiUlWifhvod94sgXr SMiY= X-Google-Smtp-Source: AGHT+IE5R6AboSBb8Di1T6aHLwwIKfHMlrSCnKoGj+QNNINcELDzkg+j6dsMJI70HOdzAvWCPA3cuA== X-Received: by 2002:a2e:7d09:0:b0:2e2:1647:f671 with SMTP id 38308e7fff4ca-2e5205c817emr75141601fa.47.1715586448686; Mon, 13 May 2024 00:47:28 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 13/45] target/hppa: Add space arguments to install_iaq_entries Date: Mon, 13 May 2024 09:46:45 +0200 Message-Id: <20240513074717.130949-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move space assighments to a central location. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 58 +++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d24220c60f..05383dcd04 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -624,8 +624,9 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, } } -static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, - uint64_t ni, TCGv_i64 nv) +static void install_iaq_entries(DisasContext *ctx, + uint64_t bi, TCGv_i64 bv, TCGv_i64 bs, + uint64_t ni, TCGv_i64 nv, TCGv_i64 ns) { copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); @@ -639,6 +640,12 @@ static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, gva_offset_mask(ctx->tb_flags)); } + if (bs) { + tcg_gen_mov_i64(cpu_iasq_f, bs); + } + if (ns || bs) { + tcg_gen_mov_i64(cpu_iasq_b, ns ? ns : bs); + } } static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) @@ -670,7 +677,8 @@ static void gen_excp_1(int exception) static void gen_excp(DisasContext *ctx, int exception) { - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, NULL, + ctx->iaoq_b, cpu_iaoq_b, NULL); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp = DISAS_NORETURN; @@ -724,10 +732,11 @@ static void gen_goto_tb(DisasContext *ctx, int which, { if (use_goto_tb(ctx, b, n)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, b, NULL, n, NULL); + install_iaq_entries(ctx, b, NULL, NULL, n, NULL, NULL); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, b, cpu_iaoq_b, n, ctx->iaoq_n_var); + install_iaq_entries(ctx, b, cpu_iaoq_b, ctx->iasq_b, + n, ctx->iaoq_n_var, ctx->iasq_n); tcg_gen_lookup_and_goto_ptr(); } } @@ -1916,7 +1925,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, -1, NULL); + install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; @@ -1935,10 +1944,11 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, -1, NULL); + install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, next); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + -1, next, NULL); nullify_set(ctx, is_n); } @@ -2026,7 +2036,7 @@ static void do_page_zero(DisasContext *ctx) tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); tmp = tcg_temp_new_i64(); tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - install_iaq_entries(ctx, -1, tmp, -1, NULL); + install_iaq_entries(ctx, -1, tmp, NULL, -1, NULL, NULL); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; break; @@ -2770,8 +2780,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) nullify_over(ctx); /* Advance the instruction queue. */ - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, - ctx->iaoq_n, ctx->iaoq_n_var); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + ctx->iaoq_n, ctx->iaoq_n_var, ctx->iasq_n); nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3921,16 +3931,11 @@ static bool trans_be(DisasContext *ctx, arg_be *a) load_spr(ctx, new_spc, a->sp); install_link(ctx, a->l, true); if (a->n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, tmp, -1, NULL); - tcg_gen_mov_i64(cpu_iasq_f, new_spc); - tcg_gen_mov_i64(cpu_iasq_b, new_spc); + install_iaq_entries(ctx, -1, tmp, new_spc, -1, NULL, new_spc); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp); - if (ctx->iasq_b) { - tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); - } - tcg_gen_mov_i64(cpu_iasq_b, new_spc); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + -1, tmp, new_spc); nullify_set(ctx, a->n); } tcg_gen_lookup_and_goto_ptr(); @@ -4041,11 +4046,8 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) dest = do_ibranch_priv(ctx, dest); install_link(ctx, a->l, false); - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); - if (ctx->iasq_b) { - tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); - } - tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + -1, dest, space_select(ctx, 0, dest)); nullify_set(ctx, a->n); tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; @@ -4781,13 +4783,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) } /* FALLTHRU */ case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, fi, fv, bi, bv); - if (fs) { - tcg_gen_mov_i64(cpu_iasq_f, fs); - } - if (bs) { - tcg_gen_mov_i64(cpu_iasq_b, bs); - } + install_iaq_entries(ctx, fi, fv, fs, bi, bv, bs); nullify_save(ctx); if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 14/45] target/hppa: Add space argument to do_ibranch Date: Mon, 13 May 2024 09:46:46 +0200 Message-Id: <20240513074717.130949-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This allows unification of BE, BLR, BV, BVE with a common helper. Since we can now track space with IAQ_Next, we can now let the TranslationBlock continue across the delay slot with BE, BVE. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 76 ++++++++++++++--------------------------- 1 file changed, 26 insertions(+), 50 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 05383dcd04..ae66068123 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1913,8 +1913,8 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, - unsigned link, bool is_n) +static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, + unsigned link, bool with_sr0, bool is_n) { TCGv_i64 next; @@ -1922,10 +1922,10 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, next = tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); - install_link(ctx, link, false); + install_link(ctx, link, with_sr0); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); + install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; @@ -1934,6 +1934,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, } ctx->iaoq_n = -1; ctx->iaoq_n_var = next; + ctx->iasq_n = dspc; return true; } @@ -1942,13 +1943,13 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, next = tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); - install_link(ctx, link, false); + install_link(ctx, link, with_sr0); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); + install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); nullify_set(ctx, 0); } else { install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, next, NULL); + -1, next, dspc); nullify_set(ctx, is_n); } @@ -3915,33 +3916,18 @@ static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a) static bool trans_be(DisasContext *ctx, arg_be *a) { - TCGv_i64 tmp; + TCGv_i64 dest = tcg_temp_new_i64(); + TCGv_i64 space = NULL; - tmp = tcg_temp_new_i64(); - tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); - tmp = do_ibranch_priv(ctx, tmp); + tcg_gen_addi_i64(dest, load_gpr(ctx, a->b), a->disp); + dest = do_ibranch_priv(ctx, dest); -#ifdef CONFIG_USER_ONLY - return do_ibranch(ctx, tmp, a->l, a->n); -#else - TCGv_i64 new_spc = tcg_temp_new_i64(); - - nullify_over(ctx); - - load_spr(ctx, new_spc, a->sp); - install_link(ctx, a->l, true); - if (a->n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, tmp, new_spc, -1, NULL, new_spc); - nullify_set(ctx, 0); - } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, tmp, new_spc); - nullify_set(ctx, a->n); - } - tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp = DISAS_NORETURN; - return nullify_end(ctx); +#ifndef CONFIG_USER_ONLY + space = tcg_temp_new_i64(); + load_spr(ctx, space, a->sp); #endif + + return do_ibranch(ctx, dest, space, a->l, true, a->n); } static bool trans_bl(DisasContext *ctx, arg_bl *a) @@ -4010,7 +3996,7 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); /* The computation here never changes privilege level. */ - return do_ibranch(ctx, tmp, a->l, a->n); + return do_ibranch(ctx, tmp, NULL, a->l, false, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ return do_dbranch(ctx, 0, a->l, a->n); @@ -4029,30 +4015,20 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } dest = do_ibranch_priv(ctx, dest); - return do_ibranch(ctx, dest, 0, a->n); + return do_ibranch(ctx, dest, NULL, 0, false, a->n); } static bool trans_bve(DisasContext *ctx, arg_bve *a) { - TCGv_i64 dest; + TCGv_i64 b = load_gpr(ctx, a->b); + TCGv_i64 dest = do_ibranch_priv(ctx, b); + TCGv_i64 space = NULL; -#ifdef CONFIG_USER_ONLY - dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); - return do_ibranch(ctx, dest, a->l, a->n); -#else - nullify_over(ctx); - dest = tcg_temp_new_i64(); - tcg_gen_mov_i64(dest, load_gpr(ctx, a->b)); - dest = do_ibranch_priv(ctx, dest); - - install_link(ctx, a->l, false); - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, dest, space_select(ctx, 0, dest)); - nullify_set(ctx, a->n); - tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp = DISAS_NORETURN; - return nullify_end(ctx); +#ifndef CONFIG_USER_ONLY + space = space_select(ctx, 0, b); #endif + + return do_ibranch(ctx, dest, space, a->l, false, a->n); } static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) From patchwork Mon May 13 07:46:47 2024 Content-Type: text/plain; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 15/45] target/hppa: Use umax in do_ibranch_priv Date: Mon, 13 May 2024 09:46:47 +0200 Message-Id: <20240513074717.130949-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ae66068123..22935f4645 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1981,7 +1981,7 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) dest = tcg_temp_new_i64(); tcg_gen_andi_i64(dest, offset, -4); tcg_gen_ori_i64(dest, dest, ctx->privilege); - tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset); + tcg_gen_umax_i64(dest, dest, offset); break; } return dest; From patchwork Mon May 13 07:46:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85E5DC25B79 for ; Mon, 13 May 2024 07:51:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPI-0002qN-HV; Mon, 13 May 2024 03:47:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPF-0002nb-SC for qemu-devel@nongnu.org; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 16/45] target/hppa: Always make a copy in do_ibranch_priv Date: Mon, 13 May 2024 09:46:48 +0200 Message-Id: <20240513074717.130949-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This simplifies callers, which might otherwise have to make another copy. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hppa/translate.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 22935f4645..f267de14c6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1967,18 +1967,17 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, */ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) { - TCGv_i64 dest; + TCGv_i64 dest = tcg_temp_new_i64(); switch (ctx->privilege) { case 0: /* Privilege 0 is maximum and is allowed to decrease. */ - return offset; + tcg_gen_mov_i64(dest, offset); + break; case 3: /* Privilege 3 is minimum and is never allowed to increase. */ - dest = tcg_temp_new_i64(); tcg_gen_ori_i64(dest, offset, 3); break; default: - dest = tcg_temp_new_i64(); tcg_gen_andi_i64(dest, offset, -4); tcg_gen_ori_i64(dest, dest, ctx->privilege); tcg_gen_umax_i64(dest, dest, offset); From patchwork Mon May 13 07:46:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C801C25B10 for ; Mon, 13 May 2024 07:49:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPN-0002sG-Ny; Mon, 13 May 2024 03:47:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPI-0002qT-LE for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:37 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPF-0001Md-E0 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:36 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-420157ee56cso5247395e9.2 for ; Mon, 13 May 2024 00:47:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586451; x=1716191251; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ADkbGYKP910g+fruRN3VmASk0ItWfrwKOLvahbn+fLw=; b=kmURmhjRoCupMpCDMnFRLRiZl1R8zotPZMVcerKYj2rOReCW3HAceIoda87uvVzoPi 4bnHXvswUFTbhZQhVMRlI90skF/hCUM99pptNYH+PDF4P4aGFM2jdI3fu9MkDe/itzrI ZnKxLXnPbF8/3sNsZBRTbemNbZxkDq2D7PFdJ8chzhJsRcnUlKUJnLvbptmV0lylWZaI NFJ40g6+4lYizjnYWlWTbMmZKRQlRyffhmAj1azr2cLPSzjFIlOpCE5QkHMjKPQx5xrP CnLQcKXqmq9ztvYM5sGR3fhHqdw/0qUH0bIVRSKDXUOR06h6CaWR44IfE/7Qh+t9Agfh 7HQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586451; x=1716191251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ADkbGYKP910g+fruRN3VmASk0ItWfrwKOLvahbn+fLw=; b=nC29vsPiogx7hfRaazvrhDoUrkQg0PCBJQokFeaR/cHEMunVBSiNOXUAJjLI5UVFjX nI2BWM3ihBAbNTsBfBW3zaTz28Pu/v7v5iXpHQspCxWcInxUem04mXlY0uu0B+DxDDhM Xf4zeIS5BiGFn4k1ljZEzhjHqIZoCpzGnNMHZPGEk5y8eTRuezIIQivBFunfOh1ZLWl0 H6bQ5vnIwe7hdX66kxNR06DgHoIFhUgAqnqWoB0ol/zCOqcda6GarTOnNuukmZplOJKV CTttbkRNKZZQ+Mg1XWQa2CGt9BaaryC6fQmLAIGU/L3+GvT6egidL5VZwJOPsC7j2no0 nEGQ== X-Gm-Message-State: AOJu0YxHSgVzh/mie9kEJl56hqzd29xXRCN6iAq4rxwnymYe0BVDCt87 ojv3o1tQbfsBV8a5USfsY3HZPmr7dFpxZ51D0XBO4+dqhw+T4XDzEegm2pq920Rtq3oh0vOxSFx puk8= X-Google-Smtp-Source: AGHT+IHwdiTnw0gNsxxbmwa5teuhfbFkHMlke+CV6urKijBnBpRsxVaqdwkySc8oMgZOw7fmhj2QFw== X-Received: by 2002:a05:600c:3108:b0:416:536b:683a with SMTP id 5b1f17b1804b1-41fead65000mr59810125e9.32.1715586451481; Mon, 13 May 2024 00:47:31 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 17/45] target/hppa: Introduce and use DisasIAQE for branch management Date: Mon, 13 May 2024 09:46:49 +0200 Message-Id: <20240513074717.130949-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Wrap offset and space together in one structure, ensuring that they're copied together as required. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 378 +++++++++++++++++++++------------------- 1 file changed, 198 insertions(+), 180 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f267de14c6..4e2e35f9cc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -42,21 +42,23 @@ typedef struct DisasCond { TCGv_i64 a0, a1; } DisasCond; +typedef struct DisasIAQE { + /* IASQ; may be null for no change from TB. */ + TCGv_i64 space; + /* IAOQ base; may be null for immediate absolute address. */ + TCGv_i64 base; + /* IAOQ addend; absolute immedate address if base is null. */ + int64_t disp; +} DisasIAQE; + typedef struct DisasContext { DisasContextBase base; CPUState *cs; - uint64_t iaoq_f; - uint64_t iaoq_b; - uint64_t iaoq_n; - TCGv_i64 iaoq_n_var; - /* - * Null when IASQ_Back unchanged from IASQ_Front, - * or cpu_iasq_b, when IASQ_Back has been changed. - */ - TCGv_i64 iasq_b; - /* Null when IASQ_Next unchanged from IASQ_Back, or set by branch. */ - TCGv_i64 iasq_n; + /* IAQ_Front, IAQ_Back. */ + DisasIAQE iaq_f, iaq_b; + /* IAQ_Next, for jumps, otherwise null for simple advance. */ + DisasIAQE iaq_j, *iaq_n; DisasCond null_cond; TCGLabel *null_lab; @@ -602,49 +604,67 @@ static bool nullify_end(DisasContext *ctx) return true; } +static bool iaqe_variable(const DisasIAQE *e) +{ + return e->base || e->space; +} + +static DisasIAQE iaqe_incr(const DisasIAQE *e, int64_t disp) +{ + return (DisasIAQE){ + .space = e->space, + .base = e->base, + .disp = e->disp + disp, + }; +} + +static DisasIAQE iaqe_branchi(DisasContext *ctx, int64_t disp) +{ + return (DisasIAQE){ + .space = ctx->iaq_b.space, + .disp = ctx->iaq_f.disp + 8 + disp, + }; +} + +static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) +{ + return (DisasIAQE){ + .space = ctx->iaq_b.space, + .base = var, + }; +} + static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, - uint64_t ival, TCGv_i64 vval) + const DisasIAQE *src) { uint64_t mask = gva_offset_mask(ctx->tb_flags); - if (ival != -1) { - tcg_gen_movi_i64(dest, ival & mask); - return; - } - tcg_debug_assert(vval != NULL); - - /* - * We know that the IAOQ is already properly masked. - * This optimization is primarily for "iaoq_f = iaoq_b". - */ - if (vval == cpu_iaoq_f || vval == cpu_iaoq_b) { - tcg_gen_mov_i64(dest, vval); + if (src->base == NULL) { + tcg_gen_movi_i64(dest, src->disp & mask); + } else if (src->disp == 0) { + tcg_gen_andi_i64(dest, src->base, mask); } else { - tcg_gen_andi_i64(dest, vval, mask); + tcg_gen_addi_i64(dest, src->base, src->disp); + tcg_gen_andi_i64(dest, dest, mask); } } -static void install_iaq_entries(DisasContext *ctx, - uint64_t bi, TCGv_i64 bv, TCGv_i64 bs, - uint64_t ni, TCGv_i64 nv, TCGv_i64 ns) +static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, + const DisasIAQE *b) { - copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); + DisasIAQE b_next; - /* Allow ni variable, with nv null, to indicate a trivial advance. */ - if (ni != -1 || nv) { - copy_iaoq_entry(ctx, cpu_iaoq_b, ni, nv); - } else if (bi != -1) { - copy_iaoq_entry(ctx, cpu_iaoq_b, bi + 4, NULL); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); + if (b == NULL) { + b_next = iaqe_incr(f, 4); + b = &b_next; } - if (bs) { - tcg_gen_mov_i64(cpu_iasq_f, bs); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + copy_iaoq_entry(ctx, cpu_iaoq_b, b); + if (f->space) { + tcg_gen_mov_i64(cpu_iasq_f, f->space); } - if (ns || bs) { - tcg_gen_mov_i64(cpu_iasq_b, ns ? ns : bs); + if (b->space || f->space) { + tcg_gen_mov_i64(cpu_iasq_b, b->space ? : f->space); } } @@ -652,10 +672,11 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) { tcg_debug_assert(ctx->null_cond.c == TCG_COND_NEVER); if (link) { - if (ctx->iaoq_b == -1) { - tcg_gen_addi_i64(cpu_gr[link], cpu_iaoq_b, 4); + if (ctx->iaq_b.base) { + tcg_gen_addi_i64(cpu_gr[link], ctx->iaq_b.base, + ctx->iaq_b.disp + 4); } else { - tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_b + 4); + tcg_gen_movi_i64(cpu_gr[link], ctx->iaq_b.disp + 4); } #ifndef CONFIG_USER_ONLY if (with_sr0) { @@ -665,11 +686,6 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) } } -static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) -{ - return ctx->iaoq_f + disp + 8; -} - static void gen_excp_1(int exception) { gen_helper_excp(tcg_env, tcg_constant_i32(exception)); @@ -677,8 +693,7 @@ static void gen_excp_1(int exception) static void gen_excp(DisasContext *ctx, int exception) { - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, NULL, - ctx->iaoq_b, cpu_iaoq_b, NULL); + install_iaq_entries(ctx, &ctx->iaq_f, &ctx->iaq_b); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp = DISAS_NORETURN; @@ -710,10 +725,12 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif -static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) +static bool use_goto_tb(DisasContext *ctx, const DisasIAQE *f, + const DisasIAQE *b) { - return (bofs != -1 && nofs != -1 && - translator_use_goto_tb(&ctx->base, bofs)); + return (!iaqe_variable(f) && + (b == NULL || !iaqe_variable(b)) && + translator_use_goto_tb(&ctx->base, f->disp)); } /* If the next insn is to be nullified, and it's on the same page, @@ -723,20 +740,19 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) static bool use_nullify_skip(DisasContext *ctx) { return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) - && ctx->iaoq_b != -1 - && is_same_page(&ctx->base, ctx->iaoq_b)); + && !iaqe_variable(&ctx->iaq_b) + && is_same_page(&ctx->base, ctx->iaq_b.disp)); } static void gen_goto_tb(DisasContext *ctx, int which, - uint64_t b, uint64_t n) + const DisasIAQE *f, const DisasIAQE *b) { - if (use_goto_tb(ctx, b, n)) { + if (use_goto_tb(ctx, f, b)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, b, NULL, NULL, n, NULL, NULL); + install_iaq_entries(ctx, f, b); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, b, cpu_iaoq_b, ctx->iasq_b, - n, ctx->iaoq_n_var, ctx->iasq_n); + install_iaq_entries(ctx, f, b); tcg_gen_lookup_and_goto_ptr(); } } @@ -1817,37 +1833,35 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, static bool do_dbranch(DisasContext *ctx, int64_t disp, unsigned link, bool is_n) { - uint64_t dest = iaoq_dest(ctx, disp); + ctx->iaq_j = iaqe_branchi(ctx, disp); if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, dest, dest + 4); + gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); ctx->base.is_jmp = DISAS_NORETURN; return true; } ctx->null_cond.c = TCG_COND_ALWAYS; } - ctx->iaoq_n = dest; - ctx->iaoq_n_var = NULL; + ctx->iaq_n = &ctx->iaq_j; } else { nullify_over(ctx); install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, dest, dest + 4); + gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); } else { nullify_set(ctx, is_n); - gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); + gen_goto_tb(ctx, 0, &ctx->iaq_b, &ctx->iaq_j); } - nullify_end(ctx); nullify_set(ctx, 0); - gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); + gen_goto_tb(ctx, 1, &ctx->iaq_b, NULL); ctx->base.is_jmp = DISAS_NORETURN; } return true; @@ -1858,7 +1872,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, DisasCond *cond) { - uint64_t dest = iaoq_dest(ctx, disp); + DisasIAQE next; TCGLabel *taken = NULL; TCGCond c = cond->c; bool n; @@ -1878,26 +1892,29 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, n = is_n && disp < 0; if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4); + next = iaqe_incr(&ctx->iaq_b, 4); + gen_goto_tb(ctx, 0, &next, NULL); } else { if (!n && ctx->null_lab) { gen_set_label(ctx->null_lab); ctx->null_lab = NULL; } nullify_set(ctx, n); - gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); + gen_goto_tb(ctx, 0, &ctx->iaq_b, NULL); } gen_set_label(taken); /* Taken: Condition satisfied; nullify on forward branches. */ n = is_n && disp >= 0; + + next = iaqe_branchi(ctx, disp); if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 1, dest, dest + 4); + gen_goto_tb(ctx, 1, &next, NULL); } else { nullify_set(ctx, n); - gen_goto_tb(ctx, 1, ctx->iaoq_b, dest); + gen_goto_tb(ctx, 1, &ctx->iaq_b, &next); } /* Not taken: the branch itself was nullified. */ @@ -1911,45 +1928,36 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, return true; } -/* Emit an unconditional branch to an indirect target. This handles - nullification of the branch itself. */ -static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, - unsigned link, bool with_sr0, bool is_n) +/* + * Emit an unconditional branch to an indirect target, in ctx->iaq_j. + * This handles nullification of the branch itself. + */ +static bool do_ibranch(DisasContext *ctx, unsigned link, + bool with_sr0, bool is_n) { - TCGv_i64 next; - if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { - next = tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); - install_link(ctx, link, with_sr0); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); + install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; } ctx->null_cond.c = TCG_COND_ALWAYS; } - ctx->iaoq_n = -1; - ctx->iaoq_n_var = next; - ctx->iasq_n = dspc; + ctx->iaq_n = &ctx->iaq_j; return true; } nullify_over(ctx); - next = tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); - install_link(ctx, link, with_sr0); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); + install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, next, dspc); + install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); nullify_set(ctx, is_n); } @@ -1996,8 +2004,6 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) aforementioned BE. */ static void do_page_zero(DisasContext *ctx) { - TCGv_i64 tmp; - /* If by some means we get here with PSW[N]=1, that implies that the B,GATE instruction would be skipped, and we'd fault on the next insn within the privileged page. */ @@ -2017,11 +2023,11 @@ static void do_page_zero(DisasContext *ctx) non-sequential instruction execution. Normally the PSW[B] bit detects this by disallowing the B,GATE instruction to execute under such conditions. */ - if (ctx->iaoq_b != ctx->iaoq_f + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { goto do_sigill; } - switch (ctx->iaoq_f & -4) { + switch (ctx->iaq_f.disp & -4) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_IMP); ctx->base.is_jmp = DISAS_NORETURN; @@ -2033,11 +2039,15 @@ static void do_page_zero(DisasContext *ctx) break; case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); - tmp = tcg_temp_new_i64(); - tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - install_iaq_entries(ctx, -1, tmp, NULL, -1, NULL, NULL); - ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; + { + DisasIAQE next = { .base = tcg_temp_new_i64() }; + + tcg_gen_st_i64(cpu_gr[26], tcg_env, + offsetof(CPUHPPAState, cr[27])); + tcg_gen_ori_i64(next.base, cpu_gr[31], 3); + install_iaq_entries(ctx, &next, NULL); + ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; + } break; case 0x100: /* SYSCALL */ @@ -2076,11 +2086,12 @@ static bool trans_sync(DisasContext *ctx, arg_sync *a) static bool trans_mfia(DisasContext *ctx, arg_mfia *a) { - unsigned rt = a->t; - TCGv_i64 tmp = dest_gpr(ctx, rt); - tcg_gen_movi_i64(tmp, ctx->iaoq_f & ~3ULL); - save_gpr(ctx, rt, tmp); + TCGv_i64 dest = dest_gpr(ctx, a->t); + copy_iaoq_entry(ctx, dest, &ctx->iaq_f); + tcg_gen_andi_i64(dest, dest, -4); + + save_gpr(ctx, a->t, dest); cond_free(&ctx->null_cond); return true; } @@ -2780,8 +2791,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) nullify_over(ctx); /* Advance the instruction queue. */ - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - ctx->iaoq_n, ctx->iaoq_n_var, ctx->iasq_n); + install_iaq_entries(ctx, &ctx->iaq_b, NULL); nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3915,18 +3925,18 @@ static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a) static bool trans_be(DisasContext *ctx, arg_be *a) { - TCGv_i64 dest = tcg_temp_new_i64(); - TCGv_i64 space = NULL; - - tcg_gen_addi_i64(dest, load_gpr(ctx, a->b), a->disp); - dest = do_ibranch_priv(ctx, dest); - #ifndef CONFIG_USER_ONLY - space = tcg_temp_new_i64(); - load_spr(ctx, space, a->sp); + ctx->iaq_j.space = tcg_temp_new_i64(); + load_spr(ctx, ctx->iaq_j.space, a->sp); #endif - return do_ibranch(ctx, dest, space, a->l, true, a->n); + ctx->iaq_j.base = tcg_temp_new_i64(); + ctx->iaq_j.disp = 0; + + tcg_gen_addi_i64(ctx->iaq_j.base, load_gpr(ctx, a->b), a->disp); + ctx->iaq_j.base = do_ibranch_priv(ctx, ctx->iaq_j.base); + + return do_ibranch(ctx, a->l, true, a->n); } static bool trans_bl(DisasContext *ctx, arg_bl *a) @@ -3936,7 +3946,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a) static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { - uint64_t dest = iaoq_dest(ctx, a->disp); + int64_t disp = a->disp; nullify_over(ctx); @@ -3951,7 +3961,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) * b evil * in which instructions at evil would run with increased privs. */ - if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { return gen_illegal(ctx); } @@ -3969,10 +3979,11 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) } /* No change for non-gateway pages or for priv decrease. */ if (type >= 4 && type - 4 < ctx->privilege) { - dest = deposit64(dest, 0, 2, type - 4); + disp -= ctx->privilege; + disp += type - 4; } } else { - dest &= -4; /* priv = 0 */ + disp -= ctx->privilege; /* priv = 0 */ } #endif @@ -3985,17 +3996,23 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) save_gpr(ctx, a->l, tmp); } - return do_dbranch(ctx, dest - iaoq_dest(ctx, 0), 0, a->n); + return do_dbranch(ctx, disp, 0, a->n); } static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); - tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); + DisasIAQE next = iaqe_incr(&ctx->iaq_f, 8); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + /* The computation here never changes privilege level. */ - return do_ibranch(ctx, tmp, NULL, a->l, false, a->n); + copy_iaoq_entry(ctx, t0, &next); + tcg_gen_shli_i64(t1, load_gpr(ctx, a->x), 3); + tcg_gen_add_i64(t0, t0, t1); + + ctx->iaq_j = iaqe_next_absv(ctx, t0); + return do_ibranch(ctx, a->l, false, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ return do_dbranch(ctx, 0, a->l, a->n); @@ -4014,20 +4031,22 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } dest = do_ibranch_priv(ctx, dest); - return do_ibranch(ctx, dest, NULL, 0, false, a->n); + ctx->iaq_j = iaqe_next_absv(ctx, dest); + + return do_ibranch(ctx, 0, false, a->n); } static bool trans_bve(DisasContext *ctx, arg_bve *a) { TCGv_i64 b = load_gpr(ctx, a->b); - TCGv_i64 dest = do_ibranch_priv(ctx, b); - TCGv_i64 space = NULL; #ifndef CONFIG_USER_ONLY - space = space_select(ctx, 0, b); + ctx->iaq_j.space = space_select(ctx, 0, b); #endif + ctx->iaq_j.base = do_ibranch_priv(ctx, b); + ctx->iaq_j.disp = 0; - return do_ibranch(ctx, dest, space, a->l, false, a->n); + return do_ibranch(ctx, a->l, false, a->n); } static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) @@ -4599,9 +4618,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); ctx->mmu_idx = MMU_USER_IDX; - ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; - ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; - ctx->iasq_b = NULL; + ctx->iaq_f.disp = ctx->base.pc_first | ctx->privilege; + ctx->iaq_b.disp = ctx->base.tb->cs_base | ctx->privilege; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4614,9 +4632,13 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) uint64_t iasq_f = cs_base & ~0xffffffffull; int32_t diff = cs_base; - ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; - ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); - ctx->iasq_b = (diff ? NULL : cpu_iasq_b); + ctx->iaq_f.disp = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + if (diff) { + ctx->iaq_b.disp = ctx->iaq_f.disp + diff; + } else { + ctx->iaq_b.base = cpu_iaoq_b; + ctx->iaq_b.space = cpu_iasq_b; + } #endif ctx->zero = tcg_constant_i64(0); @@ -4644,7 +4666,10 @@ static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b, 0); + tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); + tcg_gen_insn_start(ctx->iaq_f.disp, + iaqe_variable(&ctx->iaq_b) ? -1 : ctx->iaq_b.disp, + 0); ctx->insn_start_updated = false; } @@ -4667,11 +4692,12 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) the page permissions for execute. */ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); - /* Set up the IA queue for the next insn. - This will be overwritten by a branch. */ - ctx->iasq_n = NULL; - ctx->iaoq_n_var = NULL; - ctx->iaoq_n = ctx->iaoq_b == -1 ? -1 : ctx->iaoq_b + 4; + /* + * Set up the IA queue for the next insn. + * This will be overwritten by a branch. + */ + ctx->iaq_n = NULL; + memset(&ctx->iaq_j, 0, sizeof(ctx->iaq_j)); if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { ctx->null_cond.c = TCG_COND_NEVER; @@ -4692,7 +4718,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } /* Note this also detects a priority change. */ - if (ctx->iaoq_b != ctx->iaoq_f + 4 || ctx->iasq_b) { + if (iaqe_variable(&ctx->iaq_b) + || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { ctx->base.is_jmp = DISAS_IAQ_N_STALE; return; } @@ -4701,20 +4728,25 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) * Advance the insn queue. * The only exit now is DISAS_TOO_MANY from the translator loop. */ - ctx->iaoq_f = ctx->iaoq_b; - ctx->iaoq_b = ctx->iaoq_n; - if (ctx->iaoq_b == -1) { - if (ctx->iaoq_n_var) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); - } + ctx->iaq_f.disp = ctx->iaq_b.disp; + if (!ctx->iaq_n) { + ctx->iaq_b.disp += 4; + return; } - if (ctx->iasq_n) { - tcg_gen_mov_i64(cpu_iasq_b, ctx->iasq_n); - ctx->iasq_b = cpu_iasq_b; + /* + * If IAQ_Next is variable in any way, we need to copy into the + * IAQ_Back globals, in case the next insn raises an exception. + */ + if (ctx->iaq_n->base) { + copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaq_n); + ctx->iaq_b.base = cpu_iaoq_b; + ctx->iaq_b.disp = 0; + } else { + ctx->iaq_b.disp = ctx->iaq_n->disp; + } + if (ctx->iaq_n->space) { + tcg_gen_mov_i64(cpu_iasq_b, ctx->iaq_n->space); + ctx->iaq_b.space = cpu_iasq_b; } } @@ -4722,43 +4754,29 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasJumpType is_jmp = ctx->base.is_jmp; - uint64_t fi, bi; - TCGv_i64 fv, bv; - TCGv_i64 fs, bs; - /* Assume the insn queue has not been advanced. */ - fi = ctx->iaoq_b; - fv = cpu_iaoq_b; - fs = ctx->iasq_b; - bi = ctx->iaoq_n; - bv = ctx->iaoq_n_var; - bs = ctx->iasq_n; + DisasIAQE *f = &ctx->iaq_b; + DisasIAQE *b = ctx->iaq_n; switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: /* The insn queue has not been advanced. */ - bi = fi; - bv = fv; - bs = fs; - fi = ctx->iaoq_f; - fv = NULL; - fs = NULL; + f = &ctx->iaq_f; + b = &ctx->iaq_b; /* FALLTHRU */ case DISAS_IAQ_N_STALE: - if (fs == NULL - && bs == NULL - && use_goto_tb(ctx, fi, bi) + if (use_goto_tb(ctx, f, b) && (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); - gen_goto_tb(ctx, 0, fi, bi); + gen_goto_tb(ctx, 0, f, b); break; } /* FALLTHRU */ case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, fi, fv, fs, bi, bv, bs); + install_iaq_entries(ctx, f, b); nullify_save(ctx); if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); @@ -4814,6 +4832,6 @@ static const TranslatorOps hppa_tr_ops = { void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc) { - DisasContext ctx; + DisasContext ctx = { }; translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base); } From patchwork Mon May 13 07:46:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87661C25B74 for ; Mon, 13 May 2024 07:49:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QQi-0004AO-Tw; Mon, 13 May 2024 03:49:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPI-0002q8-T9 for qemu-devel@nongnu.org; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 18/45] target/hppa: Use displacements in DisasIAQE Date: Mon, 13 May 2024 09:46:50 +0200 Message-Id: <20240513074717.130949-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This is a first step in enabling CF_PCREL, but for now we regenerate the absolute address before writeback. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 43 ++++++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4e2e35f9cc..196297422b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -45,9 +45,9 @@ typedef struct DisasCond { typedef struct DisasIAQE { /* IASQ; may be null for no change from TB. */ TCGv_i64 space; - /* IAOQ base; may be null for immediate absolute address. */ + /* IAOQ base; may be null for relative address. */ TCGv_i64 base; - /* IAOQ addend; absolute immedate address if base is null. */ + /* IAOQ addend; if base is null, relative to ctx->iaoq_first. */ int64_t disp; } DisasIAQE; @@ -60,6 +60,9 @@ typedef struct DisasContext { /* IAQ_Next, for jumps, otherwise null for simple advance. */ DisasIAQE iaq_j, *iaq_n; + /* IAOQ_Front at entry to TB. */ + uint64_t iaoq_first; + DisasCond null_cond; TCGLabel *null_lab; @@ -640,7 +643,7 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, uint64_t mask = gva_offset_mask(ctx->tb_flags); if (src->base == NULL) { - tcg_gen_movi_i64(dest, src->disp & mask); + tcg_gen_movi_i64(dest, (ctx->iaoq_first + src->disp) & mask); } else if (src->disp == 0) { tcg_gen_andi_i64(dest, src->base, mask); } else { @@ -672,12 +675,8 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) { tcg_debug_assert(ctx->null_cond.c == TCG_COND_NEVER); if (link) { - if (ctx->iaq_b.base) { - tcg_gen_addi_i64(cpu_gr[link], ctx->iaq_b.base, - ctx->iaq_b.disp + 4); - } else { - tcg_gen_movi_i64(cpu_gr[link], ctx->iaq_b.disp + 4); - } + DisasIAQE next = iaqe_incr(&ctx->iaq_b, 4); + copy_iaoq_entry(ctx, cpu_gr[link], &next); #ifndef CONFIG_USER_ONLY if (with_sr0) { tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); @@ -730,7 +729,7 @@ static bool use_goto_tb(DisasContext *ctx, const DisasIAQE *f, { return (!iaqe_variable(f) && (b == NULL || !iaqe_variable(b)) && - translator_use_goto_tb(&ctx->base, f->disp)); + translator_use_goto_tb(&ctx->base, ctx->iaoq_first + f->disp)); } /* If the next insn is to be nullified, and it's on the same page, @@ -741,7 +740,8 @@ static bool use_nullify_skip(DisasContext *ctx) { return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) && !iaqe_variable(&ctx->iaq_b) - && is_same_page(&ctx->base, ctx->iaq_b.disp)); + && (((ctx->iaoq_first + ctx->iaq_b.disp) ^ ctx->iaoq_first) + & TARGET_PAGE_MASK) == 0); } static void gen_goto_tb(DisasContext *ctx, int which, @@ -2004,6 +2004,8 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) aforementioned BE. */ static void do_page_zero(DisasContext *ctx) { + assert(ctx->iaq_f.disp == 0); + /* If by some means we get here with PSW[N]=1, that implies that the B,GATE instruction would be skipped, and we'd fault on the next insn within the privileged page. */ @@ -2023,11 +2025,11 @@ static void do_page_zero(DisasContext *ctx) non-sequential instruction execution. Normally the PSW[B] bit detects this by disallowing the B,GATE instruction to execute under such conditions. */ - if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != 4) { goto do_sigill; } - switch (ctx->iaq_f.disp & -4) { + switch (ctx->base.pc_first) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_IMP); ctx->base.is_jmp = DISAS_NORETURN; @@ -4618,8 +4620,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); ctx->mmu_idx = MMU_USER_IDX; - ctx->iaq_f.disp = ctx->base.pc_first | ctx->privilege; - ctx->iaq_b.disp = ctx->base.tb->cs_base | ctx->privilege; + ctx->iaoq_first = ctx->base.pc_first | ctx->privilege; + ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4632,9 +4634,10 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) uint64_t iasq_f = cs_base & ~0xffffffffull; int32_t diff = cs_base; - ctx->iaq_f.disp = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + ctx->iaoq_first = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + if (diff) { - ctx->iaq_b.disp = ctx->iaq_f.disp + diff; + ctx->iaq_b.disp = diff; } else { ctx->iaq_b.base = cpu_iaoq_b; ctx->iaq_b.space = cpu_iasq_b; @@ -4667,9 +4670,9 @@ static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); - tcg_gen_insn_start(ctx->iaq_f.disp, - iaqe_variable(&ctx->iaq_b) ? -1 : ctx->iaq_b.disp, - 0); + tcg_gen_insn_start(ctx->iaoq_first + ctx->iaq_f.disp, + (iaqe_variable(&ctx->iaq_b) ? -1 : + ctx->iaoq_first + ctx->iaq_b.disp), 0); ctx->insn_start_updated = false; } From patchwork Mon May 13 07:46:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2EAB0C25B10 for ; Mon, 13 May 2024 07:50:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPc-00031E-6r; Mon, 13 May 2024 03:47:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPI-0002q9-1e for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:36 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPG-0001N0-3N for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:35 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-41fc5645bb1so30505765e9.1 for ; Mon, 13 May 2024 00:47:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586453; x=1716191253; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fgExMg673JAx2cq5L5XNhe8VfWiBmskFq1MitzRUfrY=; b=TMPO7lsqoLJn4EcjGPKXwK+eqkDFIWwPbc1Q4MwC4vt251XtQ58Wg2i9QsIUxv/VZT QAwTOhrIpzjgUCILWBiLYogpMiNNaFqt3MjWDeQPIBQpO1wOL3k+UXLRIlI0igdvtpmo D5bmo5b5ugOfhh1O4LLsTVQgztS24ohrJiFgk3UlnADQeWMqdt4nNZHiIOLRz8EzDeia ponZTjalW8dhzXnlc1kiOh7T5b5+pW9WJS37HyFl7ugyfEdJYXdXTivB+4uF1YKp4ujX 3T6Jm5/NkDFjGe39vBmtjC0GQnbKYoS731JXd27xwZ9kXQIgK/z3aSObZ5mLhZrH4g8Z uV1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586453; x=1716191253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fgExMg673JAx2cq5L5XNhe8VfWiBmskFq1MitzRUfrY=; b=R8dH01BreP7V0p5DKazWiXeJFaPhwpM9BVCyUdVO/Ban9bWJbZB13XJJvcSr/Y+df7 lP6gWwCeK3kO10yLDM3Rl6oMPmEOHndQOhhrNB87e8Zw6GZb5S82+VlrznLRc0bjOE4j TRv4pjBV4utWnEnXZ5UoGV5Nt2KxAAg3AVQOHDq3Kuby4NvKmuUL9trZyCFG8dbMzDN0 PLjdAKHJLu5gLU59ZdWDXZfoAyibmmjm9rLU10h2muRTnZkZSnQNvHUCKhVGdt3TaF5c ujlG1fIF3Ocpg3Ahzhyr47ZT51bMag8sUvvWmDBq/Ehv8QbNwKlP1E1w0AYZKFvWrfd8 mb2Q== X-Gm-Message-State: AOJu0YwGCfxctxWKTbQ+2os3Zq5HyFOq0ZuRyBLClFRzG4P/YMBCveU1 o45Oz8efe5iC+22ysHBlYyor7DE4RJWaA0jGFvVQ4GVm2AzipUzUsXNrO7vLueqQmQUXb3A8W3I qumk= X-Google-Smtp-Source: AGHT+IGwnpDU2OZy7V9x7Fnoo7ALYTPmXigXTchhdFsqm8lOFYWVlPNsEGP/njDEtXaaljW8IWAPrQ== X-Received: by 2002:a05:600c:4688:b0:420:e63:5b2b with SMTP id 5b1f17b1804b1-4200e635cdbmr45513355e9.18.1715586452679; Mon, 13 May 2024 00:47:32 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 19/45] target/hppa: Rename cond_make_* helpers Date: Mon, 13 May 2024 09:46:51 +0200 Message-Id: <20240513074717.130949-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use 'v' for a variable that needs copying, 't' for a temp that doesn't need copying, and 'i' for an immediate, and use this naming for both arguments of the comparison. So: cond_make_tmp -> cond_make_tt cond_make_0_tmp -> cond_make_ti cond_make_0 -> cond_make_vi cond_make -> cond_make_vv Pass 0 explictly, rather than implicitly in the function name. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 52 ++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 196297422b..5e32d985c9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -345,32 +345,32 @@ static DisasCond cond_make_n(void) }; } -static DisasCond cond_make_tmp(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) +static DisasCond cond_make_tt(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 }; } -static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0) +static DisasCond cond_make_ti(TCGCond c, TCGv_i64 a0, uint64_t imm) { - return cond_make_tmp(c, a0, tcg_constant_i64(0)); + return cond_make_tt(c, a0, tcg_constant_i64(imm)); } -static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0) +static DisasCond cond_make_vi(TCGCond c, TCGv_i64 a0, uint64_t imm) { TCGv_i64 tmp = tcg_temp_new_i64(); tcg_gen_mov_i64(tmp, a0); - return cond_make_0_tmp(c, tmp); + return cond_make_ti(c, tmp, imm); } -static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) +static DisasCond cond_make_vv(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); tcg_gen_mov_i64(t0, a0); tcg_gen_mov_i64(t1, a1); - return cond_make_tmp(c, t0, t1); + return cond_make_tt(c, t0, t1); } static void cond_free(DisasCond *cond) @@ -788,7 +788,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_ext32u_i64(tmp, res); res = tmp; } - cond = cond_make_0(TCG_COND_EQ, res); + cond = cond_make_vi(TCG_COND_EQ, res, 0); break; case 2: /* < / >= (N ^ V / !(N ^ V) */ tmp = tcg_temp_new_i64(); @@ -796,7 +796,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, if (!d) { tcg_gen_ext32s_i64(tmp, tmp); } - cond = cond_make_0_tmp(TCG_COND_LT, tmp); + cond = cond_make_ti(TCG_COND_LT, tmp, 0); break; case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ /* @@ -818,10 +818,10 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_sari_i64(tmp, tmp, 63); tcg_gen_and_i64(tmp, tmp, res); } - cond = cond_make_0_tmp(TCG_COND_EQ, tmp); + cond = cond_make_ti(TCG_COND_EQ, tmp, 0); break; case 4: /* NUV / UV (!UV / UV) */ - cond = cond_make_0(TCG_COND_EQ, uv); + cond = cond_make_vi(TCG_COND_EQ, uv, 0); break; case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */ tmp = tcg_temp_new_i64(); @@ -829,7 +829,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, if (!d) { tcg_gen_ext32u_i64(tmp, tmp); } - cond = cond_make_0_tmp(TCG_COND_EQ, tmp); + cond = cond_make_ti(TCG_COND_EQ, tmp, 0); break; case 6: /* SV / NSV (V / !V) */ if (!d) { @@ -837,12 +837,12 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_ext32s_i64(tmp, sv); sv = tmp; } - cond = cond_make_0(TCG_COND_LT, sv); + cond = cond_make_ti(TCG_COND_LT, sv, 0); break; case 7: /* OD / EV */ tmp = tcg_temp_new_i64(); tcg_gen_andi_i64(tmp, res, 1); - cond = cond_make_0_tmp(TCG_COND_NE, tmp); + cond = cond_make_ti(TCG_COND_NE, tmp, 0); break; default: g_assert_not_reached(); @@ -904,9 +904,9 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_ext32s_i64(t1, in1); tcg_gen_ext32s_i64(t2, in2); } - return cond_make_tmp(tc, t1, t2); + return cond_make_tt(tc, t1, t2); } - return cond_make(tc, in1, in2); + return cond_make_vv(tc, in1, in2); } /* @@ -978,9 +978,9 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, } else { tcg_gen_ext32s_i64(tmp, res); } - return cond_make_0_tmp(tc, tmp); + return cond_make_ti(tc, tmp, 0); } - return cond_make_0(tc, res); + return cond_make_vi(tc, res, 0); } /* Similar, but for shift/extract/deposit conditions. */ @@ -1039,7 +1039,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) tcg_gen_andc_i64(tmp, tmp, res); tcg_gen_andi_i64(tmp, tmp, sgns); - return cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp); + return cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp, 0); } static TCGv_i64 get_carry(DisasContext *ctx, bool d, @@ -1453,7 +1453,7 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } tcg_gen_andi_i64(cb, cb, test_cb); - cond = cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb); + cond = cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb, 0); } if (is_tc) { @@ -3542,7 +3542,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) tcg_gen_shl_i64(tmp, tcg_r, tmp); } - cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); + cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); return do_cbranch(ctx, a->disp, a->n, &cond); } @@ -3559,7 +3559,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) p = a->p | (a->d ? 0 : 32); tcg_gen_shli_i64(tmp, tcg_r, p); - cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); + cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); return do_cbranch(ctx, a->disp, a->n, &cond); } @@ -4363,7 +4363,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) switch (a->c) { case 0: /* simple */ tcg_gen_andi_i64(t, t, 0x4000000); - ctx->null_cond = cond_make_0(TCG_COND_NE, t); + ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); goto done; case 2: /* rej */ inv = true; @@ -4393,16 +4393,16 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) if (inv) { TCGv_i64 c = tcg_constant_i64(mask); tcg_gen_or_i64(t, t, c); - ctx->null_cond = cond_make(TCG_COND_EQ, t, c); + ctx->null_cond = cond_make_tt(TCG_COND_EQ, t, c); } else { tcg_gen_andi_i64(t, t, mask); - ctx->null_cond = cond_make_0(TCG_COND_EQ, t); + ctx->null_cond = cond_make_ti(TCG_COND_EQ, t, 0); } } else { unsigned cbit = (a->y ^ 1) - 1; tcg_gen_extract_i64(t, t, 21 - cbit, 1); - ctx->null_cond = cond_make_0(TCG_COND_NE, t); + ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); } done: From patchwork Mon May 13 07:46:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9755BC25B74 for ; Mon, 13 May 2024 07:52:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QQ6-0003l8-Uw; Mon, 13 May 2024 03:48:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPS-0002uW-7D for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:46 -0400 Received: from mail-lf1-x130.google.com ([2a00:1450:4864:20::130]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPH-0001NN-Kd for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:45 -0400 Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-51f0b6b682fso4225651e87.1 for ; Mon, 13 May 2024 00:47:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586453; x=1716191253; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ytQjG6Gl1mpHlQJot6xkpWtqvAkw0tueQGjZp7W5mw4=; b=l0cNlrTBcqe4hSF4R5C70MVvDl+7d8ZenfkqzLkLCoTG3qKBmUvHWUPtBvQZBNyChA VlWgdJ5jsOaMNJV0wmEnHBlI1zUx+6Rk9RYC5fEnzq11eZREm4LNcHb0HkXd6T/93cLa brztfHzedZZWWTFqiQKlHLrJeQzVqlZxS4/b5V/5Yrbd684/m7h+3/T+p6DfjKqTYNoc k3HKGhgPpSSSwdmwHo5A67fp7IwXNMPPhl8FpanH8GYjbQQduVikFPIWxEeHjLLaGMWg U/Ld4APZB0umr1bftY8j2IWjY1kxmzSVdHFN6q7oujuLhM1AW5qbaHQubV8+ZP9rtqYD N+FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586453; x=1716191253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ytQjG6Gl1mpHlQJot6xkpWtqvAkw0tueQGjZp7W5mw4=; b=FZyPyzvtP7x8RxRLsilcWlqiFDknALcwrqS9LNsMX82fM5su27mhxptetGS8ay/n9A vswaEGRVVPgfnAIV9XKPXxHyZ1Ifnt84pn9OU6M4UqEJU+xBPbPARE+ycCinwDEHPtDT p1XQNvh6hnMKtjzGDXrG82djYlvgCztdZgeJSA5LrwHyb/NXtduI28oNDmNkZGZ+u3d+ U8TaNvHsmGHl1iV5eBV6kB83bfdhsSysR5QsleX1jauucS24SHKhN/eLnplik5al4XPs mR9j1PHfeSwB8Za/FxQy/hawB65loq1kzeuvNhybdwqjc9jhOCX8Zxk06xt+oWf4NhH+ 8+yQ== X-Gm-Message-State: AOJu0YzpyPsnJstqC0OzHqs2VVvwG/QhdpD07E7nqHZpki2l4lKKSG4L bqZByjO8dL9u0dqRSxO8E7rRDP0KGRa6kJSOYT9kterCE6b08Re0acb/+6AoA3g0YbtXIiVjyT5 eOH0= X-Google-Smtp-Source: AGHT+IGjP/C9p/dykiyAYCYmu1H2h8b9AKPb9O1TetmGeTafyVqcVJWNYEoZb0WCE4iR+n62Iwb8Jw== X-Received: by 2002:a05:6512:32ba:b0:521:43b2:3194 with SMTP id 2adb3069b0e04-5220fd7bf83mr8637146e87.41.1715586453445; Mon, 13 May 2024 00:47:33 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 20/45] target/hppa: Use TCG_COND_TST* in do_cond Date: Mon, 13 May 2024 09:46:52 +0200 Message-Id: <20240513074717.130949-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We can directly test bits of a 32-bit comparison without zero or sign-extending an intermediate result. We can directly test bit 0 for odd/even. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 64 ++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 36 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5e32d985c9..421b0df9d4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -775,28 +775,36 @@ static bool cond_need_cb(int c) static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, TCGv_i64 res, TCGv_i64 uv, TCGv_i64 sv) { + TCGCond sign_cond, zero_cond; + uint64_t sign_imm, zero_imm; DisasCond cond; TCGv_i64 tmp; + if (d) { + /* 64-bit condition. */ + sign_imm = 0; + sign_cond = TCG_COND_LT; + zero_imm = 0; + zero_cond = TCG_COND_EQ; + } else { + /* 32-bit condition. */ + sign_imm = 1ull << 31; + sign_cond = TCG_COND_TSTNE; + zero_imm = UINT32_MAX; + zero_cond = TCG_COND_TSTEQ; + } + switch (cf >> 1) { case 0: /* Never / TR (0 / 1) */ cond = cond_make_f(); break; case 1: /* = / <> (Z / !Z) */ - if (!d) { - tmp = tcg_temp_new_i64(); - tcg_gen_ext32u_i64(tmp, res); - res = tmp; - } - cond = cond_make_vi(TCG_COND_EQ, res, 0); + cond = cond_make_vi(zero_cond, res, zero_imm); break; case 2: /* < / >= (N ^ V / !(N ^ V) */ tmp = tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, res, sv); - if (!d) { - tcg_gen_ext32s_i64(tmp, tmp); - } - cond = cond_make_ti(TCG_COND_LT, tmp, 0); + cond = cond_make_ti(sign_cond, tmp, sign_imm); break; case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ /* @@ -804,21 +812,15 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, * (N ^ V) | Z * ((res < 0) ^ (sv < 0)) | !res * ((res ^ sv) < 0) | !res - * (~(res ^ sv) >= 0) | !res - * !(~(res ^ sv) >> 31) | !res - * !(~(res ^ sv) >> 31 & res) + * ((res ^ sv) < 0 ? 1 : !res) + * !((res ^ sv) < 0 ? 0 : res) */ tmp = tcg_temp_new_i64(); - tcg_gen_eqv_i64(tmp, res, sv); - if (!d) { - tcg_gen_sextract_i64(tmp, tmp, 31, 1); - tcg_gen_and_i64(tmp, tmp, res); - tcg_gen_ext32u_i64(tmp, tmp); - } else { - tcg_gen_sari_i64(tmp, tmp, 63); - tcg_gen_and_i64(tmp, tmp, res); - } - cond = cond_make_ti(TCG_COND_EQ, tmp, 0); + tcg_gen_xor_i64(tmp, res, sv); + tcg_gen_movcond_i64(sign_cond, tmp, + tmp, tcg_constant_i64(sign_imm), + ctx->zero, res); + cond = cond_make_ti(zero_cond, tmp, zero_imm); break; case 4: /* NUV / UV (!UV / UV) */ cond = cond_make_vi(TCG_COND_EQ, uv, 0); @@ -826,23 +828,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */ tmp = tcg_temp_new_i64(); tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res); - if (!d) { - tcg_gen_ext32u_i64(tmp, tmp); - } - cond = cond_make_ti(TCG_COND_EQ, tmp, 0); + cond = cond_make_ti(zero_cond, tmp, zero_imm); break; case 6: /* SV / NSV (V / !V) */ - if (!d) { - tmp = tcg_temp_new_i64(); - tcg_gen_ext32s_i64(tmp, sv); - sv = tmp; - } - cond = cond_make_ti(TCG_COND_LT, sv, 0); + cond = cond_make_vi(sign_cond, sv, sign_imm); break; case 7: /* OD / EV */ - tmp = tcg_temp_new_i64(); - tcg_gen_andi_i64(tmp, res, 1); - cond = cond_make_ti(TCG_COND_NE, tmp, 0); + cond = cond_make_vi(TCG_COND_TSTNE, res, 1); break; default: g_assert_not_reached(); From patchwork Mon May 13 07:46:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA38FC25B10 for ; Mon, 13 May 2024 07:52:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QRC-0006Ri-82; Mon, 13 May 2024 03:49:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPR-0002uU-Iw for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:45 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPH-0001Nf-Ku for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:45 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-420180b59b7so2956305e9.0 for ; Mon, 13 May 2024 00:47:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586454; x=1716191254; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hthpAUDZCE7MsS8KK7tEgLctoSvSemW+A0a2D7pgGUw=; b=OR3wn0BRMhmpVe8Uajcned/Y2FWjYVOPCwkhZf+XSdzJkNz4gfCM9gQo8mOIlwWWMO KXjo5Gbd2QRo11btCU8e+6qotrc8n2Qdjhk6r0/MNJ86yKmQaYAGTXiUkT5XSJ7UHRUe wsNH0AtEk+mXackoax8Pdp2KOikRv7q55b2aFeBBJo65TC9U1PzEClgihW+cDbEBb62F HCRmQwtlJuX455xIm/IQWZd1XJRKbKsVI0fFeKDZ5KNkSsMmP9ZZchdCYD5thfbiLKKh XPMSU/wDUOe22p0/zAlNgPfNjGwP5q0uXaCMC0i5OyxRSmpSnj1fC88Zh5NQglYJDTlF Scsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586454; x=1716191254; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hthpAUDZCE7MsS8KK7tEgLctoSvSemW+A0a2D7pgGUw=; b=d7ct5tc/Ljk6ns8IE4mlO+MwMHnCRMmI8LBNXDEsV1V1c7F++spLJ4Wgy6EdAmcMNw Qv1urtMxekzls9K8sJDRJ/yxh5EhMwAoVItcitlFntzk9ydKN7C/L8WUP1o8jiYd9+TB XBF//3BqUHn0AMDdTAkEb3+3BbiU96/FOa+KJsjd4PL0lmJrBHE7qgdaI+fFmtAnNeAv hXOU9M+JC3SHthu4BLcmP+gCKKFx5AXhvvmH7f1TiA8r7jlMFK6jzvC9APicyn8SahxW Smf8pwwwchhbJ7oL8AJkY22lhkbLhLUyhwoz13Fgl6meTOFjvZe9UVUHk/SIvLRwx1sZ KDwQ== X-Gm-Message-State: AOJu0YzOirNms7ZsqMN6e2gWSb/R3PokDMG9rammA63AajGLCnkL3zVR ux7DhKHKtPbpRz+clrW6WGT3RPEMvTQgcqKybjsFO8ObfxdciFgcZpwR3eVS9WDaxZeanWCc1BV LB7Q= X-Google-Smtp-Source: AGHT+IGEGOuoK8fKBF7O+5EUlYt/cEpwYk3x3JBil3MjSZqr9mfk5PcG6nIzjzYkTBzqgFxMJ9JRGg== X-Received: by 2002:a05:600c:450e:b0:41e:c9ad:c729 with SMTP id 5b1f17b1804b1-41feac59d29mr66574075e9.28.1715586454192; Mon, 13 May 2024 00:47:34 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 21/45] target/hppa: Use TCG_COND_TST* in do_log_cond Date: Mon, 13 May 2024 09:46:53 +0200 Message-Id: <20240513074717.130949-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We can directly test bits of a 32-bit comparison without zero or sign-extending an intermediate result. We can directly test bit 0 for odd/even. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 78 ++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 51 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 421b0df9d4..e4e8034c5f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -914,65 +914,41 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, TCGv_i64 res) { TCGCond tc; - bool ext_uns; + uint64_t imm; - switch (cf) { - case 0: /* never */ - case 9: /* undef, C */ - case 11: /* undef, C & !Z */ - case 12: /* undef, V */ - return cond_make_f(); - - case 1: /* true */ - case 8: /* undef, !C */ - case 10: /* undef, !C | Z */ - case 13: /* undef, !V */ - return cond_make_t(); - - case 2: /* == */ - tc = TCG_COND_EQ; - ext_uns = true; + switch (cf >> 1) { + case 0: /* never / always */ + case 4: /* undef, C */ + case 5: /* undef, C & !Z */ + case 6: /* undef, V */ + return cf & 1 ? cond_make_t() : cond_make_f(); + case 1: /* == / <> */ + tc = d ? TCG_COND_EQ : TCG_COND_TSTEQ; + imm = d ? 0 : UINT32_MAX; break; - case 3: /* <> */ - tc = TCG_COND_NE; - ext_uns = true; + case 2: /* < / >= */ + tc = d ? TCG_COND_LT : TCG_COND_TSTNE; + imm = d ? 0 : 1ull << 31; break; - case 4: /* < */ - tc = TCG_COND_LT; - ext_uns = false; + case 3: /* <= / > */ + tc = cf & 1 ? TCG_COND_GT : TCG_COND_LE; + if (!d) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_ext32s_i64(tmp, res); + return cond_make_ti(tc, tmp, 0); + } + return cond_make_vi(tc, res, 0); + case 7: /* OD / EV */ + tc = TCG_COND_TSTNE; + imm = 1; break; - case 5: /* >= */ - tc = TCG_COND_GE; - ext_uns = false; - break; - case 6: /* <= */ - tc = TCG_COND_LE; - ext_uns = false; - break; - case 7: /* > */ - tc = TCG_COND_GT; - ext_uns = false; - break; - - case 14: /* OD */ - case 15: /* EV */ - return do_cond(ctx, cf, d, res, NULL, NULL); - default: g_assert_not_reached(); } - - if (!d) { - TCGv_i64 tmp = tcg_temp_new_i64(); - - if (ext_uns) { - tcg_gen_ext32u_i64(tmp, res); - } else { - tcg_gen_ext32s_i64(tmp, res); - } - return cond_make_ti(tc, tmp, 0); + if (cf & 1) { + tc = tcg_invert_cond(tc); } - return cond_make_vi(tc, res, 0); + return cond_make_vi(tc, res, imm); } /* Similar, but for shift/extract/deposit conditions. */ From patchwork Mon May 13 07:46:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10350C25B79 for ; Mon, 13 May 2024 07:53:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPW-0002wq-94; Mon, 13 May 2024 03:47:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPJ-0002qj-Rm for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:37 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPI-0001No-BU for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:37 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4200ee78f34so13124005e9.3 for ; Mon, 13 May 2024 00:47:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586455; x=1716191255; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OH/TFNVOaT2AXYWTY9lqS1dHX1CKyczy6W2/79bycMU=; b=GFfBhUOYkHTy6oWD3E4FDZY4oWUHb6ixsCIC1Z3nhSVYMjctYej3f+q3P0ByA0m6/B n+3cplE6eEY/IfcKh/gdghQk8JNCXUvEsbzCh2Zj5Qr0n12mTufbTrGUNyNrvLHSLhFB kXCEdxmo3UB9Fz6nbdljDVq5vV7hi96SVg1pvWp58k8r3lrYELCjKGpIM7322F4FfKSp 9shAi2EhRjtZuptQdIsNVcDkxfiBgb7j5LjAwKbWYOChUzpNCNP2rMAPStsixAKrzuZf dNtGdZbHmtC1eOkcAYZd5EqYykpbX0FMg4x890mSlI6Fb7zOCPM6mg9Hemtd/XsP08mZ cXzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586455; x=1716191255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OH/TFNVOaT2AXYWTY9lqS1dHX1CKyczy6W2/79bycMU=; b=J4Vu/865qbCmRcn8Mn9XJzUBER7TufVqZAdAbZ/jQg/FAL3+G2w+aUaUYoG3kIwWpa vQGCsKb3e98bBNK6idzQ0XL9c8BE/RL8jh9FHCrIj3VQPaluoxA5pLJFVKtr5vNXv3XR YcNxScwySVJyBD1kNJ0XAnX3+VxcYLwlpDcSW31rzkjjr3g1QDVUuQJBXaZGFD0Si/3e o2OKY1moK8N/Lp7cTHfclhtgVZDjec3Afq/26YKualBepvIgCJmmSYQOee++IDAR139G zbNsCMU2qTEjEP39yxfaKuQImd7dH/iDxg8p5d6mYaLg9Q9WD4zyQ8gfiLEYX6jnv3+z jjKw== X-Gm-Message-State: AOJu0Yxl/nSAuN82wHqqUeZ63MPf6IBgazCwqAHZ98Xw0z39c6RgF75O ALkk0+kp8wfUblrUwV6+0wu80Fr8aeGntZ/tj1kNBZhVz8tM/UhTBofcr/dfrDLhhZ6yir25jyJ /wrI= X-Google-Smtp-Source: AGHT+IFaZt1KSKGcjUSfVwFMqTHXF6S2Gan9SuoMvYJj359V6nVeuYC/rdQ+XscfjrkGb3y4psJtew== X-Received: by 2002:a05:600c:1f93:b0:41e:dc7f:e2c with SMTP id 5b1f17b1804b1-41feac59cddmr61732345e9.30.1715586454870; Mon, 13 May 2024 00:47:34 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 22/45] target/hppa: Use TCG_COND_TST* in do_unit_zero_cond Date: Mon, 13 May 2024 09:46:54 +0200 Message-Id: <20240513074717.130949-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e4e8034c5f..50cc6decd8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1005,9 +1005,8 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) tmp = tcg_temp_new_i64(); tcg_gen_subi_i64(tmp, res, ones); tcg_gen_andc_i64(tmp, tmp, res); - tcg_gen_andi_i64(tmp, tmp, sgns); - return cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp, 0); + return cond_make_ti(cf & 1 ? TCG_COND_TSTEQ : TCG_COND_TSTNE, tmp, sgns); } static TCGv_i64 get_carry(DisasContext *ctx, bool d, From patchwork Mon May 13 07:46:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B13CC25B10 for ; Mon, 13 May 2024 07:54:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QQ2-0003eS-KE; Mon, 13 May 2024 03:48:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPL-0002rY-91 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:39 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPJ-0001O3-13 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:39 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-41ff5e3dc3bso17921055e9.1 for ; Mon, 13 May 2024 00:47:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586455; x=1716191255; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Snzaxs9GYAdAfilaaEFzVoEJKRW+Fg+Xd5Y1VwkG6O4=; b=nPShHEw6cgNL4C5djyZmMiKdOe1SQPyRfBuK75OT4Iz5h8eyr3x1LnJXnkRgLumnj8 1fVgDoNyfUs90G2wcgMxS7tqHX/Shd7fkzeTAl4FeqI8r3syHq++Og3bbjTaoKjGXqdu cHVdGfag+ItgsuNAEXBRsREEwV/7t+4PHpTRQs6DqNXqrW+ICbiEcyBkwB4tg3dJcvIP Vu9clJq8tyZfE/p6pprSxnF58x5VfGEKxdjSelEYQfeZDDRtMnfdlsMNloHzIG5JpF6Z Gaw+cnstXCBB6vkHGzQ0hkyMsd3zz5ozsiFNUd/YBb6+vE404ZhxXFoQx36fqmo4gcjx ObwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586455; x=1716191255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Snzaxs9GYAdAfilaaEFzVoEJKRW+Fg+Xd5Y1VwkG6O4=; b=InFAk7vW3n9bjsYtzHY+GY2ArkA+XqrQHh7XdOMetWJexTzXXHK3B0MkzU5yLW/t9b rPhqdanYFAFa7RbqVgQyfQVbB2PKkarnT8b2+x3wdarIFl119MKdtuI+RFFnr23mTwYJ TQVgcZLPG96/gR8NMibT2DJT2LAxlhi2IAUe3clyLCBMeCvwNGGmPftnKVtLS0S8vWzE goKcCgUyfswYNJNB03rc9RJb6xw7VyLww7uGEWUjDIqXOUlIkZfDdWGkipM4a486ZXSh hpiuFVZlAMdW47gADkks7OhVwgc35CpFz6s1QZ6vlWOyzxcFQK30gQJfB89IJllxNYhH xjdg== X-Gm-Message-State: AOJu0YxH3kNrxHnAlE6O6zszHMkeUPUbY7ZFsHa5ZDjn1lgvgFTrTuou 1XY/Y9ajNaZL3kcNrmx+0P55nb8OWH1dEE2PIhnHJkZAA2fVOSV3hV3n22cRFzINap4WHEnYt21 ZJas= X-Google-Smtp-Source: AGHT+IFiU8QG1tB8y2e3AXz5hmb5q0+4nZlXCPlcoRmVvNSTwANdj0WyfA3+5lS1TbeR4jOm6r4L3Q== X-Received: by 2002:a05:600c:4703:b0:41b:85bf:f3a8 with SMTP id 5b1f17b1804b1-41fead65a26mr61950935e9.35.1715586455592; Mon, 13 May 2024 00:47:35 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 23/45] target/hppa: Use TCG_COND_TST* in do_unit_addsub Date: Mon, 13 May 2024 09:46:55 +0200 Message-Id: <20240513074717.130949-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 50cc6decd8..47f4b23d1b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1419,8 +1419,8 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, tcg_gen_shri_i64(cb, cb, 1); } - tcg_gen_andi_i64(cb, cb, test_cb); - cond = cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb, 0); + cond = cond_make_ti(cf & 1 ? TCG_COND_TSTEQ : TCG_COND_TSTNE, + cb, test_cb); } if (is_tc) { From patchwork Mon May 13 07:46:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663104 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5A02C25B10 for ; Mon, 13 May 2024 07:49:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QQZ-00044x-UZ; Mon, 13 May 2024 03:48:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPM-0002s8-7p for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:41 -0400 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPK-0001OI-70 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:39 -0400 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2e564cad1f1so27617141fa.0 for ; Mon, 13 May 2024 00:47:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586456; x=1716191256; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bGbM1QCCaY0habo7FurSh8Ry2LOjgiLMoIY76d5RmZs=; b=GwM6d7VGKld7qgtHSzt9mLE+XqqXtmwM03laBUqFTelr3fx76C4QjmZn0dYD5e41tt h3Lfcxi3S66NKH7Ng+446ccd94g7TqJXFXuAIfv6iINiwWrTm8jYj5HdC96ffooE3ACW OJ/6VfzfHKsDPwrkTV6rt9QdcccbxsTaEvKRwwKVEFxxvzLCRHYTlNubpCk2Tf3WHMk9 EBJcGSbc/ouGaWHqvXx6U0Uy7UiPjZSc4vTVsNJp9ZZdVFBt9c7TijtrwVOPviQZX7wj EbE+clMHH6b/ok99QRPDzEZNx95/zljn5KoqPRBqTOJ/nEXQ7rGtuI/1CJYJXnz/Jxjy 1a/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586456; x=1716191256; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bGbM1QCCaY0habo7FurSh8Ry2LOjgiLMoIY76d5RmZs=; b=CzS2FIw5OfXv/eU/5DFBuqLBy0k6exZVPEN0jGe6mX782iAMl0PxSDZlcgtvcADKCr ijnK81MTHWy74kB2Ow0KQVK0PHPqXy8W8fxrP7COGkhImd/lw2nqo29Apizathxtjt+B xHHEKL59vhtJ6nKGpRpvJeKKhglBuI4q3SwWWiU7+64F6ZWbcqxqFXytX7gbadJDV5e7 4kDADm9b4Y19QAhy4+6fJL7s0hbedTsD81uAY5vsQTt0txRw8yraiGVGP25R45nmTch6 ISdJv8pk/abDxvvxhKSCGwP0GqTb5CMF2gJXMzSrGMpeBEaOwshG4q7BhQs4IPhVrtyY zWzQ== X-Gm-Message-State: AOJu0Ywl+foV+bcz+cBqUPScD9a0NQ9WFPc7UJ4kjsIBQvsqgD2yEa8a T07vNP7+FRcsynlsYnZ2uF0RhLHuvkRj1dIRrTPJfyoa5izlGanW+SGdfzidCthUIaFdJ5eN2Z5 2o5o= X-Google-Smtp-Source: AGHT+IEawTTXsIyuqmsOku9Y5c3IBsS0twtuhnLrHfPN8lJ1/VilS9m1BsZXXU6Wmdo7J278KWLZVw== X-Received: by 2002:a05:6512:1086:b0:51c:d528:c333 with SMTP id 2adb3069b0e04-5220fc7d748mr6546336e87.20.1715586456335; Mon, 13 May 2024 00:47:36 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 24/45] target/hppa: Use TCG_COND_TST* in trans_bb_imm Date: Mon, 13 May 2024 09:46:56 +0200 Message-Id: <20240513074717.130949-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 47f4b23d1b..d8973a63df 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3515,18 +3515,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) { - TCGv_i64 tmp, tcg_r; DisasCond cond; - int p; + int p = a->p | (a->d ? 0 : 32); nullify_over(ctx); - - tmp = tcg_temp_new_i64(); - tcg_r = load_gpr(ctx, a->r); - p = a->p | (a->d ? 0 : 32); - tcg_gen_shli_i64(tmp, tcg_r, p); - - cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); + cond = cond_make_vi(a->c ? TCG_COND_TSTEQ : TCG_COND_TSTNE, + load_gpr(ctx, a->r), 1ull << (63 - p)); return do_cbranch(ctx, a->disp, a->n, &cond); } From patchwork Mon May 13 07:46:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB318C25B10 for ; Mon, 13 May 2024 07:49:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QPq-0003IL-6V; Mon, 13 May 2024 03:48:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPM-0002sA-N3 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:41 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPK-0001ON-Lc for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:40 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-41fd5dc0439so26311265e9.0 for ; Mon, 13 May 2024 00:47:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586457; x=1716191257; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vj4vKOTbtwnEGSvKqqssxojACH8Pv7r+GeQwKBQHsiQ=; b=qL9XrbAgivfwHmyewXY42brK1GxBsILQfBmOaLz8riTdWprPycOi+CxzXzRlot6jCb YWzH7fILJOXsyw+ZT2fFg0d/FYfsFkI6QwSNvq6APqK0KOUW8lVRefy+HFZn45X4ecBp 7R7jKsP948GCEaEdlTSmehZZ6w1nIioCaeu4HhNfszM4+MgNXOdUyi0qCdE0fpqmAIAR ILFDerqUlgq+3EYKRNco9T3FLnZWMLnCC92YW8t+HxX14A9OPuh+ejpgZwHPSHurBepb GLKeES5PEboiN9Z4UeayoM+jOQJoeNuwKeRP50+n6SZ7I2zEjFxJ4CoupVvkSkivq7Sk wbCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586457; x=1716191257; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vj4vKOTbtwnEGSvKqqssxojACH8Pv7r+GeQwKBQHsiQ=; b=h2DMhQGlPSwgAS4csAnBcnJgYTYQtpXDdfQLuyq3YqfcfsRJuNl4E55amMH0vCuP76 rLbtLX3VbUkrZx+W3JJ6eM8hBY5vhY9nSL8WThkaWV3ZPD3Y7uVwghHRZYvk4+XFdiPH Uwxd6yqUXuq7xOJhv7U0Z/oRt3jxeAO3INAXAmDfRr47dsI3Us1a7YIVFDm5oNmJHN2U 9TmmbkZm5vbbqE+KFMfY9CM5zno7hGd1jKPpdPjwfjUegG0dRZcW5hv45RP8bLCR0qjn gvZxisEyln2n3B60Hk60uj+9Gh60OsmGnW8jfG127xHyUwtCAy1KvEgcuaFa3THVnHAi yeug== X-Gm-Message-State: AOJu0YzhdPTsP9r7cqq9PLDQyWRpWaihtfyvspqPdY8AFHKSTUJLPd/b cXbjJkrTlfgPqQ2KBi2X095ured2VEPB3YWX/eQ+I8fg1RhsFHnatYyGK0VRchFSNi68Ztnfe8E f+Kc= X-Google-Smtp-Source: AGHT+IFvO7BKo2zazfBjj5pVAhMrRJo0A8RE++TqzVQRJkXLPxzkeiGgBFM+yRxxOhUEWae4yOHl0w== X-Received: by 2002:a05:600c:4f42:b0:419:f241:632f with SMTP id 5b1f17b1804b1-41feac49273mr72853815e9.31.1715586457059; Mon, 13 May 2024 00:47:37 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 25/45] target/hppa: Use registerfields.h for FPSR Date: Mon, 13 May 2024 09:46:57 +0200 Message-Id: <20240513074717.130949-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Define all of the context dependent field definitions. Use FIELD_EX32 and FIELD_DP32 with named fields instead of extract32 and deposit32 with raw constants. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 25 +++++++++++++++++++++++++ target/hppa/fpu_helper.c | 26 +++++++++++++------------- target/hppa/translate.c | 18 ++++++++---------- 3 files changed, 46 insertions(+), 23 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 61f1353133..c37b4e12fb 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -24,6 +24,7 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" #include "qemu/interval-tree.h" +#include "hw/registerfields.h" #define MMU_ABS_W_IDX 6 #define MMU_ABS_IDX 7 @@ -152,6 +153,30 @@ #define CR_IPSW 22 #define CR_EIRR 23 +FIELD(FPSR, ENA_I, 0, 1) +FIELD(FPSR, ENA_U, 1, 1) +FIELD(FPSR, ENA_O, 2, 1) +FIELD(FPSR, ENA_Z, 3, 1) +FIELD(FPSR, ENA_V, 4, 1) +FIELD(FPSR, ENABLES, 0, 5) +FIELD(FPSR, D, 5, 1) +FIELD(FPSR, T, 6, 1) +FIELD(FPSR, RM, 9, 2) +FIELD(FPSR, CQ, 11, 11) +FIELD(FPSR, CQ0_6, 15, 7) +FIELD(FPSR, CQ0_4, 17, 5) +FIELD(FPSR, CQ0_2, 19, 3) +FIELD(FPSR, CQ0, 21, 1) +FIELD(FPSR, CA, 15, 7) +FIELD(FPSR, CA0, 21, 1) +FIELD(FPSR, C, 26, 1) +FIELD(FPSR, FLG_I, 27, 1) +FIELD(FPSR, FLG_U, 28, 1) +FIELD(FPSR, FLG_O, 29, 1) +FIELD(FPSR, FLG_Z, 30, 1) +FIELD(FPSR, FLG_V, 31, 1) +FIELD(FPSR, FLAGS, 27, 5) + typedef struct HPPATLBEntry { union { IntervalTreeNode itree; diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 576f283b04..deaed2b65d 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -30,7 +30,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) env->fr0_shadow = shadow; - switch (extract32(shadow, 9, 2)) { + switch (FIELD_EX32(shadow, FPSR, RM)) { default: rm = float_round_nearest_even; break; @@ -46,7 +46,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) } set_float_rounding_mode(rm, &env->fp_status); - d = extract32(shadow, 5, 1); + d = FIELD_EX32(shadow, FPSR, D); set_flush_to_zero(d, &env->fp_status); set_flush_inputs_to_zero(d, &env->fp_status); } @@ -57,7 +57,7 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env) } #define CONVERT_BIT(X, SRC, DST) \ - ((SRC) > (DST) \ + ((unsigned)(SRC) > (unsigned)(DST) \ ? (X) / ((SRC) / (DST)) & (DST) \ : ((X) & (SRC)) * ((DST) / (SRC))) @@ -73,12 +73,12 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) } set_float_exception_flags(0, &env->fp_status); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact, 1u << 0); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, 1u << 1); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow, 1u << 2); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, 1u << 3); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid, 1u << 4); - shadow |= hard_exp << (32 - 5); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact, R_FPSR_ENA_I_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, R_FPSR_ENA_U_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow, R_FPSR_ENA_O_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, R_FPSR_ENA_Z_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid, R_FPSR_ENA_V_MASK); + shadow |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); env->fr0_shadow = shadow; env->fr[0] = (uint64_t)shadow << 32; @@ -378,15 +378,15 @@ static void update_fr0_cmp(CPUHPPAState *env, uint32_t y, if (y) { /* targeted comparison */ /* set fpsr[ca[y - 1]] to current compare */ - shadow = deposit32(shadow, 21 - (y - 1), 1, c); + shadow = deposit32(shadow, R_FPSR_CA0_SHIFT - (y - 1), 1, c); } else { /* queued comparison */ /* shift cq right by one place */ - shadow = deposit32(shadow, 11, 10, extract32(shadow, 12, 10)); + shadow = (shadow & ~R_FPSR_CQ_MASK) | ((shadow >> 1) & R_FPSR_CQ_MASK); /* move fpsr[c] to fpsr[cq[0]] */ - shadow = deposit32(shadow, 21, 1, extract32(shadow, 26, 1)); + shadow = FIELD_DP32(shadow, FPSR, CQ0, FIELD_EX32(shadow, FPSR, C)); /* set fpsr[c] to current compare */ - shadow = deposit32(shadow, 26, 1, c); + shadow = FIELD_DP32(shadow, FPSR, C, c); } env->fr0_shadow = shadow; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d8973a63df..6d76599ea0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4323,29 +4323,28 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) switch (a->c) { case 0: /* simple */ - tcg_gen_andi_i64(t, t, 0x4000000); - ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); - goto done; + mask = R_FPSR_C_MASK; + break; case 2: /* rej */ inv = true; /* fallthru */ case 1: /* acc */ - mask = 0x43ff800; + mask = R_FPSR_C_MASK | R_FPSR_CQ_MASK; break; case 6: /* rej8 */ inv = true; /* fallthru */ case 5: /* acc8 */ - mask = 0x43f8000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_6_MASK; break; case 9: /* acc6 */ - mask = 0x43e0000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_4_MASK; break; case 13: /* acc4 */ - mask = 0x4380000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_2_MASK; break; case 17: /* acc2 */ - mask = 0x4200000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_MASK; break; default: gen_illegal(ctx); @@ -4362,11 +4361,10 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) } else { unsigned cbit = (a->y ^ 1) - 1; - tcg_gen_extract_i64(t, t, 21 - cbit, 1); + tcg_gen_extract_i64(t, t, R_FPSR_CA0_SHIFT - cbit, 1); ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); } - done: return nullify_end(ctx); } From patchwork Mon May 13 07:46:58 2024 Content-Type: text/plain; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 26/45] target/hppa: Use TCG_COND_TST* in trans_ftest Date: Mon, 13 May 2024 09:46:58 +0200 Message-Id: <20240513074717.130949-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6d76599ea0..ef62cd7e94 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4310,6 +4310,8 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) static bool trans_ftest(DisasContext *ctx, arg_ftest *a) { + TCGCond tc = TCG_COND_TSTNE; + uint32_t mask; TCGv_i64 t; nullify_over(ctx); @@ -4318,21 +4320,18 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); if (a->y == 1) { - int mask; - bool inv = false; - switch (a->c) { case 0: /* simple */ mask = R_FPSR_C_MASK; break; case 2: /* rej */ - inv = true; + tc = TCG_COND_TSTEQ; /* fallthru */ case 1: /* acc */ mask = R_FPSR_C_MASK | R_FPSR_CQ_MASK; break; case 6: /* rej8 */ - inv = true; + tc = TCG_COND_TSTEQ; /* fallthru */ case 5: /* acc8 */ mask = R_FPSR_C_MASK | R_FPSR_CQ0_6_MASK; @@ -4350,21 +4349,12 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) gen_illegal(ctx); return true; } - if (inv) { - TCGv_i64 c = tcg_constant_i64(mask); - tcg_gen_or_i64(t, t, c); - ctx->null_cond = cond_make_tt(TCG_COND_EQ, t, c); - } else { - tcg_gen_andi_i64(t, t, mask); - ctx->null_cond = cond_make_ti(TCG_COND_EQ, t, 0); - } } else { unsigned cbit = (a->y ^ 1) - 1; - - tcg_gen_extract_i64(t, t, R_FPSR_CA0_SHIFT - cbit, 1); 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 27/45] target/hppa: Remove cond_free Date: Mon, 13 May 2024 09:46:59 +0200 Message-Id: <20240513074717.130949-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that we do not need to free tcg temporaries, the only thing cond_free does is reset the condition to never. Instead, simply write a new condition over the old, which may be simply cond_make_f() for the never condition. The do_*_cond functions do the right thing with c or cf == 0, so there's no need for a special case anymore. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 102 +++++++++++----------------------------- 1 file changed, 27 insertions(+), 75 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ef62cd7e94..e06c14dd15 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -373,21 +373,6 @@ static DisasCond cond_make_vv(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) return cond_make_tt(c, t0, t1); } -static void cond_free(DisasCond *cond) -{ - switch (cond->c) { - default: - cond->a0 = NULL; - cond->a1 = NULL; - /* fallthru */ - case TCG_COND_ALWAYS: - cond->c = TCG_COND_NEVER; - break; - case TCG_COND_NEVER: - break; - } -} - static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg) { if (reg == 0) { @@ -537,7 +522,7 @@ static void nullify_over(DisasContext *ctx) tcg_gen_brcond_i64(ctx->null_cond.c, ctx->null_cond.a0, ctx->null_cond.a1, ctx->null_lab); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); } } @@ -555,7 +540,7 @@ static void nullify_save(DisasContext *ctx) ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero = true; } - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); } /* Set a PSW[N] to X. The intention is that this is used immediately @@ -1165,7 +1150,6 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1262,7 +1246,6 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1317,7 +1300,6 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_i64 in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1332,10 +1314,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_i64 in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (cf) { - ctx->null_cond = do_log_cond(ctx, cf, d, dest); - } + ctx->null_cond = do_log_cond(ctx, cf, d, dest); } static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, @@ -1430,7 +1409,6 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } save_gpr(ctx, rt, dest); - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1853,7 +1831,6 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, taken = gen_new_label(); tcg_gen_brcond_i64(c, cond->a0, cond->a1, taken); - cond_free(cond); /* Not taken: Condition not satisfied; nullify on backward branches. */ n = is_n && disp < 0; @@ -2035,7 +2012,7 @@ static void do_page_zero(DisasContext *ctx) static bool trans_nop(DisasContext *ctx, arg_nop *a) { - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2049,7 +2026,7 @@ static bool trans_sync(DisasContext *ctx, arg_sync *a) /* No point in nullifying the memory barrier. */ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2061,7 +2038,7 @@ static bool trans_mfia(DisasContext *ctx, arg_mfia *a) tcg_gen_andi_i64(dest, dest, -4); save_gpr(ctx, a->t, dest); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2076,7 +2053,7 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) save_gpr(ctx, rt, t0); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2121,7 +2098,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) save_gpr(ctx, rt, tmp); done: - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2161,7 +2138,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2235,7 +2212,7 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2252,7 +2229,7 @@ static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) #endif save_gpr(ctx, a->t, dest); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2414,7 +2391,7 @@ static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) tcg_gen_add_i64(dest, src1, src2); save_gpr(ctx, a->b, dest); } - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2656,7 +2633,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) since the entire address space is coherent. */ save_gpr(ctx, a->t, ctx->zero); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2733,7 +2710,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) unsigned rt = a->t; if (rt == 0) { /* NOP */ - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } if (r2 == 0) { /* COPY */ @@ -2744,7 +2721,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) } else { save_gpr(ctx, rt, cpu_gr[r1]); } - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } #ifndef CONFIG_USER_ONLY @@ -2809,11 +2786,7 @@ static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) tcg_gen_xor_i64(dest, tcg_r1, tcg_r2); save_gpr(ctx, a->t, dest); - cond_free(&ctx->null_cond); - if (a->cf) { - ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); - } - + ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); return nullify_end(ctx); } @@ -2839,7 +2812,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) tcg_gen_subi_i64(tmp, tmp, 1); } save_gpr(ctx, a->t, tmp); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3365,7 +3338,7 @@ static bool trans_ldil(DisasContext *ctx, arg_ldil *a) tcg_gen_movi_i64(tcg_rt, a->i); save_gpr(ctx, a->t, tcg_rt); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3376,7 +3349,7 @@ static bool trans_addil(DisasContext *ctx, arg_addil *a) tcg_gen_addi_i64(tcg_r1, tcg_rt, a->i); save_gpr(ctx, 1, tcg_r1); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3392,7 +3365,7 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a) tcg_gen_addi_i64(tcg_rt, cpu_gr[a->b], a->i); } save_gpr(ctx, a->t, tcg_rt); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3618,10 +3591,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3661,10 +3631,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3706,10 +3673,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3742,10 +3706,7 @@ static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3782,10 +3743,7 @@ static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3818,10 +3776,7 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3855,10 +3810,7 @@ static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, save_gpr(ctx, rt, dest); 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 28/45] target/hppa: Introduce DisasDelayException Date: Mon, 13 May 2024 09:47:00 +0200 Message-Id: <20240513074717.130949-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Allow an exception to be emitted at the end of the TranslationBlock, leaving only the conditional branch inline. Use it for simple exception instructions like break, which happen to be nullified. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 60 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 55 insertions(+), 5 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e06c14dd15..e75e7e5b54 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -51,6 +51,17 @@ typedef struct DisasIAQE { int64_t disp; } DisasIAQE; +typedef struct DisasDelayException { + struct DisasDelayException *next; + TCGLabel *lab; + uint32_t insn; + bool set_iir; + int8_t set_n; + uint8_t excp; + /* Saved state at parent insn. */ + DisasIAQE iaq_f, iaq_b; +} DisasDelayException; + typedef struct DisasContext { DisasContextBase base; CPUState *cs; @@ -66,6 +77,7 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; + DisasDelayException *delay_excp_list; TCGv_i64 zero; uint32_t insn; @@ -683,13 +695,38 @@ static void gen_excp(DisasContext *ctx, int exception) ctx->base.is_jmp = DISAS_NORETURN; } +static DisasDelayException *delay_excp(DisasContext *ctx, uint8_t excp) +{ + DisasDelayException *e = tcg_malloc(sizeof(DisasDelayException)); + + memset(e, 0, sizeof(*e)); + e->next = ctx->delay_excp_list; + ctx->delay_excp_list = e; + + e->lab = gen_new_label(); + e->insn = ctx->insn; + e->set_iir = true; + e->set_n = ctx->psw_n_nonzero ? 0 : -1; + e->excp = excp; + e->iaq_f = ctx->iaq_f; + e->iaq_b = ctx->iaq_b; + + return e; +} + static bool gen_excp_iir(DisasContext *ctx, int exc) { - nullify_over(ctx); - tcg_gen_st_i64(tcg_constant_i64(ctx->insn), - tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); - gen_excp(ctx, exc); - return nullify_end(ctx); + if (ctx->null_cond.c == TCG_COND_NEVER) { + tcg_gen_st_i64(tcg_constant_i64(ctx->insn), + tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); + gen_excp(ctx, exc); + } else { + DisasDelayException *e = delay_excp(ctx, exc); + tcg_gen_brcond_i64(tcg_invert_cond(ctx->null_cond.c), + ctx->null_cond.a0, ctx->null_cond.a1, e->lab); + ctx->null_cond = cond_make_f(); + } + return true; } static bool gen_illegal(DisasContext *ctx) @@ -4696,6 +4733,19 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) default: g_assert_not_reached(); } + + for (DisasDelayException *e = ctx->delay_excp_list; e ; e = e->next) { + gen_set_label(e->lab); + if (e->set_n >= 0) { + tcg_gen_movi_i64(cpu_psw_n, e->set_n); + } + if (e->set_iir) { + tcg_gen_st_i64(tcg_constant_i64(e->insn), tcg_env, + offsetof(CPUHPPAState, cr[CR_IIR])); + } + install_iaq_entries(ctx, &e->iaq_f, &e->iaq_b); + gen_excp_1(e->excp); + } } static void hppa_tr_disas_log(const DisasContextBase *dcbase, From patchwork Mon May 13 07:47:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B32BFC25B10 for ; Mon, 13 May 2024 07:53:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QR7-0005mZ-3v; Mon, 13 May 2024 03:49:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPU-0002vg-1J for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:48 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPO-0001PH-9x for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:47 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-41ffad242c8so17045325e9.3 for ; Mon, 13 May 2024 00:47:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586460; x=1716191260; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bJ2zWrxauyBUqiQFnwtq38MnWD5HOgNqg9osnBJC91k=; b=VtCtym0I7ay7cP37UNF0/FRGZutltWTwSu0BjmrhXn4EFLvYDQHoVF0GY22kO0vk2y 6Aqo7a3sQViTqqU4bn5e3fhHta4ZOybE5WF2AaetryvUOeqgbDIKFnDudnpVPZz/lFK3 bqcpUsGHqEf1J1miNyKXIv02jG5C9/Vgg2R1qfzrLpk+bp6UctzScLXYlzY+RssgX1uF K8VOdWJcULKciItVi9vFFQLizZQXnBO0se6QSa7nCl9i+gCEGr96YFvJ5tpS1uc6xMee tzQDgSsc5KabeyGqfcoOwNM8mOXtcB9gBLm8rwziEB9iPRupqmaJLG4ucF0jTEQoiwfB Y7xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586460; x=1716191260; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bJ2zWrxauyBUqiQFnwtq38MnWD5HOgNqg9osnBJC91k=; b=XZfv8sqEPp8/eoyWaeHJt1gefQpnIHFOZ7IN5JkQiWCxQA49caXE2VtbyfFZYM1jU3 ZvLj7OD06Ot3pYfxGEy2ZoWOhdfs3694vZ5WG+0vvr1f09rj2KeLesqkDk5S/c4N6szJ ptfaSQElQKZ7dYL9Kkwsz8LtfBR1LDRU+44u76CmqFBS7CniDtFUCWiTs5gZ2/xf8gOG +k1+823tzIyJodHMpumZ+I3dDsCp0XK5Z1B5Rc0I15Mu13G/0a53vtFLOoHIXuTXlTRS ya9mYZUOEa2kPJgw1h6w1WArAD9fPK4KwCd7gqMCpy/0BpQVzb9vKtc0yNWJxFbdVgym +p2Q== X-Gm-Message-State: AOJu0Yz3kL6+0UKpKGOoMXD/v5jNCmBFfnKPfkApCJ0hJiCbXH8PIsvP PsOV6QqeBx5imbKTeENVmkmGbEUEEHv4931XAGBwY+WRDYHbazsu3wjlx+XwPdCcOFkd32Lsybw /3WY= X-Google-Smtp-Source: AGHT+IFIWZc87eJnq0n3u8ioOBMGooX3YoC4kx7jtwFydWNTyX1YVqrGIQOzgiiDJkHxcHfYph0CqQ== X-Received: by 2002:a05:600c:45c5:b0:41b:935:2492 with SMTP id 5b1f17b1804b1-41fead6443fmr107475565e9.36.1715586459971; Mon, 13 May 2024 00:47:39 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 29/45] target/hppa: Use delay_excp for conditional traps Date: Mon, 13 May 2024 09:47:01 +0200 Message-Id: <20240513074717.130949-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/helper.h | 1 - target/hppa/int_helper.c | 2 +- target/hppa/op_helper.c | 7 ------- target/hppa/translate.c | 41 ++++++++++++++++++++++++++++++---------- 4 files changed, 32 insertions(+), 19 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 5900fd70bc..3d0d143aed 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,6 +1,5 @@ DEF_HELPER_2(excp, noreturn, env, int) DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index a667ee380d..1aa3e88ef1 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -134,13 +134,13 @@ void hppa_cpu_do_interrupt(CPUState *cs) switch (i) { case EXCP_ILL: case EXCP_BREAK: + case EXCP_COND: case EXCP_PRIV_REG: case EXCP_PRIV_OPR: /* IIR set via translate.c. */ break; case EXCP_OVERFLOW: - case EXCP_COND: case EXCP_ASSIST: case EXCP_DTLB_MISS: case EXCP_NA_ITLB_MISS: diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 6cf49f33b7..a8b69fd481 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -49,13 +49,6 @@ void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) } } -void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) -{ - if (unlikely(cond)) { - hppa_dynamic_excp(env, EXCP_COND, GETPC()); - } -} - static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e75e7e5b54..7fa0c86a8f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1116,6 +1116,25 @@ static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, return sv; } +static void gen_tc(DisasContext *ctx, DisasCond *cond) +{ + DisasDelayException *e; + + switch (cond->c) { + case TCG_COND_NEVER: + break; + case TCG_COND_ALWAYS: + gen_excp_iir(ctx, EXCP_COND); + break; + default: + e = delay_excp(ctx, EXCP_COND); + tcg_gen_brcond_i64(cond->c, cond->a0, cond->a1, e->lab); + /* In the non-trap path, the condition is known false. */ + *cond = cond_make_f(); + break; + } +} + static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) @@ -1174,9 +1193,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, /* Emit any conditional trap before any writeback. */ cond = do_cond(ctx, cf, d, dest, uv, sv); if (is_tc) { - tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + gen_tc(ctx, &cond); } /* Write back the result. */ @@ -1195,6 +1212,10 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, { TCGv_i64 tcg_r1, tcg_r2; + if (unlikely(is_tc && a->cf == 1)) { + /* Unconditional trap on condition. */ + return gen_excp_iir(ctx, EXCP_COND); + } if (a->cf) { nullify_over(ctx); } @@ -1210,6 +1231,10 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, { TCGv_i64 tcg_im, tcg_r2; + if (unlikely(is_tc && a->cf == 1)) { + /* Unconditional trap on condition. */ + return gen_excp_iir(ctx, EXCP_COND); + } if (a->cf) { nullify_over(ctx); } @@ -1224,7 +1249,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, TCGv_i64 in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf, bool d) { - TCGv_i64 dest, sv, cb, cb_msb, tmp; + TCGv_i64 dest, sv, cb, cb_msb; unsigned c = cf >> 1; DisasCond cond; @@ -1272,9 +1297,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, /* Emit any conditional trap before any writeback. */ if (is_tc) { - tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + gen_tc(ctx, &cond); } /* Write back the result. */ @@ -1440,9 +1463,7 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } if (is_tc) { - TCGv_i64 tmp = tcg_temp_new_i64(); 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 30/45] target/hppa: Use delay_excp for conditional trap on overflow Date: Mon, 13 May 2024 09:47:02 +0200 Message-Id: <20240513074717.130949-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/helper.h | 1 - target/hppa/int_helper.c | 2 +- target/hppa/op_helper.c | 7 ------- target/hppa/translate.c | 21 +++++++++++++-------- 4 files changed, 14 insertions(+), 17 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 3d0d143aed..c12b48a04a 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_2(excp, noreturn, env, int) -DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 1aa3e88ef1..97e5f0b9a7 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -134,13 +134,13 @@ void hppa_cpu_do_interrupt(CPUState *cs) switch (i) { case EXCP_ILL: case EXCP_BREAK: + case EXCP_OVERFLOW: case EXCP_COND: case EXCP_PRIV_REG: case EXCP_PRIV_OPR: /* IIR set via translate.c. */ break; - case EXCP_OVERFLOW: case EXCP_ASSIST: case EXCP_DTLB_MISS: case EXCP_NA_ITLB_MISS: diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a8b69fd481..66cad78a57 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -42,13 +42,6 @@ G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra) cpu_loop_exit_restore(cs, ra); } -void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) -{ - if (unlikely((target_long)cond < 0)) { - hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC()); - } -} - static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7fa0c86a8f..d061b30191 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1135,6 +1135,17 @@ static void gen_tc(DisasContext *ctx, DisasCond *cond) } } +static void gen_tsv(DisasContext *ctx, TCGv_i64 *sv, bool d) +{ + DisasCond cond = do_cond(ctx, /* SV */ 12, d, NULL, NULL, *sv); + DisasDelayException *e = delay_excp(ctx, EXCP_OVERFLOW); + + tcg_gen_brcond_i64(cond.c, cond.a0, cond.a1, e->lab); + + /* In the non-trap path, V is known zero. */ + *sv = tcg_constant_i64(0); +} + static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) @@ -1177,10 +1188,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, if (is_tsv || cond_need_sv(c)) { sv = do_add_sv(ctx, dest, in1, in2, orig_in1, shift, d); if (is_tsv) { - if (!d) { - tcg_gen_ext32s_i64(sv, sv); - } - gen_helper_tsv(tcg_env, sv); + gen_tsv(ctx, &sv, d); } } @@ -1281,10 +1289,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_sub_sv(ctx, dest, in1, in2); if (is_tsv) { - if (!d) { - tcg_gen_ext32s_i64(sv, sv); - } - gen_helper_tsv(tcg_env, sv); + gen_tsv(ctx, &sv, d); } } From patchwork Mon May 13 07:47:03 2024 Content-Type: text/plain; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 31/45] linux-user/hppa: Force all code addresses to PRIV_USER Date: Mon, 13 May 2024 09:47:03 +0200 Message-Id: <20240513074717.130949-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The kernel does this along the return path to user mode. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- linux-user/hppa/target_cpu.h | 4 ++-- target/hppa/cpu.h | 3 +++ linux-user/elfload.c | 4 ++-- linux-user/hppa/cpu_loop.c | 14 +++++++------- linux-user/hppa/signal.c | 6 ++++-- target/hppa/cpu.c | 7 +++++-- target/hppa/gdbstub.c | 6 ++++++ target/hppa/translate.c | 4 ++-- 8 files changed, 31 insertions(+), 17 deletions(-) diff --git a/linux-user/hppa/target_cpu.h b/linux-user/hppa/target_cpu.h index aacf3e9e02..4b84422a90 100644 --- a/linux-user/hppa/target_cpu.h +++ b/linux-user/hppa/target_cpu.h @@ -28,8 +28,8 @@ static inline void cpu_clone_regs_child(CPUHPPAState *env, target_ulong newsp, /* Indicate child in return value. */ env->gr[28] = 0; /* Return from the syscall. */ - env->iaoq_f = env->gr[31]; - env->iaoq_b = env->gr[31] + 4; + env->iaoq_f = env->gr[31] | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; } static inline void cpu_clone_regs_parent(CPUHPPAState *env, unsigned flags) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c37b4e12fb..5a1e720bb6 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -42,6 +42,9 @@ #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) +#define PRIV_KERNEL 0 +#define PRIV_USER 3 + #define TARGET_INSN_START_EXTRA_WORDS 2 /* No need to flush MMU_ABS*_IDX */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b473cda6b4..c1e1511ff2 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1887,8 +1887,8 @@ static inline void init_thread(struct target_pt_regs *regs, static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) { - regs->iaoq[0] = infop->entry; - regs->iaoq[1] = infop->entry + 4; + regs->iaoq[0] = infop->entry | PRIV_USER; + regs->iaoq[1] = regs->iaoq[0] + 4; regs->gr[23] = 0; regs->gr[24] = infop->argv; regs->gr[25] = infop->argc; diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index d5232f37fe..bc093b8fe8 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -129,8 +129,8 @@ void cpu_loop(CPUHPPAState *env) default: env->gr[28] = ret; /* We arrived here by faking the gateway page. Return. */ - env->iaoq_f = env->gr[31]; - env->iaoq_b = env->gr[31] + 4; + env->iaoq_f = env->gr[31] | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; break; case -QEMU_ERESTARTSYS: case -QEMU_ESIGRETURN: @@ -140,8 +140,8 @@ void cpu_loop(CPUHPPAState *env) case EXCP_SYSCALL_LWS: env->gr[21] = hppa_lws(env); /* We arrived here by faking the gateway page. Return. */ - env->iaoq_f = env->gr[31]; - env->iaoq_b = env->gr[31] + 4; + env->iaoq_f = env->gr[31] | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; break; case EXCP_IMP: force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->iaoq_f); @@ -152,9 +152,9 @@ void cpu_loop(CPUHPPAState *env) case EXCP_PRIV_OPR: /* check for glibc ABORT_INSTRUCTION "iitlbp %r0,(%sr0, %r0)" */ if (env->cr[CR_IIR] == 0x04000000) { - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f); } else { - force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f); } break; case EXCP_PRIV_REG: @@ -170,7 +170,7 @@ void cpu_loop(CPUHPPAState *env) force_sig_fault(TARGET_SIGFPE, 0, env->iaoq_f); break; case EXCP_BREAK: - force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f & ~3); + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f); break; case EXCP_DEBUG: force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f); diff --git a/linux-user/hppa/signal.c b/linux-user/hppa/signal.c index 682ba25922..f6f094c960 100644 --- a/linux-user/hppa/signal.c +++ b/linux-user/hppa/signal.c @@ -101,7 +101,9 @@ static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc) cpu_hppa_loaded_fr0(env); __get_user(env->iaoq_f, &sc->sc_iaoq[0]); + env->iaoq_f |= PRIV_USER; __get_user(env->iaoq_b, &sc->sc_iaoq[1]); + env->iaoq_b |= PRIV_USER; __get_user(env->cr[CR_SAR], &sc->sc_sar); } @@ -162,8 +164,8 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, unlock_user(fdesc, haddr, 0); haddr = dest; } - env->iaoq_f = haddr; - env->iaoq_b = haddr + 4; + env->iaoq_f = haddr | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; env->psw_n = 0; return; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index be8c558014..a007de5521 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -32,6 +32,9 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu = HPPA_CPU(cs); +#ifdef CONFIG_USER_ONLY + value |= PRIV_USER; +#endif cpu->env.iaoq_f = value; cpu->env.iaoq_b = value + 4; } @@ -93,8 +96,8 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); #ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f = tb->pc; - cpu->env.iaoq_b = tb->cs_base; + cpu->env.iaoq_f = tb->pc | PRIV_USER; + cpu->env.iaoq_b = tb->cs_base | PRIV_USER; #else /* Recover the IAOQ values from the GVA + PRIV. */ uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 4a965b38d7..0daa52f7af 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -163,12 +163,18 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31); break; case 33: +#ifdef CONFIG_USER_ONLY + val |= PRIV_USER; +#endif env->iaoq_f = val; break; case 34: env->iasq_f = (uint64_t)val << 32; break; case 35: +#ifdef CONFIG_USER_ONLY + val |= PRIV_USER; +#endif env->iaoq_b = val; break; case 36: diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d061b30191..aad5323a53 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2053,7 +2053,7 @@ static void do_page_zero(DisasContext *ctx) tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); - tcg_gen_ori_i64(next.base, cpu_gr[31], 3); + tcg_gen_ori_i64(next.base, cpu_gr[31], PRIV_USER); install_iaq_entries(ctx, &next, NULL); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; } @@ -4582,7 +4582,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); #ifdef CONFIG_USER_ONLY - ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); + ctx->privilege = PRIV_USER; ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_first = ctx->base.pc_first | ctx->privilege; ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first; From patchwork Mon May 13 07:47:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B708C25B10 for ; Mon, 13 May 2024 07:50:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QR8-00062q-OE; Mon, 13 May 2024 03:49:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPU-0002wS-AQ for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:48 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPP-0001Pn-S3 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:48 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-420180b5897so2669745e9.3 for ; Mon, 13 May 2024 00:47:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586462; x=1716191262; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p6q1brGiaM7JKUk74R+0kS4pUgiSskJRKzJ4QnaV9A0=; b=AXHlXLproRTEH+3UGGzfHfGdp0/UmNVJ6GNBU2uoZFz7oGSz6ULG0/NA5IBZ56j/VF ru29WumqMH2Oqzfjs89q1Je/ZUdzruo3mf5K7G/4pVfolSSUaSSNv0Tbwz6POJiRBTtF JvTYeM0d1cgcQ8sh+84AaaiWx7YAURN16jFFDBK3p8DU8TAU4O8nemP7b6gXq6KtiLF9 BcVMuZ2EztgDint53YRDeSCXP/nfpxPIhhOkpW+D4hYmDO1h6NClYhTfTWgtp8KV/W1w LA5oREET8+r/NYlAFWihZnFkySPbEjwb+Q+9SryRoPJlI8vjIiFIMxt9Dzq31S2KMGE8 cVOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586462; x=1716191262; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p6q1brGiaM7JKUk74R+0kS4pUgiSskJRKzJ4QnaV9A0=; b=DelDKcTh6cHkd9k+AUPKKHBkdX2Ojz3onD/Ud6MCPouTktMsWpDWJMAcPD8ObqKt4S s7v/dkYwnpkNzd3FBIQ5fqi6axXTyKSylTH7TvRd0yb4K2MRri5WXH082Pnj8tYrizy/ 1TA4bPHawjPpLtTiN4+clOmASNkvGqm1XSJo4OR2Q6fomnp6xp3//WRV9GUY1ZxC6zwl V8EeTV4VqjeNOlx+O7p91I/dck9JiVC+VpxCDj0EMvTO4x3EDVfUo2NF0Y0c2EE+VMHe tsZNtWXGcJ1QJgzHPfpV5ImrAGyB23bneqf4nMRmGut/DI7anqgLUeSfdlmug8N5KJHA dqqA== X-Gm-Message-State: AOJu0Yze9+y9JT0mFpcbFz5Z+P9wmdjG1utZAPY5xyLxfkWQtSWTD/ee z6gvtdgBsTBEF6efzbu09/3FPKbApk4ai0EirivlHS1ZhMaztgwbJcFKc9diI4wr4eXghg19PRd DH7k= X-Google-Smtp-Source: AGHT+IFK1501WAGmdx22Fj1xDOZZijUpnuMEoUc2voOLw3XZd7RmKhtuWqb5xw6QeUsosi/HvP4BzA== X-Received: by 2002:a05:600c:434a:b0:41b:e55c:8e14 with SMTP id 5b1f17b1804b1-41feaa38a5cmr67251155e9.14.1715586462080; Mon, 13 May 2024 00:47:42 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 32/45] target/hppa: Store full iaoq_f and page offset of iaoq_b in TB Date: Mon, 13 May 2024 09:47:04 +0200 Message-Id: <20240513074717.130949-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation for CF_PCREL. store the iaoq_f in 3 parts: high bits in cs_base, middle bits in pc, and low bits in priv. For iaoq_b, set a bit for either of space or page differing, else the page offset. Install iaq entries before goto_tb. The change to not record the full direct branch difference in TB means that we have to store at least iaoq_b before goto_tb. But we since we'll need both updated before goto_tb for CF_PCREL, do that now. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 2 ++ target/hppa/cpu.c | 72 ++++++++++++++++++----------------------- target/hppa/translate.c | 29 +++++++++-------- 3 files changed, 48 insertions(+), 55 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 5a1e720bb6..1232a4cef2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -341,6 +341,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 +#define CS_BASE_DIFFPAGE (1 << 12) +#define CS_BASE_DIFFSPACE (1 << 13) void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index a007de5521..003af63e20 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -48,36 +48,43 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) } void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) + uint64_t *pcsbase, uint32_t *pflags) { uint32_t flags = env->psw_n * PSW_N; + uint64_t cs_base = 0; + + /* + * TB lookup assumes that PC contains the complete virtual address. + * If we leave space+offset separate, we'll get ITLB misses to an + * incomplete virtual address. This also means that we must separate + * out current cpu privilege from the low bits of IAOQ_F. + */ + *pc = hppa_cpu_get_pc(env_cpu(env)); + flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + if (hppa_is_pa20(env)) { + cs_base = env->iaoq_f & MAKE_64BIT_MASK(32, 32); + } + + /* + * The only really interesting case is if IAQ_Back is on the same page + * as IAQ_Front, so that we can use goto_tb between the blocks. In all + * other cases, we'll be ending the TranslationBlock with one insn and + * not linking between them. + */ + if (env->iasq_f != env->iasq_b) { + cs_base |= CS_BASE_DIFFSPACE; + } else if ((env->iaoq_f ^ env->iaoq_b) & TARGET_PAGE_MASK) { + cs_base |= CS_BASE_DIFFPAGE; + } else { + cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; + } - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ #ifdef CONFIG_USER_ONLY - *pc = env->iaoq_f & -4; - *cs_base = env->iaoq_b & -4; flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B bits need to be here, when implemented. */ flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); - flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc = hppa_cpu_get_pc(env_cpu(env)); - *cs_base = env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a page. - Failure is indicated by a zero difference. */ - if (env->iasq_f == env->iasq_b) { - target_long diff = env->iaoq_b - env->iaoq_f; - if (diff == (int32_t)diff) { - *cs_base |= (uint32_t)diff; - } - } if ((env->sr[4] == env->sr[5]) & (env->sr[4] == env->sr[6]) & (env->sr[4] == env->sr[7])) { @@ -85,6 +92,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, } #endif + *pcsbase = cs_base; *pflags = flags; } @@ -93,25 +101,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, { HPPACPU *cpu = HPPA_CPU(cs); - tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); - -#ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f = tb->pc | PRIV_USER; - cpu->env.iaoq_b = tb->cs_base | PRIV_USER; -#else - /* Recover the IAOQ values from the GVA + PRIV. */ - uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; - target_ulong cs_base = tb->cs_base; - target_ulong iasq_f = cs_base & ~0xffffffffull; - int32_t diff = cs_base; - - cpu->env.iasq_f = iasq_f; - cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; - if (diff) { - cpu->env.iaoq_b = cpu->env.iaoq_f + diff; - } -#endif - + /* IAQ is always up-to-date before goto_tb. */ cpu->env.psw_n = (tb->flags & PSW_N) != 0; } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index aad5323a53..67197e98b3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -769,12 +769,11 @@ static bool use_nullify_skip(DisasContext *ctx) static void gen_goto_tb(DisasContext *ctx, int which, const DisasIAQE *f, const DisasIAQE *b) { + install_iaq_entries(ctx, f, b); if (use_goto_tb(ctx, f, b)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, f, b); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, f, b); tcg_gen_lookup_and_goto_ptr(); } } @@ -4575,6 +4574,7 @@ static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + uint64_t cs_base, iaoq_f, iaoq_b; int bound; ctx->cs = cs; @@ -4584,29 +4584,30 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege = PRIV_USER; ctx->mmu_idx = MMU_USER_IDX; - ctx->iaoq_first = ctx->base.pc_first | ctx->privilege; - ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx = (ctx->tb_flags & PSW_D ? PRIV_P_TO_MMU_IDX(ctx->privilege, ctx->tb_flags & PSW_P) : ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); +#endif /* Recover the IAOQ values from the GVA + PRIV. */ - uint64_t cs_base = ctx->base.tb->cs_base; - uint64_t iasq_f = cs_base & ~0xffffffffull; - int32_t diff = cs_base; + cs_base = ctx->base.tb->cs_base; + iaoq_f = cs_base & MAKE_64BIT_MASK(32, 32); + iaoq_f |= ctx->base.pc_first & MAKE_64BIT_MASK(2, 30); + iaoq_f |= ctx->privilege; + ctx->iaoq_first = iaoq_f; - ctx->iaoq_first = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; - - if (diff) { - ctx->iaq_b.disp = diff; - } else { - ctx->iaq_b.base = cpu_iaoq_b; + if (unlikely(cs_base & CS_BASE_DIFFSPACE)) { ctx->iaq_b.space = cpu_iasq_b; + ctx->iaq_b.base = cpu_iaoq_b; + } else if (unlikely(cs_base & CS_BASE_DIFFPAGE)) { + ctx->iaq_b.base = cpu_iaoq_b; + } else { + iaoq_b = (iaoq_f & TARGET_PAGE_MASK) | (cs_base & ~TARGET_PAGE_MASK); + ctx->iaq_b.disp = iaoq_b - iaoq_f; } -#endif ctx->zero = tcg_constant_i64(0); From patchwork Mon May 13 07:47:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B961C25B10 for ; Mon, 13 May 2024 07:54:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QRA-0006C9-0Y; Mon, 13 May 2024 03:49:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPW-0002yd-K1 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:50 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPQ-0001Pz-Os for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:50 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-42011507a4eso9205025e9.0 for ; Mon, 13 May 2024 00:47:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586463; x=1716191263; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lYICVLRWbF85s9jaYUNXAJVer+rQQT46dzOe8LbGwwQ=; b=uR+vzGJKkk5+PNN4DkB2wGLJnaSzWzgDgaAzr52QGzF4VjFGOVra2jJqPI9THXxbOU BdAUPzrT8j9WcOmOdSpdSG7t9CXgqM/84QTlLLWmeIV8DNOl4PrAyxNhvH1nj4oRwBHM XaNEB+KSfcmndMyyI2qn3DP9ZGRdM1ekTYDVT1xfIAbqrbfF1jHyyP4HYlDhpo3sskuF btfySwtBVTrGQgPIT0oTOJ07W1R+ZrQaSQzc5Tqxg/d5NVyKCR1jsioZt7SGsgzc+Ujo 0ogFhtG5kd2uPJnwY+7fF0XfaogGLmyh0MvQewMxlakgG+P2I4a3dGNHkF7VnS19y3fL KsCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586463; x=1716191263; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lYICVLRWbF85s9jaYUNXAJVer+rQQT46dzOe8LbGwwQ=; b=gNIpWghDbOxr/bwCDv+jZLujzLHUoCpCOXbZ42f3qzycigt6we1zFLchZTQsHi9Hzs eCSmLIPDoXUwLCjlo4YnnIyEYKqnVzqq8MhPWWgXmMIlLbqSJsEpzyj+MW1v0Jj1d1KK v+8gADfIbo5Se+t8De6XeVBFLS4qmj7Vm/HOs63opac9PiQxJGYrieuwVdvHuKJff9E9 qML6CiZ1rO4/F41LfToMmGWA6FTZJMVfrvs7a+QLygBKRIe/s844lEbmZXdI4oHmB8CA Hyi8X5FN6tzk1K1RpGpRUxvIfPzUX8qwdLXDclAlm02u/pfD55NFDrjLWCFjGmDs+IRL Oobg== X-Gm-Message-State: AOJu0YzjsaktF1+aYCXalFc5J7Ht3EdvGDdvY+fDkl4g6ICx2D8Kl86K bKtreB89tY8P4hLnsfm29uoNAco2LUDoKlW3lxK6alUJ4bF8/fQc1yWvECnPtFSzMCPD4noplYD a4eA= X-Google-Smtp-Source: AGHT+IE8Tfqc7itqhvg4N0cWGf50/8CZNFBibz0GSdJYGTmjwkJPcl+PYRpxL6JQh6alaaCKrDbc9A== X-Received: by 2002:a05:600c:4f04:b0:420:139e:9eda with SMTP id 5b1f17b1804b1-420139ea0c7mr24276865e9.12.1715586462861; Mon, 13 May 2024 00:47:42 -0700 (PDT) Received: from stoup.. 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In qemu, this is in cpu_get_tb_cpu_state. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 67197e98b3..abb21b05c8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -637,15 +637,10 @@ static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, const DisasIAQE *src) { - uint64_t mask = gva_offset_mask(ctx->tb_flags); - if (src->base == NULL) { - tcg_gen_movi_i64(dest, (ctx->iaoq_first + src->disp) & mask); - } else if (src->disp == 0) { - tcg_gen_andi_i64(dest, src->base, mask); + tcg_gen_movi_i64(dest, ctx->iaoq_first + src->disp); } else { tcg_gen_addi_i64(dest, src->base, src->disp); - tcg_gen_andi_i64(dest, dest, mask); } } From patchwork Mon May 13 07:47:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663153 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A03EC25B74 for ; Mon, 13 May 2024 07:54:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QR4-0005LP-Nl; Mon, 13 May 2024 03:49:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPV-0002wm-IT for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:49 -0400 Received: from mail-lj1-x230.google.com ([2a00:1450:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPR-0001QF-C7 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:49 -0400 Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2e0933d3b5fso58355281fa.2 for ; Mon, 13 May 2024 00:47:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586463; x=1716191263; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5fHOltBHJMUYAs0ifImrgAbY5phtILtBQ88LfAq6uw0=; b=MjY8TUWcjoJEqiO9gLNWvlWrV5vlRZJ7xitLPjdqzHLosGqOF1n1/6CCeGDmiZVRto pQxMJyi4B+cPwUUgVp2hsmKl9DdeJJNHQ3FipSY0Du2KH4WTeAIb10HSqWfyx58p89A4 s2133UcrTtE0jBTiWiYPuMcNok4XpXJ6aWA84Am9hunKFkfbaMzA0PWO+fOpQcXSr+HB 44pOADLhg5E3UtB4fYwq2CEKWsEPTsTysc8hTJi7j+LxYDQ335azaruywyr5eio+XGll gsuW8VmkTeYaqnGVwgkVsgtqrYhN57av8RkHQujWnxw/F/kROO1Du/j7w819PwtimBJZ DdzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586463; x=1716191263; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5fHOltBHJMUYAs0ifImrgAbY5phtILtBQ88LfAq6uw0=; b=XohluoPHr3Dv2R9P2rLclkOxODhcNbHQAYSakSFQamtud9sOQMLZYwRhaQS91BlJ7J /+u0Vc0pb57RqPfqI3rPVBkFjVLCcIKgOrM4N6WwyDXdBjL9Kr3x9l+blW/G5WJ31TfF A4EaDzaR6WSlkfOSKBg+wdDjpn7dW0Ezrj3/CQJ+TKEZ/HQT5GL+spZab5jjqleBjc67 Ryzc34JNJWBnrggIXkO8zvMv46adyUzbhs6xr6sgLVokzZUnPFxP+hlsPGiKeeJ8M7Uy T0YT6Pl9C5x4OVO2HzOkJc5tA9Dqe0LHSJbcROp8w3J4XHl4/zhLuLJUq52Q9GEnp/BR Ql+w== X-Gm-Message-State: AOJu0YyeVuRig0j/OCvVbmA9LMnrz5fsvttCiApnZCiqhAlzrpfUW3Wk xQLVby/7oG9DcwK2kTYTVhPFovn+aH6N3ZjlClJoPwt0QCAsGp025kAKe9dzsz9Ih7bJ3/m02+S e8Ac= X-Google-Smtp-Source: AGHT+IHpiw0rxSNxvecMQU54mMr37rH2BS2K5CUI5K6OBOGcwGnFb5IiggF1T3r1BFIhbUOp4PkLMg== X-Received: by 2002:a05:6512:39d3:b0:51c:5087:909f with SMTP id 2adb3069b0e04-5220fa71af9mr7684054e87.10.1715586463712; Mon, 13 May 2024 00:47:43 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 34/45] target/hppa: Improve hppa_cpu_dump_state Date: Mon, 13 May 2024 09:47:06 +0200 Message-Id: <20240513074717.130949-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Print both raw IAQ_Front and IAQ_Back as well as the GVAs. Print control registers in system mode. Print floating point register if CPU_DUMP_FPU. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/helper.c | 60 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 6 deletions(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 9d217d051c..7d22c248fb 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -102,6 +102,19 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) { +#ifndef CONFIG_USER_ONLY + static const char cr_name[32][5] = { + "RC", "CR1", "CR2", "CR3", + "CR4", "CR5", "CR6", "CR7", + "PID1", "PID2", "CCR", "SAR", + "PID3", "PID4", "IVA", "EIEM", + "ITMR", "ISQF", "IOQF", "IIR", + "ISR", "IOR", "IPSW", "EIRR", + "TR0", "TR1", "TR2", "TR3", + "TR4", "TR5", "TR6", "TR7", + }; +#endif + CPUHPPAState *env = cpu_env(cs); target_ulong psw = cpu_hppa_get_psw(env); target_ulong psw_cb; @@ -117,11 +130,12 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) m = UINT32_MAX; } - qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx - " IIR %0*" PRIx64 "\n", + qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n" + "IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n", + env->iasq_f >> 32, w, m & env->iaoq_f, hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), - hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b), - w, m & env->cr[CR_IIR]); + env->iasq_b >> 32, w, m & env->iaoq_b, + hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); @@ -154,12 +168,46 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) (i & 3) == 3 ? '\n' : ' '); } #ifndef CONFIG_USER_ONLY + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "%-4s %0*" PRIx64 "%c", + cr_name[i], w, m & env->cr[i], + (i & 3) == 3 ? '\n' : ' '); + } + qemu_fprintf(f, "ISQB %0*" PRIx64 " IOQB %0*" PRIx64 "\n", + w, m & env->cr_back[0], w, m & env->cr_back[1]); for (i = 0; i < 8; i++) { qemu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32), (i & 3) == 3 ? '\n' : ' '); } #endif - qemu_fprintf(f, "\n"); - /* ??? FR */ + if (flags & CPU_DUMP_FPU) { + static const char rm[4][4] = { "RN", "RZ", "R+", "R-" }; + char flg[6], ena[6]; + uint32_t fpsr = env->fr0_shadow; + + flg[0] = (fpsr & R_FPSR_FLG_V_MASK ? 'V' : '-'); + flg[1] = (fpsr & R_FPSR_FLG_Z_MASK ? 'Z' : '-'); + flg[2] = (fpsr & R_FPSR_FLG_O_MASK ? 'O' : '-'); + flg[3] = (fpsr & R_FPSR_FLG_U_MASK ? 'U' : '-'); + flg[4] = (fpsr & R_FPSR_FLG_I_MASK ? 'I' : '-'); + flg[5] = '\0'; + + ena[0] = (fpsr & R_FPSR_ENA_V_MASK ? 'V' : '-'); + ena[1] = (fpsr & R_FPSR_ENA_Z_MASK ? 'Z' : '-'); + ena[2] = (fpsr & R_FPSR_ENA_O_MASK ? 'O' : '-'); + ena[3] = (fpsr & R_FPSR_ENA_U_MASK ? 'U' : '-'); + ena[4] = (fpsr & R_FPSR_ENA_I_MASK ? 'I' : '-'); + ena[5] = '\0'; + + qemu_fprintf(f, "FPSR %08x flag %s enable %s %s\n", + fpsr, flg, ena, rm[FIELD_EX32(fpsr, FPSR, RM)]); + + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "FR%02d %016" PRIx64 "%c", + i, env->fr[i], (i & 3) == 3 ? '\n' : ' '); + } + } + + qemu_fprintf(f, "\n"); } From patchwork Mon May 13 07:47:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2978C25B78 for ; Mon, 13 May 2024 07:53:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QRB-0006Lj-7E; Mon, 13 May 2024 03:49:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPX-0002zA-FJ for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:53 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPS-0001QJ-Og for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:51 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-42011507a57so9658565e9.1 for ; Mon, 13 May 2024 00:47:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586464; x=1716191264; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E8/1fo4XxPxuANS4fw7f9IOfFNtGCwACN8n5KfI7MiY=; b=ZLnZ4lTS6WPgJzNZ04u8Okzcerm99/WU+3DtuV+fxy/BBGTArVdAN2x9zy5gIYnQBg Av6tB8W4Ca/n7f92SLqLYvJGRoCQ+jfIBkahCEdGGKovR55KzflU/1HVKHPO+chGrd/h UQsd02wsFCXAK0yGctUGccJ62kzbZrpTyJH4lqjzhGbriJpfnof1Qkg21bQwuQ7X70gA LE2TYx0ueQpb4Ldc835lh8HP5Zky92m4MdQ73Nb0opsn9I/Zv/maoGhb8SNOj6W2s+Lv 2eaaH3YsdTJLk0WpsCngOq9dk7vwH9m7dexBmWzYNQLQ7kxcvcY0jrAer1/7vZVpZQs7 y33w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586464; x=1716191264; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E8/1fo4XxPxuANS4fw7f9IOfFNtGCwACN8n5KfI7MiY=; b=lvQYAkQ59PQqs7CbOVMXkA4zVVavKSi67XbotnNFcDXnLS9igOpetiIUSt1y6Qq1by tqUgh6ba/hFGb67i7WVrseydjkg+PS7rlALXJOqhW/r8SWO4sKNwRPJuIJ2bES6jv0o8 G4zR6KV4eQFDTUHK3rQIT9zgQymJNZ3ZWYZ099hiUXSLRP07+yGn39kS30o0iM8mAwlv BylF6ylGF2yZLutA5dnM++qo+OCV+x7eVok+QBaf0FjPc34/TGZTnjsn9sPfYzri8dJ2 X4uxIxL69+zaSmnk7cHIs6307BzjnfVWbgi/2XP2dMM4nF+lecGa69YWDioZK3WfmZo4 FzYQ== X-Gm-Message-State: AOJu0YzY6QPheld/QbVdYFJQWovERIHyjhdcF3kHzhrUiWN9gjQ6bsOs 2QCV35Q44RiosCMleaPgFyPklE98XrdUXPcYG84NYVC434H3kRgWFloeB0mOj18AamuvqsZsNxr 1K9M= X-Google-Smtp-Source: AGHT+IEhseMmHyfHtOgN0lOBClYyPXYRIjh1i7uZPys6LpxqhsGtiHQEuoCOtMP7arc9XIzHMO8zqA== X-Received: by 2002:a05:600c:1d1c:b0:420:98d:e101 with SMTP id 5b1f17b1804b1-420098de3c7mr49278315e9.15.1715586464420; Mon, 13 May 2024 00:47:44 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 35/45] target/hppa: Split PSW X and B into their own field Date: Mon, 13 May 2024 09:47:07 +0200 Message-Id: <20240513074717.130949-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Generally, both of these bits are cleared at the end of each instruction. By separating these, we will be able to clear both with a single insn, instead of 2 or 3. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/cpu.h | 3 ++- target/hppa/helper.c | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 1232a4cef2..f247ad56d7 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -208,7 +208,8 @@ typedef struct CPUArchState { uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ - target_ulong psw; /* All psw bits except the following: */ + uint32_t psw; /* All psw bits except the following: */ + uint32_t psw_xb; /* X and B, in their normal positions */ target_ulong psw_n; /* boolean */ target_long psw_v; /* in most significant bit */ diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 7d22c248fb..b79ddd8184 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -54,7 +54,7 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) psw |= env->psw_n * PSW_N; psw |= (env->psw_v < 0) * PSW_V; - psw |= env->psw; + psw |= env->psw | env->psw_xb; return psw; } @@ -76,8 +76,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) } psw &= ~reserved; - env->psw = psw & (uint32_t)~(PSW_N | PSW_V | PSW_CB); - + env->psw = psw & (uint32_t)~(PSW_B | PSW_N | PSW_V | PSW_X | PSW_CB); + env->psw_xb = psw & (PSW_X | PSW_B); env->psw_n = (psw / PSW_N) & 1; env->psw_v = -((psw / PSW_V) & 1); From patchwork Mon May 13 07:47:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA8CCC25B10 for ; Mon, 13 May 2024 07:52:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QR1-0004m2-Hh; Mon, 13 May 2024 03:49:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPW-0002yg-NA for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:50 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPS-0001QO-DB for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:50 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-420104e5336so8098915e9.1 for ; Mon, 13 May 2024 00:47:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586465; x=1716191265; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TlXJccalJ3CeZTGsUdbhgiIr1TQBFsVdUQlxtQmyKbI=; b=KkXgO7y4I8MxqU6cz23/MlmYydT+O2tJEunKzM4hGnrXSXXsRpe7Sgg1dMIDBRGPCC b6Kdrmk0WCYc2ulrrV7vDt7zGYlcZPn2qyKrRnsFQCZsEkIhE5H9EPnuo0apa31Qt5hi rxJACwqGdXS1W3FPudEhvc1JsLfcuRz6oCJi0uCLeogJcObgRaHMJic2OIXb4exKf/Wp BTtOLFQU0jdrjXGbtMqJ5LLyjk+LaE5EeNMRS2YXUxachPlbpdOMw/psDuUtf6Xnu7MZ WZLBe/4ixpbfOHj0yUXPPN1EWVA3nWv4vEinf/8OWpukWDwUw8VeVZEudXjJv4IV3Qza R6mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586465; x=1716191265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TlXJccalJ3CeZTGsUdbhgiIr1TQBFsVdUQlxtQmyKbI=; b=atgSjAS8n6tPmsc7xslBhuxtt651gwlwtcQ3eRpvPUtekSgr3O6ufg1OuPadSLmEfq mWHeY1H6utr6plkT8Vo5GIuBFQ1Lormpi7UdwZCGKlbxzN7617wN8bHc9KW5h2FM24zt C9EByG2Cs4IyqsjV/RIWYLbczUCUQfSQ6qJWLlI+z9Unb2D4yaUGaITu91L+dKbw7CAm TcSnHIhH3wimid2lM9pq/xKUFZqejWPNIU04MrjcvhtJKdMA+TG3BHvxcFzMbxoOgh0I oBPu3SySdN14+GGS1TpOk1tPQRgvJmi6A1AoJ7TeYLeECVE5bJK7pksmcgb1el8yCLVH oMEA== X-Gm-Message-State: AOJu0YykdcG4+nmR66X0ewsg7ahbEewdk9ipGiCZ/qmAYvy49rcgFQk2 1NwZhV2yMOU9BWgaUDIcPJ0Xqhhr84EC6wfQRJvQdfijNXD6xYecM79FavZVoVMyE3fyaRU1y3h bIno= X-Google-Smtp-Source: AGHT+IGI9xRBkXVxZ8oPOG6mOs2VRYZqc4YKD2vOX7XKWy8yVRVEcKxluFD/0rKPmTDJnWfi5eq/GA== X-Received: by 2002:a05:600c:1381:b0:41a:56b7:eb37 with SMTP id 5b1f17b1804b1-41fead61bc5mr69516565e9.20.1715586464986; Mon, 13 May 2024 00:47:44 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 36/45] target/hppa: Manage PSW_X and PSW_B in translator Date: Mon, 13 May 2024 09:47:08 +0200 Message-Id: <20240513074717.130949-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org PSW_X is cleared after every instruction, and only set by RFI. PSW_B is cleared after every non-branch, or branch not taken, and only set by taken branches. We can clear both bits with a single store, at most once per TB. Taken branches set PSW_B, at most once per TB. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.c | 10 ++++++--- target/hppa/translate.c | 50 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 3 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 003af63e20..5f0df0697a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -50,7 +50,7 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, uint64_t *pcsbase, uint32_t *pflags) { - uint32_t flags = env->psw_n * PSW_N; + uint32_t flags = 0; uint64_t cs_base = 0; /* @@ -80,11 +80,14 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; } + /* ??? E, T, H, L bits need to be here, when implemented. */ + flags |= env->psw_n * PSW_N; + flags |= env->psw_xb; + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + #ifdef CONFIG_USER_ONLY flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else - /* ??? E, T, H, L, B bits need to be here, when implemented. */ - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); if ((env->sr[4] == env->sr[5]) & (env->sr[4] == env->sr[6]) & (env->sr[4] == env->sr[7])) { @@ -103,6 +106,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, /* IAQ is always up-to-date before goto_tb. */ cpu->env.psw_n = (tb->flags & PSW_N) != 0; + cpu->env.psw_xb = tb->flags & (PSW_X | PSW_B); } static void hppa_restore_state_to_opc(CPUState *cs, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index abb21b05c8..1a6a140d6f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -84,7 +84,9 @@ typedef struct DisasContext { uint32_t tb_flags; int mmu_idx; int privilege; + uint32_t psw_xb; bool psw_n_nonzero; + bool psw_b_next; bool is_pa20; bool insn_start_updated; @@ -263,6 +265,7 @@ static TCGv_i64 cpu_psw_n; static TCGv_i64 cpu_psw_v; static TCGv_i64 cpu_psw_cb; static TCGv_i64 cpu_psw_cb_msb; +static TCGv_i32 cpu_psw_xb; void hppa_translate_init(void) { @@ -315,6 +318,9 @@ void hppa_translate_init(void) *v->var = tcg_global_mem_new(tcg_env, v->ofs, v->name); } + cpu_psw_xb = tcg_global_mem_new_i32(tcg_env, + offsetof(CPUHPPAState, psw_xb), + "psw_xb"); cpu_iasq_f = tcg_global_mem_new_i64(tcg_env, offsetof(CPUHPPAState, iasq_f), "iasq_f"); @@ -509,6 +515,25 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) #endif } +/* + * Write a value to psw_xb, bearing in mind the known value. + * To be used just before exiting the TB, so do not update the known value. + */ +static void store_psw_xb(DisasContext *ctx, uint32_t xb) +{ + tcg_debug_assert(xb == 0 || xb == PSW_B); + if (ctx->psw_xb != xb) { + tcg_gen_movi_i32(cpu_psw_xb, xb); + } +} + +/* Write a value to psw_xb, and update the known value. */ +static void set_psw_xb(DisasContext *ctx, uint32_t xb) +{ + store_psw_xb(ctx, xb); + ctx->psw_xb = xb; +} + /* Skip over the implementation of an insn that has been nullified. Use this when the insn is too complex for a conditional move. */ static void nullify_over(DisasContext *ctx) @@ -576,6 +601,8 @@ static bool nullify_end(DisasContext *ctx) /* For NEXT, NORETURN, STALE, we can easily continue (or exit). For UPDATED, we cannot update on the nullified path. */ assert(status != DISAS_IAQ_N_UPDATED); + /* Taken branches are handled manually. */ + assert(!ctx->psw_b_next); if (likely(null_lab == NULL)) { /* The current insn wasn't conditional or handled the condition @@ -1842,6 +1869,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (is_n) { if (use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); ctx->base.is_jmp = DISAS_NORETURN; return true; @@ -1849,20 +1877,24 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, ctx->null_cond.c = TCG_COND_ALWAYS; } ctx->iaq_n = &ctx->iaq_j; + ctx->psw_b_next = true; } else { nullify_over(ctx); install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); } else { nullify_set(ctx, is_n); + store_psw_xb(ctx, PSW_B); gen_goto_tb(ctx, 0, &ctx->iaq_b, &ctx->iaq_j); } nullify_end(ctx); nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 1, &ctx->iaq_b, NULL); ctx->base.is_jmp = DISAS_NORETURN; } @@ -1893,6 +1925,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, n = is_n && disp < 0; if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); next = iaqe_incr(&ctx->iaq_b, 4); gen_goto_tb(ctx, 0, &next, NULL); } else { @@ -1901,6 +1934,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, ctx->null_lab = NULL; } nullify_set(ctx, n); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_b, NULL); } @@ -1912,9 +1946,11 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, next = iaqe_branchi(ctx, disp); if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 1, &next, NULL); } else { nullify_set(ctx, n); + store_psw_xb(ctx, PSW_B); gen_goto_tb(ctx, 1, &ctx->iaq_b, &next); } @@ -1948,6 +1984,7 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, ctx->null_cond.c = TCG_COND_ALWAYS; } ctx->iaq_n = &ctx->iaq_j; + ctx->psw_b_next = true; return true; } @@ -1957,9 +1994,11 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, if (is_n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); + store_psw_xb(ctx, 0); } else { install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); nullify_set(ctx, is_n); + store_psw_xb(ctx, PSW_B); } tcg_gen_lookup_and_goto_ptr(); @@ -2386,6 +2425,7 @@ static bool trans_halt(DisasContext *ctx, arg_halt *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY + set_psw_xb(ctx, 0); nullify_over(ctx); gen_helper_halt(tcg_env); ctx->base.is_jmp = DISAS_NORETURN; @@ -2397,6 +2437,7 @@ static bool trans_reset(DisasContext *ctx, arg_reset *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY + set_psw_xb(ctx, 0); nullify_over(ctx); gen_helper_reset(tcg_env); ctx->base.is_jmp = DISAS_NORETURN; @@ -2791,6 +2832,9 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ /* No need to check for supervisor, as userland can only pause until the next timer interrupt. */ + + set_psw_xb(ctx, 0); + nullify_over(ctx); /* Advance the instruction queue. */ @@ -4575,6 +4619,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cs = cs; ctx->tb_flags = ctx->base.tb->flags; ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); + ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B); #ifdef CONFIG_USER_ONLY ctx->privilege = PRIV_USER; @@ -4661,6 +4706,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) */ ctx->iaq_n = NULL; memset(&ctx->iaq_j, 0, sizeof(ctx->iaq_j)); + ctx->psw_b_next = false; if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { ctx->null_cond.c = TCG_COND_NEVER; @@ -4673,6 +4719,10 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ret = ctx->base.is_jmp; assert(ctx->null_lab == NULL); } + + if (ret != DISAS_NORETURN) { + set_psw_xb(ctx, ctx->psw_b_next ? PSW_B : 0); + } } /* If the TranslationBlock must end, do so. */ From patchwork Mon May 13 07:47:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C35A0C25B10 for ; Mon, 13 May 2024 07:51:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QQi-0004A1-UR; Mon, 13 May 2024 03:49:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPW-0002yf-LC for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:50 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPT-0001QU-0j for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:50 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-41ff5e3dc3bso17922065e9.1 for ; Mon, 13 May 2024 00:47:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586465; x=1716191265; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e5GRNpEQvFWJc+tF6eTBVa97b3dnETbzXExkDc8WgAI=; b=bRnU31lbRThKVjamRSWRV4tRWEMwInbq6T/yw1cHp1hx6xtKNSxWh2ckjB5/HeuRkB +nafIWRJUukeU1lLyZPt89SWrBdZvyzr0o6/VJZ0Y0Ht42W9FNLgLiCNIcKzyOQOt9J+ uqtCbBjutY/6krV3aUwJVsUlUUxQafg6BexUdAZcuYO7AosYaLlcCs/oZbTF7GCjCm4T TL+QUD4iA20Cgpfvqik7ZW20SA8D9Le9+nVVVrNrGZzuJzdFy6EVb22RA3UbaxrIYJRg On6HiBFTdiyt7AnUPn7/UMlII/iNWLkPJZvVQU/PV/xaB+oPNNzm8kALcsfN0TdtYuSn w3XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586465; x=1716191265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e5GRNpEQvFWJc+tF6eTBVa97b3dnETbzXExkDc8WgAI=; b=DaQGk1oz1f9fNJOf9oOxVAPkPfQttzahWZm/avMfdFnvdTTWJpFBsEPMC/uUSRnqmh Sri8qIEv3D9RcMlCVbjphaAwn5bWwgmzMKkJrN3a03Iw2BNow8bXBJR89SA+1jJSid2P BdHUzlbyUX8EIz4pxVWdHud3f0PGcci7G8DMWGiByDxne5eRfj3PrPuUVgA4CTBur1/t oR0NUYa4u/gUNzolYoqS+3mc85MRL+9o2crvylwy/G3qnQv5sH3klvWx5rmgcXE72oJq XdnpjnGIlAbpZOntj3Cpd3tRUWja15rP4dHvRKoV4zo9xX57/QN55g/2ypNZnKWEg7SJ NhZw== X-Gm-Message-State: AOJu0YxYc0hTmcbnsHtf1sP110u29EgZCy5+jJ8WCDEWN4/AP44fzAHE SBfYkbbMwRjkzZWSYW5zlEEVXeOkT1Cpd4GRAeXaS9cw1NGctbl1BxTuEZ79LLTcaF/DTlV27/y CsFQ= X-Google-Smtp-Source: AGHT+IHO/w8dlaY4PL/nHAw9GUPeAfqhDiPAAWIOTNAIIhCUx6L1QcsT8Ugfe6YJ7S896z2jVPkUcg== X-Received: by 2002:a05:600c:1c9a:b0:41b:8660:c530 with SMTP id 5b1f17b1804b1-41fea932021mr76999535e9.5.1715586465612; Mon, 13 May 2024 00:47:45 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 37/45] target/hppa: Implement PSW_B Date: Mon, 13 May 2024 09:47:09 +0200 Message-Id: <20240513074717.130949-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org PSW_B causes B,GATE to trap as an illegal instruction, removing the sequential execution test that was merely an approximation. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 25 ++++++------------------- 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1a6a140d6f..2d8410b8ea 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2061,11 +2061,8 @@ static void do_page_zero(DisasContext *ctx) g_assert_not_reached(); } - /* Check that we didn't arrive here via some means that allowed - non-sequential instruction execution. Normally the PSW[B] bit - detects this by disallowing the B,GATE instruction to execute - under such conditions. */ - if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != 4) { + /* If PSW[B] is set, the B,GATE insn would trap. */ + if (ctx->psw_xb & PSW_B) { goto do_sigill; } @@ -3964,23 +3961,13 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { int64_t disp = a->disp; - nullify_over(ctx); - - /* Make sure the caller hasn't done something weird with the queue. - * ??? This is not quite the same as the PSW[B] bit, which would be - * expensive to track. Real hardware will trap for - * b gateway - * b gateway+4 (in delay slot of first branch) - * However, checking for a non-sequential instruction queue *will* - * diagnose the security hole - * b gateway - * b evil - * in which instructions at evil would run with increased privs. - */ - if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { + /* Trap if PSW[B] is set. */ + if (ctx->psw_xb & PSW_B) { return gen_illegal(ctx); } + nullify_over(ctx); + #ifndef CONFIG_USER_ONLY if (ctx->tb_flags & PSW_C) { int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next); From patchwork Mon May 13 07:47:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B602C25B7A for ; Mon, 13 May 2024 07:53:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QR4-0005BA-19; Mon, 13 May 2024 03:49:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QPY-0002zD-0d for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:53 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QPW-0001SQ-BH for qemu-devel@nongnu.org; Mon, 13 May 2024 03:47:51 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-420180b5897so2670395e9.3 for ; Mon, 13 May 2024 00:47:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586467; x=1716191267; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IqZwbuhaC0QOpVi9GDZS/pvS08Z41AQGVLa7yPdeApE=; b=W/yVSJkdd4pOZXCBB66qD+P3sy2ewlkiWvpbFuj42Vy9pymIPkvLVV01OvxL0tptWq 2RH8uuMjmFZDp9UzhgMEcMGE/Yn+G2+fiOZnMlSivdNR26/z11c1DOvLVbMJhjreXfKM l/piu708vqnDsYrtGfWOkMsrSrQOCDApcAQlyRBEowsXnLhnBT5TyAfSEMmKbTeXj2b7 ywe0/autNEq9c4YqfkNK2iIJo++PdvtpcY9mbt+wzuskS7PZhHcyh5xkD8vKxpPXSz6h T1vQKGa0GLmBrMeTkloKTWAIYmGygYZ1gaN9He01+I1T+02FhOqjmxJU9tDKBaBwwFN5 +SDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586467; x=1716191267; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IqZwbuhaC0QOpVi9GDZS/pvS08Z41AQGVLa7yPdeApE=; b=w5MHok/3Wkt/IgPp/nF/qJvLBvXTy6QNqO59RqdHyrzqFwQ97B4CpkC2jeEJKACh+h EV2CIZo2HlIaJDWtOPNrXWGE6sxrEnHnniWtQrVcSjymYLu10tYwY7H/g7K1QNy+pivK X9rlL5rjJA/La0VFrREBWlRiFFLtSbirVuP0h1ZyB7Vg9Psv1HzPEGA1ZBIHmziFRN0i aMRSEFce+qDyF5oqqr4e6oUgBE3k9j1TufUZS7XRoMqYqsOqtfPLchEH4Oo3MzrcufAj UffrxNBpJ7BxmGveeMsX+jvzDa9Py9b/P9zd+N+mZOX3aY6rTlg29LroSP4h1sbl9Fp2 uVcg== X-Gm-Message-State: AOJu0YyDYFDEaVPiN8bW3AilNKTRIL8GdOicEy0wezVFMIQHHkd7KDPq p5XHkZPu+8dbuYxBtIwtFspg19mwLOeKyhTvta3FaFaq6HNtbtCDQq/bOUnuKeHg2Z9ZHfhrZlN okwc= X-Google-Smtp-Source: AGHT+IGXLwsD3p+T/YA61TZd8uvEMY2ULcZGeBqSKWKhyQWff7q2FM+L4k8QLt7CdlDjDeYt3tqZ3A== X-Received: by 2002:a05:600c:434a:b0:41b:e55c:8e14 with SMTP id 5b1f17b1804b1-41feaa38a5cmr67252675e9.14.1715586467647; Mon, 13 May 2024 00:47:47 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 38/45] target/hppa: Implement PSW_X Date: Mon, 13 May 2024 09:47:10 +0200 Message-Id: <20240513074717.130949-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use PAGE_WRITE_INV to temporarily enable write permission on for a given page, driven by PSW_X being set. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/mem_helper.c | 46 +++++++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index d09877afd7..ca7bbe0a7c 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -296,30 +296,38 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } - /* In reverse priority order, check for conditions which raise faults. - As we go, remove PROT bits that cover the condition we want to check. - In this way, the resulting PROT will force a re-check of the - architectural TLB entry for the next access. */ - if (unlikely(!ent->d)) { - if (type & PAGE_WRITE) { - /* The D bit is not set -- TLB Dirty Bit Fault. */ - ret = EXCP_TLB_DIRTY; - } - prot &= PAGE_READ | PAGE_EXEC; - } - if (unlikely(ent->b)) { - if (type & PAGE_WRITE) { - /* The B bit is set -- Data Memory Break Fault. */ - ret = EXCP_DMB; - } - prot &= PAGE_READ | PAGE_EXEC; - } + /* + * In priority order, check for conditions which raise faults. + * Remove PROT bits that cover the condition we want to check, + * so that the resulting PROT will force a re-check of the + * architectural TLB entry for the next access. + */ if (unlikely(ent->t)) { + prot &= PAGE_EXEC; if (!(type & PAGE_EXEC)) { /* The T bit is set -- Page Reference Fault. */ ret = EXCP_PAGE_REF; } - prot &= PAGE_EXEC; + } else if (!ent->d) { + prot &= PAGE_READ | PAGE_EXEC; + if (type & PAGE_WRITE) { + /* The D bit is not set -- TLB Dirty Bit Fault. */ + ret = EXCP_TLB_DIRTY; + } + } else if (unlikely(ent->b)) { + prot &= PAGE_READ | PAGE_EXEC; + if (type & PAGE_WRITE) { + /* + * The B bit is set -- Data Memory Break Fault. + * Except when PSW_X is set, allow this single access to succeed. + * The write bit will be invalidated for subsequent accesses. + */ + if (env->psw_xb & PSW_X) { + prot |= PAGE_WRITE_INV; + } else { + ret = EXCP_DMB; + } + } } egress: From patchwork Mon May 13 07:47:11 2024 Content-Type: text/plain; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 39/45] target/hppa: Drop tlb_entry return from hppa_get_physical_address Date: Mon, 13 May 2024 09:47:11 +0200 Message-Id: <20240513074717.130949-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The return-by-reference is never used. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/cpu.h | 3 +-- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 19 ++++--------------- target/hppa/op_helper.c | 3 +-- 4 files changed, 7 insertions(+), 20 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f247ad56d7..78ab0adcd0 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -371,8 +371,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot, - HPPATLBEntry **tlb_entry); + int type, hwaddr *pphys, int *pprot); void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 97e5f0b9a7..b82f32fd12 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -167,7 +167,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, - 0, &paddr, &prot, NULL); + 0, &paddr, &prot); if (t >= 0) { /* We can't re-load the instruction. */ env->cr[CR_IIR] = 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index ca7bbe0a7c..2929226874 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -197,18 +197,13 @@ static int match_prot_id64(CPUHPPAState *env, uint32_t access_id) } int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot, - HPPATLBEntry **tlb_entry) + int type, hwaddr *pphys, int *pprot) { hwaddr phys; int prot, r_prot, w_prot, x_prot, priv; HPPATLBEntry *ent; int ret = -1; - if (tlb_entry) { - *tlb_entry = NULL; - } - /* Virtual translation disabled. Map absolute to physical. */ if (MMU_IDX_MMU_DISABLED(mmu_idx)) { switch (mmu_idx) { @@ -238,10 +233,6 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } - if (tlb_entry) { - *tlb_entry = ent; - } - /* We now know the physical address. */ phys = ent->pa + (addr - ent->itree.start); @@ -350,7 +341,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) cpu->env.psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, - &phys, &prot, NULL); + &phys, &prot); /* Since we're translating for debugging, the only error that is a hard error is no translation at all. Otherwise, while a real cpu @@ -432,7 +423,6 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; - HPPATLBEntry *ent; int prot, excp, a_prot; hwaddr phys; @@ -448,8 +438,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; } - excp = hppa_get_physical_address(env, addr, mmu_idx, - a_prot, &phys, &prot, &ent); + excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); if (unlikely(excp >= 0)) { if (probe) { return false; @@ -690,7 +679,7 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) int prot, excp; excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, - &phys, &prot, NULL); + &phys, &prot); if (excp >= 0) { if (excp == EXCP_DTLB_MISS) { excp = EXCP_NA_DTLB_MISS; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 66cad78a57..7f79196fff 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -334,8 +334,7 @@ target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr, } mmu_idx = PRIV_P_TO_MMU_IDX(level, env->psw & PSW_P); - excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, - &prot, NULL); + excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, &prot); if (excp >= 0) { cpu_restore_state(env_cpu(env), GETPC()); hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); From patchwork Mon May 13 07:47:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23E18C25B74 for ; Mon, 13 May 2024 07:53:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QSU-0005Cu-7S; Mon, 13 May 2024 03:50:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QST-0005Aw-F6 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:50:53 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QSR-0001ya-BH for qemu-devel@nongnu.org; Mon, 13 May 2024 03:50:53 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-34de61b7ca4so2857893f8f.2 for ; Mon, 13 May 2024 00:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586650; x=1716191450; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3FDffdEHv+AM3yGjV7Jyc3t/YLBxETSVfvDP/Ffczzk=; b=QK8wlainYEBfWb94E8K2EcqA15o4rSCLRpdYfKhN8BMUs3jbFeAO4nIq0DuW4cPFF/ joGtLxezWWwfFFTLVUp/LuLHQIaJYiI6ksdHK7bctQMv+ds/bwhxIvVyVUIypYbjWXKo CTrBZJl8mBObI+cBBwl0bqlLi1utsxMHGQXbB5JCIRZ2u96IiB+Eh0nIZ7r76OkkrrRh P0FqNPBNF4jamXQ9EdI9crIf0lfEvIOPunr+VTIOrI6e+HKBV/YF6zuyCR+Y2OGafyk8 MLF3JFYLr7/FZsQSDu0yBLlv3IiJf5qpFqM3dkiiz7zYUaXkN0G2pn6H5wAEbqdGxJyw t7Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586650; x=1716191450; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3FDffdEHv+AM3yGjV7Jyc3t/YLBxETSVfvDP/Ffczzk=; b=qBRQC8hhgLCXaeg0kKsAoJQQG/9T5pqk+cYsBTByz3V8HjViVc/JIuupiHcvZfW3NM USAkLOvFdd+HEzJQR3zuipUjq/ab5gb0UxNZ2eYEDD4U3Nwp75kwEubmBfKBMpPOvWCn HchsTXteAAjevEiLGjXD8szk0gHjzxQKgzDDTa035Yl6KDRSa6VQRm6r+nrkvaTj6Sip 09sdaFmMvgsG0PjpNZ+Y1g2QqgRwDpwZNQ9gU1sGV8rEs2k7ft4AAe02HtruF19L8lq4 iIKXW5Afc1Ogtq/hOk1+8z7/Z2+CtlTDnFScDt5f7Ut5b5o2UZghdSK6TFj8suFaZoNS zyoA== X-Gm-Message-State: AOJu0Ywo+4H0SbCXD8dZTNpHB7yf0mBRVIUXoKmMbPofLxLrxdKOzlHS WAVlPxo5PtfaxWvHIf1LaQ/fU89/LIz9Lqm00Z4mTAx2FtFDQDnahytqXZwILJ+Qt6NR8iqiwYr FIs8= X-Google-Smtp-Source: AGHT+IFSpi1oUbMaarMqa0G37CQ3pqSvONTrQjI3qkb5jRPr0Mb1MP3f7Z4OjyPCbOtbsjZjOcVR6g== X-Received: by 2002:adf:f145:0:b0:34d:7def:a2 with SMTP id ffacd0b85a97d-3504a96b873mr8814018f8f.68.1715586649602; Mon, 13 May 2024 00:50:49 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 40/45] target/hppa: Adjust priv for B,GATE at runtime Date: Mon, 13 May 2024 09:47:12 +0200 Message-Id: <20240513074717.130949-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Do not compile in the priv change based on the first translation; look up the PTE at execution time. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 1 - target/hppa/helper.h | 1 + target/hppa/mem_helper.c | 34 +++++++++++++++++++++++++++------- target/hppa/translate.c | 36 +++++++++++++++++++----------------- 4 files changed, 47 insertions(+), 25 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 78ab0adcd0..2bcb3b602b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -380,7 +380,6 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, extern const MemoryRegionOps hppa_io_eir_ops; extern const VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); -int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); #endif G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); diff --git a/target/hppa/helper.h b/target/hppa/helper.h index c12b48a04a..de411923d9 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -86,6 +86,7 @@ DEF_HELPER_1(halt, noreturn, env) DEF_HELPER_1(reset, noreturn, env) DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(b_gate_priv, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tl, env, tl) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 2929226874..b984f730aa 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -691,13 +691,6 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) return phys; } -/* Return the ar_type of the TLB at VADDR, or -1. */ -int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) -{ - HPPATLBEntry *ent = hppa_find_tlb(env, vaddr); - return ent ? ent->ar_type : -1; -} - /* * diag_btlb() emulates the PDC PDC_BLOCK_TLB firmware call to * allow operating systems to modify the Block TLB (BTLB) entries. @@ -793,3 +786,30 @@ void HELPER(diag_btlb)(CPUHPPAState *env) break; } } + +uint64_t HELPER(b_gate_priv)(CPUHPPAState *env, uint64_t iaoq_f) +{ + uint64_t gva = hppa_form_gva(env, env->iasq_f, iaoq_f); + HPPATLBEntry *ent = hppa_find_tlb(env, gva); + + if (ent == NULL) { + raise_exception_with_ior(env, EXCP_ITLB_MISS, GETPC(), gva, false); + } + + /* + * There should be no need to check page permissions, as that will + * already have been done by tb_lookup via get_page_addr_code. + * All we need at this point is to check the ar_type. + * + * No change for non-gateway pages or for priv decrease. + */ + if (ent->ar_type & 4) { + int old_priv = iaoq_f & 3; + int new_priv = ent->ar_type & 3; + + if (new_priv < old_priv) { + iaoq_f = (iaoq_f & -4) | new_priv; + } + } + return iaoq_f; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2d8410b8ea..fa79116d5b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3960,6 +3960,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a) static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { int64_t disp = a->disp; + bool indirect = false; /* Trap if PSW[B] is set. */ if (ctx->psw_xb & PSW_B) { @@ -3969,24 +3970,22 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) nullify_over(ctx); #ifndef CONFIG_USER_ONLY - if (ctx->tb_flags & PSW_C) { - int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next); - /* If we could not find a TLB entry, then we need to generate an - ITLB miss exception so the kernel will provide it. - The resulting TLB fill operation will invalidate this TB and - we will re-translate, at which point we *will* be able to find - the TLB entry and determine if this is in fact a gateway page. */ - if (type < 0) { - gen_excp(ctx, EXCP_ITLB_MISS); - return true; - } - /* No change for non-gateway pages or for priv decrease. */ - if (type >= 4 && type - 4 < ctx->privilege) { - disp -= ctx->privilege; - disp += type - 4; - } + if (ctx->privilege == 0) { + /* Privilege cannot decrease. */ + } else if (!(ctx->tb_flags & PSW_C)) { + /* With paging disabled, priv becomes 0. */ + disp -= ctx->privilege; } else { - disp -= ctx->privilege; /* priv = 0 */ + /* Adjust the dest offset for the privilege change from the PTE. */ + TCGv_i64 off = tcg_temp_new_i64(); + + gen_helper_b_gate_priv(off, tcg_env, + tcg_constant_i64(ctx->iaoq_first + + ctx->iaq_f.disp)); + + ctx->iaq_j.base = off; + ctx->iaq_j.disp = disp + 8; + indirect = true; } #endif @@ -3999,6 +3998,9 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) save_gpr(ctx, a->l, tmp); } + if (indirect) { + return do_ibranch(ctx, 0, false, a->n); + } return do_dbranch(ctx, disp, 0, a->n); } From patchwork Mon May 13 07:47:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2433C25B7B for ; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 41/45] target/hppa: Implement CF_PCREL Date: Mon, 13 May 2024 09:47:13 +0200 Message-Id: <20240513074717.130949-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that the groundwork has been laid, enabling CF_PCREL within the translator proper is a simple matter of updating copy_iaoq_entry and install_iaq_entries. We also need to modify the unwind info, since we no longer have absolute addresses to install. As expected, this reduces the runtime overhead of compilation when running a Linux kernel with address space randomization enabled. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.c | 19 ++++++------ target/hppa/translate.c | 68 ++++++++++++++++++++++++++++------------- 2 files changed, 55 insertions(+), 32 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5f0df0697a..f0507874ce 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -62,10 +62,6 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, *pc = hppa_cpu_get_pc(env_cpu(env)); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - if (hppa_is_pa20(env)) { - cs_base = env->iaoq_f & MAKE_64BIT_MASK(32, 32); - } - /* * The only really interesting case is if IAQ_Back is on the same page * as IAQ_Front, so that we can use goto_tb between the blocks. In all @@ -113,19 +109,19 @@ static void hppa_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = cpu_env(cs); - cpu->env.iaoq_f = data[0]; - if (data[1] != (target_ulong)-1) { - cpu->env.iaoq_b = data[1]; + env->iaoq_f = (env->iaoq_f & TARGET_PAGE_MASK) | data[0]; + if (data[1] != INT32_MIN) { + env->iaoq_b = env->iaoq_f + data[1]; } - cpu->env.unwind_breg = data[2]; + env->unwind_breg = data[2]; /* * Since we were executing the instruction at IAOQ_F, and took some * sort of action that provoked the cpu_restore_state, we can infer * that the instruction was not nullified. */ - cpu->env.psw_n = 0; + env->psw_n = 0; } static bool hppa_cpu_has_work(CPUState *cs) @@ -191,6 +187,9 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) hppa_ptlbe(&cpu->env); } #endif + + /* Use pc-relative instructions always to simplify the translator. */ + tcg_cflags_set(cs, CF_PCREL); } static void hppa_cpu_initfn(Object *obj) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index fa79116d5b..79e29d722f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -47,7 +47,7 @@ typedef struct DisasIAQE { TCGv_i64 space; /* IAOQ base; may be null for relative address. */ TCGv_i64 base; - /* IAOQ addend; if base is null, relative to ctx->iaoq_first. */ + /* IAOQ addend; if base is null, relative to cpu_iaoq_f. */ int64_t disp; } DisasIAQE; @@ -664,11 +664,7 @@ static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, const DisasIAQE *src) { - if (src->base == NULL) { - tcg_gen_movi_i64(dest, ctx->iaoq_first + src->disp); - } else { - tcg_gen_addi_i64(dest, src->base, src->disp); - } + tcg_gen_addi_i64(dest, src->base ? : cpu_iaoq_f, src->disp); } static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, @@ -680,8 +676,28 @@ static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, b_next = iaqe_incr(f, 4); b = &b_next; } - copy_iaoq_entry(ctx, cpu_iaoq_f, f); - copy_iaoq_entry(ctx, cpu_iaoq_b, b); + + /* + * There is an edge case + * bv r0(rN) + * b,l disp,r0 + * for which F will use cpu_iaoq_b (from the indirect branch), + * and B will use cpu_iaoq_f (from the direct branch). + * In this case we need an extra temporary. + */ + if (f->base != cpu_iaoq_b) { + copy_iaoq_entry(ctx, cpu_iaoq_b, b); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + } else if (f->base == b->base) { + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, b->disp - f->disp); + } else { + TCGv_i64 tmp = tcg_temp_new_i64(); + copy_iaoq_entry(ctx, tmp, b); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + tcg_gen_mov_i64(cpu_iaoq_b, tmp); + } + if (f->space) { tcg_gen_mov_i64(cpu_iasq_f, f->space); } @@ -3979,9 +3995,8 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) /* Adjust the dest offset for the privilege change from the PTE. */ TCGv_i64 off = tcg_temp_new_i64(); - gen_helper_b_gate_priv(off, tcg_env, - tcg_constant_i64(ctx->iaoq_first - + ctx->iaq_f.disp)); + copy_iaoq_entry(ctx, off, &ctx->iaq_f); + gen_helper_b_gate_priv(off, tcg_env, off); ctx->iaq_j.base = off; ctx->iaq_j.disp = disp + 8; @@ -4602,7 +4617,7 @@ static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - uint64_t cs_base, iaoq_f, iaoq_b; + uint64_t cs_base; int bound; ctx->cs = cs; @@ -4621,12 +4636,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) : ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); #endif - /* Recover the IAOQ values from the GVA + PRIV. */ cs_base = ctx->base.tb->cs_base; - iaoq_f = cs_base & MAKE_64BIT_MASK(32, 32); - iaoq_f |= ctx->base.pc_first & MAKE_64BIT_MASK(2, 30); - iaoq_f |= ctx->privilege; - ctx->iaoq_first = iaoq_f; + ctx->iaoq_first = ctx->base.pc_first + ctx->privilege; if (unlikely(cs_base & CS_BASE_DIFFSPACE)) { ctx->iaq_b.space = cpu_iasq_b; @@ -4634,8 +4645,9 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) } else if (unlikely(cs_base & CS_BASE_DIFFPAGE)) { ctx->iaq_b.base = cpu_iaoq_b; } else { - iaoq_b = (iaoq_f & TARGET_PAGE_MASK) | (cs_base & ~TARGET_PAGE_MASK); - ctx->iaq_b.disp = iaoq_b - iaoq_f; + uint64_t iaoq_f_pgofs = ctx->iaoq_first & ~TARGET_PAGE_MASK; + uint64_t iaoq_b_pgofs = cs_base & ~TARGET_PAGE_MASK; + ctx->iaq_b.disp = iaoq_b_pgofs - iaoq_f_pgofs; } ctx->zero = tcg_constant_i64(0); @@ -4662,11 +4674,23 @@ static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + uint64_t iaoq_f, iaoq_b; + int64_t diff; tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); - tcg_gen_insn_start(ctx->iaoq_first + ctx->iaq_f.disp, - (iaqe_variable(&ctx->iaq_b) ? -1 : - ctx->iaoq_first + ctx->iaq_b.disp), 0); + + iaoq_f = ctx->iaoq_first + ctx->iaq_f.disp; + if (iaqe_variable(&ctx->iaq_b)) { + diff = INT32_MIN; + } else { + iaoq_b = ctx->iaoq_first + ctx->iaq_b.disp; + diff = iaoq_b - iaoq_f; + /* Direct branches can only produce a 24-bit displacement. */ + tcg_debug_assert(diff == (int32_t)diff); + tcg_debug_assert(diff != INT32_MIN); + } + + tcg_gen_insn_start(iaoq_f & ~TARGET_PAGE_MASK, diff, 0); ctx->insn_start_updated = false; } From patchwork Mon May 13 07:47:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46025C41513 for ; Mon, 13 May 2024 07:54:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QSZ-0005HR-5H; Mon, 13 May 2024 03:50:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QSW-0005EA-Jc for qemu-devel@nongnu.org; Mon, 13 May 2024 03:50:56 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QST-0001yl-7Q for qemu-devel@nongnu.org; Mon, 13 May 2024 03:50:56 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-34f7d8bfaa0so2921723f8f.0 for ; Mon, 13 May 2024 00:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586651; x=1716191451; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OXJrXEo5lvj8nKkiVWwei0sGVNNJi1pj05AdZLYlOuA=; b=Knr9wDdZFJS1hOl1g7yUAlBt1SYoMm/ngxKB8ZDoabfLixRJLwb7fnnFYRlvVsf0up BnxFybrCQu885oPiEDItVdNmMlUSy5e9HGHNYPDLUIZ/d/fBCMVjnO8Ewhp3wo4yDQfS AcIGr+I1QekWmZJUWJ9UASHCpaW5fYvnGAo9HvhIj5A+6zSBzwIeFIVy64+lIwL9oxhY BDMa4FpHpH05ByCstdZhf08Tgj32xBr65BLPM6kjwzAIFyREUb72+trsR90ZK+PDlMpo wR6T+f82L3LvlNqvBAj7ZGoORr73utw34BJo3qYICwleXwbTu3TTQK4lELPwfW3Tq4rQ 89oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586651; x=1716191451; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OXJrXEo5lvj8nKkiVWwei0sGVNNJi1pj05AdZLYlOuA=; b=nUyyEG8y1D7FlUEsrsTtAvxn7WXMqT8cQAf84/PpgkyWpA06frZIS+dgGV++8W2GXI wEiFzsX2VFCqpGQhGO+WDtoa05t9z94BUCFEgahDpANmHi6Fiyue60kWg+12H8elImtl 75gvyVko9g1Oj/LzvB+IXd10ZReXiINMwwaDofeckTwNH7q+NxVN8IBQ3b9zYx2QvN7Y dYnGt858nCRGmads2aJEOkr++Z9xXQycF+HU8VnJK0vWnQVK+elvSyA2VtxQCq8LYIPT XyJQm/ngq1YAZewmLY8RsXGnsvuGl3CIIz7Fnrscp7MunVN/cYY8WMauBnY+d/5s8YLy 6pNg== X-Gm-Message-State: AOJu0Yzm/gygs+cusfwhKtsvB9jAVIMkqS1YCnIm8sP+LY6RN7UnuDrr WfPaMdVJJHrUP8SXOBOpPz9UnMeWtTudIv40ziHqdmLlX95aJuQC7Kl9i0IW9ZV+vAxojbF5mud kv9w= X-Google-Smtp-Source: AGHT+IEy1eM5gQjJ9nVtgG/VVDukr7JjpYwiouKvmDReuIdoSEkFMB3C7PT33ZhdfyIv/RVWs87idg== X-Received: by 2002:adf:ed8d:0:b0:34d:b993:fe6e with SMTP id ffacd0b85a97d-3504a20a400mr6013029f8f.0.1715586651394; Mon, 13 May 2024 00:50:51 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 42/45] target/hppa: Implement PSW_T Date: Mon, 13 May 2024 09:47:14 +0200 Message-Id: <20240513074717.130949-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org PSW_T enables a trap on taken branches, at the very end of the execution of the branch instruction. Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 4 +-- target/hppa/translate.c | 55 +++++++++++++++++++++++++++++++---------- 2 files changed, 44 insertions(+), 15 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index f0507874ce..2a3b5fc498 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -76,10 +76,10 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; } - /* ??? E, T, H, L bits need to be here, when implemented. */ + /* ??? E, H, L bits need to be here, when implemented. */ flags |= env->psw_n * PSW_N; flags |= env->psw_xb; - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P | PSW_T); #ifdef CONFIG_USER_ONLY flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 79e29d722f..2290dc8533 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1873,6 +1873,23 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, return nullify_end(ctx); } +static bool do_taken_branch_trap(DisasContext *ctx, DisasIAQE *next, bool n) +{ + if (unlikely(ctx->tb_flags & PSW_T)) { + /* + * The X, B and N bits are updated, and the instruction queue + * is advanced before the trap is recognized. + */ + nullify_set(ctx, n); + store_psw_xb(ctx, PSW_B); + install_iaq_entries(ctx, &ctx->iaq_b, next); + gen_excp_1(EXCP_TB); + ctx->base.is_jmp = DISAS_NORETURN; + return true; + } + return false; +} + /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ static bool do_dbranch(DisasContext *ctx, int64_t disp, @@ -1882,6 +1899,9 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); + if (do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { + return true; + } if (is_n) { if (use_nullify_skip(ctx)) { nullify_set(ctx, 0); @@ -1898,7 +1918,9 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, nullify_over(ctx); install_link(ctx, link, false); - if (is_n && use_nullify_skip(ctx)) { + if (do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { + /* done */ + } else if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); @@ -1960,7 +1982,9 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, n = is_n && disp >= 0; next = iaqe_branchi(ctx, disp); - if (n && use_nullify_skip(ctx)) { + if (do_taken_branch_trap(ctx, &next, is_n)) { + /* done */ + } else if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); store_psw_xb(ctx, 0); gen_goto_tb(ctx, 1, &next, NULL); @@ -1990,6 +2014,9 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, { if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, with_sr0); + if (do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { + return true; + } if (is_n) { if (use_nullify_skip(ctx)) { install_iaq_entries(ctx, &ctx->iaq_j, NULL); @@ -2005,20 +2032,22 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, } nullify_over(ctx); - install_link(ctx, link, with_sr0); - if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, &ctx->iaq_j, NULL); - nullify_set(ctx, 0); - store_psw_xb(ctx, 0); - } else { - install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); - nullify_set(ctx, is_n); - store_psw_xb(ctx, PSW_B); + + if (!do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { + if (is_n && use_nullify_skip(ctx)) { + install_iaq_entries(ctx, &ctx->iaq_j, NULL); + nullify_set(ctx, 0); + store_psw_xb(ctx, 0); + } else { + install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); + nullify_set(ctx, is_n); + store_psw_xb(ctx, PSW_B); + } + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp = DISAS_NORETURN; } - tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp = DISAS_NORETURN; return nullify_end(ctx); } From patchwork Mon May 13 07:47:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 379E4C25B10 for ; Mon, 13 May 2024 07:54:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QSb-0005Lf-BD; Mon, 13 May 2024 03:51:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QSY-0005Fa-CM for qemu-devel@nongnu.org; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 43/45] target/hppa: Implement PSW_H, PSW_L Date: Mon, 13 May 2024 09:47:15 +0200 Message-Id: <20240513074717.130949-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 4 +-- target/hppa/translate.c | 68 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 64 insertions(+), 8 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2a3b5fc498..f53e5a2788 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -76,10 +76,10 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; } - /* ??? E, H, L bits need to be here, when implemented. */ + /* ??? E bits need to be here, when implemented. */ flags |= env->psw_n * PSW_N; flags |= env->psw_xb; - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P | PSW_T); + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_H | PSW_L | PSW_P | PSW_T); #ifdef CONFIG_USER_ONLY flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2290dc8533..3ccec023af 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -56,6 +56,7 @@ typedef struct DisasDelayException { TCGLabel *lab; uint32_t insn; bool set_iir; + bool set_b; int8_t set_n; uint8_t excp; /* Saved state at parent insn. */ @@ -745,6 +746,7 @@ static DisasDelayException *delay_excp(DisasContext *ctx, uint8_t excp) e->insn = ctx->insn; e->set_iir = true; e->set_n = ctx->psw_n_nonzero ? 0 : -1; + e->set_b = false; e->excp = excp; e->iaq_f = ctx->iaq_f; e->iaq_b = ctx->iaq_b; @@ -1873,6 +1875,54 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, return nullify_end(ctx); } +/* + * Since B,GATE can only increase priv, and other indirect branches can + * only decrease priv, we only need to test in one direction. + * If maybe_priv == 0, no priv is possible with the current insn; + * if maybe_priv < 0, priv might increase, otherwise priv might decrease. + */ +static void do_priv_branch_trap(DisasContext *ctx, int maybe_priv, + DisasIAQE *next, bool n) +{ + DisasDelayException *e; + uint32_t psw_bit, excp; + TCGv_i64 new_priv; + TCGCond cond; + + if (likely(maybe_priv == 0)) { + return; + } + if (maybe_priv < 0) { + psw_bit = PSW_H; + excp = EXCP_HPT; + cond = TCG_COND_LTU; + } else { + psw_bit = PSW_L; + excp = EXCP_LPT; + cond = TCG_COND_GTU; + } + if (likely(!(ctx->tb_flags & psw_bit))) { + return; + } + + e = tcg_malloc(sizeof(DisasDelayException)); + memset(e, 0, sizeof(*e)); + e->next = ctx->delay_excp_list; + ctx->delay_excp_list = e; + + e->lab = gen_new_label(); + e->set_n = n ? 1 : ctx->psw_n_nonzero ? 0 : -1; + e->set_b = ctx->psw_xb != PSW_B; + e->excp = excp; + e->iaq_f = ctx->iaq_b; + e->iaq_b = *next; + + new_priv = tcg_temp_new_i64(); + copy_iaoq_entry(ctx, new_priv, next); + tcg_gen_andi_i64(new_priv, new_priv, 3); + tcg_gen_brcondi_i64(cond, new_priv, ctx->privilege, e->lab); +} + static bool do_taken_branch_trap(DisasContext *ctx, DisasIAQE *next, bool n) { if (unlikely(ctx->tb_flags & PSW_T)) { @@ -2010,10 +2060,12 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, * This handles nullification of the branch itself. */ static bool do_ibranch(DisasContext *ctx, unsigned link, - bool with_sr0, bool is_n) + bool with_sr0, bool is_n, int maybe_priv) { if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, with_sr0); + + do_priv_branch_trap(ctx, maybe_priv, &ctx->iaq_j, is_n); if (do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { return true; } @@ -2034,6 +2086,7 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, nullify_over(ctx); install_link(ctx, link, with_sr0); + do_priv_branch_trap(ctx, maybe_priv, &ctx->iaq_j, is_n); if (!do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { if (is_n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, &ctx->iaq_j, NULL); @@ -3994,7 +4047,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) tcg_gen_addi_i64(ctx->iaq_j.base, load_gpr(ctx, a->b), a->disp); ctx->iaq_j.base = do_ibranch_priv(ctx, ctx->iaq_j.base); - return do_ibranch(ctx, a->l, true, a->n); + return do_ibranch(ctx, a->l, true, a->n, ctx->privilege == 3 ? 0 : 1); } static bool trans_bl(DisasContext *ctx, arg_bl *a) @@ -4043,7 +4096,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) } if (indirect) { - return do_ibranch(ctx, 0, false, a->n); + return do_ibranch(ctx, 0, false, a->n, -1); } return do_dbranch(ctx, disp, 0, a->n); } @@ -4061,7 +4114,7 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) tcg_gen_add_i64(t0, t0, t1); ctx->iaq_j = iaqe_next_absv(ctx, t0); - return do_ibranch(ctx, a->l, false, a->n); + return do_ibranch(ctx, a->l, false, a->n, 0); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ return do_dbranch(ctx, 0, a->l, a->n); @@ -4082,7 +4135,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) dest = do_ibranch_priv(ctx, dest); ctx->iaq_j = iaqe_next_absv(ctx, dest); - return do_ibranch(ctx, 0, false, a->n); + return do_ibranch(ctx, 0, false, a->n, ctx->privilege == 3 ? 0 : 1); } static bool trans_bve(DisasContext *ctx, arg_bve *a) @@ -4095,7 +4148,7 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) ctx->iaq_j.base = do_ibranch_priv(ctx, b); ctx->iaq_j.disp = 0; - return do_ibranch(ctx, a->l, false, a->n); + return do_ibranch(ctx, a->l, false, a->n, ctx->privilege == 3 ? 0 : 1); } static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) @@ -4853,6 +4906,9 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) if (e->set_n >= 0) { tcg_gen_movi_i64(cpu_psw_n, e->set_n); } + if (e->set_b) { + tcg_gen_movi_i32(cpu_psw_xb, PSW_B); + } if (e->set_iir) { tcg_gen_st_i64(tcg_constant_i64(e->insn), tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); From patchwork Mon May 13 07:47:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663152 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB4CDC25B78 for ; Mon, 13 May 2024 07:54:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QSX-0005F8-Rz; Mon, 13 May 2024 03:50:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QSW-0005E3-GR for qemu-devel@nongnu.org; Mon, 13 May 2024 03:50:56 -0400 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QSU-0001z6-KG for qemu-devel@nongnu.org; Mon, 13 May 2024 03:50:56 -0400 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-51f45104ef0so4193757e87.3 for ; Mon, 13 May 2024 00:50:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586653; x=1716191453; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=420RbZAGJjbzrfJsdBQyYhnJyXLQSLvrDO7PgYHuwLQ=; b=bwSD3UgsgHnQAO1SdY6P4BYhDUvHoNxPP4WF8KoKYd7mjjSdbdMjRTqaq+qVjZcdRy GpkaRUnpH13+0x+FBr4xFBr1srtl6oH2419sKdPOwjO70myy8xr0RKgoe5T0vi+RVruo pmk6LOGNRhxQtgxfcQqBNlKMjoHmRtiv2toUk08pV6Nl7+nXikUDaTOFlNmfiKLYN05q PcJ4pnfX3sJ12raG8MR9LcO/xyKUw42qQTkpf+NeercQsUDingYgJAF1NU0vokkriGze kN6lrYhJc16eKkW42u+qIuLrvmrPI0ala5H6Lywf666x96yfjFxP14Nas9zLgemSiG5k 7XMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586653; x=1716191453; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=420RbZAGJjbzrfJsdBQyYhnJyXLQSLvrDO7PgYHuwLQ=; b=QS3qui96/u/SphuwJppn7YVOYrl1v53ja9V6HIjC2sqkrvBFI3irE6s9TXHv4S/SXz w/U5yWV950k0bSKW1GodrOWFNWf2ePcWN3XtZpAgtYzli1QJLrNXzKS7dgUbj92MO37p IQsRp774H4z6x+oULUl5Fgyb5HTts1jWVcE6w0kSF0qOhRU6VamW+YtoICk4Yv3jEgzH R7eRAAWXdRvNeX+T/YdfczHULr+BLpHWfHy85s3xugubnKGcrAayO6a5vMHr/W0R2jwZ ha+d0Bm4z75Wb4QIOFLNirdPAD+FpthBXk7zjSR2JeT5X/YubtoaO+8Ce1CMs6gsi62T 7cqg== X-Gm-Message-State: AOJu0Yx7xSDHNvVd5q4/3K8mkRUI7w15E2WZKZ+ESxyn/FK6gOz5NhIK SV1MhTD8fqCCZNGf7xGdlN5XMDgYpIov04vXXHYLf7R5wrTysCG8UVwjU7/ozoHvZvxzeanAVsd TPHU= X-Google-Smtp-Source: AGHT+IFqeJ8lRT+z8knIpyx0JG9QUHlUGV1efyinRARrAevIsLdT0QhjCeN0QjBDZmwXiKs/E91VNw== X-Received: by 2002:a05:6512:402a:b0:520:dc1c:3c5d with SMTP id 2adb3069b0e04-5220fe799a5mr7038308e87.42.1715586652841; Mon, 13 May 2024 00:50:52 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index b82f32fd12..391f32f27d 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -241,21 +241,22 @@ void hppa_cpu_do_interrupt(CPUState *cs) [EXCP_SYSCALL_LWS] = "syscall-lws", [EXCP_TOC] = "TOC (transfer of control)", }; - static int count; - const char *name = NULL; - char unknown[16]; - if (i >= 0 && i < ARRAY_SIZE(names)) { - name = names[i]; + FILE *logfile = qemu_log_trylock(); + if (logfile) { + const char *name = NULL; + + if (i >= 0 && i < ARRAY_SIZE(names)) { + name = names[i]; + } + if (name) { + fprintf(logfile, "INT: cpu %d %s\n", cs->cpu_index, name); + } else { + fprintf(logfile, "INT: cpu %d unknown %d\n", cs->cpu_index, i); + } + hppa_cpu_dump_state(cs, logfile, 0); + qemu_log_unlock(logfile); } - if (!name) { - snprintf(unknown, sizeof(unknown), "unknown %d", i); - name = unknown; - } - qemu_log("INT %6d: %s @ " TARGET_FMT_lx ":" TARGET_FMT_lx - " for " TARGET_FMT_lx ":" TARGET_FMT_lx "\n", - ++count, name, env->cr[CR_IIASQ], env->cr[CR_IIAOQ], - env->cr[CR_ISR], env->cr[CR_IOR]); } cs->exception_index = -1; } From patchwork Mon May 13 07:47:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13663137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CA2AC25B10 for ; Mon, 13 May 2024 07:52:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s6QSc-0005Oh-N9; Mon, 13 May 2024 03:51:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s6QSX-0005FC-Tt for qemu-devel@nongnu.org; Mon, 13 May 2024 03:50:57 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s6QSU-0001zD-W3 for qemu-devel@nongnu.org; Mon, 13 May 2024 03:50:57 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-34e28e32ea4so2520456f8f.2 for ; Mon, 13 May 2024 00:50:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715586653; x=1716191453; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IL2hAokqpmQr3sSx0rCsqvvhI5ki9eqOu02SaoXaEMQ=; b=wqDvvEL66jQSH8KvL0FPFNSZOR4vRc16C+dKHkpq/5/arxF54cNdxDRwlh2sBrfjWU oUuq5eKmdVfxO7NSc+vICJiy5Zq3K7L9m/vXZAKu55q7TwR96nzpuRNv4q3WNfVX3OMX 0xHV4JrgvVjBTT7QU4C3mNsQIA2vSIdNS+3rj54terTxzYbdRPrqZISZ1aw1PfdjeG/K r1cE99I4ZXvGYR38RsaEaaMbcyz/ebCuq0rmATR9BLwuqfiWC1Rmi6TgZ7EczesQuh8M nWmIvxzkQARztLaD9R8QqW74fZ3q9ndKFfKU6hXsXZK0TWiRmklgCKQznGgutWrbI5XB i++A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715586653; x=1716191453; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IL2hAokqpmQr3sSx0rCsqvvhI5ki9eqOu02SaoXaEMQ=; b=PcWsWzJFcL1l5LdRWYmpNPEYC4yXZB0SvNBEYLnq2w29FT13Jjv2eU/R8k+baU45TZ SVJS3dUKC8bazCPZsx8DJUUPywoQdgZKS5pzV8Vy1xt3867+M9hJJA4ZiPXnWK6A4R4b ifJdIh0OihwByPROXI89tL5M24kChWtaJWLjHH5f8DcjFiJoXwaR1zNA+sp59J2bdn2/ K723IDg/29ny2u2mSoQX3YRqE8IJoE8fSta2gk9mzIQ6VGUyn77PbYdk8HyLGiwy/2Bm vAblgiQMf6NpXHqvw2ny7pjeDiFqZk30Q3IeXFxL8eyTyo+lZ6JULhM8vC53e9ldqDJ6 JGwg== X-Gm-Message-State: AOJu0Yw/Nh7P1vblfXgaldauBqAI32p/VQAK2Udhoh2qIiAzA9nLKLOg 8TX3EKRZCXbqgQxlWLCL0hGRfUWc1TmCPiNhOGu8AKKt465KW1CCm6dXYShnKyIgRfH+Ud6ANyQ O744= X-Google-Smtp-Source: AGHT+IFXCNQkKT6F9xFmWb1yRl1jHxWjLWM7fQQV+7dDAx1w6JBgoZ+GYV7fdAVXMW7KAklDxJCWcQ== X-Received: by 2002:adf:e649:0:b0:34b:81b3:2c62 with SMTP id ffacd0b85a97d-3504a73e850mr5604558f8f.35.1715586653713; Mon, 13 May 2024 00:50:53 -0700 (PDT) Received: from stoup.. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 45/45] target/hppa: Log cpu state on return-from-interrupt Date: Mon, 13 May 2024 09:47:17 +0200 Message-Id: <20240513074717.130949-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Inverse of the logging on taking an interrupt. Signed-off-by: Richard Henderson --- target/hppa/sys_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index 22d6c89964..9b43b556fd 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -93,6 +94,17 @@ void HELPER(rfi)(CPUHPPAState *env) env->iaoq_b = env->cr_back[1]; env->iasq_f = (env->cr[CR_IIASQ] << 32) & ~(env->iaoq_f & mask); env->iasq_b = (env->cr_back[0] << 32) & ~(env->iaoq_b & mask); + + if (qemu_loglevel_mask(CPU_LOG_INT)) { + FILE *logfile = qemu_log_trylock(); + if (logfile) { + CPUState *cs = env_cpu(env); + + fprintf(logfile, "RFI: cpu %d\n", cs->cpu_index); + hppa_cpu_dump_state(cs, logfile, 0); + qemu_log_unlock(logfile); + } + } } static void getshadowregs(CPUHPPAState *env)