From patchwork Tue May 14 05:09:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongxing Zhu X-Patchwork-Id: 13663792 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 556E114A96 for ; Tue, 14 May 2024 05:28:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715664526; cv=none; b=atvbhQBz7FSmQLlUsSWbMdLztu68nXIivfyWEOCvlO8VuSkJyd3kBfHk7+7ZY1YPKK5cPuKyQDddwQruYxCNEGbwwNeqoYVzG4YTlwXod4VlxMBfZPZYvf7Gk2OFaOV21lmf520ETzSMesRezQO8jeiqyJYRCZaGJ6nQRnea/1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715664526; c=relaxed/simple; bh=NRqzaYlat30Cka6lLWm1QfveJqU5KFy7bW8Zc9IvWpI=; h=From:To:Cc:Subject:Date:Message-Id; b=q5YTI1nlWEjyIZrjULWQEa8xWql8lyULcj3htX0O1gMn9xNHi24MFqW6QsJQ76KYPwb0sOCBf4dx1WGYJezNy8BmbiPlUR708BK4Y++PnOK42sc++yiMpjnqU9EKCRIZtEjeQegOB04VOycfT4qVonCPV+RrTtnWdHJx5Tho4uY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 59DB71A0BC9; Tue, 14 May 2024 07:28:38 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 0FA831A0BA8; Tue, 14 May 2024 07:28:38 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 56BBC1820F77; Tue, 14 May 2024 13:28:36 +0800 (+08) From: Richard Zhu To: bhelgaas@google.com, lorenzo.pieralisi@arm.com, frank.li@nxp.com, mani@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev, Richard Zhu Subject: [PATCH v1] PCI: dwc: Fix resume failure if no EP is connected at some platforms. Date: Tue, 14 May 2024 13:09:18 +0800 Message-Id: <1715663358-8900-1-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: The dw_pcie_suspend_noirq() function currently returns success directly if no endpoint (EP) device is connected. However, on some platforms, power loss occurs during suspend, causing dw_resume() to do nothing in this case. This results in a system halt because the DWC controller is not initialized after power-on during resume. Change call to deinit() in suspend and init() at resume regardless of whether there are EP device connections or not. It is not harmful to perform deinit() and init() again for the no power-off case, and it keeps the code simple and consistent in logic. Fixes: 4774faf854f5 ("PCI: dwc: Implement generic suspend/resume functionality") Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=controller/dwc This patch depends on the branch listed above, because it's not in pci-next. But suppose it will be in there soon. .../pci/controller/dwc/pcie-designware-host.c | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index a0822d5371bc5..cb8c3c2bcc790 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -933,23 +933,23 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1) return 0; - if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) - return 0; - - if (pci->pp.ops->pme_turn_off) - pci->pp.ops->pme_turn_off(&pci->pp); - else - ret = dw_pcie_pme_turn_off(pci); + if (dw_pcie_get_ltssm(pci) > DW_PCIE_LTSSM_DETECT_ACT) { + /* Only send out PME_TURN_OFF when PCIE link is up */ + if (pci->pp.ops->pme_turn_off) + pci->pp.ops->pme_turn_off(&pci->pp); + else + ret = dw_pcie_pme_turn_off(pci); - if (ret) - return ret; + if (ret) + return ret; - ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, - PCIE_PME_TO_L2_TIMEOUT_US/10, - PCIE_PME_TO_L2_TIMEOUT_US, false, pci); - if (ret) { - dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); - return ret; + ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, + PCIE_PME_TO_L2_TIMEOUT_US/10, + PCIE_PME_TO_L2_TIMEOUT_US, false, pci); + if (ret) { + dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); + return ret; + } } if (pci->pp.ops->deinit)