From patchwork Tue May 14 12:02:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13664027 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 459B743AD7; Tue, 14 May 2024 12:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688190; cv=none; b=VrYHAfwOuuMY/yz+w4dpWy3ZpKbv3kXKWh0O6gafeiGhmnR/5QmObmprPQjQizCTQ4hVzlC4jthJGSSeDqI3S9rGCSWjbbN0DNtimF5SvJqUTnRfksNZlufmDOOqSFS5mUaEf5+Xt4F+2RagqoLJCXN0iWpNKBGyHDVAOkVikDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688190; c=relaxed/simple; bh=6Ot2Zt8xQ6gTbpCKhK6ZQoVffyGKgVaC07JA7IwyaZk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A99Adnq0VbrvXQB3fFu2Ey6NAIOWV46PIsCfD9Kjk/tVXGPgHEKEkBQgl+QGOHvupmlCnzJMHN7X1PCa3lSpd9jeBZ3NKPwWJ1i6UbJemGvdwp+GkRBNNF6Ucobvgf2pyOYLc2zX3wgMDA7qBg5QKHSe4RZ35VIlVaZgr7SiJyU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DbPK5rCY; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DbPK5rCY" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-34eb52bfca3so4831475f8f.0; Tue, 14 May 2024 05:03:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715688186; x=1716292986; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3wShCpOhd/iedbhwtjzlwTTiwMIbq6GX/2w8mb07zQE=; b=DbPK5rCYsEyxU7/djfnFWkuEHHsFI8kQdhnNHKfSa3eI5I8SXm5ZvYUQGcy3poAQ5W DXEhImWY7JzxmUeNsJSmCevUjZaHgVjciH/yDEh83R+nZV1IpbnBhbotpWEi0qli+0AQ fTmUuroidgGgw924V3KWvOo77IZlSGUnMLHqSI/wbzmXRjtFokSfe2iO9mnAKS7cibgm c/vmHSxQ+xiclwr39wUBnpmNo0pnaQk56jLR2ihybP3MSOrO1dBBVDK8IlgQVyZft4Yl 14QYu7sQirmtKygkC0cOiuMOHt6N5NVWymyFBZtkrVNvHNqSDP5HXEF4DgkrPRUT+y1H ntPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715688186; x=1716292986; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3wShCpOhd/iedbhwtjzlwTTiwMIbq6GX/2w8mb07zQE=; b=HBNiGyQcUpPs+MHs+sb3KR20N0QWE6OUkYmbJ/MKNNmPnbQEubYZ04UXgHIyRwnGQP 57ozvPOAUtaO6nim+jww1EwRWcJYDaLcf8dJUUQxOxb7hSvZCtK0mVsH+hKbMCW3CsXN G4t1z/1oNNkYfn/ELFnWbyBCWZT0i/+O1PFY81GX/qXNxI8XHdfIMIWWgY+Hbd63xf1K aT8fbCqI/eZuY0rB/3gXWKc62hWBLD1okMfdIJrJ3kVvcxOMUIqzPIsw437m3Vp22EoF bLVBku2VuKYiDz8DSBBjAVjytO/Zmmys4B7t+5z/X7kX/bcyEY9UO7eaSMIgSlVd/Rp3 NXQw== X-Forwarded-Encrypted: i=1; AJvYcCVoHeEDZ+/7lEcKXp4nIGJxkFNcsUKoU5m41sI9Srz9asJAupoQczJw1IqmXMm7CYFhT4DE+j0jUEDdLjlIJoNXD+lLfHS9991+hFl9a25WBFNMzxot3K+zUJEkv0aD31lkSc3Al5dJIGCNj7gyWQNTKSkO8rda4nn2qsjE+xH9e5G5qA== X-Gm-Message-State: AOJu0Yx3fAjXtjaZAxUHxptbysnJwJ3me/ZWPtVeIJH2hK6tWK9kJ6wh nZP+VVE+TgiSi/ka256elkXfE+pbFLwKbJntjiXggm0H0IewaJO7 X-Google-Smtp-Source: AGHT+IF1a0jH5jIVuFxznr5QdpiLEiQgPPglZXTXHsPzv2TPyfUR2w82XhovUswZJ6dMVjD9/K1EXA== X-Received: by 2002:a5d:4fd0:0:b0:34b:dc21:68f2 with SMTP id ffacd0b85a97d-3504a738229mr11790901f8f.28.1715688186251; Tue, 14 May 2024 05:03:06 -0700 (PDT) Received: from spiri.. ([2a02:2f08:a105:8300:5179:8171:3530:3b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a06sm13593927f8f.27.2024.05.14.05.03.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 May 2024 05:03:06 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: michael.hennerich@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, andy@kernel.org, nuno.sa@analog.com, marcelo.schmitt@analog.com, bigunclemax@gmail.com, dlechner@baylibre.com, okan.sahin@analog.com, fr0st61te@gmail.com, alisa.roman@analog.com, marcus.folkesson@gmail.com, schnelle@linux.ibm.com, liambeguin@gmail.com Subject: [PATCH v8 1/6] iio: adc: ad7192: Use standard attribute Date: Tue, 14 May 2024 15:02:17 +0300 Message-Id: <20240514120222.56488-2-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240514120222.56488-1-alisa.roman@analog.com> References: <20240514120222.56488-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Replace custom attribute filter_low_pass_3db_frequency_available with standard attribute. Store the available values in ad7192_state struct. The function that used to compute those values replaced by ad7192_update_filter_freq_avail(). Function ad7192_show_filter_avail() is no longer needed. Note that the initial available values are hardcoded. Also moved the mutex lock and unlock in order to protect the whole switch statement since each branch modifies the state of the device. Reviewed-by: David Lechner Signed-off-by: Alisa-Dariana Roman --- drivers/iio/adc/ad7192.c | 75 ++++++++++++++++++---------------------- 1 file changed, 34 insertions(+), 41 deletions(-) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index 7bcc7e2aa2a2..ace81e3817a1 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -190,6 +190,7 @@ struct ad7192_state { u32 mode; u32 conf; u32 scale_avail[8][2]; + u32 filter_freq_avail[4][2]; u32 oversampling_ratio_avail[4]; u8 gpocon; u8 clock_sel; @@ -473,6 +474,16 @@ static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev) st->oversampling_ratio_avail[2] = 8; st->oversampling_ratio_avail[3] = 16; + st->filter_freq_avail[0][0] = 600; + st->filter_freq_avail[1][0] = 800; + st->filter_freq_avail[2][0] = 2300; + st->filter_freq_avail[3][0] = 2720; + + st->filter_freq_avail[0][1] = 1000; + st->filter_freq_avail[1][1] = 1000; + st->filter_freq_avail[2][1] = 1000; + st->filter_freq_avail[3][1] = 1000; + return 0; } @@ -586,48 +597,24 @@ static int ad7192_get_f_adc(struct ad7192_state *st) f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); } -static void ad7192_get_available_filter_freq(struct ad7192_state *st, - int *freq) +static void ad7192_update_filter_freq_avail(struct ad7192_state *st) { unsigned int fadc; /* Formulas for filter at page 25 of the datasheet */ fadc = ad7192_compute_f_adc(st, false, true); - freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); + st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); fadc = ad7192_compute_f_adc(st, true, true); - freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); + st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); fadc = ad7192_compute_f_adc(st, false, false); - freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024); + st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024); fadc = ad7192_compute_f_adc(st, true, false); - freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024); + st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024); } -static ssize_t ad7192_show_filter_avail(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct iio_dev *indio_dev = dev_to_iio_dev(dev); - struct ad7192_state *st = iio_priv(indio_dev); - unsigned int freq_avail[4], i; - size_t len = 0; - - ad7192_get_available_filter_freq(st, freq_avail); - - for (i = 0; i < ARRAY_SIZE(freq_avail); i++) - len += sysfs_emit_at(buf, len, "%d.%03d ", freq_avail[i] / 1000, - freq_avail[i] % 1000); - - buf[len - 1] = '\n'; - - return len; -} - -static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available, - 0444, ad7192_show_filter_avail, NULL, 0); - static IIO_DEVICE_ATTR(bridge_switch_en, 0644, ad7192_show_bridge_switch, ad7192_set, AD7192_REG_GPOCON); @@ -637,7 +624,6 @@ static IIO_DEVICE_ATTR(ac_excitation_en, 0644, AD7192_REG_CONF); static struct attribute *ad7192_attributes[] = { - &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, &iio_dev_attr_bridge_switch_en.dev_attr.attr, NULL }; @@ -647,7 +633,6 @@ static const struct attribute_group ad7192_attribute_group = { }; static struct attribute *ad7195_attributes[] = { - &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, &iio_dev_attr_bridge_switch_en.dev_attr.attr, &iio_dev_attr_ac_excitation_en.dev_attr.attr, NULL @@ -665,17 +650,15 @@ static unsigned int ad7192_get_temp_scale(bool unipolar) static int ad7192_set_3db_filter_freq(struct ad7192_state *st, int val, int val2) { - int freq_avail[4], i, ret, freq; + int i, ret, freq; unsigned int diff_new, diff_old; int idx = 0; diff_old = U32_MAX; freq = val * 1000 + val2; - ad7192_get_available_filter_freq(st, freq_avail); - - for (i = 0; i < ARRAY_SIZE(freq_avail); i++) { - diff_new = abs(freq - freq_avail[i]); + for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) { + diff_new = abs(freq - st->filter_freq_avail[i][0]); if (diff_new < diff_old) { diff_old = diff_new; idx = i; @@ -792,10 +775,11 @@ static int ad7192_write_raw(struct iio_dev *indio_dev, if (ret) return ret; + mutex_lock(&st->lock); + switch (mask) { case IIO_CHAN_INFO_SCALE: ret = -EINVAL; - mutex_lock(&st->lock); for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) if (val2 == st->scale_avail[i][1]) { ret = 0; @@ -809,7 +793,6 @@ static int ad7192_write_raw(struct iio_dev *indio_dev, ad7192_calibrate_all(st); break; } - mutex_unlock(&st->lock); break; case IIO_CHAN_INFO_SAMP_FREQ: if (!val) { @@ -826,13 +809,13 @@ static int ad7192_write_raw(struct iio_dev *indio_dev, st->mode &= ~AD7192_MODE_RATE_MASK; st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div); ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + ad7192_update_filter_freq_avail(st); break; case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); break; case IIO_CHAN_INFO_OVERSAMPLING_RATIO: ret = -EINVAL; - mutex_lock(&st->lock); for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) if (val == st->oversampling_ratio_avail[i]) { ret = 0; @@ -845,12 +828,14 @@ static int ad7192_write_raw(struct iio_dev *indio_dev, 3, st->mode); break; } - mutex_unlock(&st->lock); + ad7192_update_filter_freq_avail(st); break; default: ret = -EINVAL; } + mutex_unlock(&st->lock); + iio_device_release_direct_mode(indio_dev); return ret; @@ -888,6 +873,12 @@ static int ad7192_read_avail(struct iio_dev *indio_dev, /* Values are stored in a 2D matrix */ *length = ARRAY_SIZE(st->scale_avail) * 2; + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + *vals = (int *)st->filter_freq_avail; + *type = IIO_VAL_FRACTIONAL; + *length = ARRAY_SIZE(st->filter_freq_avail) * 2; + return IIO_AVAIL_LIST; case IIO_CHAN_INFO_OVERSAMPLING_RATIO: *vals = (int *)st->oversampling_ratio_avail; @@ -956,7 +947,9 @@ static const struct iio_info ad7195_info = { BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ (_mask_all), \ .info_mask_shared_by_type_available = (_mask_type_av), \ - .info_mask_shared_by_all_available = (_mask_all_av), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ + (_mask_all_av), \ .ext_info = (_ext_info), \ .scan_index = (_si), \ .scan_type = { \ From patchwork Tue May 14 12:02:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13664028 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE3B04F602; Tue, 14 May 2024 12:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688192; cv=none; b=hTmeWkNIYI6bXtoZMPngIzp/SBY76ceLVZBtMibtFldcxnai7lPUW279hZXzSYxBwC1G+H6bJNQAIwUkGSpoTTRy2eO/hJyFJNM4EiY+sLbm0iPW8khHxSVyPN8U7/ky7atLVkc7GiW5O/W4GEtG7ynZRq+FcwlVnFjOF41IzTo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688192; c=relaxed/simple; bh=xxXwGUgzcyjKmbdWvmTXYmHdWOU+W3I5jGlXNZcADpY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S1wc+HeCh7bH2AhviOCiMVXPk7kc51LHX/T+1di3rSp3wbP3W1qg6ekYrDWf93syp1Q6Zz4C79qqPicwrsCZNGPOu6RnNodhkOFCUUj//qEnj+0lqHf9/sRJ/67HPlAmvqhBvWfU3B9PzSOA1CQrqQTF7zbvDbTbesrLJfTXRwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eSD13p/Y; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eSD13p/Y" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-420180b58c5so13438875e9.3; Tue, 14 May 2024 05:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715688189; x=1716292989; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sHavMm7bNBHTHKKGjlS2nj7k0TOoIyHmRNV2CUCKaX4=; b=eSD13p/YtcIR4hYDmxXiZ05Fs/egHReDFm160SNaHwJrGTcjoMhoFbtYUWe2THpJft 9OecTFJuWnb2rU2BbmRFioETE9xlHZMT8r4cifVsmCNswT4/y/esLHN1GvNiSZ6FkgRF tyPxRSscO8oAwRcPv7VxA/GM1g6afd9p6SXDBUibK7itbTH8m2eDBlosmzYtqRKM5VL5 yD60YbCEQ9p2xntSUvzbsJnVwALpWqIYnG8JeFa8w3kZbwbgIY1ieeUDNS/PrSQ6iamc x2XucwtolD9s5u1XpGMToghd8R1Jd2N8bzjiPP88pRxC2otRh4tpUVi99Zxehp/0bKTk aDNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715688189; x=1716292989; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sHavMm7bNBHTHKKGjlS2nj7k0TOoIyHmRNV2CUCKaX4=; b=hNrFyB4kHy2qSEwNEtrpZBg7lTwP/4AEDFQm0PhMcuDdTaBOn8xCr22nKoiDbexGlF Xa5HkL8Pm5Q54OHvP8XFVwHokshUFXoetISl0bNX/pJQkWsv/+NZ8GDC3jvqZjmWgLpK Avalqui/YHzx2sic2gjk0aVhWPEyhgBWHXOyfYjtCRQW5OEfB4cEBeyCkMnIoyF+9U0D 7eIriAjqwPoAcRbWIZLZ63psVCwWVZ3TudVZCO1s1+3B9A+AjXsVGxC0W+uWsEhHNIhn sXLxfmr05hXD2czZ9eCroimBJnQMzhDGyK9ldQZC7w9DCN9G9CGnWRngHZi6rKNqaZ3k i3cg== X-Forwarded-Encrypted: i=1; AJvYcCVckecw+pEMkQxOprZCUtQT4T1xdulN8JAWlC2go1nSFGOLAFsU6By/kMQ2BaiFiy8OulzG/dDxxJKr1iAAyh/JJlrgXb0GKWCZrYfDfwhOUxo2z+rs933sjIZh4ef+fTRM7jWKsOReXmD7eTx8v0W6jYTvC2W4DRxvz+nn6W2/OyfMoA== X-Gm-Message-State: AOJu0YzWM6rVSqLkGeJlQjIVc3XD7YeSrKZIvfBGMBHGbTA2+TcWTIN2 ZFRRkU66IYS9npaRx1Myo4TJoEOC58wl4R+jwZpHrmVQG23IUO6P X-Google-Smtp-Source: AGHT+IHJOofmHT9w31P5aBOVCtuP1//HCLKm8MNkHj1gB2giujrpiajcutSvE5qnmpVL3tmq+9R/aQ== X-Received: by 2002:a05:600c:4ba2:b0:41a:9fc2:a6b1 with SMTP id 5b1f17b1804b1-41feaa4352amr93856665e9.22.1715688189156; Tue, 14 May 2024 05:03:09 -0700 (PDT) Received: from spiri.. ([2a02:2f08:a105:8300:5179:8171:3530:3b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a06sm13593927f8f.27.2024.05.14.05.03.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 May 2024 05:03:08 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: michael.hennerich@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, andy@kernel.org, nuno.sa@analog.com, marcelo.schmitt@analog.com, bigunclemax@gmail.com, dlechner@baylibre.com, okan.sahin@analog.com, fr0st61te@gmail.com, alisa.roman@analog.com, marcus.folkesson@gmail.com, schnelle@linux.ibm.com, liambeguin@gmail.com Subject: [PATCH v8 2/6] dt-bindings: iio: adc: ad7192: Add aincom supply Date: Tue, 14 May 2024 15:02:18 +0300 Message-Id: <20240514120222.56488-3-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240514120222.56488-1-alisa.roman@analog.com> References: <20240514120222.56488-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 AINCOM should actually be a supply. AINx inputs are referenced to AINCOM in pseudo-differential operation mode. AINCOM voltage represents the offset of corresponding channels. Reviewed-by: Rob Herring (Arm) Signed-off-by: Alisa-Dariana Roman --- Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index 16def2985ab4..cf5c568f140a 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -41,6 +41,11 @@ properties: interrupts: maxItems: 1 + aincom-supply: + description: | + AINCOM voltage supply. Analog inputs AINx are referenced to this input + when configured for pseudo-differential operation. + dvdd-supply: description: DVdd voltage supply @@ -117,6 +122,7 @@ examples: clock-names = "mclk"; interrupts = <25 0x2>; interrupt-parent = <&gpio>; + aincom-supply = <&aincom>; dvdd-supply = <&dvdd>; avdd-supply = <&avdd>; vref-supply = <&vref>; From patchwork Tue May 14 12:02:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13664029 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E048D5FEE4; Tue, 14 May 2024 12:03:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688196; cv=none; b=L3/mXybAMMO+BxFnNxyC1fATCZOuIcUgTfQHZzwPGSvVeaU6JZjjtgG27EmcTAYOvIMIsX+ZmYjSa9Ue4FGfKbJ+khaOAF3EDm8GTgItCOJRtexIVOvHiHK6Nbe5QFqE8irKv78qVKIiOQBdVux8FTDhn18phSsAfz+dB0iXUDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688196; c=relaxed/simple; bh=EQWvzqoU04KDHd33CkauRp+nkwkc/ti3p0XhQIZRmF0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qWnZpFTFQ9/ynNADtR1VT7+CAIHwWmg8TE9Gj1o4mnKDG+cWaqC6CUJN8tGXmOdOUWB7y2Okk8lxftG0+qoazEoafKblKh/uGCei4OOO3AGMP34a57EWVOAyn1X6ZX9NXtS9cIDxDGBg3mb17l9vH2RCAhLiLd4hHFvkRBqTSaI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=iICkAfPQ; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iICkAfPQ" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4200ee78f35so22723525e9.1; Tue, 14 May 2024 05:03:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715688193; x=1716292993; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X+ClX4/6SPoY39TuEqmIN0lGGOvZxu0o0KST6aWhbYc=; b=iICkAfPQY6uxqQfWx5ydMROt6xlzY8iozChfKRq1Rc9g4phBkh7QhzujjwI8cUyy9v +lsHJk4CyK2x9nuKqc71lx1DWihE5ZONWGzcdI4jpCp4uXpXhE42fA36Y8xmpPNCfdfr QUwf8Wr2exAcgsR7q4CJxWj41ynPey/6QndZyztvzi3YcD50pt2NEB55gOa395Ho9Bbp py23KvaucfV+PoHRaYO0UC1nIvScDrRLZ7nEum8I/hpImq4qSlk69i24w0z6hDnRH5+L inNz01ze2s76HLc0H0Xm2YTW/f6k261ugMNiErmWWezjTKy/oWxG8k8jKjw1BdtYk1Gq O12w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715688193; x=1716292993; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X+ClX4/6SPoY39TuEqmIN0lGGOvZxu0o0KST6aWhbYc=; b=mzBuBSQ7DqCDu0ToAruf933jnyLGI/FpNU16X5QA9buoTDhJax20C7T0lhB7ZKcLSO vVTAxIkIgS39bWcN9huILWgTjM51BFjD8jtdBICYH/+LpXO3Xb4SoVpiXrOYHExNlj0q sMkwfNwD1cAzHUxEv2Rc9AmGBKb3sivMGvtopGAS1Xn1lUvFtm2Y2F8LDvjlaC12Cy9w 1O6ydzOkZ9rwXjKOHnUP4gdxnLtrONzZTE8CP2TpStL6NCM8yiLS/eoSuqDEO8lUGLY5 YFWDtiAIlhA38DhrxpwyibiLFemIZ4G7I+u/oaStEl9UKQ/uKxqXkWV3oEiXTptYIHQI hTEA== X-Forwarded-Encrypted: i=1; AJvYcCV3nTQiPt8Oko9Tnc/Y8Gk31uXSs4XucQpl2tZJwVSC0r3RDtDX4dQjirFAndfIRxOddTWzj7odbsf8jUIOx4f+f7OXYATmx5G0jrDfV2gFo4eh2YSnpG2iOp2W2G6yQUdODGrqOD9/RKQ842uNm6xlEqJcyTuy1j4mkLylniA/E7Ra8Q== X-Gm-Message-State: AOJu0Yxu1G1bM+m8DKDH8mvSNv6zFltonT9ec9hByPGawL9qIJjrGLT9 VqALbOs7QkQF5tWgO0LHEG2EsAfRDjzudb3yewQvWVUxwJBWdYhq X-Google-Smtp-Source: AGHT+IGwC791NsX0hJyiZ+f+Ii4Nij4DHtoJr93rsArexxpggsnaf8lP60pdL/XPpB7KmwinMiEU0A== X-Received: by 2002:adf:e983:0:b0:34d:106a:1bd2 with SMTP id ffacd0b85a97d-3504a61c827mr11643599f8f.5.1715688193184; Tue, 14 May 2024 05:03:13 -0700 (PDT) Received: from spiri.. ([2a02:2f08:a105:8300:5179:8171:3530:3b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a06sm13593927f8f.27.2024.05.14.05.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 May 2024 05:03:12 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: michael.hennerich@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, andy@kernel.org, nuno.sa@analog.com, marcelo.schmitt@analog.com, bigunclemax@gmail.com, dlechner@baylibre.com, okan.sahin@analog.com, fr0st61te@gmail.com, alisa.roman@analog.com, marcus.folkesson@gmail.com, schnelle@linux.ibm.com, liambeguin@gmail.com Subject: [PATCH v8 3/6] iio: adc: ad7192: Add aincom supply Date: Tue, 14 May 2024 15:02:19 +0300 Message-Id: <20240514120222.56488-4-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240514120222.56488-1-alisa.roman@analog.com> References: <20240514120222.56488-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 AINCOM should actually be a supply. AINx inputs are referenced to AINCOM in pseudo-differential operation mode. AINCOM voltage represents the offset of corresponding channels. Signed-off-by: Alisa-Dariana Roman --- drivers/iio/adc/ad7192.c | 50 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index ace81e3817a1..7160929d32c9 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -186,6 +187,7 @@ struct ad7192_state { struct regulator *vref; struct clk *mclk; u16 int_vref_mv; + u32 aincom_mv; u32 fclk; u32 mode; u32 conf; @@ -742,10 +744,24 @@ static int ad7192_read_raw(struct iio_dev *indio_dev, *val = -(1 << (chan->scan_type.realbits - 1)); else *val = 0; + + switch (chan->type) { + case IIO_VOLTAGE: + /* + * Only applies to pseudo-differential inputs. + * AINCOM voltage has to be converted to "raw" units. + */ + if (st->aincom_mv && !chan->differential) + *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO, + st->scale_avail[gain][1]); + return IIO_VAL_INT; /* Kelvin to Celsius */ - if (chan->type == IIO_TEMP) + case IIO_TEMP: *val -= 273 * ad7192_get_temp_scale(unipolar); - return IIO_VAL_INT; + return IIO_VAL_INT; + default: + return -EINVAL; + } case IIO_CHAN_INFO_SAMP_FREQ: *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024); return IIO_VAL_INT; @@ -1052,6 +1068,7 @@ static int ad7192_probe(struct spi_device *spi) { struct ad7192_state *st; struct iio_dev *indio_dev; + struct regulator *aincom; int ret; if (!spi->irq) { @@ -1067,6 +1084,35 @@ static int ad7192_probe(struct spi_device *spi) mutex_init(&st->lock); + /* + * Regulator aincom is optional to maintain compatibility with older DT. + * Newer firmware should provide a zero volt fixed supply if wired to + * ground. + */ + aincom = devm_regulator_get_optional(&spi->dev, "aincom"); + if (IS_ERR(aincom)) { + if (PTR_ERR(aincom) != -ENODEV) + return dev_err_probe(&spi->dev, PTR_ERR(aincom), + "Failed to get AINCOM supply\n"); + + st->aincom_mv = 0; + } else { + ret = regulator_enable(aincom); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to enable specified AINCOM supply\n"); + + ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, aincom); + if (ret) + return ret; + + ret = regulator_get_voltage(aincom); + if (ret < 0) + return dev_err_probe(&spi->dev, ret, + "Device tree error, AINCOM voltage undefined\n"); + st->aincom_mv = ret / MILLI; + } + st->avdd = devm_regulator_get(&spi->dev, "avdd"); if (IS_ERR(st->avdd)) return PTR_ERR(st->avdd); From patchwork Tue May 14 12:02:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13664030 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 259476D1A1; Tue, 14 May 2024 12:03:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688199; cv=none; b=LtnjqU7YMjlhjvIBrzgH8ekr/esX3yAYEJbEVCOdEXpu1BfNphOnB7E328gYuH7j4h5Vevnst3DHod5YMnt/VzYc8L4Hy8GaG2T7cf4UepQ9gztc7ewJoE0A5xLkhoOrAjiBfqLEJYzOU/vOGw7xhEV8o3h+Nab2UPQb0+bec8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688199; c=relaxed/simple; bh=X8r4hIrOJ9C+pyj1LUuZECEONg78eNjz7pRSFpnWAUc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uY1Y0pdWj+UhoW6A2WdbVP8jSuGkV8hGxHlNZttdMU/gMPrB4y4Lu3jD4advtEiraHu/TYzytIw6p7xFqbW0tjUFxnAL7OvvV+w0lFE04286IOf/ptgNTmrgKUcU/Y1q3YdjP5i7fCa1EBuZsujl3ldcYnRH4W0T1QnUqNEweZs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ipCqiPUD; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ipCqiPUD" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-34db6a299b8so4159502f8f.3; Tue, 14 May 2024 05:03:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715688196; x=1716292996; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PswJmJ1fl3Wt97HYv1Mi+7SG4jeTtm76Cj1AvJ081Rk=; b=ipCqiPUDO798Ifl0sdHEEbKQSr4neaFSC1765PbCR+kcjsgKpg3rKUgeG9gCHOS92P y4AvcK5l5r/YTusGoREzRPamVeLKlJPS2TQiXlOFxSIsjdPQ1YwZmxbxSFNyeN1LuoTQ iyy+yg2Drrp/28Z1zmvM522Z71al2hjQncIQNFAMjQ/ZHg7cT7+Jr3P0P39TZo0pNDD2 KxjWTHbhKnjOGAb6GhD/NmFd7UuGCWb8fkR6zd/t28vGX1KUM0NdY8YuB8gE8jLPjAIt cifWXUlpN2730vNvYkVajASVL/8cdt0d0oIUdSo8bkb9zu2jAA9hdukctDEFPJDMExHU 1Xww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715688196; x=1716292996; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PswJmJ1fl3Wt97HYv1Mi+7SG4jeTtm76Cj1AvJ081Rk=; b=aWpAUq21ROJpkMNpSK124N7EruIb743pN+GjmIFok5WprYQJmVEelPSBFuyLh7ah65 DmsLOs5hofyTgRx2QrmzetqpkKwF7XkRkQ5C2GSd30/ITctR9Wrr99SHfH68lyXxfZE3 I81Z1q1uIhWu9ZE99q2cmEu4bvwy55AZgdXvOJbCqSkbJGrG0VFKfbJcw6eAWqJDKMkE xdBRa7qebw9ui+++BoDYDnLfcDca6HkrVjDrgcpVExWI564GpVjIseRT54h64ocq3fwU gy4Y566/QCPKlNyHEoI4FmB02yqUniBWWQ5uApjdrr9wcEarVm3JSlBHVd8UBfqfJY1X k14w== X-Forwarded-Encrypted: i=1; AJvYcCX/+4Dxxiy79iwsCDl9Lc1WIDLUQsESXr674hJvjMtJyexZvnqbTGDZ1bbkTMqCqnKxVgpoB1J7KTTWBHHmxb+XrJZxXjeNeuGgrSGVwcLaSlvekp3qYUnAeiSeUBmzq8E5CNnRheh9x84r8wiz9jClGl+Wxqm1GM1sjww4GxZjWmGGGg== X-Gm-Message-State: AOJu0Yy3S9dwmKQEnbOsqAZ3TYeFu9rVzhlipiUjiss2lpU2fnAnIh31 hBCB1T9fNPXNFwJ25KS/7ioUGDcAavbsxZafPyaMIdrr06c+SKUt X-Google-Smtp-Source: AGHT+IFrqTl+dhTyyRFP5KW68C8aR4ykId6cwc9RT+MSlr07ZzuvpFvrtwWICJj8yytuM9HhbFBh6A== X-Received: by 2002:adf:c58a:0:b0:34a:56e7:5cc4 with SMTP id ffacd0b85a97d-351bfd2aa96mr4493095f8f.2.1715688196381; Tue, 14 May 2024 05:03:16 -0700 (PDT) Received: from spiri.. ([2a02:2f08:a105:8300:5179:8171:3530:3b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a06sm13593927f8f.27.2024.05.14.05.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 May 2024 05:03:16 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: michael.hennerich@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, andy@kernel.org, nuno.sa@analog.com, marcelo.schmitt@analog.com, bigunclemax@gmail.com, dlechner@baylibre.com, okan.sahin@analog.com, fr0st61te@gmail.com, alisa.roman@analog.com, marcus.folkesson@gmail.com, schnelle@linux.ibm.com, liambeguin@gmail.com Subject: [PATCH v8 4/6] dt-bindings: iio: adc: Add single-channel property Date: Tue, 14 May 2024 15:02:20 +0300 Message-Id: <20240514120222.56488-5-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240514120222.56488-1-alisa.roman@analog.com> References: <20240514120222.56488-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Devices that have both single-ended channels and differential channels cause a bit of confusion when the channels are configured in the devicetree. Clarify difference between these two types of channels for such devices by adding single-channel property alongside diff-channels. They should be mutually exclusive. Devices that have only single-ended channels can still use reg property to reference a channel like before. Suggested-by: Jonathan Cameron Signed-off-by: Alisa-Dariana Roman Reviewed-by: Conor Dooley --- .../devicetree/bindings/iio/adc/adc.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adc.yaml b/Documentation/devicetree/bindings/iio/adc/adc.yaml index 36775f8f71df..0a77592f7388 100644 --- a/Documentation/devicetree/bindings/iio/adc/adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adc.yaml @@ -38,6 +38,14 @@ properties: The first value specifies the positive input pin, the second specifies the negative input pin. + single-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + When devices combine single-ended and differential channels, allow the + channel for a single element to be specified, independent of reg (as for + differential channels). If this and diff-channels are not present reg + shall be used instead. + settling-time-us: description: Time between enabling the channel and first stable readings. @@ -50,4 +58,15 @@ properties: device design and can interact with other characteristics such as settling time. +anyOf: + - oneOf: + - required: + - reg + - diff-channels + - required: + - reg + - single-channel + - required: + - reg + additionalProperties: true From patchwork Tue May 14 12:02:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13664031 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 855F46F077; Tue, 14 May 2024 12:03:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688203; cv=none; b=mQd55fOT7Xq7899Sv4UjHFA9+5kXOfTp5CVnCV6i2BERfjtqJUjR+lDU5GFglc83/GGu18DY+yx66031FuTRo2YCWUwguIW4RiI8IIYrY5EtfniSOfKxm2V4RV7xvVfjvFnm+quA4hOxSWML22LkHrsVKWCdQTQXtqg6EbkYutQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688203; c=relaxed/simple; bh=hPDh075JBpq3peh9Fr0V6GtyB2F0d/4Fij2IT6owDC4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TC4d9i75+6cmalgj2zVVBs/TB4NhH184ZRV512G4Rjz2ctCtOXHJwIuiOmqLcX9NpuS9ZHWhLNwGSn2pgtrWWKYbdFZvlVJOK7dn0vSDDK9ZLf2jZ9hI+o8fAjc1hBO9vJqXhdRizqQMamEBtXA15fsNYkk2tBOjEhSSobAewn8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RnkjSMX8; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RnkjSMX8" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-34eb52bfca3so4831892f8f.0; Tue, 14 May 2024 05:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715688200; x=1716293000; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JSiIXjI+3kMzFgnCbJIBlPNQooVamTjjn6nT5fcwssI=; b=RnkjSMX8FRF+ZNv2sgzNC8B8227Ke1/cBJNBQFRRntYp+Upt0hI78zzn8qgdZM1eL8 GkOYoFkPhr7lOa//gmKjFuIgU6klbT4blW1ZR3NQug7waKiZ1wovQv3/h485NpfokhQ0 exDJ9y2OD7hhKJucLinbv+LO9cIwrUK0JAVsdZvmqwlZ0yBrpg7W1805XkYXy08b4lrm NM62Ds+UMwn2kmV07O+xU5u4JMO3o7Ny1zNCY+1jLJlgLCYKrvgVxdDP9N9CTVjLZldi Ts4Id/6IYWQel15BM7pOPll3T8jNpmwAFENmj2dqsZKx5pCCQxxLFoUhaJ4jOPmsKT4J RW0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715688200; x=1716293000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JSiIXjI+3kMzFgnCbJIBlPNQooVamTjjn6nT5fcwssI=; b=WE5NScYfOZYv9bw4jdWye8hoEt/b++BLu20ajVZe1oGwnfJf3mqc+snbCRIPOSiJwv ydK7Dp4PvYVtpNvKZaDxzlN9CwLtPXH8zQLJ0QGBXqLafmEJQ/+UZbODLYtSSmr40MRq BxcbvTFzi3KDE/WgRxbLPtfmBbxsBWeGWbWQOSvqAgBXfZOiytQ/BFzQvzUbjtb01098 aLd03S7D58em+mH63CVVTCp/YhyHEhUwJOWVDCpKrD6homSK+dk1diQp/N4egcYZvreo Bf27IlMNo5EfteYsF2Q4D+17/GT0fm1t+JDqcTd7VI56stfoWp5Ru8wKnxTb9og1H9k2 HEfA== X-Forwarded-Encrypted: i=1; AJvYcCVKmvIGh9p07f8d1eIKyWygdjgfigeZzElsmo144svH19G/rjNdUyuFDi9Wr++1RqfVyKL7p3ePbF2OWoASoeAgSFzynioUTRo73cq8J5cNeqnvxMw2Nq4pvBs65VN5IU1MUo+7ICodbjJhNB5fe6Lj/o386cS86gvG0rkc/1+7nsCEYA== X-Gm-Message-State: AOJu0YwGkyURj/kIuVXP79b9oJjnrdiIz3ROkRBHP64Fh0bxdPB66WOf dW3CvVwxS7Fkvl+Cnfx5rD1xGfQrty7yrtcNvqodbcwkbbSrU06F9ho6zXjV X-Google-Smtp-Source: AGHT+IGlcB6bUZAHpl/7Dlpmh9vhHUtVRRxWrfO5j0lLI0Z3FCwPOSC9HJTJfBNZjY0fb1jCtlmpcg== X-Received: by 2002:adf:fa4d:0:b0:34d:a8d1:76bd with SMTP id ffacd0b85a97d-3504a73ed8emr12229376f8f.41.1715688199902; Tue, 14 May 2024 05:03:19 -0700 (PDT) Received: from spiri.. ([2a02:2f08:a105:8300:5179:8171:3530:3b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a06sm13593927f8f.27.2024.05.14.05.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 May 2024 05:03:19 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: michael.hennerich@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, andy@kernel.org, nuno.sa@analog.com, marcelo.schmitt@analog.com, bigunclemax@gmail.com, dlechner@baylibre.com, okan.sahin@analog.com, fr0st61te@gmail.com, alisa.roman@analog.com, marcus.folkesson@gmail.com, schnelle@linux.ibm.com, liambeguin@gmail.com Subject: [PATCH v8 5/6] dt-bindings: iio: adc: ad7192: Add AD7194 support Date: Tue, 14 May 2024 15:02:21 +0300 Message-Id: <20240514120222.56488-6-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240514120222.56488-1-alisa.roman@analog.com> References: <20240514120222.56488-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Unlike the other AD719Xs, AD7194 has configurable channels. The user can dynamically configure them in the devicetree. Also add an example for AD7194 devicetree. Signed-off-by: Alisa-Dariana Roman Reviewed-by: Conor Dooley --- .../bindings/iio/adc/adi,ad7192.yaml | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index cf5c568f140a..a03da9489ed9 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -21,8 +21,15 @@ properties: - adi,ad7190 - adi,ad7192 - adi,ad7193 + - adi,ad7194 - adi,ad7195 + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + reg: maxItems: 1 @@ -89,6 +96,42 @@ properties: description: see Documentation/devicetree/bindings/iio/adc/adc.yaml type: boolean +patternProperties: + "^channel@[0-9a-f]+$": + type: object + $ref: adc.yaml + unevaluatedProperties: false + + properties: + reg: + description: The channel index. + minimum: 0 + maximum: 271 + + diff-channels: + description: + Both inputs can be connected to pins AIN1 to AIN16 by choosing the + appropriate value from 1 to 16. + items: + minimum: 1 + maximum: 16 + + single-channel: + description: + Positive input can be connected to pins AIN1 to AIN16 by choosing the + appropriate value from 1 to 16. Negative input is connected to AINCOM. + items: + minimum: 1 + maximum: 16 + + oneOf: + - required: + - reg + - diff-channels + - required: + - reg + - single-channel + required: - compatible - reg @@ -103,6 +146,17 @@ required: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + enum: + - adi,ad7190 + - adi,ad7192 + - adi,ad7193 + - adi,ad7195 + then: + patternProperties: + "^channel@[0-9a-f]+$": false unevaluatedProperties: false @@ -133,3 +187,38 @@ examples: adi,burnout-currents-enable; }; }; + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7194"; + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; + clocks = <&ad7192_mclk>; + clock-names = "mclk"; + interrupts = <25 0x2>; + interrupt-parent = <&gpio>; + aincom-supply = <&aincom>; + dvdd-supply = <&dvdd>; + avdd-supply = <&avdd>; + vref-supply = <&vref>; + + channel@0 { + reg = <0>; + diff-channels = <1 6>; + }; + + channel@1 { + reg = <1>; + single-channel = <1>; + }; + }; + }; From patchwork Tue May 14 12:02:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alisa-Dariana Roman X-Patchwork-Id: 13664032 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF17076033; Tue, 14 May 2024 12:03:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688206; cv=none; b=HIjhU3IkNePkQR9Q18l1OmpPODArvNqC1ZGKWLjESpLeV8O3v5V04BelsOpht0anCniireJRpcSHVxnrOGjknzHLcmeAcVyXLq9kuL3gooNy8cdy/ApFHvo1/BE3hTgrEw/PX8G5UoBD8kNfIefzFEvB4FHVzksQWKLCwNhxYuA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715688206; c=relaxed/simple; bh=ikxE01aoGV4tRcZ7NfOLDfnea7FzmDvezDsUlqxjp3A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rHnQNZ8O1lmkBsf8D2lZHQYzihkVtUfB1O3+FWoRHV0VRt83/ISqxWym6o4kJq92lJmBrxFwcRtFvPXa+Xubp6jLE6ldny7m3eCUAvxxc+MruTE5A/nbTRJGgZHMPjed0PdWXAHTRQKjpKg4+KfdSp5JFFEOxLEvZ4Y2i2hugwE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aIBAgJhv; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aIBAgJhv" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-41ff5e3dc3bso29384635e9.1; Tue, 14 May 2024 05:03:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715688203; x=1716293003; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sa7AlJjKWENRhUjEnOGX/dr50bh+bVd2TQ8DfybLZfk=; b=aIBAgJhvxYlLhnVG+P9++8xdbg8re/hLxwoVgCIS2XlmadefzzfPLjyX5LU2D3FEAf p8rLbVktli7Jo2MWPEBvxquC6nsk2A/qSdHKuaSWSaglFJ4To5Xuwk71MeMJKvI9uDYB nN/8D8oXjyoLELr4ncCeyeK9O5LMTXBd6QLwECvTINRUm7Jo0jBWRShRjQMYhRJafSUI PE63UT7cYh8mduoTYHoFmMuJEQUvjyM4X20bi83/e+x+nBxG+53xDuzKYf6cO7CCACrQ JeWqQLZk4AR3ODWjQDGY2jEsnSqpB9E+uV/2DCNHIqs9CpH+f18T83i2oZnYpXmtDd5m ZFAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715688203; x=1716293003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sa7AlJjKWENRhUjEnOGX/dr50bh+bVd2TQ8DfybLZfk=; b=NpGQ6HN5PA2d8eqzwbp1Yod9mHr2cWWoGJaXMNh2+ehBZx8AYeXDCBXfxZ+o8Gz4qV 3OAj6Bopirl0fdFxMh0UOELpWzJ8jqloZmXj+9JReuJ2ti4zuscMpOtbyUQbW79g9/jR 9nhfs3VEE+J1pQpzbBh8pOrZfzapNqYu/0E5gKypRlz0idF2Ho47jwcQC7mZcgVaUm6c dVvun1ZBKzAYNNJBL5Us16jQd3aF7EpekEDyK4HVNS/zhubVOSZuAOhIz2zDqcONO4EV U4n0JqPQWWoKitYV3Z63IRl5f7mb0u1/v693XPSdVFP8Q9018EmfBFxlx8kRVCNk/F8c wnzg== X-Forwarded-Encrypted: i=1; AJvYcCUmHXBazAmRC7IwJ/fns01L/BpBoFLTsuQW+HaW7bLesMwtV1zPCJaI5bR8AD7uz3ghzpKHj9jbIHIeuU8Glf8LvmwD2Xh4FggoDodz3pjFgbOvAsqWZvSla/ttpZhZdwvMwrP9bhDtsF3o+yxZG8lEfJNql3HRPJv3DxDzr0OlRiTIeg== X-Gm-Message-State: AOJu0YzIkCuv+LldtKpr11JVn3hmE+RoE3iPHAlvyg0EHGgXLE+Q+bJ9 sGoLc/3zCw+d/uUaItbrGiqLWDmuUS/M/w1lJgs+ITQjCBfR+MURl0CnX1RY X-Google-Smtp-Source: AGHT+IG1PZv5YOxQMvoy0pL9eOxPBmMPv+OdHDffcmKNQbmO/5jt1P68iXfcYogmvbpXAvJXkfKxrQ== X-Received: by 2002:adf:e4c7:0:b0:34d:e252:b57d with SMTP id ffacd0b85a97d-3504a73217emr9942037f8f.17.1715688203152; Tue, 14 May 2024 05:03:23 -0700 (PDT) Received: from spiri.. ([2a02:2f08:a105:8300:5179:8171:3530:3b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a06sm13593927f8f.27.2024.05.14.05.03.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 May 2024 05:03:22 -0700 (PDT) From: Alisa-Dariana Roman X-Google-Original-From: Alisa-Dariana Roman To: michael.hennerich@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, andy@kernel.org, nuno.sa@analog.com, marcelo.schmitt@analog.com, bigunclemax@gmail.com, dlechner@baylibre.com, okan.sahin@analog.com, fr0st61te@gmail.com, alisa.roman@analog.com, marcus.folkesson@gmail.com, schnelle@linux.ibm.com, liambeguin@gmail.com Subject: [PATCH v8 6/6] iio: adc: ad7192: Add AD7194 support Date: Tue, 14 May 2024 15:02:22 +0300 Message-Id: <20240514120222.56488-7-alisa.roman@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240514120222.56488-1-alisa.roman@analog.com> References: <20240514120222.56488-1-alisa.roman@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Unlike the other AD719Xs, AD7194 has configurable channels. The user can dynamically configure them in the devicetree. Add sigma_delta_info member to chip_info structure. Since AD7194 is the only chip that has no channel sequencer, num_slots should remain undefined. Also modify config AD7192 description for better scaling. Signed-off-by: Alisa-Dariana Roman --- drivers/iio/adc/Kconfig | 11 ++- drivers/iio/adc/ad7192.c | 147 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 150 insertions(+), 8 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 8db68b80b391..74fecc284f1a 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -88,12 +88,17 @@ config AD7173 called ad7173. config AD7192 - tristate "Analog Devices AD7190 AD7192 AD7193 AD7195 ADC driver" + tristate "Analog Devices AD7192 and similar ADC driver" depends on SPI select AD_SIGMA_DELTA help - Say yes here to build support for Analog Devices AD7190, - AD7192, AD7193 or AD7195 SPI analog to digital converters (ADC). + Say yes here to build support for Analog Devices SPI analog to digital + converters (ADC): + - AD7190 + - AD7192 + - AD7193 + - AD7194 + - AD7195 If unsure, say N (but it's safe to say "Y"). To compile this driver as a module, choose M here: the diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index 7160929d32c9..fe2d8d55fa76 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * AD7190 AD7192 AD7193 AD7195 SPI ADC driver + * AD7192 and similar SPI ADC driver * * Copyright 2011-2015 Analog Devices Inc. */ @@ -129,10 +129,22 @@ #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */ #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */ +#define AD7194_CH_POS(x) (((x) - 1) << 4) +#define AD7194_CH_NEG(x) ((x) - 1) +#define AD7194_CH(p) (BIT(10) | AD7194_CH_POS(p)) + /* 10th bit corresponds to CON18(Pseudo) */ +#define AD7194_DIFF_CH(p, n) (AD7194_CH_POS(p) | AD7194_CH_NEG(n)) +#define AD7194_CH_TEMP 0x100 /* Temp sensor */ +#define AD7194_CH_BASE_NR 2 +#define AD7194_CH_AIN_START 1 +#define AD7194_CH_AIN_NR 16 +#define AD7194_CH_MAX_NR 272 + /* ID Register Bit Designations (AD7192_REG_ID) */ #define CHIPID_AD7190 0x4 #define CHIPID_AD7192 0x0 #define CHIPID_AD7193 0x2 +#define CHIPID_AD7194 0x3 #define CHIPID_AD7195 0x6 #define AD7192_ID_MASK GENMASK(3, 0) @@ -170,6 +182,7 @@ enum { ID_AD7190, ID_AD7192, ID_AD7193, + ID_AD7194, ID_AD7195, }; @@ -178,7 +191,9 @@ struct ad7192_chip_info { const char *name; const struct iio_chan_spec *channels; u8 num_channels; + const struct ad_sigma_delta_info *sigma_delta_info; const struct iio_info *info; + int (*parse_channels)(struct iio_dev *indio_dev); }; struct ad7192_state { @@ -346,6 +361,18 @@ static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { .irq_flags = IRQF_TRIGGER_FALLING, }; +static const struct ad_sigma_delta_info ad7194_sigma_delta_info = { + .set_channel = ad7192_set_channel, + .append_status = ad7192_append_status, + .disable_all = ad7192_disable_all, + .set_mode = ad7192_set_mode, + .has_registers = true, + .addr_shift = 3, + .read_mask = BIT(6), + .status_ch_mask = GENMASK(3, 0), + .irq_flags = IRQF_TRIGGER_FALLING, +}; + static const struct ad_sd_calib_data ad7192_calib_arr[8] = { {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, @@ -937,6 +964,14 @@ static const struct iio_info ad7192_info = { .update_scan_mode = ad7192_update_scan_mode, }; +static const struct iio_info ad7194_info = { + .read_raw = ad7192_read_raw, + .write_raw = ad7192_write_raw, + .write_raw_get_fmt = ad7192_write_raw_get_fmt, + .read_avail = ad7192_read_avail, + .validate_trigger = ad_sd_validate_trigger, +}; + static const struct iio_info ad7195_info = { .read_raw = ad7192_read_raw, .write_raw = ad7192_write_raw, @@ -1028,12 +1063,96 @@ static const struct iio_chan_spec ad7193_channels[] = { IIO_CHAN_SOFT_TIMESTAMP(14), }; +static int ad7194_validate_ain_channel(struct device *dev, u32 ain) +{ + if (!in_range(ain, AD7194_CH_AIN_START, AD7194_CH_AIN_NR)) + return dev_err_probe(dev, -EINVAL, + "Invalid AIN channel: %u\n", ain); + + return 0; +} + +static int ad7194_parse_channels(struct iio_dev *indio_dev) +{ + struct device *dev = indio_dev->dev.parent; + struct iio_chan_spec *ad7194_channels; + const struct iio_chan_spec ad7194_chan = AD7193_CHANNEL(0, 0, 0); + const struct iio_chan_spec ad7194_chan_diff = AD7193_DIFF_CHANNEL(0, 0, 0, 0); + const struct iio_chan_spec ad7194_chan_temp = AD719x_TEMP_CHANNEL(0, 0); + const struct iio_chan_spec ad7194_chan_timestamp = IIO_CHAN_SOFT_TIMESTAMP(0); + unsigned int num_channels, index = 0; + u32 ain[2]; + int ret; + + num_channels = device_get_child_node_count(dev); + if (num_channels > AD7194_CH_MAX_NR) + return dev_err_probe(dev, -EINVAL, + "Too many channels: %u\n", num_channels); + + num_channels += AD7194_CH_BASE_NR; + + ad7194_channels = devm_kcalloc(dev, num_channels, + sizeof(*ad7194_channels), GFP_KERNEL); + if (!ad7194_channels) + return -ENOMEM; + + indio_dev->channels = ad7194_channels; + indio_dev->num_channels = num_channels; + + device_for_each_child_node_scoped(dev, child) { + ret = fwnode_property_read_u32_array(child, "diff-channels", + ain, ARRAY_SIZE(ain)); + if (ret == 0) { + ret = ad7194_validate_ain_channel(dev, ain[0]); + if (ret) + return ret; + + ret = ad7194_validate_ain_channel(dev, ain[1]); + if (ret) + return ret; + + *ad7194_channels = ad7194_chan_diff; + ad7194_channels->scan_index = index++; + ad7194_channels->channel = ain[0]; + ad7194_channels->channel2 = ain[1]; + ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]); + } else { + ret = fwnode_property_read_u32(child, "single-channel", + &ain[0]); + if (ret) + return dev_err_probe(dev, ret, + "Missing channel property\n"); + + ret = ad7194_validate_ain_channel(dev, ain[0]); + if (ret) + return ret; + + *ad7194_channels = ad7194_chan; + ad7194_channels->scan_index = index++; + ad7194_channels->channel = ain[0]; + ad7194_channels->address = AD7194_CH(ain[0]); + } + ad7194_channels++; + } + + *ad7194_channels = ad7194_chan_temp; + ad7194_channels->scan_index = index++; + ad7194_channels->address = AD7194_CH_TEMP; + ad7194_channels++; + + *ad7194_channels = ad7194_chan_timestamp; + ad7194_channels->scan_index = index; + + return 0; +} + static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { [ID_AD7190] = { .chip_id = CHIPID_AD7190, .name = "ad7190", .channels = ad7192_channels, .num_channels = ARRAY_SIZE(ad7192_channels), + .sigma_delta_info = &ad7192_sigma_delta_info, .info = &ad7192_info, }, [ID_AD7192] = { @@ -1041,6 +1160,7 @@ static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { .name = "ad7192", .channels = ad7192_channels, .num_channels = ARRAY_SIZE(ad7192_channels), + .sigma_delta_info = &ad7192_sigma_delta_info, .info = &ad7192_info, }, [ID_AD7193] = { @@ -1048,13 +1168,22 @@ static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { .name = "ad7193", .channels = ad7193_channels, .num_channels = ARRAY_SIZE(ad7193_channels), + .sigma_delta_info = &ad7192_sigma_delta_info, .info = &ad7192_info, }, + [ID_AD7194] = { + .chip_id = CHIPID_AD7194, + .name = "ad7194", + .info = &ad7194_info, + .sigma_delta_info = &ad7194_sigma_delta_info, + .parse_channels = ad7194_parse_channels, + }, [ID_AD7195] = { .chip_id = CHIPID_AD7195, .name = "ad7195", .channels = ad7192_channels, .num_channels = ARRAY_SIZE(ad7192_channels), + .sigma_delta_info = &ad7192_sigma_delta_info, .info = &ad7195_info, }, }; @@ -1161,11 +1290,17 @@ static int ad7192_probe(struct spi_device *spi) st->chip_info = spi_get_device_match_data(spi); indio_dev->name = st->chip_info->name; indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->channels = st->chip_info->channels; - indio_dev->num_channels = st->chip_info->num_channels; indio_dev->info = st->chip_info->info; + if (st->chip_info->parse_channels) { + ret = st->chip_info->parse_channels(indio_dev); + if (ret) + return ret; + } else { + indio_dev->channels = st->chip_info->channels; + indio_dev->num_channels = st->chip_info->num_channels; + } - ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); + ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info); if (ret) return ret; @@ -1202,6 +1337,7 @@ static const struct of_device_id ad7192_of_match[] = { { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] }, { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] }, { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] }, + { .compatible = "adi,ad7194", .data = &ad7192_chip_info_tbl[ID_AD7194] }, { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] }, {} }; @@ -1211,6 +1347,7 @@ static const struct spi_device_id ad7192_ids[] = { { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] }, { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] }, { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] }, + { "ad7194", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7194] }, { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] }, {} }; @@ -1227,6 +1364,6 @@ static struct spi_driver ad7192_driver = { module_spi_driver(ad7192_driver); MODULE_AUTHOR("Michael Hennerich "); -MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC"); +MODULE_DESCRIPTION("Analog Devices AD7192 and similar ADC"); MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);