From patchwork Tue May 14 19:13:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D28DC04FFE for ; Tue, 14 May 2024 19:14:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F288710E686; Tue, 14 May 2024 19:14:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kODhV1FU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 05DCA10E53F for ; Tue, 14 May 2024 19:14:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714057; x=1747250057; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=cueiYG9zerXsrx8PgoBTPCzMVz0ZP7NFU/vgx+Vn1uQ=; b=kODhV1FU4+IP9bbkfkwAYMKmnXzxyW1lxYzjhu35DCBQ7ZcMo8k4cukt 6RK22/CkD0MuCCfTGACCGW7Vp1ReP03Tu4LbZkSLZSSc8AAE3cVFYqYqI LbJPqalWQnbEwIzUKvBEtD0bcFALKLWBnXbCBELfFKxokJbwHqndIiN3R BIxj7V9iQ9ZprdBOxWG/IUqWgDg3trLGncLlPq2NXF1WHLd3z3/TF7rY7 lYAnPYHod/o2A4pfQBkIuZsBuET5CX25Wad/aaMU5mxHob9noddp8E9uN uYPfIFvf5X5g4BhZYN6uO25Iizj58YQBnPzNUH3UaBDiFH9/eDs8f9/MY A==; X-CSE-ConnectionGUID: hgtkWr65QzigNlTOlYQbdw== X-CSE-MsgGUID: nAOto9QAQ/SJgiVPl4TcvQ== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124983" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124983" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:17 -0700 X-CSE-ConnectionGUID: vHNs5VqfTB+WkARKy0VJKw== X-CSE-MsgGUID: bEnYrvsPRIeY/MHdRLGSvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724588" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:16 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 01/20] drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs Date: Tue, 14 May 2024 22:13:59 +0300 Message-ID: <20240514191418.2863344-2-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Symbols consisting of multiple (4) TU timeslots may get split across MTPs when using 2 or 1 link lanes. Avoid this, as required by Bspec by aligning the allocated TUs to 2 when using 2 lanes and 4 when using 1 lane. Atm, we also have to align the PBNs used to allocate BW along the MST path, since DRM core keeps track of its own TU value, derived from the PBN and that TU value must match what the driver calculates. On some platforms the alignment is only required on 8b/10b links, a follow-up patch will remove the limitation for those. Bspec: 49266, 68922 Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 27 ++++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c772ba19c5477..c9c5d235744ab 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -207,6 +207,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, int remote_bw_overhead; int link_bpp_x16; int remote_tu; + fixed20_12 pbn; drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -237,11 +238,29 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, * crtc_state->dp_m_n.tu), provided that the driver doesn't * enable SSC on the corresponding link. */ - crtc_state->pbn = intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, - link_bpp_x16, - remote_bw_overhead); + pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, + link_bpp_x16, + remote_bw_overhead)); + remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full); - remote_tu = DIV_ROUND_UP(dfixed_const(crtc_state->pbn), mst_state->pbn_div.full); + /* + * Aligning the TUs ensures that symbols consisting of multiple + * (4) symbol cycles don't get split between two consecutive + * MTPs, as required by Bspec. + * TODO: remove the alignment restriction for 128b/132b links + * on some platforms, where Bspec allows this. + */ + remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count); + + /* + * Also align PBNs accordingly, since MST core will derive its + * own copy of TU from the PBN in drm_dp_atomic_find_time_slots(). + * The above comment about the difference between the PBN + * allocated for the whole path and the TUs allocated for the + * first branch device's link also applies here. + */ + pbn.full = remote_tu * mst_state->pbn_div.full; + crtc_state->pbn = dfixed_trunc(pbn); drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu); crtc_state->dp_m_n.tu = remote_tu; From patchwork Tue May 14 19:14:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 606ECC25B75 for ; Tue, 14 May 2024 19:14:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EC2C710E703; Tue, 14 May 2024 19:14:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ibyBithm"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id D173D10E53F for ; Tue, 14 May 2024 19:14:17 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="30724591" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:17 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 02/20] drm/i915/dp: Move link train params to a substruct in intel_dp Date: Tue, 14 May 2024 22:14:00 +0300 Message-ID: <20240514191418.2863344-3-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For clarity move the link training parameters updated during link training based on the pass/fail LT result under a substruct in intel_dp. This prepares for later patches in this patchset adding similar params here. Rename intel_dp_reset_max_link_params() to intel_dp_reset_link_train_params() to better reflect what state gets reset. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 12 ++++---- drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++---------- 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index fec3de25ea54e..7edb533758416 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1738,7 +1738,6 @@ struct intel_dp { u8 lane_count; u8 sink_count; bool link_trained; - bool reset_link_params; bool use_max_params; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; @@ -1759,10 +1758,13 @@ struct intel_dp { /* intersection of source and sink rates */ int num_common_rates; int common_rates[DP_MAX_SUPPORTED_RATES]; - /* Max lane count for the current link */ - int max_link_lane_count; - /* Max rate for the current link */ - int max_link_rate; + struct { + /* Max lane count for the current link */ + int max_lane_count; + /* Max rate for the current link */ + int max_rate; + } link_train; + bool reset_link_params; int mso_link_count; int mso_pixel_overlap; /* sink or branch descriptor */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6b8a94d0ca999..ffa627c63e048 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -372,13 +372,13 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) int intel_dp_max_lane_count(struct intel_dp *intel_dp) { - switch (intel_dp->max_link_lane_count) { + switch (intel_dp->link_train.max_lane_count) { case 1: case 2: case 4: - return intel_dp->max_link_lane_count; + return intel_dp->link_train.max_lane_count; default: - MISSING_CASE(intel_dp->max_link_lane_count); + MISSING_CASE(intel_dp->link_train.max_lane_count); return 1; } } @@ -644,7 +644,7 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, * boot-up. */ if (link_rate == 0 || - link_rate > intel_dp->max_link_rate) + link_rate > intel_dp->link_train.max_rate) return false; if (lane_count == 0 || @@ -705,8 +705,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, "Retrying Link training for eDP with same parameters\n"); return 0; } - intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->max_link_lane_count = lane_count; + intel_dp->link_train.max_rate = intel_dp_common_rate(intel_dp, index - 1); + intel_dp->link_train.max_lane_count = lane_count; } else if (lane_count > 1) { if (intel_dp_is_edp(intel_dp) && !intel_dp_can_link_train_fallback_for_edp(intel_dp, @@ -716,8 +716,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, "Retrying Link training for eDP with same parameters\n"); return 0; } - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->max_link_lane_count = lane_count >> 1; + intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link_train.max_lane_count = lane_count >> 1; } else { drm_err(&i915->drm, "Link Training Unsuccessful\n"); return -1; @@ -1382,7 +1382,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp) { int len; - len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); + len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link_train.max_rate); return intel_dp_common_rate(intel_dp, len - 1); } @@ -3017,10 +3017,10 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, intel_dp->lane_count = lane_count; } -static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp) +static void intel_dp_reset_link_train_params(struct intel_dp *intel_dp) { - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link_train.max_lane_count = intel_dp_max_common_lane_count(intel_dp); + intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp); } /* Enable backlight PWM and backlight PP control. */ @@ -3355,7 +3355,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder, intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); if (crtc_state) - intel_dp_reset_max_link_params(intel_dp); + intel_dp_reset_link_train_params(intel_dp); } bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, @@ -5888,7 +5888,7 @@ intel_dp_detect(struct drm_connector *connector, * supports link training fallback params. */ if (intel_dp->reset_link_params || intel_dp->is_mst) { - intel_dp_reset_max_link_params(intel_dp); + intel_dp_reset_link_train_params(intel_dp); intel_dp->reset_link_params = false; } @@ -6740,7 +6740,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, intel_dp_set_source_rates(intel_dp); intel_dp_set_common_rates(intel_dp); - intel_dp_reset_max_link_params(intel_dp); + intel_dp_reset_link_train_params(intel_dp); /* init MST on ports that can support it */ intel_dp_mst_encoder_init(dig_port, From patchwork Tue May 14 19:14:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D1FFC04FFE for ; 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X-CSE-ConnectionGUID: JfT4kdWFTAe7IAuhmxr3wg== X-CSE-MsgGUID: EJ4fCiOKRrKBnh0lFqWfSg== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124985" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124985" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:19 -0700 X-CSE-ConnectionGUID: KEt32ed0RjKExnlBXVt90g== X-CSE-MsgGUID: sgwTwJTsSWOXCGnFOvyxtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724596" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:17 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 03/20] drm/i915/dp: Move link train fallback to intel_dp_link_training.c Date: Tue, 14 May 2024 22:14:01 +0300 Message-ID: <20240514191418.2863344-4-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move the functions used to reduce the link parameters during link training to intel_dp_link_training.c . Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 76 +------------------ drivers/gpu/drm/i915/display/intel_dp.h | 4 +- .../drm/i915/display/intel_dp_link_training.c | 73 ++++++++++++++++++ 3 files changed, 77 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ffa627c63e048..9951ea8d0a139 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -329,7 +329,7 @@ static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, intel_dp->num_common_rates, max_rate); } -static int intel_dp_common_rate(struct intel_dp *intel_dp, int index) +int intel_dp_common_rate(struct intel_dp *intel_dp, int index) { if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm, index < 0 || index >= intel_dp->num_common_rates)) @@ -604,7 +604,7 @@ static int intersect_rates(const int *source_rates, int source_len, } /* return index of rate in rates array, or -1 if not found */ -static int intel_dp_rate_index(const int *rates, int len, int rate) +int intel_dp_rate_index(const int *rates, int len, int rate) { int i; @@ -654,78 +654,6 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, return true; } -static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, - int link_rate, - u8 lane_count) -{ - /* FIXME figure out what we actually want here */ - const struct drm_display_mode *fixed_mode = - intel_panel_preferred_fixed_mode(intel_dp->attached_connector); - int mode_rate, max_rate; - - mode_rate = intel_dp_link_required(fixed_mode->clock, 18); - max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); - if (mode_rate > max_rate) - return false; - - return true; -} - -int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count) -{ - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int index; - - /* - * TODO: Enable fallback on MST links once MST link compute can handle - * the fallback params. - */ - if (intel_dp->is_mst) { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); - return -1; - } - - if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with max parameters\n"); - intel_dp->use_max_params = true; - return 0; - } - - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - link_rate); - if (index > 0) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_common_rate(intel_dp, index - 1), - lane_count)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link_train.max_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->link_train.max_lane_count = lane_count; - } else if (lane_count > 1) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_max_common_rate(intel_dp), - lane_count >> 1)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->link_train.max_lane_count = lane_count >> 1; - } else { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); - return -1; - } - - return 0; -} - u32 intel_dp_mode_to_fec_clock(u32 mode_clock) { return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index aad2223df2a35..e7b47e7bcd98b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -55,8 +55,6 @@ void intel_dp_connector_sync_state(struct intel_connector *connector, const struct intel_crtc_state *crtc_state); void intel_dp_set_link_params(struct intel_dp *intel_dp, int link_rate, int lane_count); -int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count); int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask); @@ -107,6 +105,8 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); int intel_dp_max_common_rate(struct intel_dp *intel_dp); int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); +int intel_dp_common_rate(struct intel_dp *intel_dp, int index); +int intel_dp_rate_index(const int *rates, int len, int rate); void intel_dp_update_sink_caps(struct intel_dp *intel_dp); void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 947575140059d..1b4694b46cea7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -25,6 +25,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" +#include "intel_panel.h" #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ @@ -1091,6 +1092,78 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp, return ret; } +static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, + int link_rate, + u8 lane_count) +{ + /* FIXME figure out what we actually want here */ + const struct drm_display_mode *fixed_mode = + intel_panel_preferred_fixed_mode(intel_dp->attached_connector); + int mode_rate, max_rate; + + mode_rate = intel_dp_link_required(fixed_mode->clock, 18); + max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); + if (mode_rate > max_rate) + return false; + + return true; +} + +static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, + int link_rate, u8 lane_count) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int index; + + /* + * TODO: Enable fallback on MST links once MST link compute can handle + * the fallback params. + */ + if (intel_dp->is_mst) { + drm_err(&i915->drm, "Link Training Unsuccessful\n"); + return -1; + } + + if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with max parameters\n"); + intel_dp->use_max_params = true; + return 0; + } + + index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + link_rate); + if (index > 0) { + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, + intel_dp_common_rate(intel_dp, index - 1), + lane_count)) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + intel_dp->link_train.max_rate = intel_dp_common_rate(intel_dp, index - 1); + intel_dp->link_train.max_lane_count = lane_count; + } else if (lane_count > 1) { + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, + intel_dp_max_common_rate(intel_dp), + lane_count >> 1)) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link_train.max_lane_count = lane_count >> 1; + } else { + drm_err(&i915->drm, "Link Training Unsuccessful\n"); + return -1; + } + + return 0; +} + static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { From patchwork Tue May 14 19:14:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C55BC25B7A for ; Tue, 14 May 2024 19:14:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 57AAA10E6CE; Tue, 14 May 2024 19:14:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KfTdUmly"; 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d="scan'208";a="23124986" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:20 -0700 X-CSE-ConnectionGUID: auoG7QByQCqYefYAiEZa+Q== X-CSE-MsgGUID: Dv6NcwXtQLysrE0OrCGvQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724599" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:19 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 04/20] drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values() Date: Tue, 14 May 2024 22:14:02 +0300 Message-ID: <20240514191418.2863344-5-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reduce the indentation in intel_dp_get_link_train_fallback_values() by adding separate helpers to reduce the link rate and lane count. Also simplify things by passing crtc_state to the function. This also prepares for later patches in the patchset adding a limitation on how the link params are reduced. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_dp_link_training.c | 82 ++++++++++++------- 1 file changed, 51 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 1b4694b46cea7..1ea4aaf9592f1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1109,11 +1109,37 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, return true; } +static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) +{ + int rate_index; + int new_rate; + + rate_index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + current_rate); + + if (rate_index <= 0) + return -1; + + new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); + + return new_rate; +} + +static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) +{ + if (current_lane_count > 1) + return current_lane_count >> 1; + + return -1; +} + static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count) + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int index; + int new_link_rate; + int new_lane_count; /* * TODO: Enable fallback on MST links once MST link compute can handle @@ -1131,36 +1157,32 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, return 0; } - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - link_rate); - if (index > 0) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_common_rate(intel_dp, index - 1), - lane_count)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link_train.max_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->link_train.max_lane_count = lane_count; - } else if (lane_count > 1) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_max_common_rate(intel_dp), - lane_count >> 1)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->link_train.max_lane_count = lane_count >> 1; - } else { + new_lane_count = crtc_state->lane_count; + new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); + if (new_link_rate < 0) { + new_lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); + new_link_rate = intel_dp_max_common_rate(intel_dp); + } + + if (new_lane_count < 0) { drm_err(&i915->drm, "Link Training Unsuccessful\n"); return -1; } + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + + drm_dbg_kms(&i915->drm, "Reducing link parameters from %dx%d to %dx%d\n", + crtc_state->port_clock, crtc_state->lane_count, + new_link_rate, new_lane_count); + + intel_dp->link_train.max_rate = new_link_rate; + intel_dp->link_train.max_lane_count = new_lane_count; + return 0; } @@ -1178,9 +1200,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed with HOBL active, not enabling it from now on\n"); intel_dp->hobl_failed = true; - } else if (intel_dp_get_link_train_fallback_values(intel_dp, - crtc_state->port_clock, - crtc_state->lane_count)) { + } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { return; } From patchwork Tue May 14 19:14:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3236C25B79 for ; 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X-CSE-ConnectionGUID: 9iyZuHu+RAONxOKDBjaELA== X-CSE-MsgGUID: Icsk7A/OQoGGtgpPYwWVyg== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124987" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124987" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:21 -0700 X-CSE-ConnectionGUID: UW+igsXUTPOwBew98A30Kw== X-CSE-MsgGUID: dd4U5YPlRfWpUxYzYZrWTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724601" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:19 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 05/20] drm/i915: Factor out function to modeset commit a set of pipes Date: Tue, 14 May 2024 22:14:03 +0300 Message-ID: <20240514191418.2863344-6-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Factor out a function to modeset commit a set of pipes, which a later patch will reuse for DP link retraining. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 31 +----------------- drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.h | 3 ++ 3 files changed, 38 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3c3fc53376ce3..170ba01786cf8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4441,35 +4441,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) return connector; } -static int modeset_pipe(struct drm_crtc *crtc, - struct drm_modeset_acquire_ctx *ctx) -{ - struct drm_atomic_state *state; - struct drm_crtc_state *crtc_state; - int ret; - - state = drm_atomic_state_alloc(crtc->dev); - if (!state) - return -ENOMEM; - - state->acquire_ctx = ctx; - to_intel_atomic_state(state)->internal = true; - - crtc_state = drm_atomic_get_crtc_state(state, crtc); - if (IS_ERR(crtc_state)) { - ret = PTR_ERR(crtc_state); - goto out; - } - - crtc_state->connectors_changed = true; - - ret = drm_atomic_commit(state); -out: - drm_atomic_state_put(state); - - return ret; -} - static int intel_hdmi_reset_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { @@ -4539,7 +4510,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, * would be perfectly happy if were to just reconfigure * the SCDC settings on the fly. */ - return modeset_pipe(&crtc->base, ctx); + return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); } static enum intel_hotplug_state diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef986b5084317..2884fea809242 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5567,6 +5567,40 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state, return 0; } +int intel_modeset_commit_pipes(struct drm_i915_private *i915, + u8 pipe_mask, + struct drm_modeset_acquire_ctx *ctx) +{ + struct drm_atomic_state *state; + struct intel_crtc *crtc; + int ret; + + state = drm_atomic_state_alloc(&i915->drm); + if (!state) + return -ENOMEM; + + state->acquire_ctx = ctx; + to_intel_atomic_state(state)->internal = true; + + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { + struct intel_crtc_state *crtc_state = + intel_atomic_get_crtc_state(state, crtc); + + if (IS_ERR(crtc_state)) { + ret = PTR_ERR(crtc_state); + goto out; + } + + crtc_state->uapi.connectors_changed = true; + } + + ret = drm_atomic_commit(state); +out: + drm_atomic_state_put(state); + + return ret; +} + /* * This implements the workaround described in the "notes" section of the mode * set sequence documentation. When going from no pipes or single pipe to diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 56d1c0e3e62cd..dfdc42cef8723 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -537,6 +537,9 @@ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, const char *reason, u8 pipe_mask); int intel_modeset_all_pipes_late(struct intel_atomic_state *state, const char *reason); +int intel_modeset_commit_pipes(struct drm_i915_private *i915, + u8 pipe_mask, + struct drm_modeset_acquire_ctx *ctx); void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, struct intel_power_domain_mask *old_domains); void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, From patchwork Tue May 14 19:14:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7846DC04FFE for ; Tue, 14 May 2024 19:14:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E3D3610E859; Tue, 14 May 2024 19:14:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="L1Wklnpq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id B207B10E53F for ; Tue, 14 May 2024 19:14:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714062; x=1747250062; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=t7fjGSZMw9Lcbb/lEMiMgezF8gn7u6IXU2kOlp3l8C0=; b=L1Wklnpqp94bSwGCxl8m85/k/61Qep8S1J+6akYaOseXkbhz7M+jpV6/ baZRnp0oD0uE7ny+5mXbYANnb2ESe4/2zdQKdLyzfT1n+Dwi+dE0j6qmI SDedqh0rEDIbkbWw7zfb+o1zyYBt6oc4d1Lj30pwpJl689b+Xo0CeORvF rIgjLQ2H7VyJcFpuPC+S8cBGZj/6IPEWxSd9fv1gVaO5IUXA+1kT+qkV/ Ddyl1KNyXq+PukkcCo7aqH/4YsJDSFZl7C2hX+NmDEBsy/63j1q5lfxEw xayq9GSh0FMIfvqj6RMlEqgxFwq/YMyvAngk1nPH7uorBkAjer6qPXsDD Q==; X-CSE-ConnectionGUID: OrNiAbVdRsG13eezLagFBw== X-CSE-MsgGUID: J1GCeQwTRXq2rfkfsDq3Cw== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124988" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124988" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:22 -0700 X-CSE-ConnectionGUID: LdlC8aVYRc+4z9s9KsUkDw== X-CSE-MsgGUID: 2dULMEbkRyKV3oalRtHFUw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724602" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:20 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 06/20] drm/i915/dp: Use a commit modeset for link retraining MST links Date: Tue, 14 May 2024 22:14:04 +0300 Message-ID: <20240514191418.2863344-7-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Instead of direct calls to the link train functions, retrain the link via a commit modeset. The direct call means that the output port will be disabled/re-enabled while the rest of the pipeline (transcoder) is active, which doesn't seem to work on MST at least. It leads to underruns and black screen, presumedly because the transcoder is not disabled/re-enabled along the port. Leave switching to a commit modeset on SST for a later patchset, as that seems to work ok currently (though better to using a commit there too, due to the suppressed underruns). Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9951ea8d0a139..abf1aec2f3217 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5147,6 +5147,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_crtc *crtc; u8 pipe_mask; + bool mst_output = false; int ret; if (!intel_dp_is_connected(intel_dp)) @@ -5177,6 +5178,11 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { + mst_output = true; + break; + } + /* Suppress underruns caused by re-training */ intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); if (crtc_state->has_pch_encoder) @@ -5184,16 +5190,23 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, intel_crtc_pch_transcoder(crtc), false); } + /* TODO: use a modeset for SST as well. */ + if (mst_output) { + ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); + + if (ret && ret != -EDEADLK) + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] link retraining failed: %pe\n", + encoder->base.base.id, encoder->base.name, + ERR_PTR(ret)); + + return ret; + } + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - /* retrain on the MST master transcoder */ - if (DISPLAY_VER(dev_priv) >= 12 && - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && - !intel_dp_mst_is_master_trans(crtc_state)) - continue; - intel_dp_check_frl_training(intel_dp); intel_dp_pcon_dsc_configure(intel_dp, crtc_state); intel_dp_start_link_train(intel_dp, crtc_state); From patchwork Tue May 14 19:14:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACF4CC04FFE for ; Tue, 14 May 2024 19:14:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24A3F10EB29; Tue, 14 May 2024 19:14:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="gxm+j0IV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 928F910E703 for ; Tue, 14 May 2024 19:14:22 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="30724603" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:21 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 07/20] drm/i915/dp: Recheck link state after modeset Date: Tue, 14 May 2024 22:14:05 +0300 Message-ID: <20240514191418.2863344-8-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Recheck the link state after a passing link training, with a 2 sec delay to account for cases where the link goes bad following the link training and the sink doesn't report this via an HPD IRQ. The delayed work added here will be also used by a later patch after a failed link training to try to retrain the link with unchanged link params before reducing the link params. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp.c | 24 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + .../drm/i915/display/intel_dp_link_training.c | 10 +++++--- 4 files changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 7edb533758416..0da7649e4ba9e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1773,6 +1773,8 @@ struct intel_dp { u32 aux_busy_last_status; u8 train_set[4]; + struct delayed_work check_link_work; + struct intel_pps pps; bool is_mst; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index abf1aec2f3217..2ec6e9c34e282 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -75,6 +75,7 @@ #include "intel_hotplug_irq.h" #include "intel_lspcon.h" #include "intel_lvds.h" +#include "intel_modeset_lock.h" #include "intel_panel.h" #include "intel_pch_display.h" #include "intel_pps.h" @@ -5230,6 +5231,26 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, return 0; } +static void intel_dp_link_check_work_fn(struct work_struct *work) +{ + struct intel_dp *intel_dp = + container_of(work, typeof(*intel_dp), check_link_work.work); + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + struct drm_modeset_acquire_ctx ctx; + int ret; + + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) + ret = intel_dp_retrain_link(encoder, &ctx); +} + +void intel_dp_queue_link_check(struct intel_dp *intel_dp, int delay_ms) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + mod_delayed_work(i915->unordered_wq, + &intel_dp->check_link_work, msecs_to_jiffies(delay_ms)); +} + static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) @@ -6000,6 +6021,8 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder) struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); struct intel_dp *intel_dp = &dig_port->dp; + cancel_delayed_work_sync(&intel_dp->check_link_work); + intel_dp_mst_encoder_cleanup(dig_port); intel_dp_tunnel_destroy(intel_dp); @@ -6609,6 +6632,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, /* Initialize the work for modeset in case of link train failure */ intel_dp_init_modeset_retry_work(intel_connector); + INIT_DELAYED_WORK(&intel_dp->check_link_work, intel_dp_link_check_work_fn); if (drm_WARN(dev, dig_port->max_lanes < 1, "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index e7b47e7bcd98b..6a1f2a2856998 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -60,6 +60,7 @@ int intel_dp_get_active_pipes(struct intel_dp *intel_dp, u8 *pipe_mask); int intel_dp_retrain_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx); +void intel_dp_queue_link_check(struct intel_dp *intel_dp, int delay_ms); void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 1ea4aaf9592f1..85074c1c2281d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1483,6 +1483,11 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, else passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); + if (passed) { + intel_dp_queue_link_check(intel_dp, 2000); + return; + } + /* * Ignore the link failure in CI * @@ -1495,13 +1500,12 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, * For test cases which rely on the link training or processing of HPDs * ignore_long_hpd flag can unset from the testcase. */ - if (!passed && i915->display.hotplug.ignore_long_hpd) { + if (i915->display.hotplug.ignore_long_hpd) { lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); return; } - if (!passed) - intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, From patchwork Tue May 14 19:14:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0038C25B79 for ; Tue, 14 May 2024 19:14:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4C7810EB19; Tue, 14 May 2024 19:14:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="23124990" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124990" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:23 -0700 X-CSE-ConnectionGUID: tysHQ9yATV2bGgFe+xsWrg== X-CSE-MsgGUID: gAMhqa/hS/iZNN27Lc/YfA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724610" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:22 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 08/20] drm/i915/dp: Reduce link params only after retrying with unchanged params Date: Tue, 14 May 2024 22:14:06 +0300 Message-ID: <20240514191418.2863344-9-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Try to maintain the current link parameters by retrying the link training with unchanged link parameters before reducing these parameters (sending an uevent to userspace to retrain the link instead). Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 ++++++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 0da7649e4ba9e..a173b9c105981 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1763,6 +1763,8 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + /* Sequential failures after a passing LT */ + int seq_failures; } link_train; bool reset_link_params; int mso_link_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2ec6e9c34e282..da56a2b7fa0f8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2950,6 +2950,7 @@ static void intel_dp_reset_link_train_params(struct intel_dp *intel_dp) { intel_dp->link_train.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link_train.seq_failures = 0; } /* Enable backlight PWM and backlight PP control. */ @@ -5056,6 +5057,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) intel_dp->lane_count)) return false; + if (intel_dp->link_train.seq_failures) + return true; + /* Retrain if link not ok */ return !intel_dp_link_ok(intel_dp, link_status); } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 85074c1c2281d..6b0aab278ae8d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1484,10 +1484,13 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); if (passed) { + intel_dp->link_train.seq_failures = 0; intel_dp_queue_link_check(intel_dp, 2000); return; } + intel_dp->link_train.seq_failures++; + /* * Ignore the link failure in CI * @@ -1505,6 +1508,11 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, return; } + if (intel_dp->link_train.seq_failures < 2) { + intel_dp_queue_link_check(intel_dp, 0); + return; + } + intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); } From patchwork Tue May 14 19:14:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664376 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3847C04FFE for ; Tue, 14 May 2024 19:14:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3617E10E9A9; Tue, 14 May 2024 19:14:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OfQhsvLd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id A1F8810E859 for ; Tue, 14 May 2024 19:14:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714065; x=1747250065; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=SZZN/rF77InupC9zlToJN3pi5cyChzRs0RHeLYNkIWs=; b=OfQhsvLdsdrXYAaBre/uCb7Gxo13xyZfTUP1KHxa3l0n3PR/khC/PKAL J2akFBJt+A2e5dnBh7Rg/oFLgXN0nXgqC9qhiXVY1Zd+ArfuIsJIRj34I FwIB4EUfbExTn7E4EFaW65kWqrTHmyEOa42Kjm80gJxZ9yc2CqVXi40Lu 0cLX3g/dUEs0uK/QorUshkmrZREfdgXLttDcGm59bSFw2o5IpUrxn8JL4 peW3S/SaeSwi40SL25ZXZKNgQXOkqMy+d6m53Bc8Xqsgrrg3NfbAlLL9D +gLAO5us/7H+3Sup17qZxYTP6/TT+YOpTGUPWjfsbdNQGq9roLgSZ0BSu w==; X-CSE-ConnectionGUID: 49JPvhrcTkuY3cBumPRv0w== X-CSE-MsgGUID: gdYflm6jSqe57xAbyjeSZg== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124991" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124991" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:25 -0700 X-CSE-ConnectionGUID: OW7zReJKTjO0hMCMMttFDg== X-CSE-MsgGUID: j83H1b4SRyubcbbmFwcLHw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724613" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:23 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 09/20] drm/i915/dp: Remove the modeset retry event's dependece on atomic state Date: Tue, 14 May 2024 22:14:07 +0300 Message-ID: <20240514191418.2863344-10-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" When notifying userspace to retry a modeset, the notified connectors are not really specific to those contained in the atomic state. For MST, where this makes a difference, all enabled connectors in the same MST topology should be notified which is guaranteed by the commit adding all these connectors to the atomic state. Instead of relying on this we can notify all the relevant connectors based on their (root) encoder. Using intel_dp_has_connector() simplifies the SST case as well. This prepares for a later patch sending a notification during link training, to which the atomic state is not passed down. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 29 ++++++++++--------- drivers/gpu/drm/i915/display/intel_dp.h | 5 +--- .../gpu/drm/i915/display/intel_dp_tunnel.c | 2 +- 3 files changed, 17 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index da56a2b7fa0f8..6969d35b6bb0a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2800,29 +2800,30 @@ void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) drm_connector_put(&connector->base); } -void -intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, - struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static bool intel_dp_has_connector(struct intel_dp *intel_dp, + const struct drm_connector_state *conn_state); + +void intel_dp_queue_modeset_retry_for_link(struct intel_encoder *encoder) { + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct drm_connector_list_iter conn_iter; struct intel_connector *connector; - struct intel_digital_connector_state *conn_state; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - int i; - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { - intel_dp_queue_modeset_retry_work(intel_dp->attached_connector); + drm_connector_list_iter_begin(&i915->drm, &conn_iter); + for_each_intel_connector_iter(connector, &conn_iter) { + struct drm_connector_state *conn_state = + connector->base.state; - return; - } + if (!intel_dp_has_connector(intel_dp, conn_state)) + continue; - for_each_new_intel_connector_in_state(state, connector, conn_state, i) { - if (!conn_state->base.crtc) + if (!conn_state->crtc) continue; - if (connector->mst_port == intel_dp) - intel_dp_queue_modeset_retry_work(connector); + intel_dp_queue_modeset_retry_work(connector); } + drm_connector_list_iter_end(&conn_iter); } int diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 6a1f2a2856998..05016e13fb944 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -45,10 +45,7 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, int intel_dp_min_bpp(enum intel_output_format output_format); void intel_dp_init_modeset_retry_work(struct intel_connector *connector); void intel_dp_queue_modeset_retry_work(struct intel_connector *connector); -void -intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, - struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state); +void intel_dp_queue_modeset_retry_for_link(struct intel_encoder *encoder); bool intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector); void intel_dp_connector_sync_state(struct intel_connector *connector, diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c index 6503abdc2b988..34a00b2a40e36 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c @@ -722,7 +722,7 @@ static void queue_retry_work(struct intel_atomic_state *state, encoder->base.base.id, encoder->base.name); - intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); + intel_dp_queue_modeset_retry_for_link(encoder); } static void atomic_increase_bw(struct intel_atomic_state *state) From patchwork Tue May 14 19:14:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 741CBC25B75 for ; Tue, 14 May 2024 19:14:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7458710EA30; Tue, 14 May 2024 19:14:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eBH2WfHs"; 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d="scan'208";a="23124992" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:26 -0700 X-CSE-ConnectionGUID: VGXRxvpnQw6fcFuq8duaWw== X-CSE-MsgGUID: UTJ/vKrqRcSeh+WTwz2Z7Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724617" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:24 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 10/20] drm/i915/dp: Send a link training modeset-retry uevent to all MST connectors Date: Tue, 14 May 2024 22:14:08 +0300 Message-ID: <20240514191418.2863344-11-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Send a modeset-retry uevent to all connectors in the same MST topology after a link training failure and reduction of the link parameters. This matches the way the same uevent is sent after a DP tunnel BW allocation failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.h | 1 - drivers/gpu/drm/i915/display/intel_dp_link_training.c | 4 ++-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6969d35b6bb0a..e0f1d020033ce 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2791,7 +2791,7 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder, intel_dp_is_uhbr(pipe_config); } -void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) +static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(connector->base.dev); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 05016e13fb944..9d75a9446df58 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -44,7 +44,6 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); int intel_dp_min_bpp(enum intel_output_format output_format); void intel_dp_init_modeset_retry_work(struct intel_connector *connector); -void intel_dp_queue_modeset_retry_work(struct intel_connector *connector); void intel_dp_queue_modeset_retry_for_link(struct intel_encoder *encoder); bool intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 6b0aab278ae8d..769ad93f615e8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1189,7 +1189,7 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { - struct intel_connector *intel_connector = intel_dp->attached_connector; + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); @@ -1205,7 +1205,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, } /* Schedule a Hotplug Uevent to userspace to start modeset */ - intel_dp_queue_modeset_retry_work(intel_connector); + intel_dp_queue_modeset_retry_for_link(encoder); } /* Perform the link training on all LTTPRs and the DPRX on a link. */ From patchwork Tue May 14 19:14:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 460DDC25B7A for ; Tue, 14 May 2024 19:14:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7065010E8CC; Tue, 14 May 2024 19:14:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="O4XvYA4+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8BBD010E859 for ; Tue, 14 May 2024 19:14:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714067; x=1747250067; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hRG/9LbobfkRz6i5dajpTqkvq7Ui//uUUSlrGk9uAgo=; b=O4XvYA4+OPKn1fvwjPx+FBEAma+W9z9dU+az8UtlGPoRQXhrVTUgGqLL mWnFDh9KGO9NFn4Rk4CSTuMoObkGRq0UQQPhf7cJEMANWw3JIxU75XDux frUIia41dBi3GEh2GJX757IaEw2kUee7Ppi8lTfHnySHSTZmFhXUpnIG8 iuWPZdOVArC08TR0nXQYp4GYOdmjR6nMqe7UmseRODWNOa0qRt34dKLLB 9oy70Scn6NI6BZBi0c1rZq/NswFybij/LPGLXwKBOGANabvqc7wQRXsWP vdK7itdpB2vFsrkqMKRdaCQkbvrPCqZHt9CgCDQl+YbZLc0emuXHCqWda g==; X-CSE-ConnectionGUID: teLlaYQqQUS0u+btGR8ZDg== X-CSE-MsgGUID: UlN3vlDlRQOdLsHKjoDrIQ== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124993" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124993" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:27 -0700 X-CSE-ConnectionGUID: oEN1MiM3Qj2UFiYM3H6VAA== X-CSE-MsgGUID: 7GdNWT63Qxa4f8jMAI07SQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724618" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:25 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 11/20] drm/i915/dp: Use check link state work in the hotplug handler Date: Tue, 14 May 2024 22:14:09 +0300 Message-ID: <20240514191418.2863344-12-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Simplify things by retraining a DP link if a bad link is detected in the hotplug handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/g4x_dp.c | 20 +------------------- drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++------ drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + 4 files changed, 13 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 06ec04e667e32..fd353472ebe66 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -1159,9 +1159,7 @@ intel_dp_hotplug(struct intel_encoder *encoder, struct intel_connector *connector) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct drm_modeset_acquire_ctx ctx; enum intel_hotplug_state state; - int ret; if (intel_dp->compliance.test_active && intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { @@ -1172,23 +1170,7 @@ intel_dp_hotplug(struct intel_encoder *encoder, state = intel_encoder_hotplug(encoder, connector); - drm_modeset_acquire_init(&ctx, 0); - - for (;;) { - ret = intel_dp_retrain_link(encoder, &ctx); - - if (ret == -EDEADLK) { - drm_modeset_backoff(&ctx); - continue; - } - - break; - } - - drm_modeset_drop_locks(&ctx); - drm_modeset_acquire_fini(&ctx); - drm_WARN(encoder->base.dev, ret, - "Acquiring modeset locks failed with %i\n", ret); + intel_dp_check_link_state(intel_dp); /* * Keeping it consistent with intel_ddi_hotplug() and diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 170ba01786cf8..c6602962e6a84 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4534,14 +4534,13 @@ intel_ddi_hotplug(struct intel_encoder *encoder, state = intel_encoder_hotplug(encoder, connector); if (!intel_tc_port_link_reset(dig_port)) { - intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { - if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) + if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) ret = intel_hdmi_reset_link(encoder, &ctx); - else - ret = intel_dp_retrain_link(encoder, &ctx); + drm_WARN_ON(encoder->base.dev, ret); + } else { + intel_dp_check_link_state(intel_dp); } - - drm_WARN_ON(encoder->base.dev, ret); } /* diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e0f1d020033ce..e47c4daafa348 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5256,6 +5256,12 @@ void intel_dp_queue_link_check(struct intel_dp *intel_dp, int delay_ms) &intel_dp->check_link_work, msecs_to_jiffies(delay_ms)); } +void intel_dp_check_link_state(struct intel_dp *intel_dp) +{ + if (intel_dp_needs_link_retrain(intel_dp)) + intel_dp_queue_link_check(intel_dp, 0); +} + static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 9d75a9446df58..afebe0e889c32 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -56,6 +56,7 @@ int intel_dp_get_active_pipes(struct intel_dp *intel_dp, u8 *pipe_mask); int intel_dp_retrain_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx); +void intel_dp_check_link_state(struct intel_dp *intel_dp); void intel_dp_queue_link_check(struct intel_dp *intel_dp, int delay_ms); void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, From patchwork Tue May 14 19:14:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4716BC04FFE for ; Tue, 14 May 2024 19:14:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A0FE710EA36; Tue, 14 May 2024 19:14:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fv7+ml5B"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 808E610E816 for ; Tue, 14 May 2024 19:14:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714068; x=1747250068; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=tsjqdW6VzsXxwAiTu/9B3MvtF75/ZtaJLQYmgWaDhMc=; b=fv7+ml5BUKnWALX5TCqbT3bnnhlzczFNMvx9Nw1YcIRU9SKdpuUfxoV9 +3uGTp6qmzqExjdn+0nVVuTqZtNV/3cRGreg5XmvVe4PZrhYttMZKmdBa 9ph6cr4XvUcBqUWBegm51lcxqAlS4oGnDbRQYoiZdvUC4CJFJtBMrO3b5 95SX1cg+fv+tQjuZ3x+ECJuyuJotUgtk3EdwncQgMFJwGu2LfsjwNixCU rnj64U05KC8DLZjKHWlKdbQPfkOGpt7tJ868JgH/ptSJOleZsr1sg+c7f 9uCh7LS0OCrbLtqyT86ZWIY+wEby61esHeL1o3AXDXcfFnZWcRlRtt/Bt w==; X-CSE-ConnectionGUID: YGO3av/hRROeHGxe1KSuww== X-CSE-MsgGUID: AYvzUw3kR9uuAFmYJjGKpw== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124995" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124995" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:27 -0700 X-CSE-ConnectionGUID: 7otojH3zQnys1FOqEqxMFg== X-CSE-MsgGUID: ZLt77+CZQMWhral2LxDl7g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724621" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:26 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 12/20] drm/i915/dp: Use check link state work in the detect handler Date: Tue, 14 May 2024 22:14:10 +0300 Message-ID: <20240514191418.2863344-13-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Simplify things by retraining a DP link if a bad link is detected in the connector detect handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++------- drivers/gpu/drm/i915/display/intel_dp.h | 2 -- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e47c4daafa348..a41a63b8ae5f0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5146,8 +5146,8 @@ static bool intel_dp_is_connected(struct intel_dp *intel_dp) intel_dp->is_mst; } -int intel_dp_retrain_link(struct intel_encoder *encoder, - struct drm_modeset_acquire_ctx *ctx) +static int intel_dp_retrain_link(struct intel_encoder *encoder, + struct drm_modeset_acquire_ctx *ctx) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -5881,11 +5881,8 @@ intel_dp_detect(struct drm_connector *connector, * Some external monitors do not signal loss of link synchronization * with an IRQ_HPD, so force a link status check. */ - if (!intel_dp_is_edp(intel_dp)) { - ret = intel_dp_retrain_link(encoder, ctx); - if (ret) - return ret; - } + if (!intel_dp_is_edp(intel_dp)) + intel_dp_check_link_state(intel_dp); /* * Clearing NACK and defer counts to get their exact values diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index afebe0e889c32..7c938327fc725 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -54,8 +54,6 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask); -int intel_dp_retrain_link(struct intel_encoder *encoder, - struct drm_modeset_acquire_ctx *ctx); void intel_dp_check_link_state(struct intel_dp *intel_dp); void intel_dp_queue_link_check(struct intel_dp *intel_dp, int delay_ms); void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); From patchwork Tue May 14 19:14:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8ACBC25B75 for ; Tue, 14 May 2024 19:14:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 22AEE10E8FB; Tue, 14 May 2024 19:14:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="iZ4qESGq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4EE4810E816 for ; Tue, 14 May 2024 19:14:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714068; x=1747250068; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=eSRMWlLhhY9GjAynN+Gi/fiL/nyRS/JKidjqsh1Akrw=; b=iZ4qESGqAhmTBtR9iBtcLnYo97jF1HrWBc95fMsI1wTD8Llz1GZWHdxp m9jmibLYXdQxloNdbCRLl5gD+BhHhPzWcXEfr7NzeHhQ1bNgaWDcOVIqy 9ZjcgItqrm5yiNxWO4qRWlDSFuVh/DsdDJ2tc1pKS6lS7sFCwHk1YAlvL eaXHmONpU+jrE/3reprTYpF/NXIQNlI+Ivo5bv+2jvsIarZ9nnnR/dZh/ fXmvKzMmLTu1YbBbfZdX+00rPt8NqI+PHc9/Xk26TTjASy9NP+raqTqwm nUKoXE6BGPNyhD3YSuXv+9L0fpx0yuj2w2bjDzy+QOOTBIz9/DfjEjkch w==; X-CSE-ConnectionGUID: X/IEoUNyTd2f7nH0OXe7Rg== X-CSE-MsgGUID: j71yK94TTJqB3DJkJdfcew== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124996" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124996" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:28 -0700 X-CSE-ConnectionGUID: uiBoxndsQsi4oIgB7d1ZhQ== X-CSE-MsgGUID: mRHPl1a6QPiCMFKJOrBFIA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724624" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:27 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 13/20] drm/i915/dp: Use check link state work in the HPD IRQ handler Date: Tue, 14 May 2024 22:14:11 +0300 Message-ID: <20240514191418.2863344-14-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Simplify things by retraining a DP link if a bad link is detected in the HPD IRQ handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a41a63b8ae5f0..e5bd2bbcc8d89 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4996,7 +4996,10 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); } - return link_ok && !reprobe_needed; + if (!link_ok) + intel_dp_queue_link_check(intel_dp, 0); + + return !reprobe_needed; } static void @@ -5472,9 +5475,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp) /* Handle CEC interrupts, if any */ drm_dp_cec_irq(&intel_dp->aux); - /* defer to the hotplug work for link retraining if needed */ - if (intel_dp_needs_link_retrain(intel_dp)) - return false; + intel_dp_check_link_state(intel_dp); intel_psr_short_pulse(intel_dp); From patchwork Tue May 14 19:14:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23240C25B7A for ; Tue, 14 May 2024 19:14:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1598710EB27; Tue, 14 May 2024 19:14:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AyhkmBvT"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2295210E8CC for ; Tue, 14 May 2024 19:14:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714069; x=1747250069; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=X3nTdg/G/fGtUCgK3L+WMzVbjg/n7J8u+b2jp8PUfh4=; b=AyhkmBvTDyFbfHbKcAL9wQzhH2TlUO5n2DYim6dSjBizRssT4gxpVB/C WGhy5Fm68MAWE49NOy65wV7FejY56KtkpI9zJJa0GRUlFhZ3W1mQuIwvE VHgFQtPnRWDG1q26kfhIA7b5972O6AHxLc0PeQyXqNc2e6iSoHqNyUHX0 LdIaGUwVSgNDTrIKx7ZlOweW5tXLhCUjs91RmhRbroXXmxNTd7e6N7Zpr PjebW0MGI+ckY9pQL+9UL5b5wtNHs39IyBgBQ0HO6qjl6ez+xceFGSGTm n+eE+Q6p6cJcfQUmX4FFrfLj23NYbr/TtmSv+M8iZ2iV6l862tSwcAuHP A==; X-CSE-ConnectionGUID: 6mqcPXKySKenEHU3WiZ9SA== X-CSE-MsgGUID: BuXnoSxNSeOaWia1n7RHJA== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124998" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124998" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:29 -0700 X-CSE-ConnectionGUID: 5z+pKnUaQWO2MvjHpN2DHA== X-CSE-MsgGUID: hw1ayoWxSnWHCQZhaMrt+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724627" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:28 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 14/20] drm/i915/dp: Disable link retraining after the last fallback step Date: Tue, 14 May 2024 22:14:12 +0300 Message-ID: <20240514191418.2863344-15-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" After a link training failure if the link parameters can't be further reduced, there is no point in trying to retrain the link in the driver. This avoids excessive retrain attempts after detecting a bad link, for instance while handling MST HPD IRQs, which is likely redundant as the link training failed already twice with the same minimum link parameters. Userspace can still try to retrain the link with these parameters via a modeset. While at it make the error message more accurate and emit instead a debug message if the link training failure was only forced for testing purposes. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ .../drm/i915/display/intel_dp_link_training.c | 22 +++++++++++++------ 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index a173b9c105981..fb71bc7eb3d9a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1763,6 +1763,7 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + bool retrain_disabled; /* Sequential failures after a passing LT */ int seq_failures; } link_train; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e5bd2bbcc8d89..fedc0afaf99d5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2951,6 +2951,7 @@ static void intel_dp_reset_link_train_params(struct intel_dp *intel_dp) { intel_dp->link_train.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link_train.retrain_disabled = false; intel_dp->link_train.seq_failures = 0; } @@ -5061,6 +5062,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) intel_dp->lane_count)) return false; + if (intel_dp->link_train.retrain_disabled) + return false; + if (intel_dp->link_train.seq_failures) return true; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 769ad93f615e8..bc3a653e4ce4a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1164,10 +1164,8 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, new_link_rate = intel_dp_max_common_rate(intel_dp); } - if (new_lane_count < 0) { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); + if (new_lane_count < 0) return -1; - } if (intel_dp_is_edp(intel_dp) && !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { @@ -1186,14 +1184,14 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, return 0; } -static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, +static bool intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); - return; + return true; } if (intel_dp->hobl_active) { @@ -1201,11 +1199,13 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, "Link Training failed with HOBL active, not enabling it from now on\n"); intel_dp->hobl_failed = true; } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { - return; + return false; } /* Schedule a Hotplug Uevent to userspace to start modeset */ intel_dp_queue_modeset_retry_for_link(encoder); + + return true; } /* Perform the link training on all LTTPRs and the DPRX on a link. */ @@ -1513,7 +1513,15 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, return; } - intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + if (intel_dp_schedule_fallback_link_training(intel_dp, crtc_state)) + return; + + intel_dp->link_train.retrain_disabled = true; + + if (!passed) + lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); + else + lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n"); } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, From patchwork Tue May 14 19:14:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A27DC25B75 for ; Tue, 14 May 2024 19:14:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C040D10EA79; Tue, 14 May 2024 19:14:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="P+lBg77p"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1E87710E8CC for ; Tue, 14 May 2024 19:14:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714070; x=1747250070; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=NbNjisrR5vHYONOIzXp45mVJDkxy7l9tX7MDhe/T+eE=; b=P+lBg77pwmn39NIzjhbhxFY2n3COPTIouVuGRSvZIMhzDPbAd89iLgx0 C4DypPfUvQx6pdmB2RKxxP1DSHEGgEDuNdegju0kXC6JrUa0UTDNpC4gz h6UO5Fk3PPHnrBAQvj24RHt//wYueSdkr628mxYVTHP0R5rgdJh3OhgW9 F9LoB+bZ8gyIT//8rJFaE9HOvLM1RThWxMPRFfG1mNdp1f7HNTBKhrimS iQnULchObjNl10wLsn5B6O8GGMhba9TFa/fiazzBJVBS6q/r+NB5yp9US Hms8AWAYu+mrOUeA4Pf33hxaTDlVbzPX4xUiMb9pZOsJrNoogfbeCyDN3 A==; X-CSE-ConnectionGUID: 2ZDVqCSORcSWb/EZyegWhA== X-CSE-MsgGUID: okTmZdXbQXufyjb3HNazJw== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23124999" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23124999" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:30 -0700 X-CSE-ConnectionGUID: V+prkI+fThGQrymv6Ju5RQ== X-CSE-MsgGUID: Re8Kr4pBSuq9Nxa+V2CiiQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724631" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:29 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 15/20] drm/i915/dp_mst: Reset intel_dp->link_trained during disabling Date: Tue, 14 May 2024 22:14:13 +0300 Message-ID: <20240514191418.2863344-16-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reset the flag indicating an active link after disabling an MST link, similarly to how this is done for SST outputs. This avoids trying to retrain an MST link while its disabled. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c9c5d235744ab..66c1c59268167 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -981,6 +981,9 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, drm_dbg_kms(&i915->drm, "active links %d\n", intel_dp->active_mst_links); + if (intel_dp->active_mst_links == 1) + intel_dp->link_trained = false; + intel_hdcp_disable(intel_mst->connector); intel_dp_sink_disable_decompression(state, connector, old_crtc_state); From patchwork Tue May 14 19:14:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2327C25B79 for ; Tue, 14 May 2024 19:14:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E409E10EB32; Tue, 14 May 2024 19:14:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fTzRxLgj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE71810EB2F for ; Tue, 14 May 2024 19:14:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714072; x=1747250072; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=2MI0m7SBV/n6V276+2v99WG2wc5OP25jPNAPL2FWMJM=; b=fTzRxLgjTgCRd+yB4B09ruHutyduQMxnRHNI5i5QK2ysKtfhK1E/DN6n 8jV+SZ+Kr+6fmNVja9mU5Dp5GoCVZ/MN/szhR44jyKD/zGNLWJu2poymd MOHxKXCPjivHkfXdqKLf4lGzqEDiNGfm+wlArzk8b0S5uiCLRguYYRfuw bEN23sWnLEu5JCCOu1Tpm6UZGpzPV5hN3IgW6gQiU35MouCe4m3KigzzK WCXLDaiGfzwekFKX5+8bDsWuozxeJXSkI3tJYgYJZgj7xYo1vZKxMR7Kh BzruK6FjS34E6ZDf4EZT+rYJV3b8vpOeBZ57KyGgN0CeMJyx1i98CHMtD w==; X-CSE-ConnectionGUID: mhBSsE3jSOuvRGpAuQ3eKg== X-CSE-MsgGUID: HtxiHHFPR9O0tdRrQYTiuw== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23125000" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23125000" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:31 -0700 X-CSE-ConnectionGUID: ZH4vwyR6TmKtcnmUMuXeMw== X-CSE-MsgGUID: 4ENuiIKfSOyx7BSemaJaiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724634" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:30 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 16/20] drm/i915/dp_mst: Enable link training fallback for MST Date: Tue, 14 May 2024 22:14:14 +0300 Message-ID: <20240514191418.2863344-17-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reduce the link parameters after a link training failure for MST outputs, similarly to how this is done for SST. For now allow the reduction only by staying in the 8b/10b vs. 128b/132b mode. Enabling the mode switch is left for a follow-up patchset, after taking measures ensuring that the mode switch happens properly. In particular a rediscovery of the whole MST topology may be required for such a switch, see the References below. Link: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10970 Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 6 +----- .../gpu/drm/i915/display/intel_dp_link_training.c | 13 ++++--------- 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index fedc0afaf99d5..5eafda7175e2a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5861,11 +5861,7 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_mst_configure(intel_dp); - /* - * TODO: Reset link params when switching to MST mode, until MST - * supports link training fallback params. - */ - if (intel_dp->reset_link_params || intel_dp->is_mst) { + if (intel_dp->reset_link_params) { intel_dp_reset_link_train_params(intel_dp); intel_dp->reset_link_params = false; } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index bc3a653e4ce4a..b80fb25b9204d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1123,6 +1123,10 @@ static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); + /* TODO: Make switching from UHBR to non-UHBR rates work. */ + if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate)) + return -1; + return new_rate; } @@ -1141,15 +1145,6 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, int new_link_rate; int new_lane_count; - /* - * TODO: Enable fallback on MST links once MST link compute can handle - * the fallback params. - */ - if (intel_dp->is_mst) { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); - return -1; - } - if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { drm_dbg_kms(&i915->drm, "Retrying Link training for eDP with max parameters\n"); From patchwork Tue May 14 19:14:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5AF1C25B7A for ; Tue, 14 May 2024 19:14:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD1A210EB2F; Tue, 14 May 2024 19:14:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kDjG1hH3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C23410EB2F for ; Tue, 14 May 2024 19:14:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715714072; x=1747250072; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=A40nFo0iP8g3DpeMuz2MV91dcXZByM3TXHr/iEiPRkA=; b=kDjG1hH3JNpWnscCvF1q3iGfeH1EO6J6pQU6EIco9vavKW6cj2Bno0m2 J3HoBAt0LZHXM9RItHyx+yt6Pn7dlxEAUXDNFQ9Uf33FdEChYV35vE/qn nwGgVe+t8Ym0vRjvocuLBtGoM5wd6HwWlv8wVHodT15wuNfnPaEAKIBQK lhqnxZ1o+a45MUqTWThBTTCuq7k8SnsjSZ0+Rl5OSQPX79xulDPYoUOz/ hK9uRiXJlpUuQobGTPLukbOB7CFs76mXxurKhC3LyFil570YqhppfVYeW FaN4W/6E9eUA4c7KEg1oRkTH69itCpS8oa5Nu/TaFKselv2WuOseBKW7r A==; X-CSE-ConnectionGUID: 1EZe++xiSc+GTngbSucYsA== X-CSE-MsgGUID: ultf+L1+ROeRB3xqMRmBxA== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23125001" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23125001" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:32 -0700 X-CSE-ConnectionGUID: N9DinnUASwOvcQ6ZgIGovg== X-CSE-MsgGUID: Cxsx/bO9TcG5CL8ImdMfmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724641" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:31 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 17/20] drm/i915/dp: Add debugfs entries to set a target link rate/lane count Date: Tue, 14 May 2024 22:14:15 +0300 Message-ID: <20240514191418.2863344-18-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add connector debugfs entries to set a target link rate/lane count to be used by a link training afterwards. After setting a target link rate/lane count reset the link training parameters and for a non-auto target disable reducing the link parameters via the fallback logic. The former one can be used after testing link training failure scenarios - via debugfs entries added later - to reset the reduced link parameters after the test. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_debugfs.c | 218 ++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 63 ++++- drivers/gpu/drm/i915/display/intel_dp.h | 2 + .../drm/i915/display/intel_dp_link_training.c | 6 + 5 files changed, 282 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 35f9f86ef70f4..521721a20358f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1316,6 +1316,215 @@ static const struct file_operations i915_dsc_bpc_fops = { .write = i915_dsc_bpc_write }; +static struct intel_dp *intel_connector_to_intel_dp(struct intel_connector *connector) +{ + if (connector->mst_port) + return connector->mst_port; + else + return enc_to_intel_dp(intel_attached_encoder(connector)); +} + +static int i915_dp_requested_link_rate_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int ret; + int i; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + seq_printf(m, "%sauto%s", + intel_dp->requested_link_rate == 0 ? "[" : "", + intel_dp->requested_link_rate == 0 ? "]" : ""); + + for (i = 0; i < intel_dp->num_source_rates; i++) + seq_printf(m, " %s%d%s%s", + intel_dp->source_rates[i] == intel_dp->requested_link_rate ? "[" : "", + intel_dp->source_rates[i], + intel_dp->link_trained && + intel_dp->source_rates[i] == intel_dp->link_rate ? "*" : "", + intel_dp->source_rates[i] == intel_dp->requested_link_rate ? "]" : ""); + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + seq_putc(m, '\n'); + + return 0; +} + +static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) +{ + char *kbuf; + const char *p; + int rate; + int ret = 0; + + kbuf = memdup_user_nul(ubuf, len); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); + + p = strim(kbuf); + + if (!strcmp(p, "auto")) { + rate = 0; + } else { + ret = kstrtoint(p, 0, &rate); + if (ret < 0) + goto out_free; + + if (intel_dp_rate_index(intel_dp->source_rates, + intel_dp->num_source_rates, + rate) < 0) + ret = -EINVAL; + } + +out_free: + kfree(kbuf); + + return ret < 0 ? ret : rate; +} + +static ssize_t i915_dp_requested_link_rate_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int rate; + int ret; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + rate = parse_link_rate(intel_dp, ubuf, len); + if (rate < 0) { + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return rate; + } + + intel_dp_reset_link_train_params(intel_dp); + intel_dp->requested_link_rate = rate; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + *offp += len; + + return len; +} +DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_requested_link_rate); + +static int i915_dp_requested_lane_count_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int ret; + int i; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + seq_printf(m, "%sauto%s", + intel_dp->requested_lane_count == 0 ? "[" : "", + intel_dp->requested_lane_count == 0 ? "]" : ""); + + for (i = 1; i <= 4; i <<= 1) + seq_printf(m, " %s%d%s%s", + i == intel_dp->requested_lane_count ? "[" : "", + i, + intel_dp->link_trained && + i == intel_dp->lane_count ? "*" : "", + i == intel_dp->requested_lane_count ? "]" : ""); + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + seq_putc(m, '\n'); + + return 0; +} + +static int parse_lane_count(const char __user *ubuf, size_t len) +{ + char *kbuf; + const char *p; + int lane_count; + int ret = 0; + + kbuf = memdup_user_nul(ubuf, len); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); + + p = strim(kbuf); + + if (!strcmp(p, "auto")) { + lane_count = 0; + } else { + ret = kstrtoint(p, 0, &lane_count); + if (ret < 0) + goto out_free; + + switch (lane_count) { + case 1: + case 2: + case 4: + break; + default: + ret = -EINVAL; + } + } + +out_free: + kfree(kbuf); + + return ret < 0 ? ret : lane_count; +} + +static ssize_t i915_dp_requested_lane_count_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int lane_count; + int ret; + + lane_count = parse_lane_count(ubuf, len); + if (lane_count < 0) + return lane_count; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + intel_dp_reset_link_train_params(intel_dp); + intel_dp->requested_lane_count = lane_count; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + *offp += len; + + return len; +} +DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_requested_lane_count); + static int i915_dsc_output_format_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; @@ -1523,6 +1732,15 @@ void intel_connector_debugfs_add(struct intel_connector *connector) connector, &i915_hdcp_sink_capability_fops); } + if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || + connector_type == DRM_MODE_CONNECTOR_eDP) { + debugfs_create_file("i915_dp_link_rate", 0644, root, + connector, &i915_dp_requested_link_rate_fops); + + debugfs_create_file("i915_dp_lane_count", 0644, root, + connector, &i915_dp_requested_lane_count_fops); + } + if (DISPLAY_VER(i915) >= 11 && ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst_port) || connector_type == DRM_MODE_CONNECTOR_eDP)) { diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index fb71bc7eb3d9a..351c445d3cb5b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1758,6 +1758,8 @@ struct intel_dp { /* intersection of source and sink rates */ int num_common_rates; int common_rates[DP_MAX_SUPPORTED_RATES]; + int requested_link_rate; + int requested_lane_count; struct { /* Max lane count for the current link */ int max_lane_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5eafda7175e2a..367970f956863 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -345,7 +345,7 @@ int intel_dp_max_common_rate(struct intel_dp *intel_dp) return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); } -static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) +int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) { int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); int max_lanes = dig_port->max_lanes; @@ -371,19 +371,39 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) return min3(source_max, sink_max, lane_max); } +static int requested_lane_count(struct intel_dp *intel_dp) +{ + return clamp(intel_dp->requested_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); +} + int intel_dp_max_lane_count(struct intel_dp *intel_dp) { - switch (intel_dp->link_train.max_lane_count) { + int lane_count; + + if (intel_dp->requested_lane_count) + lane_count = requested_lane_count(intel_dp); + else + lane_count = intel_dp->link_train.max_lane_count; + + switch (lane_count) { case 1: case 2: case 4: - return intel_dp->link_train.max_lane_count; + return lane_count; default: - MISSING_CASE(intel_dp->link_train.max_lane_count); + MISSING_CASE(lane_count); return 1; } } +static int intel_dp_min_lane_count(struct intel_dp *intel_dp) +{ + if (intel_dp->requested_lane_count) + return requested_lane_count(intel_dp); + + return 1; +} + /* * The required data bandwidth for a mode with given pixel clock and bpp. This * is the required net bandwidth independent of the data bandwidth efficiency. @@ -1306,16 +1326,38 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp) drm_dbg_kms(&i915->drm, "common rates: %s\n", str); } +static int requested_rate(struct intel_dp *intel_dp) +{ + int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->requested_link_rate); + + if (len == 0) + return intel_dp_common_rate(intel_dp, 0); + + return intel_dp_common_rate(intel_dp, len - 1); +} + int intel_dp_max_link_rate(struct intel_dp *intel_dp) { int len; + if (intel_dp->requested_link_rate) + return requested_rate(intel_dp); + len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link_train.max_rate); return intel_dp_common_rate(intel_dp, len - 1); } +static int +intel_dp_min_link_rate(struct intel_dp *intel_dp) +{ + if (intel_dp->requested_link_rate) + return requested_rate(intel_dp); + + return intel_dp_common_rate(intel_dp, 0); +} + int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -2285,13 +2327,14 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, bool dsc, struct link_config_limits *limits) { - limits->min_rate = intel_dp_common_rate(intel_dp, 0); + limits->min_rate = intel_dp_min_link_rate(intel_dp); limits->max_rate = intel_dp_max_link_rate(intel_dp); /* FIXME 128b/132b SST support missing */ limits->max_rate = min(limits->max_rate, 810000); + limits->min_rate = min(limits->min_rate, limits->max_rate); - limits->min_lane_count = 1; + limits->min_lane_count = intel_dp_min_lane_count(intel_dp); limits->max_lane_count = intel_dp_max_lane_count(intel_dp); limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); @@ -2307,8 +2350,10 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, * configuration, and typically on older panels these * values correspond to the native resolution of the panel. */ - limits->min_lane_count = limits->max_lane_count; - limits->min_rate = limits->max_rate; + if (intel_dp->requested_lane_count == 0) + limits->min_lane_count = limits->max_lane_count; + if (intel_dp->requested_link_rate == 0) + limits->min_rate = limits->max_rate; } intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits); @@ -2947,7 +2992,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, intel_dp->lane_count = lane_count; } -static void intel_dp_reset_link_train_params(struct intel_dp *intel_dp) +void intel_dp_reset_link_train_params(struct intel_dp *intel_dp) { intel_dp->link_train.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 7c938327fc725..2b639bb2f56ed 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -95,6 +95,7 @@ void intel_edp_backlight_off(const struct drm_connector_state *conn_state); void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); void intel_dp_mst_suspend(struct drm_i915_private *dev_priv); void intel_dp_mst_resume(struct drm_i915_private *dev_priv); +int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port); int intel_dp_max_link_rate(struct intel_dp *intel_dp); int intel_dp_max_lane_count(struct intel_dp *intel_dp); int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); @@ -104,6 +105,7 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); int intel_dp_common_rate(struct intel_dp *intel_dp, int index); int intel_dp_rate_index(const int *rates, int len, int rate); void intel_dp_update_sink_caps(struct intel_dp *intel_dp); +void intel_dp_reset_link_train_params(struct intel_dp *intel_dp); void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, u8 *link_bw, u8 *rate_select); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index b80fb25b9204d..352c77f46015e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1114,6 +1114,9 @@ static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) int rate_index; int new_rate; + if (intel_dp->requested_link_rate) + return -1; + rate_index = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, current_rate); @@ -1132,6 +1135,9 @@ static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) { + if (intel_dp->requested_lane_count) + return -1; + if (current_lane_count > 1) return current_lane_count >> 1; From patchwork Tue May 14 19:14:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD6FEC25B75 for ; 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X-CSE-ConnectionGUID: NVwCQMpSQdeAZAQSsnaX1A== X-CSE-MsgGUID: 8RJ84ppwQvitsH+95QgXIg== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23125002" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23125002" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:33 -0700 X-CSE-ConnectionGUID: bEqIrKHdR7epQ+PSwagt3A== X-CSE-MsgGUID: qqFykcGNT165hthDAjIITw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724644" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:32 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 18/20] drm/i915/dp: Add debugfs entry to force link training failure Date: Tue, 14 May 2024 22:14:16 +0300 Message-ID: <20240514191418.2863344-19-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a connector debugfs entry to force a failure during the following 1-2 link training. The entry will auto-reset after the specified link training events are complete. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_debugfs.c | 47 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 1 + .../drm/i915/display/intel_dp_link_training.c | 5 +- 3 files changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 521721a20358f..098d0f5190723 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1525,6 +1525,50 @@ static ssize_t i915_dp_requested_lane_count_write(struct file *file, } DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_requested_lane_count); +static int i915_dp_force_link_training_failure_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + *val = intel_dp->link_train.force_failure; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} + +static int i915_dp_force_link_training_failure_write(void *data, u64 val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + if (val > 2) + return -EINVAL; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + intel_dp->link_train.force_failure = val; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, + i915_dp_force_link_training_failure_show, + i915_dp_force_link_training_failure_write, "%llu\n"); + static int i915_dsc_output_format_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; @@ -1739,6 +1783,9 @@ void intel_connector_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_lane_count", 0644, root, connector, &i915_dp_requested_lane_count_fops); + + debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, + connector, &i915_dp_force_link_training_failure_fops); } if (DISPLAY_VER(i915) >= 11 && diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 351c445d3cb5b..62acec5236052 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1768,6 +1768,7 @@ struct intel_dp { bool retrain_disabled; /* Sequential failures after a passing LT */ int seq_failures; + int force_failure; } link_train; bool reset_link_params; int mso_link_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 352c77f46015e..c260299c53b7c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1484,7 +1484,10 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, else passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); - if (passed) { + if (intel_dp->link_train.force_failure) { + intel_dp->link_train.force_failure--; + lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); + } else if (passed) { intel_dp->link_train.seq_failures = 0; intel_dp_queue_link_check(intel_dp, 2000); return; From patchwork Tue May 14 19:14:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94FF7C04FFE for ; Tue, 14 May 2024 19:14:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B36AE10EA4D; Tue, 14 May 2024 19:14:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="23125003" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23125003" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:34 -0700 X-CSE-ConnectionGUID: eqwUJOgqTK2+hv4AltZyFg== X-CSE-MsgGUID: mIelShG/RYudMBmziNMS1w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724649" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:33 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 19/20] drm/i915/dp: Add debugfs entry to force link retrain Date: Tue, 14 May 2024 22:14:17 +0300 Message-ID: <20240514191418.2863344-20-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a connector debugfs entry to force retrain an active link. This can be used to test both custom link parameters (previously set via the target link lane count/rate entries) or link train failure scenarios (previously forced via the force-failure entry). The entry will autoreset after the link-retrain is complete. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_debugfs.c | 46 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 18 ++++++-- 3 files changed, 60 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 098d0f5190723..4f19d30e6972f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1569,6 +1569,49 @@ DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, i915_dp_force_link_training_failure_show, i915_dp_force_link_training_failure_write, "%llu\n"); +static int i915_dp_force_link_retrain_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + *val = intel_dp->link_train.force_retrain; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} + +static int i915_dp_force_link_retrain_write(void *data, u64 val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + + intel_dp->link_train.force_retrain = val; + intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, + i915_dp_force_link_retrain_show, + i915_dp_force_link_retrain_write, "%llu\n"); + static int i915_dsc_output_format_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; @@ -1786,6 +1829,9 @@ void intel_connector_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, connector, &i915_dp_force_link_training_failure_fops); + + debugfs_create_file("i915_dp_force_link_retrain", 0644, root, + connector, &i915_dp_force_link_retrain_fops); } if (DISPLAY_VER(i915) >= 11 && diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 62acec5236052..345e2883d9cfc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1769,6 +1769,7 @@ struct intel_dp { /* Sequential failures after a passing LT */ int seq_failures; int force_failure; + bool force_retrain; } link_train; bool reset_link_params; int mso_link_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 367970f956863..28842ae51039a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5042,7 +5042,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); } - if (!link_ok) + if (!link_ok || intel_dp->link_train.force_retrain) intel_dp_queue_link_check(intel_dp, 0); return !reprobe_needed; @@ -5091,6 +5091,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) if (intel_psr_enabled(intel_dp)) return false; + if (intel_dp->link_train.force_retrain) + return true; + if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, link_status) < 0) return false; @@ -5229,8 +5232,9 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder, if (!intel_dp_needs_link_retrain(intel_dp)) return 0; - drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", - encoder->base.base.id, encoder->base.name); + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n", + encoder->base.base.id, encoder->base.name, + str_yes_no(intel_dp->link_train.force_retrain)); for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { const struct intel_crtc_state *crtc_state = @@ -5258,7 +5262,7 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder, encoder->base.base.id, encoder->base.name, ERR_PTR(ret)); - return ret; + goto out; } for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { @@ -5285,7 +5289,11 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder, intel_crtc_pch_transcoder(crtc), true); } - return 0; +out: + if (ret != -EDEADLK) + intel_dp->link_train.force_retrain = false; + + return ret; } static void intel_dp_link_check_work_fn(struct work_struct *work) From patchwork Tue May 14 19:14:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13664387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89D62C25B7C for ; Tue, 14 May 2024 19:14:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F21610EB33; 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X-CSE-ConnectionGUID: YS38B7C1Qo6dFO1xOc0x3A== X-CSE-MsgGUID: 4RTU8StAQUaK0+hH9CetmQ== X-IronPort-AV: E=McAfee;i="6600,9927,11073"; a="23125004" X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="23125004" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:35 -0700 X-CSE-ConnectionGUID: jRDVQjtvQbWpijIfzXo4mQ== X-CSE-MsgGUID: MaB+N1fWRqW2c74LLgcnHw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,159,1712646000"; d="scan'208";a="30724654" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2024 12:14:34 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 20/20] drm/i915/dp: Add debugfs entry for link training info Date: Tue, 14 May 2024 22:14:18 +0300 Message-ID: <20240514191418.2863344-21-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240514191418.2863344-1-imre.deak@intel.com> References: <20240514191418.2863344-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add counters for link training pass/failure events and a connector debugfs entry showing these and relevant link training information. This is meant to be used by automated testing of the driver's link retraining and link parameter fallback functionality. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_debugfs.c | 38 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 3 ++ drivers/gpu/drm/i915/display/intel_dp.c | 7 +++- .../drm/i915/display/intel_dp_link_training.c | 3 ++ 4 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 4f19d30e6972f..b25af91883584 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1612,6 +1612,41 @@ DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, i915_dp_force_link_retrain_show, i915_dp_force_link_retrain_write, "%llu\n"); +static int i915_dp_link_training_info_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int ret; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + seq_printf(m, + "max_rate: %d\n" + "max_lane_count: %d\n" + "train_count: %d\n" + "retrain_count: %d\n" + "retrain_disabled: %s\n" + "all_failures: %d\n" + "seq_failures: %d\n", + intel_dp->link_train.max_rate, + intel_dp->link_train.max_lane_count, + intel_dp->link_train.train_count, + intel_dp->link_train.retrain_count, + str_yes_no(intel_dp->link_train.retrain_disabled), + intel_dp->link_train.all_failures, + intel_dp->link_train.seq_failures); + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(i915_dp_link_training_info); + static int i915_dsc_output_format_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; @@ -1832,6 +1867,9 @@ void intel_connector_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_force_link_retrain", 0644, root, connector, &i915_dp_force_link_retrain_fops); + + debugfs_create_file("i915_dp_link_training_info", 0444, root, + connector, &i915_dp_link_training_info_fops); } if (DISPLAY_VER(i915) >= 11 && diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 345e2883d9cfc..6ff1819fc225e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1765,7 +1765,10 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + int train_count; + int retrain_count; bool retrain_disabled; + int all_failures; /* Sequential failures after a passing LT */ int seq_failures; int force_failure; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 28842ae51039a..0da081c457726 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2997,6 +2997,9 @@ void intel_dp_reset_link_train_params(struct intel_dp *intel_dp) intel_dp->link_train.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link_train.max_rate = intel_dp_max_common_rate(intel_dp); intel_dp->link_train.retrain_disabled = false; + intel_dp->link_train.train_count = 0; + intel_dp->link_train.retrain_count = 0; + intel_dp->link_train.all_failures = 0; intel_dp->link_train.seq_failures = 0; } @@ -5290,8 +5293,10 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder, } out: - if (ret != -EDEADLK) + if (ret != -EDEADLK) { + intel_dp->link_train.retrain_count++; intel_dp->link_train.force_retrain = false; + } return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index c260299c53b7c..c43af290a4373 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1484,6 +1484,8 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, else passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); + intel_dp->link_train.train_count++; + if (intel_dp->link_train.force_failure) { intel_dp->link_train.force_failure--; lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); @@ -1493,6 +1495,7 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, return; } + intel_dp->link_train.all_failures++; intel_dp->link_train.seq_failures++; /*