From patchwork Wed May 15 12:58:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13665210 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C28C0C25B7A for ; Wed, 15 May 2024 12:59:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=or/uNiCqeHcFdfSILnPaAqxjZu4tZ0+cVautOFfyYsA=; b=dthc24IMeG61VQ EdZQxOXPWaKJQIxvk6ighjJBWVJyBDk9qOXvQ6G3Og9Y453Z7blB3VTnYNv3mamXlN01mV6qFY+Hj c4S9zV7FFdn4OdKcCB+t4sxT31Y7EYNSkb7K4IcD/e7zXA8jt/jD3oni3TIEuiDVrwwAMyL+UuwlL O88JJ/oLfDvyArX8lE0j6uah5yPaWoRJk7CdD7yQalE16rWRPKISCqruO/oVvfaXr//20xVa6R0oH ui3jCJWCVMhjRB8hDkJEVOZYV8TuvD2cku44aURQMj2XUP3M+/s2yNJqUS6dDIyLXX7cNo8S4SqzU gF9LFf1TV0tKqs5EC3Rg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7EDy-00000001YwX-1R06; Wed, 15 May 2024 12:59:14 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7EDv-00000001Ytp-3qAv for linux-arm-kernel@lists.infradead.org; Wed, 15 May 2024 12:59:13 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id CC0C961481; Wed, 15 May 2024 12:59:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00FDDC116B1; Wed, 15 May 2024 12:59:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715777945; bh=GI2IWdF3zL4xqby+72i7WuWwWRZ0BXl3G3oCRRITxeI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ny8C95y75+Z0AZEbmCoJbAIG/tJC5kH81PkVknncJ/LLelmKXg9dSnEOYaT34aQzf RxIJwcjSqZ9of+u2gGw62h5VJxpDhO6fVbiZ0IlDtyj+vo4ksfe9bR+tO/G8Q3MYiV xwyNuscVgkni0V30Gv3hqw9t70V1qZo0/52gWQ8Mi/Pkn32fu2c7yUZ4udvnOZ9eZl gG9xEYlut4U95FGJvM0yVcsPehEBBPV7gpcpSZm4TbHNnjlbZLSlkr3lIkywQahe9E Eg5lQ3fswOCXokYUCT5P2yjW41BqYD+km6G49kw292kKauLfsXT0t3mxRmJ1FIgS+1 64zwupkHaokNg== From: Lorenzo Bianconi To: linux-clk@vger.kernel.org Cc: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH 1/5] dt-bindings: clock: airoha: Add reset support to EN7581 clock binding Date: Wed, 15 May 2024 14:58:47 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240515_055912_010351_D0496C70 X-CRM114-Status: UNSURE ( 8.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce reset capability to EN7581 device-tree clock binding documentation. Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi Acked-by: Conor Dooley --- .../bindings/clock/airoha,en7523-scu.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index 3f4266637733..22eee1ae90d5 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -43,6 +43,10 @@ properties: clocks. const: 1 + '#reset-cells': + description: ID of the controller reset line + const: 1 + required: - compatible - reg @@ -60,6 +64,8 @@ allOf: - description: scu base address - description: misc scu base address + '#reset-cells': false + - if: properties: compatible: @@ -83,3 +89,18 @@ examples: <0x1fb00000 0x1000>; #clock-cells = <1>; }; + + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + scuclk: clock-controller@1fa20000 { + compatible = "airoha,en7581-scu"; + reg = <0x0 0x1fa20000 0x0 0x400>, + <0x0 0x1fb00000 0x0 0x1000>, + <0x0 0x1fbe3400 0x0 0xfc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; From patchwork Wed May 15 12:58:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13665211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA02AC25B75 for ; Wed, 15 May 2024 12:59:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NL4/moAP+r0QTHl8rhTsuBY/Ludn3cU+MGoz/I5n9CE=; b=ZWDpg8PgF2YHpd leI3HRu0xfCJjG64OHqtLYAfc25X7t/qPwQH9VEo8RP5akkhEdqMS+09civ62sSTaU4UrXyJXgZkc F77kFKOJFAqF/mDEaWHItPNK3eOmMeJtm/O56l7gPMTa+wWjQzIm3smXa5VdL00jWzqDgTSrctI1M 3vH7fkW58mHpY4huucl/IH97atzboQKSzpTihFvamcvj49Q+uZsg+NV0Xzu052NCi4n/jO3sPqiJG x9fggIQnSo6LWkwIChhFWl3A1LVEb+0Dn7sINvqkxDp8+aUQ3PaRBbTo6Dk4BlhwO4X+wqTWhsj2v y+OQhMUTJfxTh9Vt37Kg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7EE0-00000001YxQ-12qW; Wed, 15 May 2024 12:59:16 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7EDv-00000001YuL-3ptV for linux-arm-kernel@lists.infradead.org; Wed, 15 May 2024 12:59:13 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 9FDA7614B7; Wed, 15 May 2024 12:59:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C61ABC4AF0B; Wed, 15 May 2024 12:59:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715777949; bh=QibeM2F1gzpesVZ5F/kxf0b9lNU3TuD+OPRRNfvg/0I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CVSUmrCszwvXqMvZ6o/KZe4Rnhjezo9mSbtvHGWprvyjHq7l8kaSEDKrm5EA7kEwe oUeQxBEAS1diSLW1/jTxR72cWqAlbtuuSctFnywZ0iqfx4g8mc3R6ecNBVc7QgT8x7 GI+0l4Kc9WEqZrR09r/Mf5DPWjGicRaCHTVha5R9GDpo84sg+x74Ckg8w0wfq3ICRi xHNjxsWWkcTD+SZdBzjVG40ud9UrWtlCKB1gSnMmGI5p6kWKHcMKeo9QedOJRsPIhr mED323XijE9qlueWyzWoTfIb+YchgET7+vM7xIkaBxjx0mrqFm3Y3+cewQqSlXDUR1 /sWLRgecANCYg== From: Lorenzo Bianconi To: linux-clk@vger.kernel.org Cc: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH 2/5] dt-bindings: reset: Add reset definitions for EN7581 SoC. Date: Wed, 15 May 2024 14:58:48 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240515_055912_073982_60AD1004 X-CRM114-Status: GOOD ( 10.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce reset binding definitions for reset controller available in the Airoha EN7581 clock module. Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi --- .../dt-bindings/reset/airoha,en7581-reset.h | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h new file mode 100644 index 000000000000..1b7ee62ed164 --- /dev/null +++ b/include/dt-bindings/reset/airoha,en7581-reset.h @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Lorenzo Bianconi + */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ + +/* RST_CTRL2 */ +#define EN7581_XPON_PHY_RST 0 +#define EN7581_CPU_TIMER2_RST 2 +#define EN7581_HSUART_RST 3 +#define EN7581_UART4_RST 4 +#define EN7581_UART5_RST 5 +#define EN7581_I2C2_RST 6 +#define EN7581_XSI_MAC_RST 7 +#define EN7581_XSI_PHY_RST 8 +#define EN7581_NPU_RST 9 +#define EN7581_I2S_RST 10 +#define EN7581_TRNG_RST 11 +#define EN7581_TRNG_MSTART_RST 12 +#define EN7581_DUAL_HSI0_RST 13 +#define EN7581_DUAL_HSI1_RST 14 +#define EN7581_HSI_RST 15 +#define EN7581_DUAL_HSI0_MAC_RST 16 +#define EN7581_DUAL_HSI1_MAC_RST 17 +#define EN7581_HSI_MAC_RST 18 +#define EN7581_WDMA_RST 19 +#define EN7581_WOE0_RST 20 +#define EN7581_WOE1_RST 21 +#define EN7581_HSDMA_RST 22 +#define EN7581_TDMA_RST 24 +#define EN7581_EMMC_RST 25 +#define EN7581_SOE_RST 26 +#define EN7581_PCIE2_RST 27 +#define EN7581_XFP_MAC_RST 28 +#define EN7581_USB_HOST_P1_RST 29 +#define EN7581_USB_HOST_P1_U3_PHY_RST 30 +/* RST_CTRL1 */ +#define EN7581_PCM1_ZSI_ISI_RST 32 +#define EN7581_FE_PDMA_RST 33 +#define EN7581_FE_QDMA_RST 34 +#define EN7581_PCM_SPIWP_RST 36 +#define EN7581_CRYPTO_RST 38 +#define EN7581_TIMER_RST 40 +#define EN7581_PCM1_RST 43 +#define EN7581_UART_RST 44 +#define EN7581_GPIO_RST 45 +#define EN7581_GDMA_RST 46 +#define EN7581_I2C_MASTER_RST 48 +#define EN7581_PCM2_ZSI_ISI_RST 49 +#define EN7581_SFC_RST 50 +#define EN7581_UART2_RST 51 +#define EN7581_GDMP_RST 52 +#define EN7581_FE_RST 53 +#define EN7581_USB_HOST_P0_RST 54 +#define EN7581_GSW_RST 55 +#define EN7581_SFC2_PCM_RST 57 +#define EN7581_PCIE0_RST 58 +#define EN7581_PCIE1_RST 59 +#define EN7581_CPU_TIMER_RST 60 +#define EN7581_PCIE_HB_RST 61 +#define EN7581_XPON_MAC_RST 63 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */ From patchwork Wed May 15 12:58:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13665212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4742AC25B79 for ; Wed, 15 May 2024 12:59:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DLM32OQnYAIUMJst/Map0GAOSJolFjRsJMMpJA8lVPE=; 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Wed, 15 May 2024 12:59:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715777952; bh=epj2XTyHV0DM4jDls6ECBOh89BAXVZ99Xrhk4jkYb+o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IQBM0ynzMTcS7seNAXo/ysDIRpiyMuJNQoVcmzdIg3fnqhUA4xYFwNRd2Z5iOU9pA u/xZFeLc5Jie+orK0zFWFdzIu9FYjRgUdPm3n872mX0POvVb8P0DefaKj6cJgdlYjF 2CxZrYxSB+okXkPhWeZxJtkDHr/JuMp5CRq5E98GFI+jTMkWFhFiJ+1cD7vC5f/CYT lXnKhlqsv6H8vwWBr9x5wISVIXbmAjlzL3/hASs56AcDtuYZMKhtc71AMHDuWgCYwP GR2j8sDu+OLdEXqBEFEgETAoXTLbkxN4ppbpXZjOribiRR7WEiCe/vvlCQealuZUyX 4AY3FiDu+A9yA== From: Lorenzo Bianconi To: linux-clk@vger.kernel.org Cc: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH 3/5] arm64: dts: airoha: Add reset-controller support to EN7581 clock node Date: Wed, 15 May 2024 14:58:49 +0200 Message-ID: <7c3cff0bb3fd93efc53500c51e5e28b645e56710.1715777643.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240515_055917_518449_CE9ED834 X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce reset capability to scuclk clock-controller device-tree node for EN7581 SoC. Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi --- arch/arm64/boot/dts/airoha/en7581.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi index 77fd37222a6a..f4d41b22e505 100644 --- a/arch/arm64/boot/dts/airoha/en7581.dtsi +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -158,6 +159,7 @@ scuclk: clock-controller@1fa20000 { <0x0 0x1fb00000 0x0 0x1000>, <0x0 0x1fbe3400 0x0 0xfc>; #clock-cells = <1>; + #reset-cells = <1>; }; snfi: spi@1fa10000 { From patchwork Wed May 15 12:58:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13665213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78464C25B75 for ; Wed, 15 May 2024 12:59:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ar5AJP15+e64WmR0b/GEzxFbBIf8aFpd0nd7rB1bcJ4=; b=xImZJVGrfiQBFq hb9nWI3tbm3+D/f6tvhBvs3g+J6onv/0hdn02GVz5cyWiKJD3LyCEB1RZbU+wNY1ZrYwyMgBqELWG acAd2e8cyPNdjONFxFYGZy/zikHUcsoToprqqJtDvArfG3fG772dewOQSKg9TNlbi1num+9xk60HP bLXna38twOtSZ8EnY/MZpP2HyK72CZZQfPkThFAAjmiFtWjwN7glEGD41z9G1DZ6qjo3NIWJWTFDn XQwfoMzzfOVTOOhueACsmsZM4c1NNgRxKh2BJzC0l4OlBmUEp1FiRP4dhacotBWBPxwo+n8bbIN6J mJK44roXG3AHbFBLb0lQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7EEF-00000001Z3c-1BCx; Wed, 15 May 2024 12:59:31 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7EE4-00000001Yyd-0irc for linux-arm-kernel@lists.infradead.org; Wed, 15 May 2024 12:59:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 95FDDCE139E; Wed, 15 May 2024 12:59:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28DD5C116B1; Wed, 15 May 2024 12:59:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715777956; bh=ZB9eG4dWLioh04ljT5vudxJJ7ZSncKp0nvhSMD6GfbY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BgsSv0R+UAeBF4s5d+GGRT3As0GHu/wHBU9I7oN/rR9rReCFxBfSeYqreSDv+/q9l VSK56uIYPAxwwKmLfZPAgBUWX6CuPeCojHKga0YfdFLCczRT6sHTJ/4vXzCogVfAL6 A9EmoJMbO9PmPCoKAiqJHPss6bFduiQ7RwjI+dWlzwDABB164XldGNqT1jDa+YzF2s 9Z+P6VQWLZgpkcK1SwMb8+iM9F2/JGYyGJUvMwNL50bBCBogFsA8Xr3xTlxZYLVajr 6swcosSU90tQWDCe50mJG8uO9ZKx1vrpfCE+bq6BIKpFVLrmWpHOkebwTDDUhHMh4f f7eFqz7tVmCyg== From: Lorenzo Bianconi To: linux-clk@vger.kernel.org Cc: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH 4/5] clk: en7523: Add reset-controller support for EN7581 SoC Date: Wed, 15 May 2024 14:58:50 +0200 Message-ID: <0f7b04c2101db1a974dc45017bee285ffb25d80f.1715777643.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240515_055920_798949_DCF72A44 X-CRM114-Status: GOOD ( 17.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce reset API support to EN7581 clock driver. Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 96 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 381605be333f..18798b692b68 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #define REG_PCI_CONTROL 0x88 @@ -65,8 +66,18 @@ struct en_clk_gate { struct clk_hw hw; }; +#define RST_NR_PER_BANK 32 +struct en_reset_data { + void __iomem *mem_base; + struct reset_controller_dev rcdev; +}; + struct en_clk_soc_data { const struct clk_ops pcie_ops; + struct { + u32 base_addr; + u16 n_banks; + } reset_data; int (*hw_init)(struct platform_device *pdev, void __iomem *base, void __iomem *np_base); }; @@ -424,6 +435,81 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->num = EN7523_NUM_CLOCKS; } +static int en7523_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + int offset = id % RST_NR_PER_BANK; + int bank = id / RST_NR_PER_BANK; + struct en_reset_data *rst_data; + u32 val; + + rst_data = container_of(rcdev, struct en_reset_data, rcdev); + val = readl(rst_data->mem_base + bank * sizeof(u32)); + if (assert) + val |= BIT(offset); + else + val &= ~BIT(offset); + writel(val, rst_data->mem_base + bank * sizeof(u32)); + + return 0; +} + +static int en7523_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return en7523_reset_update(rcdev, id, true); +} + +static int en7523_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return en7523_reset_update(rcdev, id, false); +} + +static int en7523_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int offset = id % RST_NR_PER_BANK; + int bank = id / RST_NR_PER_BANK; + struct en_reset_data *rst_data; + u32 val; + + rst_data = container_of(rcdev, struct en_reset_data, rcdev); + val = readl(rst_data->mem_base + bank * sizeof(u32)); + + return !!(val & BIT(offset)); +} + +static const struct reset_control_ops en7523_reset_ops = { + .assert = en7523_reset_assert, + .deassert = en7523_reset_deassert, + .status = en7523_reset_status, +}; + +static int en7523_reset_register(struct device *dev, void __iomem *base, + const struct en_clk_soc_data *soc_data) +{ + u32 nr_resets = soc_data->reset_data.n_banks * RST_NR_PER_BANK; + struct en_reset_data *rst_data; + + /* no reset lines available */ + if (!nr_resets) + return 0; + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->mem_base = base + soc_data->reset_data.base_addr; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.ops = &en7523_reset_ops; + rst_data->rcdev.of_node = dev->of_node; + rst_data->rcdev.dev = dev; + rst_data->rcdev.nr_resets = nr_resets; + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int en7523_clk_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; @@ -456,12 +542,14 @@ static int en7523_clk_probe(struct platform_device *pdev) en7523_register_clocks(&pdev->dev, clk_data, base, np_base); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) + if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + return r; + } - return r; + return en7523_reset_register(&pdev->dev, np_base, soc_data); } static const struct en_clk_soc_data en7523_data = { @@ -480,6 +568,10 @@ static const struct en_clk_soc_data en7581_data = { .unprepare = en7581_pci_unprepare, .disable = en7581_pci_disable, }, + .reset_data = { + .base_addr = REG_RESET_CONTROL2, + .n_banks = 2, + }, .hw_init = en7581_clk_hw_init, }; From patchwork Wed May 15 12:58:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13665214 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D763C25B75 for ; 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Wed, 15 May 2024 12:59:32 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7EE8-00000001YzM-3cd6 for linux-arm-kernel@lists.infradead.org; Wed, 15 May 2024 12:59:27 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 7FD0DCE139B; Wed, 15 May 2024 12:59:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F246AC32786; Wed, 15 May 2024 12:59:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715777960; bh=t31bk/mDVqDcjRyQf5UPlVkeFHJ51T4adyE2JP2QztA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HbiDBg0UDUi6lhs5TVLRbS1FyYTKm/3ELbRp77tin5xmJYsnm9bAUZuAWcK34eylC GXP0hejfLweOE7q8XuwEG/fVZ5iY21zYzMPX1EvXE8kpmSBieA99vXcb8tQxpUWrVI 6eteGkXKpttGEnsaIR2VTNZQHMILIM7orilijoEluI4j0rec4ufWsm+UL41qNLkNV4 W1fBh3q+s9CKTTtCCjmOFQsLa21qG2ssrHZteW0fWepB34YunxbybXX17zlZgF3E6d jXjcnxWuJE371jr3IIBAJfkXWPtXRJn89S8yw9Ar6sezJUPLfyO1DQFUkIe23rrB0+ Jq8L9O/X3eFvA== From: Lorenzo Bianconi To: linux-clk@vger.kernel.org Cc: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH 5/5] clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC Date: Wed, 15 May 2024 14:58:51 +0200 Message-ID: <92afb628058a31357e0c85ed7e41eed0a780bc0f.1715777643.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240515_055925_453661_E448DBEE X-CRM114-Status: GOOD ( 11.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Get rid of prepare and unpreare callbacks for PCIe clock since they can be modeled as a reset line cosumed by the PCIe driver (pcie-mediatek-gen3) Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/clk-en7523.c | 41 ++-------------------------------------- 1 file changed, 2 insertions(+), 39 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 18798b692b68..5f2127a4b150 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -291,9 +291,8 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev, cg->base = np_base; cg->hw.init = &init; - if (init.ops->disable) - init.ops->disable(&cg->hw); - init.ops->unprepare(&cg->hw); + if (init.ops->unprepare) + init.ops->unprepare(&cg->hw); if (clk_hw_register(dev, &cg->hw)) return NULL; @@ -311,23 +310,6 @@ static int en7581_pci_is_enabled(struct clk_hw *hw) return (val & mask) == mask; } -static int en7581_pci_prepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; - - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | - REG_RESET_CONTROL_PCIEHB; - val = readl(np_base + REG_RESET_CONTROL1); - writel(val & ~mask, np_base + REG_RESET_CONTROL1); - val = readl(np_base + REG_RESET_CONTROL2); - writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2); - usleep_range(5000, 10000); - - return 0; -} - static int en7581_pci_enable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); @@ -344,23 +326,6 @@ static int en7581_pci_enable(struct clk_hw *hw) return 0; } -static void en7581_pci_unprepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; - - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | - REG_RESET_CONTROL_PCIEHB; - val = readl(np_base + REG_RESET_CONTROL1); - writel(val | mask, np_base + REG_RESET_CONTROL1); - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2; - writel(val | mask, np_base + REG_RESET_CONTROL1); - val = readl(np_base + REG_RESET_CONTROL2); - writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2); - msleep(100); -} - static void en7581_pci_disable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); @@ -563,9 +528,7 @@ static const struct en_clk_soc_data en7523_data = { static const struct en_clk_soc_data en7581_data = { .pcie_ops = { .is_enabled = en7581_pci_is_enabled, - .prepare = en7581_pci_prepare, .enable = en7581_pci_enable, - .unprepare = en7581_pci_unprepare, .disable = en7581_pci_disable, }, .reset_data = {