From patchwork Sat May 18 09:31:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BF86C25B79 for ; Sat, 18 May 2024 09:34:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQP-0006Lp-Kc; Sat, 18 May 2024 05:32:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQJ-0006Ip-O4; Sat, 18 May 2024 05:32:15 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQI-0005hn-31; Sat, 18 May 2024 05:32:15 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1edc696df2bso36166445ad.0; Sat, 18 May 2024 02:32:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024732; x=1716629532; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=91uP2jL5cMpjHFlYh8Ox6n/w/HTZkVs7U55uKl7yZTo=; b=hpox4f4R6Dzt7QZRpHQt5KwYWw0Yjmle06wDlkBYHj94HbLSz5bYryPmZmMjYoPbo4 R5bIFBm/m3ppwnKPTiKgeGJSx0kPwOyXclw9DMTlB9XqtPL/bl5g8+SDoIcIjMvnbu5c Cr02fc9DdUhRekVYioDEjiqh7N0YaLR26ikt5y8Zy+vVu5z/tVXrKBL7A+zRoIGh7yyt rW1Y3YxWKut6RLEb3RHHAN1kTEMbCde/LgJ1U2PqerCXJ+GQCCCPGAoOOeTcjYnivTLj rd/ahlvdH9axkq+0J+ehdvxwTzTJQrnlLDp1tVWBxWi2ixMuucvS7f4cp9LYOLGPkk5m jLtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024732; x=1716629532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=91uP2jL5cMpjHFlYh8Ox6n/w/HTZkVs7U55uKl7yZTo=; b=ZFf5bI8cfp9zXedpDt4Yk7Y2emm2q5khl1Vh3TMc3SWgpore0bIGBgbOVUOjELZ8kl 6BOsnCcDbg8uYHz1YORLtihqLzgmF/TFph3FTWAUEB9mWOrk5y3TjtKdEln+9ao5gxcD nClzn+8PQ1P41M/GXI0feZSfFG7FUvAQ1YGpPnrmZSn36bHhSZhr9qqyAsd/Q2WXjglY QgWQ4Evf/ltcjWPHE7oiGC9Um2lhl40kvQBOeJyQ58aNi4L7VN4GeJBSHPlpXU3bNi9m D7JEM2FkXFFtUArmtSpkiNcxaQ01d6fYVh7tfkwio18+UzdsivYR93lMQmbZjaTCVovR ZIHA== X-Forwarded-Encrypted: i=1; AJvYcCW4/SJnnoAMsHoZRCeH8zu5qyeHtz+58rbTRCzDNzloGLIHHbrb9bmn/qGi5l5kRyA6RH69vnYSz6I0bya5EPsDEZpTE+U= X-Gm-Message-State: AOJu0Yws9dTO0KqzbR+1gMkB750EGn5Fs7S6R6IWFS8NeWPZM6YtSezJ mfnrwnG4XNdpmArcJKEinGTRFqIwnlE+x6GznkNq4JsHglQF+Abm8GfJXA== X-Google-Smtp-Source: AGHT+IF4deljv39U6EykMVVdrFzAfsIpOdo8//6tfvN0VJT4Jxq/QUCWHurUIXVF7QoYYMfZumS5gg== X-Received: by 2002:a05:6a20:394f:b0:1af:cea1:7ea5 with SMTP id adf61e73a8af0-1afde1d9183mr27619667637.57.1716024732002; Sat, 18 May 2024 02:32:12 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:11 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 01/14] target/ppc: larx/stcx generation need only apply DEF_MEMOP() once Date: Sat, 18 May 2024 19:31:43 +1000 Message-ID: <20240518093157.407144-2-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use DEF_MEMOP() consistently in larx and stcx. generation, and apply it once when it's used rather than where the macros are expanded, to reduce typing. Signed-off-by: Nicholas Piggin Reviewed-by: Richard Henderson --- target/ppc/translate.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a8fd6ef3ae..0882fe2fd2 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2913,7 +2913,7 @@ static void gen_load_locked(DisasContext *ctx, MemOp memop) gen_set_access_type(ctx, ACCESS_RES); gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); + tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); tcg_gen_mov_tl(cpu_reserve, t0); tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); tcg_gen_mov_tl(cpu_reserve_val, gpr); @@ -2926,9 +2926,9 @@ static void gen_##name(DisasContext *ctx) \ } /* lwarx */ -LARX(lbarx, DEF_MEMOP(MO_UB)) -LARX(lharx, DEF_MEMOP(MO_UW)) -LARX(lwarx, DEF_MEMOP(MO_UL)) +LARX(lbarx, MO_UB) +LARX(lharx, MO_UW) +LARX(lwarx, MO_UL) static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, TCGv EA, TCGCond cond, int addend) @@ -3173,15 +3173,15 @@ static void gen_##name(DisasContext *ctx) \ gen_conditional_store(ctx, memop); \ } -STCX(stbcx_, DEF_MEMOP(MO_UB)) -STCX(sthcx_, DEF_MEMOP(MO_UW)) -STCX(stwcx_, DEF_MEMOP(MO_UL)) +STCX(stbcx_, MO_UB) +STCX(sthcx_, MO_UW) +STCX(stwcx_, MO_UL) #if defined(TARGET_PPC64) /* ldarx */ -LARX(ldarx, DEF_MEMOP(MO_UQ)) +LARX(ldarx, MO_UQ) /* stdcx. */ -STCX(stdcx_, DEF_MEMOP(MO_UQ)) +STCX(stdcx_, MO_UQ) /* lqarx */ static void gen_lqarx(DisasContext *ctx) From patchwork Sat May 18 09:31:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF848C25B7A for ; Sat, 18 May 2024 09:34:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQP-0006Lo-HE; Sat, 18 May 2024 05:32:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQN-0006KU-22; Sat, 18 May 2024 05:32:20 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQL-0005kP-Ez; Sat, 18 May 2024 05:32:18 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1edf506b216so31078635ad.2; Sat, 18 May 2024 02:32:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024735; x=1716629535; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/DkuaTx6S9bv21jsAgT9nwS8XQdb1YTrH6xUMOIF84w=; b=ReNrKZwT9djcc02Pr6o5bbGL2IDE8OZdgpIeqwvZoXlktE1kbHDqxoj7BHEa6qq+ad PrpOwWQWws0SB0PP9CEV24A+thv4PsE9coVZV3ZvMs6nNTG5z+a9uN9q43s29F3iIQLx 9o5/hKfw9hc7Nhy0ZibM2zj+wDdPX0LSe0HyJI5aLShufSTeY9icRIfNApel3tCFljRs 3prQsNcYpD91sj0NojM7HeADGI/rhcBXU7X5bQV+GcOGZN++yMU8xUgm4wFgQMpRyahz tp9C6TVp0sgti5t7josonXYdTnNWUsZgig4YlNq179Gw3gJXTH2XGYCXAPj2e4JeyyO+ 9FGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024735; x=1716629535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/DkuaTx6S9bv21jsAgT9nwS8XQdb1YTrH6xUMOIF84w=; b=YIRS3w81Cdu+8EFyA6b00cPo7vkwdw+6eUyVF4w+ybyVfIL2fPpV3dOV0QzIEr1q7F e6OilV9BUBj5zaZ5sfC2+jOlBa6kQXrCb25xu0Wh26ux9+tN0oLXw0f3wX0rQ2J7bYVl yMR8TIo2Bqha7yraQFCJiTXJ1cHaLRSausAeQ+2DbDRmd9pfrGSmzN75iiFC5mqP2wES 36Bk1MTx9wR864hFhvCAVxQum3ldOPQ+cYItSO2BzYZXIZtOK2S4QYje4H2XWMHbGRXJ 4USnR7u3g3J1sC5exXbjdF14SI267KwGhCrQ+bS3W48jsvTQjHsEEYVhDglIgtepg7IV XzLw== X-Forwarded-Encrypted: i=1; AJvYcCV+SYZZkKd4/oJSZau/4uPQePW+hYhOQiBGMUGCYCxEqtILAZYOdsxefkG6CU6TXnfEe43mQphKDd8dRWgSKpsXjSuy2pY= X-Gm-Message-State: AOJu0YwLNwpsvd0SUXJha732vBEWUIIZm8oxjBgcEwq/ashtMliwb6PO FB358BFfK8q0SOOqiHuFIA5QKnUjUcNdcFOnCAfslyltuVP6HDr1wOYMmg== X-Google-Smtp-Source: AGHT+IElv1wAahrvZxYGUKpEQsiAvx8JKDwHaPbxJ3oq1Uqmyi5zG7HI4+todDG+rDhZWw45Wfp35g== X-Received: by 2002:a05:6a20:7fa6:b0:1ad:7ff5:cb38 with SMTP id adf61e73a8af0-1afde238da3mr26284409637.60.1716024735166; Sat, 18 May 2024 02:32:15 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:14 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 02/14] target/ppc: Remove redundant MEMOP_GET_SIZE macro Date: Sat, 18 May 2024 19:31:44 +1000 Message-ID: <20240518093157.407144-3-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=npiggin@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There is a memop_size() function for this. Signed-off-by: Nicholas Piggin Reviewed-by: BALATON Zoltan Reviewed-by: Richard Henderson --- target/ppc/translate.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0882fe2fd2..cf2404330b 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2904,8 +2904,6 @@ static void gen_isync(DisasContext *ctx) ctx->base.is_jmp = DISAS_EXIT_UPDATE; } -#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) - static void gen_load_locked(DisasContext *ctx, MemOp memop) { TCGv gpr = cpu_gpr[rD(ctx->opcode)]; @@ -2938,7 +2936,7 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, TCGv u = tcg_temp_new(); tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); - tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); + tcg_gen_addi_tl(t2, EA, memop_size(memop)); tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); tcg_gen_addi_tl(u, t, addend); @@ -2948,7 +2946,7 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ - tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); + tcg_gen_movi_tl(u, 1 << (memop_size(memop) * 8 - 1)); tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); } @@ -3110,7 +3108,7 @@ static void gen_st_atomic(DisasContext *ctx, MemOp memop) TCGv ea_plus_s = tcg_temp_new(); tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); - tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); + tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); From patchwork Sat May 18 09:31:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97A39C25B74 for ; Sat, 18 May 2024 09:33:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQc-0006Q1-62; Sat, 18 May 2024 05:32:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQU-0006Mb-1l; Sat, 18 May 2024 05:32:26 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQO-0005nO-3O; Sat, 18 May 2024 05:32:24 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1ee42b97b32so32110515ad.2; Sat, 18 May 2024 02:32:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024738; x=1716629538; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=usId0Lc202jfAnfSqLrsahzDXKSkcKXOT0TjzknQTYs=; b=R+gYyilghIYJlyrxpsa+GtBSuAPsZslTDvI/kqDqn1O4cubpF6yU25o3EL/gTmegUu FJXr8TB0NhMXU3/pfnzaBe0v6oQJSR0CFpBA22ZHHgy+gmFWJVt7yfwpfQ6AN92nDd1V JiDRZ2iVvmPNRyxuZ2MIa7FqiHxOYvq2OSSL6RPNK2qmVAsxa/oBgIPoe1JAFP4SrghJ t3f2EDtoP3tOI+0IhV/bfp0Gf0+ja/f5A0dbt0IA4YV/lz1T4XhUIVtCmWtLJFpvdn2X HCK0HjogjS12KiVab1Fqg65+BBCYyu2B+zL+qmD2rlvO+LQTsLkwoBXrlYDwdmKjdNRE YacA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024738; x=1716629538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=usId0Lc202jfAnfSqLrsahzDXKSkcKXOT0TjzknQTYs=; b=FtvKH3GbdQhHTx+hQj3YYjvcasphIbGSJz+nZHJgA24noxJHfuSFmZ4blHVAZN1cGk cFvo4iTJkrcaHc7BsDVaNJEeb3bA6g80z6IFNrc3+wiB1jSM6sHMz1mPjW0TYJ0djCJi Ljtp20gSJhmwnL9fx1G/XEPf0LYrcUbq8NdlLxIc7IeaYHhMms1cn0K/skVAVE+rp1q7 MgZ8i81JwTFI10BRdYtQuIsgliR1/4o48PVyrrEGW+glie3aeAENFuJILycKvI9DKlkm G6Rr4qRtj4X4GUTiT4RVJkYvdsJyMCYSt4FlkO2gv4vodONO+XsVkkIY1crtu7tmC7xw 4KzA== X-Forwarded-Encrypted: i=1; AJvYcCXSY/M237tffIO+ZX3ZPeu08VOy87Nl9UshNZQibO1ABJbGknjBJcOwUds8pQNyEJFexYxSJP0Y+QJ46iH4Oyc+JNBehqU= X-Gm-Message-State: AOJu0YyjJWlJlX1he9QC9HgFOWwazrJb6UFPctYjV4bizpLm/uaqNQU7 LjXF/FgaxHSe1VVLLdgueLR0QrivZyooTV+5Yr9+GP30KDM9oD9zR2DhDA== X-Google-Smtp-Source: AGHT+IG4gBQf3huoEGmX0EjI343YhBArR7mukcvm6haRtMGnZnQ9FFmjLMe+XZnF2SH5GrP9HDp81g== X-Received: by 2002:a17:90b:696:b0:29b:b5a4:c040 with SMTP id 98e67ed59e1d1-2b6cd1f0510mr20912068a91.46.1716024738149; Sat, 18 May 2024 02:32:18 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:17 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 03/14] target/ppc: Make checkstop actually stop the system Date: Sat, 18 May 2024 19:31:45 +1000 Message-ID: <20240518093157.407144-4-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=npiggin@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org checkstop state does not halt the system, interrupts continue to be serviced, and other CPUs run. Make it stop the machine with qemu_system_guest_panicked. Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2e3f36a3ef..fd00c044b5 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -19,6 +19,8 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "qemu/log.h" +#include "sysemu/sysemu.h" +#include "sysemu/runstate.h" #include "cpu.h" #include "exec/exec-all.h" #include "internal.h" @@ -425,6 +427,8 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector, static void powerpc_mcheck_checkstop(CPUPPCState *env) { + /* KVM guests always have MSR[ME] enabled */ +#ifdef CONFIG_TCG CPUState *cs = env_cpu(env); if (FIELD_EX64(env->msr, MSR, ME)) { @@ -437,9 +441,15 @@ static void powerpc_mcheck_checkstop(CPUPPCState *env) if (qemu_log_separate()) { qemu_log("Machine check while not allowed. " "Entering checkstop state\n"); - } - cs->halted = 1; - cpu_interrupt_exittb(cs); + + /* + * This stops the machine and logs CPU state without killing QEMU + * (like cpu_abort()) so the machine can still be debugged (because + * it is often a guest error). + */ + qemu_system_guest_panicked(NULL); + cpu_loop_exit_noexc(cs); +#endif } static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) From patchwork Sat May 18 09:31:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0A05C25B7A for ; Sat, 18 May 2024 09:34:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQd-0006R4-Fg; Sat, 18 May 2024 05:32:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQb-0006PB-Q8; Sat, 18 May 2024 05:32:33 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQR-0005oa-Cc; Sat, 18 May 2024 05:32:26 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1eca195a7c8so31828615ad.2; Sat, 18 May 2024 02:32:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024741; x=1716629541; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VgJrCCZZWo/VI2Gs8h/qaG/qmQuOyLSxM5HbB7cUtW8=; b=YYshcTmyM1K7FI+nP7w5Ok6Q5/29XNGrWsgqwgc4SogdW5kLE/v9sj581zXAIYXGM6 smnqoFLMJ66JuerKuMxZs5RpttSlmNWcEspgdFf0wDMz3qnOiY6rOkcH735MEwc4h+Rj Ffv62uHiww23dlxw4u3TqulF3YXIoSbbsD8DEkQf+mWkBYxzg5AKv0sPgQzXjyXFLSKx BAq7PwU20bzisoA00yfPzB2CV1YkA/jzNrLiycc/LGNRAIbCdwLecxIvZSW1WVlact9V wRDry09w/zyt3wFVuN/UGXsz/oUDZEtr+oTeNeQfjsPBUY8TzPi3sfBC9Z69J4nTeVNG J8TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024741; x=1716629541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VgJrCCZZWo/VI2Gs8h/qaG/qmQuOyLSxM5HbB7cUtW8=; b=UdMC9sgWxuwSDBtrs4Oj5lod4K+16a99ey/CPvSujNiu2Q3Kb+m7XgeOK+U1W8BnAp j01dwYGLFyYOk3TgxgTTilf0Q5Sn1yf0vS0rVk9SaNqmrPsGfSss5HMyArDdrQGVkkaS bzrBspVDrCQD3Yml/nNCxL5kEY5gkjiKKGmm7RJwGovGtzDcrNoSXOJpUw+n6mDY+i5H /+n11A/FjcCPm43or4f2d2UfD32zas+nR7RBp60CxZAtV15oSxKpuOQ8CeUF3KL1NYfL mcJccUIcl/QJkxNo5HeFzyqm5tlAXLOTuYSRwNbxbrkIOhglVmxXJ5TCDuJ31SkShN04 rbzQ== X-Forwarded-Encrypted: i=1; AJvYcCU0y1GlGCZ9hpcf376VLWylb0l92sbQS5TK7THddLsh48chWLUvm6zZO5GE4GHPXSC9Z+M0tRFQoqiuWXhCc20/AE+jr7E= X-Gm-Message-State: AOJu0YxojF+iYTeIUbX/6U6ak+rfPA8Jp5q86dazkYszOR1jpn9Qzkn3 5egNS9uVutPiecbiIdpYIKYfiZSpYVIODIsRX/zVtNp/Zf/zER+gJ3b/Hg== X-Google-Smtp-Source: AGHT+IFOxM7n74TgMVUm3YbbzQFZO7XzCT2I4T8O56HkzNPPiBGp0F4OE65IyWuaagmMHzMr4qAXwg== X-Received: by 2002:a05:6a20:9190:b0:1a9:852f:6acf with SMTP id adf61e73a8af0-1afde0a8e5dmr25261146637.11.1716024741426; Sat, 18 May 2024 02:32:21 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:21 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 04/14] target/ppc: improve checkstop logging Date: Sat, 18 May 2024 19:31:46 +1000 Message-ID: <20240518093157.407144-5-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Change the logging not to print to stderr as well, because a checkstop is a guest error (or perhaps a simulated machine error) rather than a QEMU error, so send it to the log. Update the checkstop message, and log CPU registers too. Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index fd00c044b5..a283c97717 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -430,17 +430,19 @@ static void powerpc_mcheck_checkstop(CPUPPCState *env) /* KVM guests always have MSR[ME] enabled */ #ifdef CONFIG_TCG CPUState *cs = env_cpu(env); + FILE *f; if (FIELD_EX64(env->msr, MSR, ME)) { return; } - /* Machine check exception is not enabled. Enter checkstop state. */ - fprintf(stderr, "Machine check while not allowed. " - "Entering checkstop state\n"); - if (qemu_log_separate()) { - qemu_log("Machine check while not allowed. " - "Entering checkstop state\n"); + f = qemu_log_trylock(); + if (f) { + fprintf(f, "Entering checkstop state: " + "machine check with MSR[ME]=0\n"); + cpu_dump_state(cs, f, CPU_DUMP_FPU | CPU_DUMP_CCOP); + qemu_log_unlock(f); + } /* * This stops the machine and logs CPU state without killing QEMU From patchwork Sat May 18 09:31:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F3C9C25B79 for ; Sat, 18 May 2024 09:33:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQj-0006Tz-Cj; Sat, 18 May 2024 05:32:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQg-0006ST-3z; Sat, 18 May 2024 05:32:38 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQb-0005qX-Tp; Sat, 18 May 2024 05:32:37 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1ec69e3dbcfso34485645ad.0; Sat, 18 May 2024 02:32:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024745; x=1716629545; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FHqcueLBkS8ANZ0j7fPRW9oemlEK95KWCnXRcDNjUxA=; b=d8179XgBD5n2d5A3VH/r076SXiYkRlqDFqX7t/bw7bP2R5sYpiH20HeOxiOxWpc+33 B58z4h3NNfopdwVPk5Xl2Ytu+8tuDgLYuz0hgh09U8KC6pwGksrH15cD6Fp9JXfoeT1p FzCj82jukhLVj5fR81OcQc1Cgs5L5878i3aze6JwdemDFBqrZbSXKxXaas+UPsdwwPUY MIJXSXE6FjwLSkE+Rt68mHMdmeJC5LvnTGgN/z04GOvOGAPxtZEDXtMOFC3dHAK0tRVZ 1+GQyfg6GDJ4jnhmCJPFgsQ03pLaKioZgfFGkD4j40ipQZrL8GaSy9+v7u8RV7rFdLfB 5vOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024745; x=1716629545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FHqcueLBkS8ANZ0j7fPRW9oemlEK95KWCnXRcDNjUxA=; b=KSWBbJ7KcRnMDP+AiIxcGd2fKaXknaZLsu8hkS2eGk76YCSUyioNQ72/EbtOsjMgLV EC9niNa9z6oAuiS6rEhVDeYCcSpmbBHZQB/eVLZ1P39ZpPAPep8VpfJJqDMabBw0ZpFj xO91WXu8Rt1a+2gwaNriRCq2kOFWqgidM/uYsoXxd4YN9IylEC1vJ3NaPwZrXbYdeHyb y7sMKbDwylktZyM52p4nb5yx+hvZ3INyLnEWbo2gJW5FpfGrogEsETe7HzXMXcm6KGmL h7BZDnQGMP5vw8i1mEvoHCr+yJWUdd4NnnE+5jc02mWHLSbs/YosnfxyAjaRPj/W0bSt ZLlw== X-Forwarded-Encrypted: i=1; AJvYcCW5jzm841YjmGfkGmQR5dD48CkXtWSlCtQwJ3osC7T4l1CRm4p8kpboqL2e4Dg3Zwu+xsTe7SO6rdJ3fU1G3EQ2DPNDT2w= X-Gm-Message-State: AOJu0YwZc78qWhkXkQcd06xzJ8n1HIwZEsKhSWEtzQhvdtkm89Asu8A0 1awPUec6NoQCapX040PHiZ3U5JfeqpFPH9G4wgpY6nQi5GxJghauXGmYkA== X-Google-Smtp-Source: AGHT+IFHZ9zR0H59QpBiHaMQuvzRswhK7g4oaBUabLGqBSKQwbrJMHMUfD5loJOSMgpqlXurVXXPhw== X-Received: by 2002:a05:6a20:9709:b0:1af:6a37:3cfd with SMTP id adf61e73a8af0-1afde0d5439mr19060628637.24.1716024744629; Sat, 18 May 2024 02:32:24 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:24 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 05/14] target/ppc: Implement attn instruction on BookS 64-bit processors Date: Sat, 18 May 2024 19:31:47 +1000 Message-ID: <20240518093157.407144-6-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=npiggin@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org attn is an implementation-specific instruction that on POWER (and G5/ 970) can be enabled with a HID bit (disabled = illegal), and executing it causes the host processor to stop and the service processor to be notified. Generally used for debugging. Implement attn and make it checkstop the system, which should be good enough for QEMU debugging. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 16 +++++++- target/ppc/helper.h | 1 + target/ppc/cpu_init.c | 82 +++++++++++++++++++++++++++++++++++++--- target/ppc/excp_helper.c | 39 +++++++++++++++---- target/ppc/translate.c | 11 ++++++ 5 files changed, 135 insertions(+), 14 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c358927211..2f7fab22ba 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1375,6 +1375,9 @@ struct CPUArchState { /* Power management */ int (*check_pow)(CPUPPCState *env); + /* attn instruction enable */ + int (*check_attn)(CPUPPCState *env); + #if !defined(CONFIG_USER_ONLY) void *load_info; /* holds boot loading state */ #endif @@ -1523,6 +1526,7 @@ struct PowerPCCPUClass { int n_host_threads; void (*init_proc)(CPUPPCState *env); int (*check_pow)(CPUPPCState *env); + int (*check_attn)(CPUPPCState *env); }; ObjectClass *ppc_cpu_class_by_name(const char *name); @@ -2320,6 +2324,8 @@ void ppc_compat_add_property(Object *obj, const char *name, #define HID0_NAP (1 << 22) /* pre-2.06 */ #define HID0_HILE PPC_BIT(19) /* POWER8 */ #define HID0_POWER9_HILE PPC_BIT(4) +#define HID0_ENABLE_ATTN PPC_BIT(31) /* POWER8 */ +#define HID0_POWER9_ENABLE_ATTN PPC_BIT(3) /*****************************************************************************/ /* PowerPC Instructions types definitions */ @@ -2516,6 +2522,8 @@ enum { PPC2_MEM_LWSYNC = 0x0000000000200000ULL, /* ISA 2.06 BCD assist instructions */ PPC2_BCDA_ISA206 = 0x0000000000400000ULL, + /* attn instruction found in IBM POWER (including 970) */ + PPC2_ATTN = 0x0000000000800000ULL, #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ @@ -2525,7 +2533,7 @@ enum { PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \ - PPC2_BCDA_ISA206) + PPC2_BCDA_ISA206 | PPC2_ATTN) }; /*****************************************************************************/ @@ -3025,6 +3033,12 @@ static inline int check_pow_nocheck(CPUPPCState *env) return 1; } +/* attn enable check */ +static inline int check_attn_none(CPUPPCState *env) +{ + return 0; +} + /*****************************************************************************/ /* PowerPC implementations definitions */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 55293e20a9..09d50f9b76 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -825,5 +825,6 @@ DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env) #if defined(TARGET_PPC64) DEF_HELPER_1(clrbhrb, void, env) DEF_HELPER_FLAGS_2(mfbhrbe, TCG_CALL_NO_WG, i64, env, i32) +DEF_HELPER_1(attn, noreturn, env) #endif #endif diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 1ec84b5ddc..71da8d4856 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2107,6 +2107,26 @@ static int check_pow_hid0_74xx(CPUPPCState *env) return 0; } +#if defined(TARGET_PPC64) +static int check_attn_hid0(CPUPPCState *env) +{ + if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { + return 1; + } + + return 0; +} + +static int check_attn_hid0_power9(CPUPPCState *env) +{ + if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { + return 1; + } + + return 0; +} +#endif + static void init_proc_405(CPUPPCState *env) { register_40x_sprs(env); @@ -2138,6 +2158,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) dc->desc = "PowerPC 405"; pcc->init_proc = init_proc_405; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_DCR | PPC_WRTEE | PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | @@ -2210,6 +2231,7 @@ POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) dc->desc = "PowerPC 440 EP"; pcc->init_proc = init_proc_440EP; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -2248,6 +2270,7 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) dc->desc = "PowerPC 460 EX"; pcc->init_proc = init_proc_440EP; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -2308,6 +2331,7 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) dc->desc = "PowerPC 440 GP"; pcc->init_proc = init_proc_440GP; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | PPC_CACHE | PPC_CACHE_ICBI | @@ -2382,6 +2406,7 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) dc->desc = "PowerPC 440x5"; pcc->init_proc = init_proc_440x5; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_DCR | PPC_WRTEE | PPC_RFMCI | PPC_CACHE | PPC_CACHE_ICBI | @@ -2417,6 +2442,7 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) dc->desc = "PowerPC 440x5 with double precision FPU"; pcc->init_proc = init_proc_440x5; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_STFIWX | @@ -2465,6 +2491,7 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) dc->desc = "Freescale 5xx cores (aka RCPU)"; pcc->init_proc = init_proc_MPC5xx; pcc->check_pow = check_pow_none; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MEM_EIEIO | PPC_MEM_SYNC | PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | @@ -2507,6 +2534,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; pcc->init_proc = init_proc_MPC8xx; pcc->check_pow = check_pow_none; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MEM_EIEIO | PPC_MEM_SYNC | PPC_CACHE_ICBI | PPC_MFTB; @@ -2557,6 +2585,7 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) dc->desc = "PowerPC G2"; pcc->init_proc = init_proc_G2; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_STFIWX | @@ -2595,6 +2624,7 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) dc->desc = "PowerPC G2LE"; pcc->init_proc = init_proc_G2; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_STFIWX | @@ -2741,6 +2771,7 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) dc->desc = "e200 core"; pcc->init_proc = init_proc_e200; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; /* * XXX: unimplemented instructions: * dcblc @@ -3029,6 +3060,7 @@ POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) dc->desc = "e500v1 core"; pcc->init_proc = init_proc_e500v1; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_SPE | PPC_SPE_SINGLE | PPC_WRTEE | PPC_RFDI | @@ -3072,6 +3104,7 @@ POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) dc->desc = "e500v2 core"; pcc->init_proc = init_proc_e500v2; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | PPC_WRTEE | PPC_RFDI | @@ -3115,6 +3148,7 @@ POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) dc->desc = "e500mc core"; pcc->init_proc = init_proc_e500mc; pcc->check_pow = check_pow_none; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | @@ -3161,6 +3195,7 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) dc->desc = "e5500 core"; pcc->init_proc = init_proc_e5500; pcc->check_pow = check_pow_none; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | @@ -3209,6 +3244,7 @@ POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) dc->desc = "e6500 core"; pcc->init_proc = init_proc_e6500; pcc->check_pow = check_pow_none; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | PPC_WRTEE | PPC_RFDI | PPC_RFMCI | PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | @@ -3271,6 +3307,7 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data) dc->desc = "PowerPC 603"; pcc->init_proc = init_proc_603; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3310,6 +3347,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) dc->desc = "PowerPC 603e"; pcc->init_proc = init_proc_603; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3355,6 +3393,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) dc->desc = "e300 core"; pcc->init_proc = init_proc_e300; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_STFIWX | @@ -3410,6 +3449,7 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data) dc->desc = "PowerPC 604"; pcc->init_proc = init_proc_604; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3455,6 +3495,7 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) dc->desc = "PowerPC 604E"; pcc->init_proc = init_proc_604E; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3511,6 +3552,7 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data) dc->desc = "PowerPC 740"; pcc->init_proc = init_proc_740; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3576,6 +3618,7 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data) dc->desc = "PowerPC 750"; pcc->init_proc = init_proc_750; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3722,6 +3765,7 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) dc->desc = "PowerPC 750 CL"; pcc->init_proc = init_proc_750cl; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; /* * XXX: not implemented: * cache lock instructions: @@ -3829,6 +3873,7 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) dc->desc = "PowerPC 750CX"; pcc->init_proc = init_proc_750cx; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3901,6 +3946,7 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) dc->desc = "PowerPC 750FX"; pcc->init_proc = init_proc_750fx; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -3973,6 +4019,7 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) dc->desc = "PowerPC 750GX"; pcc->init_proc = init_proc_750gx; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -4032,6 +4079,7 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data) dc->desc = "PowerPC 745"; pcc->init_proc = init_proc_745; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -4077,6 +4125,7 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data) dc->desc = "PowerPC 755"; pcc->init_proc = init_proc_755; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | @@ -4143,6 +4192,7 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) dc->desc = "PowerPC 7400 (aka G4)"; pcc->init_proc = init_proc_7400; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4222,6 +4272,7 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) dc->desc = "PowerPC 7410 (aka G4)"; pcc->init_proc = init_proc_7410; pcc->check_pow = check_pow_hid0; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4322,6 +4373,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) dc->desc = "PowerPC 7440 (aka G4)"; pcc->init_proc = init_proc_7440; pcc->check_pow = check_pow_hid0_74xx; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4444,6 +4496,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) dc->desc = "PowerPC 7450 (aka G4)"; pcc->init_proc = init_proc_7450; pcc->check_pow = check_pow_hid0_74xx; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4573,6 +4626,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) dc->desc = "PowerPC 7445 (aka G4)"; pcc->init_proc = init_proc_7445; pcc->check_pow = check_pow_hid0_74xx; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4704,6 +4758,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) dc->desc = "PowerPC 7455 (aka G4)"; pcc->init_proc = init_proc_7455; pcc->check_pow = check_pow_hid0_74xx; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4855,6 +4910,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) dc->desc = "PowerPC 7457 (aka G4)"; pcc->init_proc = init_proc_7457; pcc->check_pow = check_pow_hid0_74xx; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -4989,6 +5045,7 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) dc->desc = "PowerPC e600"; pcc->init_proc = init_proc_e600; pcc->check_pow = check_pow_hid0_74xx; + pcc->check_attn = check_attn_none; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -5904,6 +5961,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) dc->desc = "PowerPC 970"; pcc->init_proc = init_proc_970; pcc->check_pow = check_pow_970; + pcc->check_attn = check_attn_hid0; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -5913,7 +5971,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data) PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_64B | PPC_ALTIVEC | PPC_SEGMENT_64B | PPC_SLBI; - pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; + pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC | PPC2_ATTN; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_VR) | (1ull << MSR_POW) | @@ -5979,6 +6037,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) dc->desc = "POWER5+"; pcc->init_proc = init_proc_power5plus; pcc->check_pow = check_pow_970; + pcc->check_attn = check_attn_hid0; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -5990,7 +6049,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) PPC_64B | PPC_POPCNTB | PPC_SEGMENT_64B | PPC_SLBI; - pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; + pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC | PPC2_ATTN; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_VR) | (1ull << MSR_POW) | @@ -6086,6 +6145,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER7; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_hid0; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6103,7 +6163,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | - PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; + PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206 | + PPC2_ATTN; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_VR) | (1ull << MSR_VSX) | @@ -6247,6 +6308,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER8; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_hid0; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6267,7 +6329,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | - PPC2_BCDA_ISA206; + PPC2_BCDA_ISA206 | PPC2_ATTN; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_HV) | (1ull << MSR_TM) | @@ -6439,6 +6501,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER9; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_hid0_power9; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6459,7 +6522,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC | - PPC2_BCDA_ISA206; + PPC2_BCDA_ISA206 | PPC2_ATTN; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_HV) | (1ull << MSR_TM) | @@ -6618,6 +6681,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc = init_proc_POWER10; pcc->check_pow = check_pow_nocheck; + pcc->check_attn = check_attn_hid0_power9; pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -6638,7 +6702,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | - PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; + PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206 | PPC2_ATTN; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_HV) | (1ull << MSR_VR) | @@ -6856,6 +6920,11 @@ static void init_ppc_proc(PowerPCCPU *cpu) warn_report("no power management check handler registered." " Attempt QEMU to crash very soon !"); } + + if (env->check_attn == NULL) { + warn_report("no attn check handler registered." + " Attempt QEMU to crash very soon !"); + } } @@ -7317,6 +7386,7 @@ static void ppc_cpu_instance_init(Object *obj) env->flags = pcc->flags; env->bfd_mach = pcc->bfd_mach; env->check_pow = pcc->check_pow; + env->check_attn = pcc->check_attn; /* * Mark HV mode as supported if the CPU has an MSR_HV bit in the diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a283c97717..28f2ab4583 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -154,6 +154,7 @@ static uint32_t ppc_ldl_code(CPUArchState *env, target_ulong addr) return insn; } + #endif static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp) @@ -425,17 +426,17 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector, env->reserve_addr = -1; } -static void powerpc_mcheck_checkstop(CPUPPCState *env) -{ - /* KVM guests always have MSR[ME] enabled */ #ifdef CONFIG_TCG +/* + * This stops the machine and logs CPU state without killing QEMU (like + * cpu_abort()) because it is often a guest error as opposed to a QEMU error, + * so the machine can still be debugged. + */ +static G_NORETURN void powerpc_checkstop(CPUPPCState *env, const char *reason) +{ CPUState *cs = env_cpu(env); FILE *f; - if (FIELD_EX64(env->msr, MSR, ME)) { - return; - } - f = qemu_log_trylock(); if (f) { fprintf(f, "Entering checkstop state: " @@ -451,6 +452,30 @@ static void powerpc_mcheck_checkstop(CPUPPCState *env) */ qemu_system_guest_panicked(NULL); cpu_loop_exit_noexc(cs); +} + +#ifdef TARGET_PPC64 +void helper_attn(CPUPPCState *env) +{ + if ((*env->check_attn)(env)) { + powerpc_checkstop(env, "host executed attn"); + } else { + raise_exception_err(env, POWERPC_EXCP_HV_EMU, + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); + } +} +#endif +#endif /* CONFIG_TCG */ + +static void powerpc_mcheck_checkstop(CPUPPCState *env) +{ + /* KVM guests always have MSR[ME] enabled */ +#ifdef CONFIG_TCG + if (FIELD_EX64(env->msr, MSR, ME)) { + return; + } + + powerpc_checkstop(env, "machine check with MSR[ME]=0"); #endif } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index cf2404330b..ee7f3ee5a2 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -5668,6 +5668,16 @@ static void gen_dform3D(DisasContext *ctx) } #if defined(TARGET_PPC64) +/* attn */ +static void gen_attn(DisasContext *ctx) +{ +#if defined(CONFIG_USER_ONLY) + GEN_PRIV(ctx); +#else + gen_helper_attn(tcg_env); +#endif +} + /* brd */ static void gen_brd(DisasContext *ctx) { @@ -5699,6 +5709,7 @@ static void gen_brh(DisasContext *ctx) static opcode_t opcodes[] = { #if defined(TARGET_PPC64) +GEN_HANDLER_E(attn, 0x00, 0x00, 0x08, 0xFFFFFDFF, PPC_NONE, PPC2_ATTN), GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), From patchwork Sat May 18 09:31:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0704EC25B74 for ; Sat, 18 May 2024 09:33:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQe-0006Rf-U5; Sat, 18 May 2024 05:32:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQd-0006Qy-Ar; Sat, 18 May 2024 05:32:35 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQb-0005s2-TS; Sat, 18 May 2024 05:32:35 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1eeabda8590so29867055ad.0; Sat, 18 May 2024 02:32:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024748; x=1716629548; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YYCH+lR4/2YjvBqi8x4eaSiKCuZqVWo68SMXWjlp9FY=; b=KqLBVpWqR+d74aYd+2gKFEdk/qHlafNsqT0GC88u8cVnc1URQaxznDTVL1/k9A2Mld k48lT46wBSgW6sEgei2OTKXXJ3gViZKJQ0ZDXKfb8kxBfKHJD+dK7osUiXVQzp+jmBxD u5vRDOL+uPXeS2mOz5MM26aFOxHgL9GmrQq1Yk8PMul3pPC2OsIoymZ2zXIfpki6hPgt u2BTtQ4E6NKw47TjKIhKuoCdhPsY1JLGlyc4oa2umPBvDutqtu7kL9kX1/uo4b41cw4U ZdZQn2F7Zd+Pk/uUTImyO78UzWzzEbHIUZukFW1o4Ibj6Hn8w4CfLr79wAjz0k2kRwZB lkhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024748; x=1716629548; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YYCH+lR4/2YjvBqi8x4eaSiKCuZqVWo68SMXWjlp9FY=; b=EhwEzHViB6Wm6TQsLKtp6cVJT3EM6xfRCc3yQ4PIR6PqnypaEhJ5vEJjrnQ+dtmS+2 CMFIcelKki9jixIAoOpFbi/TPjFAPzA0tPO/JzCJ5H7RJP4KIdWetZ83Rn++UooQd+Lm Ej1YKLOVzZlQFBaNIPRRnGflNHfaWzpntXg++d19XDw+YC2YyEelyWbdqoIpHzS0N0Xg CkJuzuN1OEu04fxYb1ayiN1DzVd3XobL1YY0z5mdUgDjs8+pR0UozSXdGJhJyUOlfcZ9 WqYEnFLYAgJ7Fqm4Cm2BksGmor0ev8tVbGhc4rKtCmMhc1w+rSubP22QzHojck+hc9Lh bPfQ== X-Forwarded-Encrypted: i=1; AJvYcCUZqUB30iJpehLQjsFTIXfMSC0v3UNzxw+DxhhtkLENdR3Ltorja7OCnB+Bm8oJ2h/+yvBpaFrib42t+VjaMTP8u+lzGw0= X-Gm-Message-State: AOJu0YximMdw2FlyHINppltq2fWx3UUj10Lxox7bVWlQQZ6wh0mvt2im zjF7PTWp2LlrN1QPqrMQ2LslFakbHdKAZyW+TioDijSGJ4YbpLO1zWzJ0A== X-Google-Smtp-Source: AGHT+IGO3+dB57JnbLOBM9+84D9gqipt5uLIVcyMMnkPVVCqLrumIQceoDfphrI9/sHa9Ms5+H7UVQ== X-Received: by 2002:a17:90b:695:b0:2ae:c8fe:a4a4 with SMTP id 98e67ed59e1d1-2b6ccd8e060mr20860965a91.46.1716024747965; Sat, 18 May 2024 02:32:27 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:27 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 06/14] target/ppc: BookE DECAR SPR is 32-bit Date: Sat, 18 May 2024 19:31:48 +1000 Message-ID: <20240518093157.407144-7-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=npiggin@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The DECAR SPR is 32-bits width. Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 71da8d4856..462246cb7d 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -792,7 +792,7 @@ static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 0x00000000); spr_register(env, SPR_BOOKE_DECAR, "DECAR", SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, + SPR_NOACCESS, &spr_write_generic32, 0x00000000); /* SPRGs */ spr_register(env, SPR_USPRG0, "USPRG0", From patchwork Sat May 18 09:31:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6AFC0C25B74 for ; Sat, 18 May 2024 09:33:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQi-0006T9-3L; Sat, 18 May 2024 05:32:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQe-0006RW-F3; Sat, 18 May 2024 05:32:36 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQb-0005tK-Tw; Sat, 18 May 2024 05:32:36 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1eca195a7c8so31830755ad.2; Sat, 18 May 2024 02:32:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024751; x=1716629551; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sYAW5npmFCrDzEP1Z4gIDF6q78kLtYXXiWAxpccYBJI=; b=E7mNFO/esd3GybA3nUGL0svf9R97LyspGma3BpfBOlb1+TUi59P/NA+pXFcZSEYk3M 29v/D5QbPOay86UZjal9wLpT52CCLi0D0SY4oj4VGfdGQoo5cyWB8EaGjzT7kpjpRmrb Xv4qdVwIoQG/WdQs1pkvRNp+qJ5ad8O82U1zSywHhdmxKwpbOG4Rmi505reb8SV0WPNr joxZTfz6obhrU3pQzBSZpkswSlnsn1QZMzpVQ71MuJqU8CJXf0kcq2buK9wU6pU9jCXw v7Zw+VXS5iSp9B/n1hWvwyrOyxizF/rqZAK60kFpii57rorZWCqn8McwOknJX65iNVdV 7jTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024751; x=1716629551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sYAW5npmFCrDzEP1Z4gIDF6q78kLtYXXiWAxpccYBJI=; b=mjtj4e4lqztecNSxdibNGLEkkhhwJse8k2L3rzcqCWZeAK9HqUIPBJ3Su9YEpENaK4 nCHElQbNq+nqZtdB2atUIKE1Zpvj+TvLh6FGX66y4eBbRk1VTNmUXV7DlUTo6psQvWKQ 5olLV/MfdY0YXFY8YUKJ3veT2HXwG9g3rC//DVm78mTYKXwubhR6X6sChr41KWhUBdAm ywrTU00HvZVh/V2O6cahm4pWw6on5nV2dnRHYOrVZrPhLO69jpu1Yfu439GuR/yiZDsq vD9139FMrAr1KQCYIK0eycVWdYfRoxVL84IULNzyr48Ub2mgELPlsLWXuplxS9PlfqMb XRfw== X-Forwarded-Encrypted: i=1; AJvYcCXjjPJmIN8ZVuuCd3uR6/PPpqTfJVkXccUOwkOVNhcc5rGwuExeePGIThJRWdolYW2nqR0AAXPCQ7RhZCEmDYxJVr+RRtE= X-Gm-Message-State: AOJu0YzMPXuIGq02QgVTzWtL/WKL8HhzSSNdejnvR0KynFhns+3qX7EP jlhjonJxLPcO/XEpJEG+HFHjemujg1RamOdT3tarj/QAgO8aUDV7QtIejA== X-Google-Smtp-Source: AGHT+IGgr64vNd0lmI6OTtLP84D8Lsd/hb5YeyxaGHkR+5NhcYGLMR2dqQyuIhhF+6J1NIyiswj/aA== X-Received: by 2002:a17:90a:1282:b0:2bd:68a4:cc88 with SMTP id 98e67ed59e1d1-2bd68a4cec1mr238843a91.47.1716024751133; Sat, 18 May 2024 02:32:31 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:30 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 07/14] target/ppc: Wire up BookE ATB registers for e500 family Date: Sat, 18 May 2024 19:31:49 +1000 Message-ID: <20240518093157.407144-8-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From the Freescale PowerPC Architecture Primer: Alternate time base APU. This APU, implemented on the e500v2, defines a 64-bit time base counter that differs from the PowerPC defined time base in that it is not writable and counts at a different, and typically much higher, frequency. The alternate time base always counts up, wrapping when the 64-bit count overflows. This implementation of ATB uses the same frequency as the TB. The existing spr_read_atbu/l functions are unused without this patch to wire them into the SPR. RTEMS uses this SPR on the e6500, though this hasn't been tested. Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 462246cb7d..e186da5ef1 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -920,6 +920,18 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, #endif } +static void register_atb_sprs(CPUPPCState *env) +{ + spr_register(env, SPR_ATBL, "ATBL", + &spr_read_atbl, SPR_NOACCESS, + &spr_read_atbl, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_ATBU, "ATBU", + &spr_read_atbu, SPR_NOACCESS, + &spr_read_atbu, SPR_NOACCESS, + 0x00000000); +} + /* SPR specific to PowerPC 440 implementation */ static void register_440_sprs(CPUPPCState *env) { @@ -2927,6 +2939,11 @@ static void init_proc_e500(CPUPPCState *env, int version) register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); register_usprgh_sprs(env); + if (version != fsl_e500v1) { + /* e500v1 has no support for alternate timebase */ + register_atb_sprs(env); + } + spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, From patchwork Sat May 18 09:31:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F449C25B74 for ; Sat, 18 May 2024 09:34:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQs-0006bY-RT; Sat, 18 May 2024 05:32:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQp-0006X6-H3; Sat, 18 May 2024 05:32:47 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQg-0005vW-Oq; Sat, 18 May 2024 05:32:47 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1ecddf96313so6221335ad.2; Sat, 18 May 2024 02:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024754; x=1716629554; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C05xE7UClbFjpcfnp/5y2S2aVeK97g5iKYmeDJkYN6Q=; b=glkkTkk/JHi1D7ITUNfiGvTeUYTwB5nOEu3NU35td3QxsBE7eY9d2leWKdRvjyhEYj ksD2Lu+ifOSvp4Bw1Kt6rqzx+8IbkAyyWcbkd/Or2JuyMt7uBr2dBimK3lKl8uYNxbD9 O0JkD8cAaXohKIxzUPUcQvDqL+41JtFjc2mgmTBMZMTrN3nMHO9E5XLkKhON22hp7p0E H5aMcOISVK/ZOqQxJ7rRpe95Y2tXIJYRGjlIpse+IZQU3WlpE/Obkby6o2jOfz73yTDL Ihenr8Bw0gYBXsr64z37L2BCLD71cziBYgQ1yoNFhpmBI6tZl8T7dx3p1S6mndDVcNs0 kJrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024754; x=1716629554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C05xE7UClbFjpcfnp/5y2S2aVeK97g5iKYmeDJkYN6Q=; b=EC0sct3915GFCLc0k2gqVWhq3BD0e4m74leI+0ZnM3fR/EKHPMepVmraORQdXEmp8F wTz2IGsy8lc/+NQaJcpN7kz4IHqpVKIAB3mwwiaaetMPQ6OU0MN/IawJrKl2xvZOSJU5 vFgqPOzunAl5gyDkvGBWCoYqDvTC70RQ8EQC6w6BbX21aR88L2Fck0BMeFtk+WsscDfC B8PqaxASMdpC2/1P0sv53ovjjxx1IWROaDImVaP1N048Qw3paTp1oM6o+YnFxxhwuOCx QdNHd5bNulzDHAdKQbCCMi90cvJ2uAvHYhEMbMipfVC7y0MMG8QxXLmY/5xtlzhQa4pQ Zuww== X-Forwarded-Encrypted: i=1; AJvYcCV5x5UsxwEZoMT9Mh2VqsoCWFrxjc0/0RupQd3OiYJ7oCB6G9F2gP9nmMtr0dLVShMlLK+89TNlrnEp0wQu0J9oeIwJ6TI= X-Gm-Message-State: AOJu0YwQeiNnD7bQFcNuHZMtpxsscvMh2XNEOCc14/r6zyfXvV/8ZiH7 X9ZUxJbzJHj4hhqx2ddiyUXVmwC8ffXClAY/BgPVO+1A2SMSP78MKCYqdg== X-Google-Smtp-Source: AGHT+IFcgKIqMUKc5FdDCOqCaKhZQ12l/eMPtTOJiGGfk0t7d9hwfRSJpq3Fii69oKZEmWppU/nBmQ== X-Received: by 2002:a05:6a21:2d05:b0:1b0:278e:34bc with SMTP id adf61e73a8af0-1b0278e36e4mr8833723637.62.1716024754374; Sat, 18 May 2024 02:32:34 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:34 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 08/14] target/ppc: Add PPR32 SPR Date: Sat, 18 May 2024 19:31:50 +1000 Message-ID: <20240518093157.407144-9-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=npiggin@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org PPR32 provides access to the upper half of PPR. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 1 + target/ppc/spr_common.h | 2 ++ target/ppc/cpu_init.c | 12 ++++++++++++ target/ppc/translate.c | 16 ++++++++++++++++ 4 files changed, 31 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2f7fab22ba..9a51e54c1c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2120,6 +2120,7 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_POWER_MMCRS (0x37E) #define SPR_WORT (0x37F) #define SPR_PPR (0x380) +#define SPR_PPR32 (0x382) #define SPR_750_GQR0 (0x390) #define SPR_440_DNV0 (0x390) #define SPR_750_GQR1 (0x391) diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index eb2561f593..9e40b3b608 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -203,6 +203,8 @@ void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn); void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn); void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn); +void spr_read_ppr32(DisasContext *ctx, int sprn, int gprn); +void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn); #endif void register_low_BATs(CPUPPCState *env); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e186da5ef1..dd45251d7a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5623,6 +5623,14 @@ static void register_HEIR64_spr(CPUPPCState *env) 0x00000000); } +static void register_power7_common_sprs(CPUPPCState *env) +{ + spr_register(env, SPR_PPR32, "PPR32", + &spr_read_ppr32, &spr_write_ppr32, + &spr_read_ppr32, &spr_write_ppr32, + 0x00000000); +} + static void register_power8_tce_address_control_sprs(CPUPPCState *env) { spr_register_kvm(env, SPR_TAR, "TAR", @@ -6118,6 +6126,7 @@ static void init_proc_POWER7(CPUPPCState *env) register_power6_common_sprs(env); register_HEIR32_spr(env); register_power6_dbg_sprs(env); + register_power7_common_sprs(env); register_power7_book4_sprs(env); /* env variables */ @@ -6265,6 +6274,7 @@ static void init_proc_POWER8(CPUPPCState *env) register_power6_common_sprs(env); register_HEIR32_spr(env); register_power6_dbg_sprs(env); + register_power7_common_sprs(env); register_power8_tce_address_control_sprs(env); register_power8_ids_sprs(env); register_power8_ebb_sprs(env); @@ -6432,6 +6442,7 @@ static void init_proc_POWER9(CPUPPCState *env) register_power6_common_sprs(env); register_HEIR32_spr(env); register_power6_dbg_sprs(env); + register_power7_common_sprs(env); register_power8_tce_address_control_sprs(env); register_power8_ids_sprs(env); register_power8_ebb_sprs(env); @@ -6626,6 +6637,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power6_common_sprs(env); register_HEIR64_spr(env); register_power6_dbg_sprs(env); + register_power7_common_sprs(env); register_power8_tce_address_control_sprs(env); register_power8_ids_sprs(env); register_power8_ebb_sprs(env); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ee7f3ee5a2..c4b4f7ea62 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1416,6 +1416,22 @@ void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) gen_load_spr(t0, sprn + 16); tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); } + +/* The PPR32 SPR accesses the upper 32-bits of PPR */ +void spr_read_ppr32(DisasContext *ctx, int sprn, int gprn) +{ + gen_load_spr(cpu_gpr[gprn], SPR_PPR); + tcg_gen_shri_tl(cpu_gpr[gprn], cpu_gpr[gprn], 32); +} + +void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + + tcg_gen_shli_tl(t0, cpu_gpr[gprn], 32); + gen_store_spr(SPR_PPR, t0); + spr_store_dump_spr(SPR_PPR); +} #endif #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ From patchwork Sat May 18 09:31:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667538 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1122C25B7A for ; Sat, 18 May 2024 09:33:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQp-0006Xs-RA; Sat, 18 May 2024 05:32:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQk-0006Ua-6M; Sat, 18 May 2024 05:32:42 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQi-0005xB-Hk; Sat, 18 May 2024 05:32:41 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1eeb1a4c10aso31516385ad.3; Sat, 18 May 2024 02:32:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024757; x=1716629557; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9E8A9YiZzilNZc0YhxzRbKs1Y14T+BqDlAP7w9sE6MI=; b=hnJwgGnYmragRHaPaChaXujDQvyOYov2Pyc/czMUlYRB4/AoYR492UBo0cdkYwtqRu zKtOb7ielzVP+8x2gJHxQMxQanuAZkhRQaQoY6RdpN33XdbLvyvObwfpjGW63AYRH72l hkmZRZ4CAWMpkLfP4MXXWoXhljKh5qgdX1wCiKC5Fz3f7UV9puRIg4vs4G+DWI6yNzt/ ndut+/1YJQ8EYrMIJZ0bXHHWk5xpREGHR7gCyDnvnnd9dvWElsPOQCnBOtF2d8/3/Zrc /dBjcStP1M+lbqlxZ7MCf/jo3VhM/U1Ea0g115M9fOIMNdgQ408FQIBTbj0BCWGdRoSK sX6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024757; x=1716629557; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9E8A9YiZzilNZc0YhxzRbKs1Y14T+BqDlAP7w9sE6MI=; b=k4ws0TdJWlf2uq9MM+22Sl9Hp9RYiCYkZA6p4JxBxtl68OAyLZOmOW+efUl/vbdC2Y rpyImZIyW9UdDpAh5pzFWIDoD7ZGZ4SUEytw12xnNFVUpjhdx9tKfSXBzXnXhobuYkQJ gbYCfUq88f8uDa+dOARjNsnqmndACDOJa9c2XQCwP5p0BxxpbGyeC0OZbgK/szGm3Dg2 J6C//ANIZEiyqzSWsh/7sVWsKuhEm2x8vr4Qk38eYKu1PbHna7dNtoxNwrLnXVFM5cM9 obaU1Chu+LCyXxKV5ZSd6P1QKMYFz38QQBuTybZpMCeA+RVxu/3bcpnahbVHm+8JiVAO 2TCA== X-Forwarded-Encrypted: i=1; AJvYcCX6UrJQrcQubCiYllCEmcLW1bl8yLsip4iYn2oMoPr6cJU7NFfAUwEgqtIOLIma5ecvgvIoPOs6hYx6HuLxElirPzi3dC4= X-Gm-Message-State: AOJu0YzQh/zZY3C5iAhjb6h4w3dMT9+OoOSQRaoedCB1s8NICIGpFcRE jQd4TaFxU+cmyEqBtkPBJEzVsmXSFezKyS4Fl3eSyg1aL+nFpqyiW/Qkjw== X-Google-Smtp-Source: AGHT+IGcfIGHvd7z0DBzZCq8d8aQNBtkkfBI+8KoifO8iVrlmPKvax+Uu9m5h2E8s8VvF5esT8+nqg== X-Received: by 2002:a17:90a:9503:b0:2b4:32be:3b8c with SMTP id 98e67ed59e1d1-2b6ccd6bab8mr22322306a91.37.1716024757458; Sat, 18 May 2024 02:32:37 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:37 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 09/14] target/ppc: add helper to write per-LPAR SPRs Date: Sat, 18 May 2024 19:31:51 +1000 Message-ID: <20240518093157.407144-10-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means per-thread or per-core, depending on 1LPAR mode. Signed-off-by: Nicholas Piggin --- target/ppc/spr_common.h | 2 ++ target/ppc/translate.c | 26 ++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 9e40b3b608..85f73b860b 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -83,6 +83,8 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_generic32(DisasContext *ctx, int sprn, int gprn); void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn); +void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn); +void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c4b4f7ea62..ccd90a5feb 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -537,6 +537,32 @@ void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) spr_store_dump_spr(sprn); } +void spr_core_write_generic32(DisasContext *ctx, int sprn, int gprn) +{ + TCGv t0 = tcg_temp_new(); + if (!(ctx->flags & POWERPC_FLAG_SMT)) { + spr_write_generic32(ctx, sprn, gprn); + return; + } + + if (!gen_serialize(ctx)) { + return; + } + + tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); + gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), t0); + spr_store_dump_spr(sprn); +} + +void spr_core_lpar_write_generic(DisasContext *ctx, int sprn, int gprn) +{ + if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { + spr_core_write_generic(ctx, sprn, gprn); + } else { + spr_write_generic(ctx, sprn, gprn); + } +} + static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) { /* This does not implement >1 thread */ From patchwork Sat May 18 09:31:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 265BCC25B74 for ; Sat, 18 May 2024 09:33:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQr-0006ZT-7h; Sat, 18 May 2024 05:32:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQm-0006WC-SQ; Sat, 18 May 2024 05:32:46 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQk-0005yZ-VB; Sat, 18 May 2024 05:32:44 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1eb0e08bfd2so33101465ad.1; Sat, 18 May 2024 02:32:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024761; x=1716629561; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o4qQ+pydW7/H/FceYCg6Igyj7xZn2LiKCjn6liCZR3A=; b=HzYvvPHMmZj55oYgux75YPxoKQZWB8JYpMaOW1MQsfJXJhsB38dgV02Mu/Kp9kuaiK AaCsU5Q0uR948jAfljm3y7lYW1wCFX/sLDUTyZRIXQ7W8yRrACmDGi2MR/d6sN1zRrwu pJSAuMH4RarUbDzkpBfzmQ2yx0nufX3oM55/QrSC7V77FbrazCp6ckftP8q1unhMifDn ih3S/4KkVyo731ji/94UAhjAOq8ACQJJvmwRcZ4j/hCppJ3J8XB+7+l/gskBY/3YAOxx skjGH2Q7T1z9kxarvaa33TRc7Ksp37bWOv0+rtbj0LXQTxVlki25ubPQJjqDRvpWkXzQ 03Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024761; x=1716629561; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o4qQ+pydW7/H/FceYCg6Igyj7xZn2LiKCjn6liCZR3A=; b=LwmaE802xs3zYYE7GNEAgbxhtGb6bVZ9NEDvbnRttXKiHaFWVFuUawNTDl2hQWVqE7 Np7zmbJ9D7pihprfwcoXC9wfwBwZWr9rdN2WkgH5ORoOZua9iluyp88nSB9a6o52Aqwt kYkwDvSPzsZoJUYZToiJEGCk1b1GHB55+S2FJYYDOhDW+KUjBSkOq3nRWmYyZa2yXXQz qp4NFWF0EOFeR1uDlJz4CODlGNLZx1avGrCTjJJ8PWd8hysPeulneagwc+DFk5lucOlQ b/wtyqSt17GSiTOYk0D2Cp2s+bLSp1flu7pSTPwqc6b/3RnC2l4NPNnukyHpcGnK8odp Z7bg== X-Forwarded-Encrypted: i=1; AJvYcCU/ZTyrSu8BcqkDWXfNqz7ORTpReJYWSK9wXcUNnYiyur1K+rxVyJH71tN7t4utZklyEPisTczmZVdusE7ZMP10k7L9TbE= X-Gm-Message-State: AOJu0YyjIBzNvbrj3ygxdl/uZ+fMHySUIcXcnBsNBwpIS3EUUFW8u1cK uixWUTyKPV5vUnvDS3nRphch+pki39hpUcHHgX+rWXgVGrhnKzDTANLHLQ== X-Google-Smtp-Source: AGHT+IEBx4kaWv+tdOvVNoAg3OPK8Kg+kZJERNqmz2RpwgkiXpMa9vKonTIiOekQsPV31lxyXoNUzQ== X-Received: by 2002:a17:90a:a395:b0:2b4:a767:193e with SMTP id 98e67ed59e1d1-2b6ccd6b9c0mr21640233a91.38.1716024760775; Sat, 18 May 2024 02:32:40 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:40 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 10/14] target/ppc: Add SMT support to simple SPRs Date: Sat, 18 May 2024 19:31:52 +1000 Message-ID: <20240518093157.407144-11-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR registers with simple (generic) implementations. Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index dd45251d7a..dc6b4fc569 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -246,7 +246,7 @@ static void register_amr_sprs(CPUPPCState *env) spr_register_hv(env, SPR_AMOR, "AMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_core_lpar_write_generic, 0); #endif /* !CONFIG_USER_ONLY */ } @@ -5489,7 +5489,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env) spr_register_hv(env, SPR_MMCRC, "MMCRC", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, + &spr_read_generic, &spr_core_write_generic32, 0x00000000); spr_register_hv(env, SPR_MMCRH, "MMCRH", SPR_NOACCESS, SPR_NOACCESS, @@ -5529,7 +5529,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env) spr_register_hv(env, SPR_HRMOR, "HRMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_core_write_generic, 0x00000000); } @@ -5757,7 +5757,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env) spr_register_hv(env, SPR_TSCR, "TSCR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, + &spr_read_generic, &spr_core_write_generic32, 0x00000000); spr_register_hv(env, SPR_HMER, "HMER", SPR_NOACCESS, SPR_NOACCESS, @@ -5767,7 +5767,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env) spr_register_hv(env, SPR_HMEER, "HMEER", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_core_write_generic, 0x00000000); spr_register_hv(env, SPR_TFMR, "TFMR", SPR_NOACCESS, SPR_NOACCESS, @@ -5843,7 +5843,7 @@ static void register_power8_rpr_sprs(CPUPPCState *env) spr_register_hv(env, SPR_RPR, "RPR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_core_write_generic, 0x00000103070F1F3F); #endif } From patchwork Sat May 18 09:31:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B3A8C25B79 for ; Sat, 18 May 2024 09:33:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQr-0006ZK-5r; Sat, 18 May 2024 05:32:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQp-0006Wc-5k; Sat, 18 May 2024 05:32:47 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQn-0005zE-OI; Sat, 18 May 2024 05:32:46 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1ee7963db64so32144535ad.1; Sat, 18 May 2024 02:32:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024764; x=1716629564; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jJb9bvfRee44JjdofCdO48Q2mvLlZY5PLzHGKaPIRNI=; b=AYhyjCbXUNNoNSfqi/pacVLfvCefbLkqehGHw0fSVeVy6oDE4Gf2gBQI9SnwC6kQD3 5KNsXbtTSptqpXWShXfT7X8NF/TNnlzH+PZHl5Cz/vWLsBWmxF9/a2NZddp9lo8KJu0I ndOoN6lTsbod0OgHJr8gZMLIqKm/rRq9pVwEVDjd+01poJCgK0PFtyLyWFYcigUKP/zA 5msdS5XddwCbKOsJbke8z1rRI9NBgVRtfiaFCieKkmMSnphmVDGXEXRQfE8ZaVSxvG2T Ca19DnLr5/GfCbq5E52Az2zLpltFCRRvPwrN8zZu9NnH21lA10KSEMbIV6Porlb09TrW 9gcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024764; x=1716629564; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jJb9bvfRee44JjdofCdO48Q2mvLlZY5PLzHGKaPIRNI=; b=fkdtq9bzZJP9D8FFF/9R/W1y1HGAiqUK2z25Qc5b/dUMOJhhuCMWOCfE/unMyZIFF/ K70OhSdA68dWcebZJABKhoWPn7CZIHGWTQy+KBg+DYtipz6Uf7n+Qrz2hrliULYrMzK/ LpURZP8uQym5aZvazppE+T8OZib0Qi+4JuHyFnjQwyCVybGPeNhvZRqiqvc3HE2BuXX2 DUN8dovxJwg/nfehXEeZ86eHh5rj/er+xbIJZSY37lzzdhwgkS/1nEIPiXicQy/9YVt5 5rJWwQmg3/Kt2nWkjMgkPDOoqDECAizrqptzS5mfHIAdktsm33sW7+qEG59IXAos8IBp wKWw== X-Forwarded-Encrypted: i=1; AJvYcCUFdIACgS2dbcfk5bDWs6v5AObsrbjpLwVxdaJqczr3d1/CTiVqR6c31Ap5uG5IwDBCfnCHi6SBB2XAPmvdclAOI4v1R24= X-Gm-Message-State: AOJu0YweJI1MdyvggDM/dkqvPbIpcxtvTq9epJR7mG6jns+Qjx6B9ld9 KAiPw+btwvbIwd1HrNcTLoiBnJ7SlaQ5nexxt0MtTX0uT9TyiCTZoqYojA== X-Google-Smtp-Source: AGHT+IHdHyC0QWcreqsO+e+AQYz3C3PzTbXk4ysfvY1pK6H/LiE7nEv7ANHVcCEIqVvmMr8U21oXfw== X-Received: by 2002:a17:90b:3a8c:b0:2b3:2a3b:dd0f with SMTP id 98e67ed59e1d1-2b6cc14b8b5mr24598312a91.8.1716024763996; Sat, 18 May 2024 02:32:43 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:43 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 11/14] target/ppc: Add SMT support to PTCR SPR Date: Sat, 18 May 2024 19:31:53 +1000 Message-ID: <20240518093157.407144-12-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org PTCR is a per-core register. Signed-off-by: Nicholas Piggin --- target/ppc/misc_helper.c | 16 ++++++++++++++-- target/ppc/translate.c | 4 ++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 6f419c9346..a67930d031 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -173,6 +173,7 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val) void helper_store_ptcr(CPUPPCState *env, target_ulong val) { if (env->spr[SPR_PTCR] != val) { + CPUState *cs = env_cpu(env); PowerPCCPU *cpu = env_archcpu(env); target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS; target_ulong patbsize = val & PTCR_PATS; @@ -194,8 +195,19 @@ void helper_store_ptcr(CPUPPCState *env, target_ulong val) return; } - env->spr[SPR_PTCR] = val; - tlb_flush(env_cpu(env)); + if (cs->nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) { + env->spr[SPR_PTCR] = val; + tlb_flush(cs); + } else { + CPUState *ccs; + + THREAD_SIBLING_FOREACH(cs, ccs) { + PowerPCCPU *ccpu = POWERPC_CPU(ccs); + CPUPPCState *cenv = &ccpu->env; + cenv->spr[SPR_PTCR] = val; + tlb_flush(ccs); + } + } } } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ccd90a5feb..60a7afb086 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -971,6 +971,10 @@ void spr_write_hior(DisasContext *ctx, int sprn, int gprn) } void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) { + if (!gen_serialize_core(ctx)) { + return; + } + gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]); } From patchwork Sat May 18 09:31:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0BE1C25B74 for ; Sat, 18 May 2024 09:34:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQv-0006dr-7o; Sat, 18 May 2024 05:32:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQs-0006c1-UY; Sat, 18 May 2024 05:32:50 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQr-0005zr-CV; Sat, 18 May 2024 05:32:50 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1ed41eb3382so30428795ad.0; Sat, 18 May 2024 02:32:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024767; x=1716629567; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dljcz6aaMRzJicXKlp7Qi2MLnj6X3mJ8Z+Z3n8U7SyE=; b=jqIWabDnbjkbkuMshXBIUXACRqwfMk111lHC/mNe+WBo2ycU0q0dcIAcTzsyk9fhEh qyBCB+gVBpfv5tGDuale/6urLpsTm1VidhspMSAofkdBDE4n2uYJVeNWJa7sk+k9q9Nm VD2v+bderYVAvDCKBFug8sdI+slzq0SyODyOOjii7RbVB+zUtJ0nYB+4oTHtQzkvswG2 Gr2CNYyAm7vYOTr/QxTgV45ib/XpajvoqYKuUXDpH9YhJu2AaZ1pXTTlJKEg2xxhCo1W RiBnKuclYiHgW3DKlTtiB523JqH12in0g5Q+DK3lS9yhUanXOm6ymXqhlaFLBu7wZG+I x8jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024767; x=1716629567; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dljcz6aaMRzJicXKlp7Qi2MLnj6X3mJ8Z+Z3n8U7SyE=; b=cJyl/r5bUrYejuGE9AFKvhzdQy6Et4GIJuTHKH6/m1h/RLui1iVBGMfyVQhsXm8djI j8RzzEuPCJCqnDZ5mrsFeVJxg29lLf5xqGWYR4W6kl9fVIBnK1SdOCib1LpPx3lWATek HsLs3GfM8F0h+e0HIQqhZz9WMTII/Mef0N3Y17onYM34enNBkQeM9O2En3O+yuHUefpP MY+WQzd4NzmVPWkR1CJ+JgTolGtnRSxLNUCEnGCBXarGWwtzmXFkqbQCnxHtQs28EodH 6xL1DTXr6ANdtmPFrzYCsP4Pj7BeCNFDtPnBVmOxhUXB3aTCSYDEGgGozvqm1pgH7wLZ DJlQ== X-Forwarded-Encrypted: i=1; AJvYcCUd4Nz4by55a9zxWitS5Q1UZFRJD7Hy3fdDeegznDo7Kvmk358Oyruzepp3CGB00O4U9/oL4zhI3C1Hn93Qilf0J8m006Y= X-Gm-Message-State: AOJu0Yzw/SiztUUqziwFay3xZAqHLlsnor4vMqCNd+h143FLoA0tGVIT y9ZK3y4CYaf3AiqeFKaeYUDTQYDoHjZ47LgUkihGXrhi8rz4GJQkLj0obg== X-Google-Smtp-Source: AGHT+IF8CwoOPaL/W3RraOGgNG2IKXgtTFeaGb7HYLuzOfd7AT+w7CBqMGuPU4D56Jm3Aq5kGhgRFg== X-Received: by 2002:a05:6a20:3d88:b0:1af:cefe:9741 with SMTP id adf61e73a8af0-1afde0b6d8dmr35700254637.17.1716024767184; Sat, 18 May 2024 02:32:47 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:46 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 12/14] target/ppc: Implement LDBAR, TTR SPRs Date: Sat, 18 May 2024 19:31:54 +1000 Message-ID: <20240518093157.407144-13-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org LDBAR, TTR are a Power-specific SPRs. These simple implementations are enough for IBM proprietary firmware for now. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 2 ++ target/ppc/cpu_init.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 9a51e54c1c..a014efc23a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2098,6 +2098,7 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_DEXCR (0x33C) #define SPR_IC (0x350) #define SPR_VTB (0x351) +#define SPR_LDBAR (0x352) #define SPR_MMCRC (0x353) #define SPR_PSSCR (0x357) #define SPR_440_INV0 (0x370) @@ -2144,6 +2145,7 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_440_IVLIM (0x399) #define SPR_TSCR (0x399) #define SPR_750_DMAU (0x39A) +#define SPR_POWER_TTR (0x39A) #define SPR_750_DMAL (0x39B) #define SPR_440_RSTCFG (0x39B) #define SPR_BOOKE_DCDBTRL (0x39C) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index dc6b4fc569..4591a68cc5 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5784,6 +5784,16 @@ static void register_power_common_book4_sprs(CPUPPCState *env) &spr_access_nop, &spr_write_generic, &spr_access_nop, &spr_write_generic, 0x00000000); + spr_register_hv(env, SPR_LDBAR, "LDBAR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_core_lpar_write_generic, + 0x00000000); + spr_register_hv(env, SPR_POWER_TTR, "TTR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_core_write_generic, + 0x00000000); #endif } From patchwork Sat May 18 09:31:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8625DC25B74 for ; Sat, 18 May 2024 09:34:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GQz-0006id-4i; Sat, 18 May 2024 05:32:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GQw-0006eJ-Ap; Sat, 18 May 2024 05:32:54 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQu-00061i-JL; Sat, 18 May 2024 05:32:54 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1eb24e3a2d9so36213225ad.1; Sat, 18 May 2024 02:32:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024770; x=1716629570; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d8QF/oLC6NmyofkxjWqVCUa8PVY6JxCh60BGtrwFLcw=; b=WCeajGZvR9aZm1Vwx7ytV9j6EMRoOZJNK3eUaeRn97MZZoNkCD9IxjMZ5OdOTUtzl/ PcF5ovDBr6M7zjhFPV89vbLfsIZojCBH6G/687G+dCRxxEENAf7Dp7XdUlOu7p8Aanm4 N+SyGL3Z+pt8W56a3NIfFZRtWpWIm/rFelOgu4+mxKGPIIaI0TtXT00Jr+RBidtVvRGO WR5X3QuzoEeyS54/SnJss9gcLFoX5mNARk7hJIsGrdv4ewlsTFP0D1qml79RXiTUZGJ9 oabjS61wq/be0jbhTct1vi2d+RX1p4LbYoXYk13YctnyYBYGYyObLzm0lao911IikwX/ QbQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024770; x=1716629570; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d8QF/oLC6NmyofkxjWqVCUa8PVY6JxCh60BGtrwFLcw=; b=KOUXRKEera9fJq9VwfMncN+lsHQPU7KAk7VtTpObjhVoRaAOs+Biavff5B9EM7G95M z+p0t9FUwMOdcsfy+OE750myk6LGSyBV2hnNqaBc0VBzEEbodY7xi6MLuiabkBAYUYxr VfCq0lhcrjMYLT1tBXQ9pnZNibJiiGZJ5xNkdL5vCf10ukU4QSMT1wu7ewHz0tpIOuq1 2Y93e/z0buajpJABza+7EY5CSNVG+4awkGwMrVA3fkPPeBweSwFSaWW3lBdCSkq/TBs7 Dt9hbW8/rskqxhTk3pfPPJGbEASJ2mf3lod2tGojDl2vgj/l/XTFWQ4iCv88/28e47eH rg+A== X-Forwarded-Encrypted: i=1; AJvYcCUfukoICUX0xV9Jjqu+oZ/kI0wXDwl3FfRzDwR78cO6uMYX48RpJ+Xjk0mD+GmBvaJjbhkZf9Y99hvqQFGcgf+H5n9ZZUU= X-Gm-Message-State: AOJu0Yw89ZIhsSVKzMtDwtLKEaJS2A03jQtzHIaASA7lQFzixRYg0s9i dB+UVZrIr6Q5mhGxH/enSAm07vZI8vq+raLbqbcWQ26CM4GylTRL8P60cg== X-Google-Smtp-Source: AGHT+IG5YMaSmejSbroAdU8Ten3CleojMt9+rpa+dp/t3YK6haE8xDd9pwFOPW1kl+FERYfo+SAMAQ== X-Received: by 2002:a17:90a:f983:b0:2b3:28be:ede3 with SMTP id 98e67ed59e1d1-2b6cd1e4f2amr21380473a91.47.1716024770376; Sat, 18 May 2024 02:32:50 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:50 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 13/14] target/ppc: Implement SPRC/SPRD SPRs Date: Sat, 18 May 2024 19:31:55 +1000 Message-ID: <20240518093157.407144-14-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that can be accessed via these indirect SPRs. SCRATCH registers only provide storage, but they are used by firmware for low level crash and progress data, so this implementation logs writes to the registers to help with analysis. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 7 +++-- target/ppc/helper.h | 3 ++ target/ppc/spr_common.h | 3 ++ target/ppc/cpu_init.c | 10 ++++++ target/ppc/misc_helper.c | 66 ++++++++++++++++++++++++++++++++++++++++ target/ppc/translate.c | 18 +++++++++++ 6 files changed, 105 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a014efc23a..8e15a9ccbb 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1264,6 +1264,9 @@ struct CPUArchState { ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ struct CPUBreakpoint *ciabr_breakpoint; struct CPUWatchpoint *dawr0_watchpoint; + + /* POWER CPU regs/state */ + target_ulong scratch[8]; /* SCRATCH registers (shared across core) */ #endif target_ulong sr[32]; /* segment registers */ uint32_t nb_BATs; /* number of BATs */ @@ -1806,9 +1809,9 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_SPRG2 (0x112) #define SPR_SPRG3 (0x113) #define SPR_SPRG4 (0x114) -#define SPR_SCOMC (0x114) +#define SPR_POWER_SPRC (0x114) #define SPR_SPRG5 (0x115) -#define SPR_SCOMD (0x115) +#define SPR_POWER_SPRD (0x115) #define SPR_SPRG6 (0x116) #define SPR_SPRG7 (0x117) #define SPR_ASR (0x118) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 09d50f9b76..57bf8354e7 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -730,6 +730,9 @@ DEF_HELPER_2(book3s_msgsndp, void, env, tl) DEF_HELPER_2(book3s_msgclrp, void, env, tl) DEF_HELPER_1(load_tfmr, tl, env) DEF_HELPER_2(store_tfmr, void, env, tl) +DEF_HELPER_FLAGS_2(store_sprc, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_1(load_sprd, TCG_CALL_NO_RWG_SE, tl, env) +DEF_HELPER_FLAGS_2(store_sprd, TCG_CALL_NO_RWG, void, env, tl) #endif DEF_HELPER_2(store_sdr1, void, env, tl) DEF_HELPER_2(store_pidr, void, env, tl) diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 85f73b860b..01aff449bc 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -207,6 +207,9 @@ void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_ppr32(DisasContext *ctx, int sprn, int gprn); void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn); +void spr_write_sprc(DisasContext *ctx, int sprn, int gprn); +void spr_read_sprd(DisasContext *ctx, int sprn, int gprn); +void spr_write_sprd(DisasContext *ctx, int sprn, int gprn); #endif void register_low_BATs(CPUPPCState *env); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 4591a68cc5..0c1837fe76 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5794,6 +5794,16 @@ static void register_power_common_book4_sprs(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_core_write_generic, 0x00000000); + spr_register_hv(env, SPR_POWER_SPRC, "SPRC", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_sprc, + 0x00000000); + spr_register_hv(env, SPR_POWER_SPRD, "SPRD", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_sprd, &spr_write_sprd, + 0x00000000); #endif } diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index a67930d031..fa47be2298 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -307,6 +307,72 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val) } bql_unlock(); } + +/* Indirect SCOM (SPRC/SPRD) access to SCRATCH0-7 are implemented. */ +void helper_store_sprc(CPUPPCState *env, target_ulong val) +{ + if (val & ~0x3f8ULL) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid SPRC register value " + TARGET_FMT_lx"\n", val); + return; + } + env->spr[SPR_POWER_SPRC] = val; +} + +target_ulong helper_load_sprd(CPUPPCState *env) +{ + target_ulong sprc = env->spr[SPR_POWER_SPRC]; + + switch (sprc & 0x3c0) { + case 0: /* SCRATCH0-7 */ + return env->scratch[(sprc >> 3) & 0x7]; + default: + qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" + TARGET_FMT_lx"\n", sprc); + break; + } + return 0; +} + +static void do_store_scratch(CPUPPCState *env, int nr, target_ulong val) +{ + CPUState *cs = env_cpu(env); + CPUState *ccs; + uint32_t nr_threads = cs->nr_threads; + + /* + * Log stores to SCRATCH, because some firmware uses these for debugging + * and logging, but they would normally be read by the BMC, which is + * not implemented in QEMU yet. This gives a way to get at the information. + * Could also dump these upon checkstop. + */ + qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr); + + if (nr_threads == 1) { + env->scratch[nr] = val; + return; + } + + THREAD_SIBLING_FOREACH(cs, ccs) { + CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; + cenv->scratch[nr] = val; + } +} + +void helper_store_sprd(CPUPPCState *env, target_ulong val) +{ + target_ulong sprc = env->spr[SPR_POWER_SPRC]; + + switch (sprc & 0x3c0) { + case 0: /* SCRATCH0-7 */ + do_store_scratch(env, (sprc >> 3) & 0x7, val); + break; + default: + qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" + TARGET_FMT_lx"\n", sprc); + break; + } +} #endif /* defined(TARGET_PPC64) */ void helper_store_pidr(CPUPPCState *env, target_ulong val) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 60a7afb086..8e944c4416 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1363,6 +1363,24 @@ void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]); } +void spr_write_sprc(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_sprc(tcg_env, cpu_gpr[gprn]); +} + +void spr_read_sprd(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_sprd(cpu_gpr[gprn], tcg_env); +} + +void spr_write_sprd(DisasContext *ctx, int sprn, int gprn) +{ + if (!gen_serialize_core(ctx)) { + return; + } + gen_helper_store_sprd(tcg_env, cpu_gpr[gprn]); +} + void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); From patchwork Sat May 18 09:31:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13667542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21BAFC25B74 for ; Sat, 18 May 2024 09:34:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s8GR8-00073d-6s; Sat, 18 May 2024 05:33:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s8GR3-0006mF-Hm; Sat, 18 May 2024 05:33:01 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s8GQy-00061y-Jc; Sat, 18 May 2024 05:33:01 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1ed835f3c3cso35024715ad.3; Sat, 18 May 2024 02:32:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716024773; x=1716629573; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1A2p9DmxJfMUyeFX9bP+SNrYOdc8qdINWJK/l0PqvFY=; b=d/25SmBc+DmIh2U2xUR9iBxjqBKKK6mx8hvGfJeXBBPIPTod3Bgp+WEWJWk0o8ZuIY OUvx2faKXvzKK4brnQrV0HIJatqKcwBqXEgEN1c+B5cQ0sP1bFgpWnW6R39riv+asBu1 t7wfGI0u+pr4YSKcWryOxQgg+9m6Gqc/1m0QALq96XjsFL4lL/YlrgMtRWGrimULyV/Y CLkx9kRcfIZxrGHZjxt+NBuvWDb4kjdqj3QAoTZKeLSTYsdAVlgcTp1l8IWyO9/pyGt1 BZI2BGCaawESE2A5wfXsKo00boFAgv+VZYEpTJ1IF+5CdE0CdxOecBjcpboEKHVsFXJJ IxGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716024773; x=1716629573; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1A2p9DmxJfMUyeFX9bP+SNrYOdc8qdINWJK/l0PqvFY=; b=NpFPQSU+az8i6ipr2sevWiHT33KU9vOxGv2z/ftG6wwFb5VqTTOyyR9zKeVlzJEyqJ f1xgauyts4iOlKX5Kypfxzk7knfotWtXG0JPnQQg10cJlSyriuFNiFPbVj4Cpa5pU6H/ Z6xvG8KkhNU9i5EPlV9h7buzVcQiSGJfCdHBFez94hvfi5iIFOfmDzvizo4AoVMOLcEE SzlMdTh+e+TvtHqnixEoa9XtSWuMtPlMuKX96Qcl3z1ItxeWQqYUVc3SLXYAVafnR2hy S4rDzZhv/xIhUcrzw3GiZbcdKvVZ8+r868xd5AV4PA/NsEsc0mozKvj9xYE8C59k0or3 840A== X-Forwarded-Encrypted: i=1; AJvYcCXrDAO0DMFdl4hNKcvqSKLWqgaDlX6Xb5GMHVMXquL/fABcBOUxXI6wrsRM3rFXwkeBQDEOwbonKr5tl3xr5An/fd/eblA= X-Gm-Message-State: AOJu0YzGaw1GitvY1oq9lSI2rYg6bHhOw9tSTEW1lY6W+gqjkFyBRU14 7JiywltKNh0glii5kvaWYGsTrM2UK06KbcLtYD67ZV3bardTdpocVKDRXQ== X-Google-Smtp-Source: AGHT+IGjcT0YfKLWq+FisJ68nZr0q9Xxw2nGNKhB3svQPEcqanpvUJ3D9SSDHTi+0EZ9/zHe/O7Sdg== X-Received: by 2002:a17:90a:fa11:b0:2a0:86b6:2e9 with SMTP id 98e67ed59e1d1-2b6cc45305amr22357797a91.12.1716024773624; Sat, 18 May 2024 02:32:53 -0700 (PDT) Received: from wheely.local0.net (110-175-65-7.tpgi.com.au. [110.175.65.7]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b628ea6a05sm18518901a91.52.2024.05.18.02.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 May 2024 02:32:53 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , Glenn Miles Subject: [PATCH 14/14] target/ppc: add SMT support to msgsnd broadcast Date: Sat, 18 May 2024 19:31:56 +1000 Message-ID: <20240518093157.407144-15-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com> References: <20240518093157.407144-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=npiggin@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org msgsnd has a broadcast mode that sends hypervisor doorbells to all threads belonging to the same core as the target. A "subcore" mode sends to all or one thread depending on 1LPAR mode. Signed-off-by: Nicholas Piggin --- target/ppc/cpu.h | 6 +- target/ppc/helper.h | 2 +- target/ppc/excp_helper.c | 57 +++++++++++++------ .../ppc/translate/processor-ctrl-impl.c.inc | 2 +- 4 files changed, 46 insertions(+), 21 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8e15a9ccbb..ee6883c037 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1163,7 +1163,11 @@ FIELD(FPSCR, FI, FPSCR_FI, 1) #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT) -#define DBELL_BRDCAST PPC_BIT(37) +#define DBELL_BRDCAST_MASK PPC_BITMASK(37, 38) +#define DBELL_BRDCAST_SHIFT 25 +#define DBELL_BRDCAST_SUBPROC (0x1 << DBELL_BRDCAST_SHIFT) +#define DBELL_BRDCAST_CORE (0x2 << DBELL_BRDCAST_SHIFT) + #define DBELL_LPIDTAG_SHIFT 14 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT) #define DBELL_PIRTAG_MASK 0x3fff diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 57bf8354e7..dd92c6a937 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -695,7 +695,7 @@ DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl) DEF_HELPER_1(msgsnd, void, tl) DEF_HELPER_2(msgclr, void, env, tl) -DEF_HELPER_1(book3s_msgsnd, void, tl) +DEF_HELPER_2(book3s_msgsnd, void, env, tl) DEF_HELPER_2(book3s_msgclr, void, env, tl) #endif diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 28f2ab4583..73837c7a14 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2969,7 +2969,7 @@ void helper_msgsnd(target_ulong rb) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *cenv = &cpu->env; - if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { + if ((rb & DBELL_BRDCAST_MASK) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { ppc_set_irq(cpu, irq, 1); } } @@ -2988,6 +2988,16 @@ static bool dbell_type_server(target_ulong rb) return (rb & DBELL_TYPE_MASK) == DBELL_TYPE_DBELL_SERVER; } +static inline bool dbell_bcast_core(target_ulong rb) +{ + return (rb & DBELL_BRDCAST_MASK) == DBELL_BRDCAST_CORE; +} + +static inline bool dbell_bcast_subproc(target_ulong rb) +{ + return (rb & DBELL_BRDCAST_MASK) == DBELL_BRDCAST_SUBPROC; +} + void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb) { if (!dbell_type_server(rb)) { @@ -2997,32 +3007,43 @@ void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb) ppc_set_irq(env_archcpu(env), PPC_INTERRUPT_HDOORBELL, 0); } -static void book3s_msgsnd_common(int pir, int irq) +void helper_book3s_msgsnd(CPUPPCState *env, target_ulong rb) { - CPUState *cs; + int pir = rb & DBELL_PROCIDTAG_MASK; + bool brdcast = false; + CPUState *cs, *ccs; + PowerPCCPU *cpu; - bql_lock(); - CPU_FOREACH(cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *cenv = &cpu->env; + if (!dbell_type_server(rb)) { + return; + } - /* TODO: broadcast message to all threads of the same processor */ - if (cenv->spr_cb[SPR_PIR].default_value == pir) { - ppc_set_irq(cpu, irq, 1); - } + cpu = ppc_get_vcpu_by_pir(pir); + if (!cpu) { + return; } - bql_unlock(); -} + cs = CPU(cpu); -void helper_book3s_msgsnd(target_ulong rb) -{ - int pir = rb & DBELL_PROCIDTAG_MASK; + if (dbell_bcast_core(rb) || (dbell_bcast_subproc(rb) && + (env->flags & POWERPC_FLAG_SMT_1LPAR))) { + brdcast = true; + } - if (!dbell_type_server(rb)) { + if (cs->nr_threads == 1 || !brdcast) { + ppc_set_irq(cpu, PPC_INTERRUPT_HDOORBELL, 1); return; } - book3s_msgsnd_common(pir, PPC_INTERRUPT_HDOORBELL); + /* + * Why is bql needed for walking CPU list? Answer seems to be because ppc + * irq handling needs it, but ppc_set_irq takes the lock itself if needed, + * so could this be removed? + */ + bql_lock(); + THREAD_SIBLING_FOREACH(cs, ccs) { + ppc_set_irq(POWERPC_CPU(ccs), PPC_INTERRUPT_HDOORBELL, 1); + } + bql_unlock(); } #ifdef TARGET_PPC64 diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/translate/processor-ctrl-impl.c.inc index 0142801985..8abbb89630 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -59,7 +59,7 @@ static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a) #if !defined(CONFIG_USER_ONLY) if (is_book3s_arch2x(ctx)) { - gen_helper_book3s_msgsnd(cpu_gpr[a->rb]); + gen_helper_book3s_msgsnd(tcg_env, cpu_gpr[a->rb]); } else { gen_helper_msgsnd(cpu_gpr[a->rb]); }