From patchwork Mon May 20 07:09:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengjiu Wang X-Patchwork-Id: 13668079 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F352018C3B; Mon, 20 May 2024 07:29:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716190175; cv=none; b=sBXyjkDC7j/KPQpy7osYSQFM+bXDDbIedlGEUX8S3+yaQRV3iMEnEHwKSKVLeijIxWoPStn8tfDq5PQJST+kUOuZB/r1nczZu9Cb4vaZ7D64So1rGMTn8yGJvsxd7Ha/cRHuJm0riDYIW6qjJ8/aXqp/Z4eiSdbwYj6bp6G5rEQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716190175; c=relaxed/simple; bh=vwhl2TItuSUrCzO5vdVWYedHOQAkUkhYVgTV88cG0tI=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References; b=JkOOCS73kbm0Qhjkx+JyW6DFzmwMWVvKrzvgbquau4gUqIRiJ1cGmZodhcmYJ1q0IdpvUZqOzKsbchjCS6GAP/w97ojSATWFlXYJXRHfxNNr2oYgVH1Mrm5jfm46X4kM3f/DuN059xsHPVSH7l+1mYxvllYKqE+k4fArac6GrMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6B4111A1A11; Mon, 20 May 2024 09:29:25 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1EFE01A1A0B; Mon, 20 May 2024 09:29:25 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id B374E1820F59; Mon, 20 May 2024 15:29:22 +0800 (+08) From: Shengjiu Wang To: abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, marex@denx.de, linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, shengjiu.wang@gmail.com Subject: [PATCH v4 1/5] dt-bindings: clock: imx8mp: Add #reset-cells property Date: Mon, 20 May 2024 15:09:19 +0800 Message-Id: <1716188963-16175-2-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> References: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The Audio Block Control contains clock distribution and gating controls, as well as reset handling to several of the AUDIOMIX peripherals. Especially the reset controls for Enhanced Audio Return Channel (EARC) PHY and Controller. So make Audio Block Control a reset provider for EARC, which is one of modules in this audio subsystem. Signed-off-by: Shengjiu Wang Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml index 0a6dc1a6e122..6588a17a7d9a 100644 --- a/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml +++ b/Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml @@ -44,6 +44,9 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs. + '#reset-cells': + const: 1 + required: - compatible - reg From patchwork Mon May 20 07:09:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengjiu Wang X-Patchwork-Id: 13668081 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72CFC1BDCF; Mon, 20 May 2024 07:29:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716190176; cv=none; b=GzAUIuMtT0Xpp2vRxt7qga3LXsARrTrzosMPRtXhdeBwOqE0g+DmdySmNSamzvKwjZrs58itMvWr04hiHrqEVmpyhTdRJQERCcIsXbsrT/kzPYzjPAGyKWBMNbh1RJvENFLXSFRXvdH+uGESdy9RzAh7SN4YsFEHlTU9DWeAu20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716190176; c=relaxed/simple; bh=jvPEQoMEoQueVYrDTidmQI5uVfBZN2H/j3C1fF+vxKk=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References; b=CemwMMlvOYRnyOfW9Mb0X78b08Y/XkSVpv2cHJjNXEOprhF9hTBjzt08uNqeLc9PzbgUGxF4bpj1j6QPJqKAjFFKKDDSmggijYHm+enhkPlvDqJndT6ofG9yLux96Kkn9iA37YdPh9864ehGw91yXuBb6xMzlkr2G6UF5pD+2qY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 4ACC620194A; Mon, 20 May 2024 09:29:27 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B37E2201952; Mon, 20 May 2024 09:29:26 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 5E5D7181D0F8; Mon, 20 May 2024 15:29:24 +0800 (+08) From: Shengjiu Wang To: abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, marex@denx.de, linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, shengjiu.wang@gmail.com Subject: [PATCH v4 2/5] clk: imx: clk-audiomix: Add reset controller Date: Mon, 20 May 2024 15:09:20 +0800 Message-Id: <1716188963-16175-3-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> References: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Audiomix block control can be a reset controller for Enhanced Audio Return Channel (EARC), which is one of modules in this audiomix subsystem. The reset controller is supported by the auxiliary device framework. Signed-off-by: Shengjiu Wang --- drivers/clk/imx/Kconfig | 1 + drivers/clk/imx/clk-imx8mp-audiomix.c | 61 +++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 6da0fba68225..9edfb030bea9 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -81,6 +81,7 @@ config CLK_IMX8MP tristate "IMX8MP CCM Clock Driver" depends on ARCH_MXC || COMPILE_TEST select MXC_CLK + select AUXILIARY_BUS help Build the driver for i.MX8MP CCM Clock Driver diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c index b381d6f784c8..d2eaabe431cd 100644 --- a/drivers/clk/imx/clk-imx8mp-audiomix.c +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Marek Vasut */ +#include #include #include #include @@ -217,6 +218,62 @@ struct clk_imx8mp_audiomix_priv { struct clk_hw_onecell_data clk_data; }; +#if IS_ENABLED(CONFIG_RESET_CONTROLLER) + +static void clk_imx8mp_audiomix_reset_unregister_adev(void *_adev) +{ + struct auxiliary_device *adev = _adev; + + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static void clk_imx8mp_audiomix_reset_adev_release(struct device *dev) +{ + struct auxiliary_device *adev = to_auxiliary_dev(dev); + + kfree(adev); +} + +static int clk_imx8mp_audiomix_reset_controller_register(struct device *dev, + struct clk_imx8mp_audiomix_priv *priv) +{ + struct auxiliary_device *adev; + int ret; + + adev = kzalloc(sizeof(*adev), GFP_KERNEL); + if (!adev) + return -ENOMEM; + + adev->name = "reset"; + adev->dev.parent = dev; + adev->dev.release = clk_imx8mp_audiomix_reset_adev_release; + + ret = auxiliary_device_init(adev); + if (ret) { + kfree(adev); + return ret; + } + + ret = auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + kfree(adev); + return ret; + } + + return devm_add_action_or_reset(dev, clk_imx8mp_audiomix_reset_unregister_adev, adev); +} + +#else /* !CONFIG_RESET_CONTROLLER */ + +static int clk_imx8mp_audiomix_reset_controller_register(struct clk_imx8mp_audiomix_priv *priv) +{ + return 0; +} + +#endif /* !CONFIG_RESET_CONTROLLER */ + static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save) { struct clk_imx8mp_audiomix_priv *priv = dev_get_drvdata(dev); @@ -337,6 +394,10 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev) if (ret) goto err_clk_register; + ret = clk_imx8mp_audiomix_reset_controller_register(dev, priv); + if (ret) + goto err_clk_register; + pm_runtime_put_sync(dev); return 0; From patchwork Mon May 20 07:09:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengjiu Wang X-Patchwork-Id: 13668082 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47EA72032D; Mon, 20 May 2024 07:29:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; 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Mon, 20 May 2024 09:29:28 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 57B3820194D; Mon, 20 May 2024 09:29:28 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id F3EEC1820F59; Mon, 20 May 2024 15:29:25 +0800 (+08) From: Shengjiu Wang To: abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, marex@denx.de, linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, shengjiu.wang@gmail.com Subject: [PATCH v4 3/5] reset: imx-aux: Add i.MX auxiliary reset driver Date: Mon, 20 May 2024 15:09:21 +0800 Message-Id: <1716188963-16175-4-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> References: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add support for the resets on i.MX8MP Audio Block Control module. The reset controller is created using the auxiliary device framework and set up in the clock driver. The EARC PHY software reset and EARC controller software reset can be supported. Signed-off-by: Shengjiu Wang --- drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-imx-aux.c | 217 ++++++++++++++++++++++++++++++++++ 3 files changed, 226 insertions(+) create mode 100644 drivers/reset/reset-imx-aux.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 7112f5932609..38fdf05b326b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -91,6 +91,14 @@ config RESET_IMX7 help This enables the reset controller driver for i.MX7 SoCs. +config RESET_IMX_AUX + tristate "i.MX Auxiliary Reset Driver" + depends on CLK_IMX8MP + select AUXILIARY_BUS + default CLK_IMX8MP + help + This enables the auxiliary reset controller driver for i.MX. + config RESET_INTEL_GW bool "Intel Reset Controller Driver" depends on X86 || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index fd8b49fa46fc..f078da14c327 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o obj-$(CONFIG_RESET_GPIO) += reset-gpio.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o +obj-$(CONFIG_RESET_IMX_AUX) += reset-imx-aux.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o obj-$(CONFIG_RESET_K210) += reset-k210.o obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o diff --git a/drivers/reset/reset-imx-aux.c b/drivers/reset/reset-imx-aux.c new file mode 100644 index 000000000000..54a5e1e627ea --- /dev/null +++ b/drivers/reset/reset-imx-aux.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The reset does not support the feature and corresponding + * values are not valid + */ +#define ASSERT_NONE BIT(0) +#define DEASSERT_NONE BIT(1) +#define STATUS_NONE BIT(2) + +/* When set this function is activated by setting(vs clearing) this bit */ +#define ASSERT_SET BIT(3) +#define DEASSERT_SET BIT(4) +#define STATUS_SET BIT(5) + +/* The following are the inverse of the above and are added for consistency */ +#define ASSERT_CLEAR (0 << 3) +#define DEASSERT_CLEAR (0 << 4) +#define STATUS_CLEAR (0 << 5) + +/** + * struct imx_reset_ctrl - reset control structure + * @assert_offset: reset assert control register offset + * @assert_bit: reset assert bit in the reset assert control register + * @deassert_offset: reset deassert control register offset + * @deassert_bit: reset deassert bit in the reset deassert control register + * @status_offset: reset status register offset + * @status_bit: reset status bit in the reset status register + * @flags: reset flag indicating how the (de)assert and status are handled + */ +struct imx_reset_ctrl { + u32 assert_offset; + u32 assert_bit; + u32 deassert_offset; + u32 deassert_bit; + u32 status_offset; + u32 status_bit; + u32 flags; +}; + +struct imx_reset_data { + const struct imx_reset_ctrl *rst_ctrl; + size_t rst_ctrl_num; +}; + +struct imx_aux_reset_priv { + struct reset_controller_dev rcdev; + void __iomem *base; + const struct imx_reset_data *data; +}; + +static int imx_aux_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx_aux_reset_priv *priv = container_of(rcdev, + struct imx_aux_reset_priv, rcdev); + const struct imx_reset_data *data = priv->data; + void __iomem *reg_addr = priv->base; + const struct imx_reset_ctrl *ctrl; + unsigned int mask, value, reg; + + if (id >= data->rst_ctrl_num) + return -EINVAL; + + ctrl = &data->rst_ctrl[id]; + + /* assert not supported for this reset */ + if (ctrl->flags & ASSERT_NONE) + return -EOPNOTSUPP; + + mask = BIT(ctrl->assert_bit); + value = (ctrl->flags & ASSERT_SET) ? mask : 0x0; + + reg = readl(reg_addr + ctrl->assert_offset); + writel(reg | value, reg_addr + ctrl->assert_offset); + + return 0; +} + +static int imx_aux_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx_aux_reset_priv *priv = container_of(rcdev, + struct imx_aux_reset_priv, rcdev); + const struct imx_reset_data *data = priv->data; + void __iomem *reg_addr = priv->base; + const struct imx_reset_ctrl *ctrl; + unsigned int mask, value, reg; + + if (id >= data->rst_ctrl_num) + return -EINVAL; + + ctrl = &data->rst_ctrl[id]; + + /* deassert not supported for this reset */ + if (ctrl->flags & DEASSERT_NONE) + return -EOPNOTSUPP; + + mask = BIT(ctrl->deassert_bit); + value = (ctrl->flags & DEASSERT_SET) ? mask : 0x0; + + reg = readl(reg_addr + ctrl->deassert_offset); + writel(reg | value, reg_addr + ctrl->deassert_offset); + + return 0; +} + +static int imx_aux_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx_aux_reset_priv *priv = container_of(rcdev, + struct imx_aux_reset_priv, rcdev); + const struct imx_reset_data *data = priv->data; + void __iomem *reg_addr = priv->base; + const struct imx_reset_ctrl *ctrl; + unsigned int reset_state; + + if (id >= data->rst_ctrl_num) + return -EINVAL; + + ctrl = &data->rst_ctrl[id]; + + /* status not supported for this reset */ + if (ctrl->flags & STATUS_NONE) + return -EOPNOTSUPP; + + reset_state = readl(reg_addr + ctrl->status_offset); + + return !(reset_state & BIT(ctrl->status_bit)) == + !(ctrl->flags & STATUS_SET); +} + +static const struct reset_control_ops imx_aux_reset_ops = { + .assert = imx_aux_reset_assert, + .deassert = imx_aux_reset_deassert, + .status = imx_aux_reset_status, +}; + +static int imx_aux_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct imx_reset_data *data = (struct imx_reset_data *)(id->driver_data); + struct imx_aux_reset_priv *priv; + struct device *dev = &adev->dev; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.nr_resets = data->rst_ctrl_num; + priv->rcdev.ops = &imx_aux_reset_ops; + priv->rcdev.of_node = dev->parent->of_node; + priv->rcdev.dev = dev; + priv->rcdev.of_reset_n_cells = 1; + priv->base = of_iomap(dev->parent->of_node, 0); + priv->data = data; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + +#define EARC 0x200 + +const struct imx_reset_ctrl imx8mp_audiomix_rst_ctrl[] = { + { + .assert_offset = EARC, + .assert_bit = 0, + .deassert_offset = EARC, + .deassert_bit = 0, + .flags = ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE, + }, + { + .assert_offset = EARC, + .assert_bit = 1, + .deassert_offset = EARC, + .deassert_bit = 1, + .flags = ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE, + }, +}; + +const struct imx_reset_data imx8mp_audiomix_rst_data = { + .rst_ctrl = imx8mp_audiomix_rst_ctrl, + .rst_ctrl_num = ARRAY_SIZE(imx8mp_audiomix_rst_ctrl), +}; + +static const struct auxiliary_device_id imx_aux_reset_ids[] = { + { + .name = "clk_imx8mp_audiomix.reset", + .driver_data = (kernel_ulong_t)&imx8mp_audiomix_rst_data, + }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, imx_aux_reset_ids); + +static struct auxiliary_driver imx_aux_reset_driver = { + .probe = imx_aux_reset_probe, + .id_table = imx_aux_reset_ids, +}; + +module_auxiliary_driver(imx_aux_reset_driver); + +MODULE_AUTHOR("Shengjiu Wang "); +MODULE_DESCRIPTION("Freescale i.MX auxiliary reset driver"); +MODULE_LICENSE("GPL"); From patchwork Mon May 20 07:09:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengjiu Wang X-Patchwork-Id: 13668083 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 386F322626; Mon, 20 May 2024 07:29:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716190179; cv=none; b=ojGmHh0zSU+NA7kaud8bQ9qldNwD23uSX4Bowld+kSo0blSeGbzdCgz8zBZZZYjT6me7u99sP8Q9B5IWIPvxahXyTNGJjw2BBMffHHZhk25h70Gxi67L95CxrefszhmtLv0gbsyRzkDsey8F+Lm6sQAWSsOWx+P8sNYJ7KxOBdc= ARC-Message-Signature: i=1; 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Mon, 20 May 2024 09:29:29 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 97D9D181D0F8; Mon, 20 May 2024 15:29:27 +0800 (+08) From: Shengjiu Wang To: abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, marex@denx.de, linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, shengjiu.wang@gmail.com Subject: [PATCH v4 4/5] clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks Date: Mon, 20 May 2024 15:09:22 +0800 Message-Id: <1716188963-16175-5-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> References: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add CLK_SET_RATE_PARENT flags that when the device driver sets the child clock rate, parent clock frequency can be refined accordingly. Signed-off-by: Shengjiu Wang --- drivers/clk/imx/clk-imx8mp-audiomix.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c index d2eaabe431cd..3d15405cedb8 100644 --- a/drivers/clk/imx/clk-imx8mp-audiomix.c +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c @@ -326,12 +326,12 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev) for (i = 0; i < ARRAY_SIZE(sels); i++) { if (sels[i].num_parents == 1) { hw = devm_clk_hw_register_gate_parent_data(dev, - sels[i].name, &sels[i].parent, 0, + sels[i].name, &sels[i].parent, CLK_SET_RATE_PARENT, base + sels[i].reg, sels[i].shift, 0, NULL); } else { hw = devm_clk_hw_register_mux_parent_data_table(dev, sels[i].name, sels[i].parents, - sels[i].num_parents, 0, + sels[i].num_parents, CLK_SET_RATE_PARENT, base + sels[i].reg, sels[i].shift, sels[i].width, 0, NULL, NULL); @@ -374,7 +374,8 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev) clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw; hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass", - 0, base + SAI_PLL_GNRL_CTL, 13, + CLK_SET_RATE_PARENT, + base + SAI_PLL_GNRL_CTL, 13, 0, NULL); if (IS_ERR(hw)) { ret = PTR_ERR(hw); @@ -383,7 +384,8 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev) clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw; hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2", - "sai_pll_out", 0, 1, 2); + "sai_pll_out", + CLK_SET_RATE_PARENT, 1, 2); if (IS_ERR(hw)) { ret = PTR_ERR(hw); goto err_clk_register; From patchwork Mon May 20 07:09:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengjiu Wang X-Patchwork-Id: 13668080 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 836181B960; Mon, 20 May 2024 07:29:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716190175; cv=none; b=B9lAmdSSAH2i+bN2d24t7cliAVcckSdR1ax4UoPcu9IWBgKkwfSx85H3R79n4FqPmSjSYU3wrMSL1x5/gxdObzZK93UAmSxWncgpdTlFetzWoLGvTXYn9hga0aCSWaerQs0u0yRuz+YHc4rMQRudLb5SGtlpanC7z8eMWPgLWDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716190175; c=relaxed/simple; bh=4aojkFZC7sCdR6e90XG+sUyXzKpg7q4F9CqGRb/pFkM=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References; b=Uq9i9Yd+YFWP1sTeiktfOW9FAia4etZ/BYuChrwHBlm4cTNeO2HhmO1+SbkPVjQf4sDhF7ml94woDZW6ar6U8ORO6xawJvY2uxkg1kNrY286TQlpV7vgn41W1ZUiVey+dYWMniv+7I0ZsgEhh1oyfiJwctkxrgvk+tgWz2qdcYE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 00478201946; Mon, 20 May 2024 09:29:32 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A82E420194D; Mon, 20 May 2024 09:29:31 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 3A768180226C; Mon, 20 May 2024 15:29:29 +0800 (+08) From: Shengjiu Wang To: abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, marex@denx.de, linux-clk@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, shengjiu.wang@gmail.com Subject: [PATCH v4 5/5] clk: imx: clk-audiomix: Corrent parent clock for earc_phy and audpll Date: Mon, 20 May 2024 15:09:23 +0800 Message-Id: <1716188963-16175-6-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> References: <1716188963-16175-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: According to Reference Manual of i.MX8MP The parent clock of "earc_phy" is "sai_pll_out_div2", The parent clock of "audpll" is "osc_24m". Add CLK_GATE_PARENT() macro for usage of specifying parent clock. Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control") Signed-off-by: Shengjiu Wang --- drivers/clk/imx/clk-imx8mp-audiomix.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c index 3d15405cedb8..4ae0cf916d78 100644 --- a/drivers/clk/imx/clk-imx8mp-audiomix.c +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c @@ -155,6 +155,15 @@ static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = { PDM_SEL, 2, 0 \ } +#define CLK_GATE_PARENT(gname, cname, pname) \ + { \ + gname"_cg", \ + IMX8MP_CLK_AUDIOMIX_##cname, \ + { .fw_name = pname, .name = pname }, NULL, 1, \ + CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32), \ + 1, IMX8MP_CLK_AUDIOMIX_##cname % 32 \ + } + struct clk_imx8mp_audiomix_sel { const char *name; int clkid; @@ -172,14 +181,14 @@ static struct clk_imx8mp_audiomix_sel sels[] = { CLK_GATE("earc", EARC_IPG), CLK_GATE("ocrama", OCRAMA_IPG), CLK_GATE("aud2htx", AUD2HTX_IPG), - CLK_GATE("earc_phy", EARC_PHY), + CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"), CLK_GATE("sdma2", SDMA2_ROOT), CLK_GATE("sdma3", SDMA3_ROOT), CLK_GATE("spba2", SPBA2_ROOT), CLK_GATE("dsp", DSP_ROOT), CLK_GATE("dspdbg", DSPDBG_ROOT), CLK_GATE("edma", EDMA_ROOT), - CLK_GATE("audpll", AUDPLL_ROOT), + CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"), CLK_GATE("mu2", MU2_ROOT), CLK_GATE("mu3", MU3_ROOT), CLK_PDM,