From patchwork Wed May 22 08:40:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13670586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8308C25B79 for ; Wed, 22 May 2024 08:40:23 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.727339.1131814 (Exim 4.92) (envelope-from ) id 1s9hWA-0002mI-4T; Wed, 22 May 2024 08:40:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 727339.1131814; Wed, 22 May 2024 08:40:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s9hWA-0002mB-1Z; Wed, 22 May 2024 08:40:14 +0000 Received: by outflank-mailman (input) for mailman id 727339; Wed, 22 May 2024 08:40:12 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s9hW8-0002m1-SO for xen-devel@lists.xenproject.org; Wed, 22 May 2024 08:40:12 +0000 Received: from pb-smtp1.pobox.com (pb-smtp1.pobox.com [64.147.108.70]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e684e0a9-1816-11ef-90a0-e314d9c70b13; Wed, 22 May 2024 10:40:11 +0200 (CEST) Received: from pb-smtp1.pobox.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 21F1F35779; Wed, 22 May 2024 04:40:10 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp1.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 1919535777; Wed, 22 May 2024 04:40:10 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp1.pobox.com (Postfix) with ESMTPSA id 9684035776; Wed, 22 May 2024 04:40:08 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e684e0a9-1816-11ef-90a0-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=/X53LE/dz4N5HVUlkrUINn3qO TL2CeuDunQfSqMtggo=; b=onfZYvPkj8IbEJkz9sPXJpYcpY8exJiNsIIYl8wde QMDG5tjDXTz8isSiP7tlytN2ZrHu/ik7pMG7FUZY7kwGPKClpL3RD0GG1J280xVZ yZwTXRZ1BoUyjpoXxpIi6uPiFHuQBSN8D/cfk3SvWD9ax1bqHeHEWRCOe8ddN1bx KA= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini Subject: [XEN PATCH v4 1/3] x86/intel: move vmce_has_lmce() routine to header Date: Wed, 22 May 2024 11:40:06 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: E5427ACA-1816-11EF-B91C-78DCEB2EC81B-90055647!pb-smtp1.pobox.com Moving this function out of mce_intel.c will make it possible to disable build of Intel MCE code later on, because the function gets called from common x86 code. Also replace boilerplate code that checks for MCG_LMCE_P flag with vmce_has_lmce(), which might contribute to readability a bit. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini CC: Jan Beulich Acked-by: Jan Beulich --- changes in v4: - changed description a bit changes in v3: - do not check for CONFIG_INTEL - remove CONFIG_INTEL from patch description changes in v2: - move vmce_has_lmce() to cpu/mcheck/mce.h - move IS_ENABLED(CONFIG_INTEL) check inside vmce_has_lmce() - changed description --- xen/arch/x86/cpu/mcheck/mce.h | 5 +++++ xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ---- xen/arch/x86/cpu/mcheck/vmce.c | 5 ++--- xen/arch/x86/include/asm/mce.h | 1 - xen/arch/x86/msr.c | 2 ++ 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 4806405f96..eba4b536c7 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -170,6 +170,11 @@ static inline int mce_bank_msr(const struct vcpu *v, uint32_t msr) return 0; } +static inline bool vmce_has_lmce(const struct vcpu *v) +{ + return v->arch.vmce.mcg_cap & MCG_LMCE_P; +} + struct mce_callbacks { void (*handler)(const struct cpu_user_regs *regs); bool (*check_addr)(uint64_t status, uint64_t misc, int addr_type); diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 3f5199b531..af43281cc6 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -1050,7 +1050,3 @@ int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) return 1; } -bool vmce_has_lmce(const struct vcpu *v) -{ - return v->arch.vmce.mcg_cap & MCG_LMCE_P; -} diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 4da6f4a3e4..5abdf4cb5f 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -203,7 +203,7 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val) * bits are always set in guest MSR_IA32_FEATURE_CONTROL by Xen, so it * does not need to check them here. */ - if ( cur->arch.vmce.mcg_cap & MCG_LMCE_P ) + if ( vmce_has_lmce(cur) ) { *val = cur->arch.vmce.mcg_ext_ctl; mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL %#"PRIx64"\n", @@ -332,8 +332,7 @@ int vmce_wrmsr(uint32_t msr, uint64_t val) break; case MSR_IA32_MCG_EXT_CTL: - if ( (cur->arch.vmce.mcg_cap & MCG_LMCE_P) && - !(val & ~MCG_EXT_CTL_LMCE_EN) ) + if ( vmce_has_lmce(cur) && !(val & ~MCG_EXT_CTL_LMCE_EN) ) cur->arch.vmce.mcg_ext_ctl = val; else ret = -1; diff --git a/xen/arch/x86/include/asm/mce.h b/xen/arch/x86/include/asm/mce.h index 6ce56b5b85..2ec47a71ae 100644 --- a/xen/arch/x86/include/asm/mce.h +++ b/xen/arch/x86/include/asm/mce.h @@ -41,7 +41,6 @@ extern void vmce_init_vcpu(struct vcpu *v); extern int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt); extern int vmce_wrmsr(uint32_t msr, uint64_t val); extern int vmce_rdmsr(uint32_t msr, uint64_t *val); -extern bool vmce_has_lmce(const struct vcpu *v); extern int vmce_enable_mca_cap(struct domain *d, uint64_t cap); DECLARE_PER_CPU(unsigned int, nr_mce_banks); diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 9babd441f9..b0ec96f021 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -24,6 +24,8 @@ #include +#include "cpu/mcheck/mce.h" + DEFINE_PER_CPU(uint32_t, tsc_aux); int init_vcpu_msr_policy(struct vcpu *v) From patchwork Wed May 22 08:42:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13670589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C05CFC25B77 for ; Wed, 22 May 2024 08:42:24 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.727345.1131824 (Exim 4.92) (envelope-from ) id 1s9hY7-0003cB-FG; Wed, 22 May 2024 08:42:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 727345.1131824; Wed, 22 May 2024 08:42:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s9hY7-0003c4-CN; Wed, 22 May 2024 08:42:15 +0000 Received: by outflank-mailman (input) for mailman id 727345; Wed, 22 May 2024 08:42:13 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s9hY5-0003br-Nw for xen-devel@lists.xenproject.org; Wed, 22 May 2024 08:42:13 +0000 Received: from pb-smtp1.pobox.com (pb-smtp1.pobox.com [64.147.108.70]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2efde923-1817-11ef-90a0-e314d9c70b13; Wed, 22 May 2024 10:42:12 +0200 (CEST) Received: from pb-smtp1.pobox.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 243D835794; Wed, 22 May 2024 04:42:12 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp1.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 1DDC335793; Wed, 22 May 2024 04:42:12 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp1.pobox.com (Postfix) with ESMTPSA id 5811F35792; Wed, 22 May 2024 04:42:11 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2efde923-1817-11ef-90a0-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=b2BmrhjIaVjxHWLhcCazmWsg7 7Ut75EvzLcrNm5R+Dc=; b=SyosGijh/FEKLb6xHf9QCa8Sn9Fc2Xda9OfbIcTso mxo9nBAN+DZUlI4DtvsGoxtN8gbaoq31C8hwp8wFSU8aCnmLdAbyoUqvxQYtifBN ldafFpWUqvW0MGik1tP3nY8zd5osL/tVtM7iY60D6z7Ku5EvoCWqz1Mk4P1bkYYN eU= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini Subject: [XEN PATCH v4 2/3] x86/MCE: add default switch case in init_nonfatal_mce_checker() Date: Wed, 22 May 2024 11:42:09 +0300 Message-Id: <9ec888c37a261c86a52f360146cbbb3ad437ad30.1716366581.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 2E697050-1817-11EF-ADA8-78DCEB2EC81B-90055647!pb-smtp1.pobox.com The default switch case block is wanted here, to handle situation e.g. of unexpected c->x86_vendor value -- then no mcheck init is done, but misleading message still gets logged anyway. Signed-off-by: Sergiy Kibrik CC: Jan Beulich Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- changes in v4: - return 0 instead of -ENODEV and put a comment - update description a bit --- xen/arch/x86/cpu/mcheck/non-fatal.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c index 33cacd15c2..5a53bcd0b7 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -29,9 +29,14 @@ static int __init cf_check init_nonfatal_mce_checker(void) /* Assume we are on K8 or newer AMD or Hygon CPU here */ amd_nonfatal_mcheck_init(c); break; + case X86_VENDOR_INTEL: intel_nonfatal_mcheck_init(c); break; + + default: + /* unhandled vendor isn't really an error */ + return 0; } printk(KERN_INFO "mcheck_poll: Machine check polling timer started.\n"); return 0; From patchwork Wed May 22 08:44:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13670590 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A94FCC25B79 for ; Wed, 22 May 2024 08:44:32 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.727352.1131833 (Exim 4.92) (envelope-from ) id 1s9ha7-00049h-P0; Wed, 22 May 2024 08:44:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 727352.1131833; Wed, 22 May 2024 08:44:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s9ha7-00049a-MG; Wed, 22 May 2024 08:44:19 +0000 Received: by outflank-mailman (input) for mailman id 727352; Wed, 22 May 2024 08:44:18 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s9ha6-00049U-Cc for xen-devel@lists.xenproject.org; Wed, 22 May 2024 08:44:18 +0000 Received: from pb-smtp1.pobox.com (pb-smtp1.pobox.com [64.147.108.70]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 7926cbdf-1817-11ef-90a0-e314d9c70b13; Wed, 22 May 2024 10:44:17 +0200 (CEST) Received: from pb-smtp1.pobox.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 357263579F; Wed, 22 May 2024 04:44:16 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp1.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 1E8333579E; Wed, 22 May 2024 04:44:16 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp1.pobox.com (Postfix) with ESMTPSA id 8621E3579D; Wed, 22 May 2024 04:44:14 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7926cbdf-1817-11ef-90a0-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=7TGP+W8jkZr2yV0hnrertRwq7 O7r+p4IX9AQgP14leA=; b=YPbKPtoPohuFUMfxlv3ra2i8mxjUzTgwmnmJC4pCp SvSHenornZ/YLsyNdaYv3/CEgmR8xPw2I+PkVyXTDA6zW5TPayzqllRnWIa1oPrr SsmpZfnH5BCEO1un5V2JaS92k+Nyao8ee+yU7/nBppi9513li9luorCB35UgJDN7 JY= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v4 3/3] x86/MCE: optional build of AMD/Intel MCE code Date: Wed, 22 May 2024 11:44:12 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 77D6EBFA-1817-11EF-B26D-78DCEB2EC81B-90055647!pb-smtp1.pobox.com Separate Intel/AMD-specific MCE code using CONFIG_{INTEL,AMD} config options. Now we can avoid build of mcheck code if support for specific platform is intentionally disabled by configuration. Also global variables lmce_support & cmci_support from Intel-specific mce_intel.c have to moved to common mce.c, as they get checked in common code. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- changes in v4: - attribute {lmce_support,cmci_support} with __ro_after_init changes in v3: - default return value of init_nonfatal_mce_checker() done in separate patch - move lmce_support & cmci_support to common mce.c code - changed patch description changes in v2: - fallback to original ordering in Makefile - redefine lmce_support & cmci_support global vars to false when !INTEL - changed patch description --- xen/arch/x86/cpu/mcheck/Makefile | 8 ++++---- xen/arch/x86/cpu/mcheck/mce.c | 4 ++++ xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ---- xen/arch/x86/cpu/mcheck/non-fatal.c | 4 ++++ 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/Makefile b/xen/arch/x86/cpu/mcheck/Makefile index f927f10b4d..e6cb4dd503 100644 --- a/xen/arch/x86/cpu/mcheck/Makefile +++ b/xen/arch/x86/cpu/mcheck/Makefile @@ -1,12 +1,12 @@ -obj-y += amd_nonfatal.o -obj-y += mce_amd.o +obj-$(CONFIG_AMD) += amd_nonfatal.o +obj-$(CONFIG_AMD) += mce_amd.o obj-y += mcaction.o obj-y += barrier.o -obj-y += intel-nonfatal.o +obj-$(CONFIG_INTEL) += intel-nonfatal.o obj-y += mctelem.o obj-y += mce.o obj-y += mce-apei.o -obj-y += mce_intel.o +obj-$(CONFIG_INTEL) += mce_intel.o obj-y += non-fatal.o obj-y += util.o obj-y += vmce.o diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index fb9dec5b89..1664ca6412 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -38,6 +38,10 @@ DEFINE_PER_CPU_READ_MOSTLY(unsigned int, nr_mce_banks); unsigned int __read_mostly firstbank; unsigned int __read_mostly ppin_msr; uint8_t __read_mostly cmci_apic_vector; +bool __ro_after_init cmci_support; + +/* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */ +bool __ro_after_init lmce_support; DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, poll_bankmask); DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, no_cmci_banks); diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index af43281cc6..dd812f4b8a 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -26,16 +26,12 @@ #include "mcaction.h" static DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, mce_banks_owned); -bool __read_mostly cmci_support; static bool __read_mostly ser_support; static bool __read_mostly mce_force_broadcast; boolean_param("mce_fb", mce_force_broadcast); static int __read_mostly nr_intel_ext_msrs; -/* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */ -bool __read_mostly lmce_support; - /* Intel SDM define bit15~bit0 of IA32_MCi_STATUS as the MC error code */ #define INTEL_MCCOD_MASK 0xFFFF diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c index 5a53bcd0b7..a9ee9bb94f 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -24,15 +24,19 @@ static int __init cf_check init_nonfatal_mce_checker(void) * Check for non-fatal errors every MCE_RATE s */ switch (c->x86_vendor) { +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: /* Assume we are on K8 or newer AMD or Hygon CPU here */ amd_nonfatal_mcheck_init(c); break; +#endif +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: intel_nonfatal_mcheck_init(c); break; +#endif default: /* unhandled vendor isn't really an error */