From patchwork Wed May 22 17:33:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13670999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8758AC25B78 for ; Wed, 22 May 2024 17:34:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 07A6910E216; Wed, 22 May 2024 17:34:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mZQC3GpR"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5AF7110E216; Wed, 22 May 2024 17:33:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399239; x=1747935239; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ALpXJBlekWVBACanBhcfadPLOt3mH4pv1niIAbO4bKw=; b=mZQC3GpR7YV1p99mNSIfiToeA/DACwWzXtxc/y+y562OSPvdDO84izOk gmEsKktNoFq7k4uYex7o+lvOV/iBD9ac7VAOYS24aVK1kN8aVlPsE06fO i4TlAD9hEL3ESqT+1Jv3XoExR2B8sYV90OFecni6NxnAeNXOtS3B1WzCc Aeyg6KUOBmxClMioMAZMF0MUSBIrKcZYv4L25dB8eihg5cUmIhSe1ALMx YL25t0X0YNAfdD8AtrKlML3PiMF4jlJO8PFXhQSO20h0lEFW8u7LUgE/f m0pmEYDLuk2W0H3fdVHjIbWmuyKmQ9pnHADGX6hz7tpMz1ebpZs3H5xDY w==; X-CSE-ConnectionGUID: rHp3j3rBQQuXXiFj9cDmZg== X-CSE-MsgGUID: AcnSb5bRQSmZM8W453LLbg== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="38053796" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="38053796" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:33:59 -0700 X-CSE-ConnectionGUID: 2bteG9IdTLCepw/Rn9Z40w== X-CSE-MsgGUID: FVvP81X8Sp6Kcx8hhUVR7g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33425134" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:33:57 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 01/10] drm/i915/display: move params copy at probe earlier Date: Wed, 22 May 2024 20:33:38 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Copy the parameters earlier to make subsequent changes easier. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_display_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index cf093bc0cb28..9edadc7270f6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -936,6 +936,8 @@ void intel_display_device_probe(struct drm_i915_private *i915) /* Add drm device backpointer as early as possible. */ i915->display.drm = &i915->drm; + intel_display_params_copy(&i915->display.params); + if (HAS_GMD_ID(i915)) info = probe_gmdid_display(i915, &ver, &rel, &step); else @@ -952,8 +954,6 @@ void intel_display_device_probe(struct drm_i915_private *i915) DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; DISPLAY_RUNTIME_INFO(i915)->ip.step = step; } - - intel_display_params_copy(&i915->display.params); } void intel_display_device_remove(struct drm_i915_private *i915) From patchwork Wed May 22 17:33:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D15ECC25B79 for ; Wed, 22 May 2024 17:34:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05DFC10E29C; Wed, 22 May 2024 17:34:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="b4OAjgi2"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0CD1910E29C; Wed, 22 May 2024 17:34:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399247; x=1747935247; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fremv7aANX/DrTGJTOuzxl38LKrfOcuucmamjy7lQ2E=; b=b4OAjgi2CizEH560O2C5eF6hsCI4IFK4vud1fIBvAQuD2MUGRp0I6qVE 5XUUPTd6kYj5Tnf9je5w8Mbw+rsEm4d/mW6CxkmucsjiEWcW8FcRPci9V 4bZ5NLMg07BPnwzEN4C5Ys29Qec/F/TpQ1PNYiWDpAv96TPHE1IcTVcY5 8MvK/8D13KFW9HO59NxaVNIxJ9ZGH3UpUYBw5i5XlbIErDyn+wEbNhiCn SSuACJoieoWITjvIuY5g05P0eIqNI6c1qdnvJAk+a4gE0W5RuNYKteh/p fnFxc7PgLjSc8HkyWFTrKSFu85m/vQVc4ZLBin96CTMA3156tOlzMnnMC Q==; X-CSE-ConnectionGUID: 5dLDBzGmT56zgtILzmK9zg== X-CSE-MsgGUID: bDcRgVj2QpWtzykUMliLRQ== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="38053804" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="38053804" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:07 -0700 X-CSE-ConnectionGUID: KKnnG2nfS6ee8AVHkzqhQQ== X-CSE-MsgGUID: m+9x8JmWQmac72w9Ew57tw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33425177" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:03 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 02/10] drm/i915/display: change probe for no display case Date: Wed, 22 May 2024 20:33:39 +0300 Message-Id: <8dfac3532a72ca6494c9955987166d9c6e0919bd.1716399081.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Return NULL for errors, and handle the no display case in one location. This will make subsequent changes easier. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- .../drm/i915/display/intel_display_device.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 9edadc7270f6..03181bb79d21 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -881,7 +881,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); if (!addr) { drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); - return &no_display; + return NULL; } val = ioread32(addr); @@ -889,7 +889,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step if (val == 0) { drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); - return &no_display; + return NULL; } *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); @@ -903,7 +903,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", *ver, *rel); - return &no_display; + return NULL; } static const struct intel_display_device_info * @@ -914,7 +914,7 @@ probe_display(struct drm_i915_private *i915) if (has_no_display(pdev)) { drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); - return &no_display; + return NULL; } for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { @@ -925,7 +925,7 @@ probe_display(struct drm_i915_private *i915) drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", pdev->device); - return &no_display; + return NULL; } void intel_display_device_probe(struct drm_i915_private *i915) @@ -943,6 +943,9 @@ void intel_display_device_probe(struct drm_i915_private *i915) else info = probe_display(i915); + if (!info) + goto no_display; + DISPLAY_INFO(i915) = info; memcpy(DISPLAY_RUNTIME_INFO(i915), @@ -954,6 +957,11 @@ void intel_display_device_probe(struct drm_i915_private *i915) DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; DISPLAY_RUNTIME_INFO(i915)->ip.step = step; } + + return; + +no_display: + DISPLAY_INFO(i915) = &no_display; } void intel_display_device_remove(struct drm_i915_private *i915) From patchwork Wed May 22 17:33:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D5EAC41513 for ; Wed, 22 May 2024 17:34:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8284210E2C4; Wed, 22 May 2024 17:34:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nRQ/I61q"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id E353310E1C7; Wed, 22 May 2024 17:34:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399251; x=1747935251; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2hd1oTsaBGWwB+YsagGLUrLw0dcd8lQCLG49MqNJDaE=; b=nRQ/I61q5i7LZuGnd6earwP/NKDvLTHG5Py88U6g40EjKi092so/59lQ k1tfCooCj64EYtix/4m+LuwlbpvHZ5MsqdrV6NPQ6BfujIRFqbZMSdpkF 6dQlBjQrIuVtgHHcSfoHoI10gHj8nM9e1FXXqqOlaswDNu4Tf7r5JJAYy 4KNUGxw71IPk1J70yhBmR7ZzgcT1qh0bO1Xtp3QFQaxPK5V2xSRuI/yq/ 5eMMd6yrcB1+/nZE3CjalsJKxUcr7wyvB703JgjU3K6HLl/tmc5WMz6tt G2JRj/eBYwVNIyXbFsiHBBTL4DnO48xZfU/19ylxjHPhR9GLeUbtN3ELN g==; X-CSE-ConnectionGUID: D8EesIBwQXCx+P/7jLuSSg== X-CSE-MsgGUID: UG5n/lpBSfuNu7KFdxIlSg== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="38053823" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="38053823" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:11 -0700 X-CSE-ConnectionGUID: +4kardNhStSFtN/oKzFWPQ== X-CSE-MsgGUID: qAgjViehRPS1chfJCgS/9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33425200" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:09 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 03/10] drm/i915/display: check platforms without display one level higher Date: Wed, 22 May 2024 20:33:40 +0300 Message-Id: <78d5d326c4c89f1942f120655c279c9274e96bfb.1716399081.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The main change here is that the check for platforms without display is now also done for GMD ID based platforms. However, without matches, the end result is the same. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_display_device.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 03181bb79d21..f548a7b0ec23 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -912,11 +912,6 @@ probe_display(struct drm_i915_private *i915) struct pci_dev *pdev = to_pci_dev(i915->drm.dev); int i; - if (has_no_display(pdev)) { - drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); - return NULL; - } - for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { if (intel_display_ids[i].devid == pdev->device) return intel_display_ids[i].info; @@ -930,6 +925,7 @@ probe_display(struct drm_i915_private *i915) void intel_display_device_probe(struct drm_i915_private *i915) { + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); const struct intel_display_device_info *info; u16 ver, rel, step; @@ -938,6 +934,11 @@ void intel_display_device_probe(struct drm_i915_private *i915) intel_display_params_copy(&i915->display.params); + if (has_no_display(pdev)) { + drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); + goto no_display; + } + if (HAS_GMD_ID(i915)) info = probe_gmdid_display(i915, &ver, &rel, &step); else From patchwork Wed May 22 17:33:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671002 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 776EAC25B79 for ; Wed, 22 May 2024 17:34:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7F3210E2A3; Wed, 22 May 2024 17:34:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cRQ42Xtw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 98AE210E2C4; Wed, 22 May 2024 17:34:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399256; x=1747935256; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=soFnXrWkTooFx8sgPjoH5RPRQWYmb9oeG5H/ggnP7kI=; b=cRQ42XtwrddAQXbr5aGCtDsEABH40QHMeopPYONah4sfnNNaZfcfSMNb 3y4uYfWJoGCtuZlGJy3hWknmHSwgIRpQ1fTCeykFsQHLe/qEbsbxK2uSG Hkn0D+ze/aAy+odkZZs8OKwF78TxUGjygWPvEt21uxbAmW5KAxilNg4FK nyipqVVfR9YGxuJjiGbEM4gHX1Qhlbvs13z+V7hey8rRD/QL5oBeBlWB+ 9sDPm73o9f9fa5/HmUQ+XCWhyjslGHE3RiK2KRIQWDMJ83pJPKCR7Sx8o DPMnhLIEYymBcio+Pw8ZgdO8q3p9DRGAjN+ozosMNmbi8d20s1jFV+zia Q==; X-CSE-ConnectionGUID: hTPftd+PTLiBSFUWs/6szg== X-CSE-MsgGUID: FeJnA4+DQ26RoygHp07wxQ== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="38053828" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="38053828" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:15 -0700 X-CSE-ConnectionGUID: UL4rm7LwS5GGDLThRkzcEg== X-CSE-MsgGUID: sTiKIMErSpaVi6DVdQaDow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33425219" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:13 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 04/10] drm/i915/display: change GMD ID display ip ver propagation at probe Date: Wed, 22 May 2024 20:33:41 +0300 Message-Id: <1610e9f5675b4d0d4f16ecd10a86486ce309a283.1716399081.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a name to the display ip version structure, and pass that around instead of a triplet of u16's. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- .../drm/i915/display/intel_display_device.c | 40 ++++++++----------- .../drm/i915/display/intel_display_device.h | 2 +- 2 files changed, 17 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index f548a7b0ec23..56b27546d1b3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -862,22 +862,14 @@ static const struct { }; static const struct intel_display_device_info * -probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step) +probe_gmdid_display(struct drm_i915_private *i915, struct intel_display_ip_ver *ip_ver) { struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + struct intel_display_ip_ver gmd_id; void __iomem *addr; u32 val; int i; - /* The caller expects to ver, rel and step to be initialized - * here, and there's no good way to check when there was a - * failure and no_display was returned. So initialize all these - * values here zero, to be sure. - */ - *ver = 0; - *rel = 0; - *step = 0; - addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); if (!addr) { drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); @@ -892,17 +884,20 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step return NULL; } - *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); - *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); - *step = REG_FIELD_GET(GMD_ID_STEP, val); + gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); + gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); + gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val); - for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) - if (*ver == gmdid_display_map[i].ver && - *rel == gmdid_display_map[i].rel) + for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) { + if (gmd_id.ver == gmdid_display_map[i].ver && + gmd_id.rel == gmdid_display_map[i].rel) { + *ip_ver = gmd_id; return gmdid_display_map[i].display; + } + } drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", - *ver, *rel); + gmd_id.ver, gmd_id.rel); return NULL; } @@ -927,7 +922,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) { struct pci_dev *pdev = to_pci_dev(i915->drm.dev); const struct intel_display_device_info *info; - u16 ver, rel, step; + struct intel_display_ip_ver ip_ver = {}; /* Add drm device backpointer as early as possible. */ i915->display.drm = &i915->drm; @@ -940,7 +935,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) } if (HAS_GMD_ID(i915)) - info = probe_gmdid_display(i915, &ver, &rel, &step); + info = probe_gmdid_display(i915, &ip_ver); else info = probe_display(i915); @@ -953,11 +948,8 @@ void intel_display_device_probe(struct drm_i915_private *i915) &DISPLAY_INFO(i915)->__runtime_defaults, sizeof(*DISPLAY_RUNTIME_INFO(i915))); - if (HAS_GMD_ID(i915)) { - DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver; - DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; - DISPLAY_RUNTIME_INFO(i915)->ip.step = step; - } + if (ip_ver.ver || ip_ver.rel || ip_ver.step) + DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; return; diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 17ddf82f0b6e..fd2d03bfe8a6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -111,7 +111,7 @@ struct drm_printer; (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) struct intel_display_runtime_info { - struct { + struct intel_display_ip_ver { u16 ver; u16 rel; u16 step; From patchwork Wed May 22 17:33:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71369C25B7A for ; Wed, 22 May 2024 17:34:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7BE3410E2E9; Wed, 22 May 2024 17:34:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NGFBesIs"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9216F10E2A3; Wed, 22 May 2024 17:34:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399261; x=1747935261; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tAmI2s2N6O/2j/pe94xlYgOT12ZpGt0ErWXpwTiQqZg=; b=NGFBesIs6OVRVGs4Jz1TF2lUZuJfExuFN4+XnBpRlGjGfzc1FMY/U4pc Rwl6SlvHk+cji1Bgz4CZC2/r3/FVCRTDftIfhS7PA28ovT1yXfCOIy3H+ OuQH6WpH4N88Zq7+ACn9JdKvDIGMAf7NpLhgkLCfvHuC/GqoTRptgC/Z7 66z5RD18eGEh7hX8Pmphytwt64DXxQg9y3WIQuGG86F2bpcSRRm92Ault Wjl26qJBL6bOMLP2gWP39niV3BJKc6fBnoxAribcqCx8TIW8aOCikR/qQ RfdN7ZAsTSeV9nzIS+H3yqJPOdptk/UE0Tds4XUSv8rcCd3wEyxUF01HI Q==; X-CSE-ConnectionGUID: 7ih66tTDSX+CpSvQ+amhwQ== X-CSE-MsgGUID: dvputes3Tl+OKHDSrV3NCg== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="38053848" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="38053848" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:20 -0700 X-CSE-ConnectionGUID: 7rezB12YQdK8/bceqqCb9g== X-CSE-MsgGUID: AzMpFrj2SMmL4LM8pUpD3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33425246" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:18 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 05/10] drm/i915/display: add platform descriptors Date: Wed, 22 May 2024 20:33:42 +0300 Message-Id: <45425c155608403efc149d4a022c0b443aa71200.1716399081.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We'll need to start identifying the platforms independently in display code in order to break free from the i915 and xe IS_() macros. This is fairly straightforward, as we already identify most platforms by PCI ID in display probe anyway. As the first step, add platform descriptors with pointers to display info. We'll have more platforms than display info, so minimize duplication: - Add separate skl/kbl/cfl/cml descriptors while they share the display info. - Add separate jsl/ehl descriptors while they share the display info. Identify ADL-P (and derivatives) and DG2 descriptors by their names even though their display info is Xe LPD or HPD. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- .../drm/i915/display/intel_display_device.c | 558 ++++++++++-------- 1 file changed, 326 insertions(+), 232 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 56b27546d1b3..d1e03437abb3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -20,6 +20,10 @@ __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); +struct platform_desc { + const struct intel_display_device_info *info; +}; + static const struct intel_display_device_info no_display = {}; #define PIPE_A_OFFSET 0x70000 @@ -200,33 +204,41 @@ static const struct intel_display_device_info no_display = {}; .__runtime_defaults.pipe_mask = BIT(PIPE_A), \ .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) -static const struct intel_display_device_info i830_display = { - I830_DISPLAY, +static const struct platform_desc i830_desc = { + .info = &(const struct intel_display_device_info) { + I830_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */ + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */ + }, }; -static const struct intel_display_device_info i845_display = { - I845_DISPLAY, +static const struct platform_desc i845_desc = { + .info = &(const struct intel_display_device_info) { + I845_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ + }, }; -static const struct intel_display_device_info i85x_display = { - I830_DISPLAY, +static const struct platform_desc i85x_desc = { + .info = &(const struct intel_display_device_info) { + I830_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info i865g_display = { - I845_DISPLAY, +static const struct platform_desc i865g_desc = { + .info = &(const struct intel_display_device_info) { + I845_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -#define GEN3_DISPLAY \ +#define GEN3_DISPLAY \ .has_gmch = 1, \ .has_overlay = 1, \ I9XX_PIPE_OFFSETS, \ @@ -238,52 +250,64 @@ static const struct intel_display_device_info i865g_display = { BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */ -static const struct intel_display_device_info i915g_display = { - GEN3_DISPLAY, - I845_COLORS, - .cursor_needs_physical = 1, - .overlay_needs_physical = 1, +static const struct platform_desc i915g_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I845_COLORS, + .cursor_needs_physical = 1, + .overlay_needs_physical = 1, + }, }; -static const struct intel_display_device_info i915gm_display = { - GEN3_DISPLAY, - I9XX_COLORS, - .cursor_needs_physical = 1, - .overlay_needs_physical = 1, - .supports_tv = 1, +static const struct platform_desc i915gm_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I9XX_COLORS, + .cursor_needs_physical = 1, + .overlay_needs_physical = 1, + .supports_tv = 1, - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info i945g_display = { - GEN3_DISPLAY, - I845_COLORS, - .has_hotplug = 1, - .cursor_needs_physical = 1, - .overlay_needs_physical = 1, +static const struct platform_desc i945g_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I845_COLORS, + .has_hotplug = 1, + .cursor_needs_physical = 1, + .overlay_needs_physical = 1, + }, }; -static const struct intel_display_device_info i945gm_display = { - GEN3_DISPLAY, - I9XX_COLORS, - .has_hotplug = 1, - .cursor_needs_physical = 1, - .overlay_needs_physical = 1, - .supports_tv = 1, - - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), +static const struct platform_desc i945gm_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I9XX_COLORS, + .has_hotplug = 1, + .cursor_needs_physical = 1, + .overlay_needs_physical = 1, + .supports_tv = 1, + + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info g33_display = { - GEN3_DISPLAY, - I845_COLORS, - .has_hotplug = 1, +static const struct platform_desc g33_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I845_COLORS, + .has_hotplug = 1, + }, }; -static const struct intel_display_device_info pnv_display = { - GEN3_DISPLAY, - I9XX_COLORS, - .has_hotplug = 1, +static const struct platform_desc pnv_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I9XX_COLORS, + .has_hotplug = 1, + }, }; #define GEN4_DISPLAY \ @@ -298,34 +322,42 @@ static const struct intel_display_device_info pnv_display = { .__runtime_defaults.cpu_transcoder_mask = \ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) -static const struct intel_display_device_info i965g_display = { - GEN4_DISPLAY, - .has_overlay = 1, +static const struct platform_desc i965g_desc = { + .info = &(const struct intel_display_device_info) { + GEN4_DISPLAY, + .has_overlay = 1, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ + }, }; -static const struct intel_display_device_info i965gm_display = { - GEN4_DISPLAY, - .has_overlay = 1, - .supports_tv = 1, +static const struct platform_desc i965gm_desc = { + .info = &(const struct intel_display_device_info) { + GEN4_DISPLAY, + .has_overlay = 1, + .supports_tv = 1, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info g45_display = { - GEN4_DISPLAY, +static const struct platform_desc g45_desc = { + .info = &(const struct intel_display_device_info) { + GEN4_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ + }, }; -static const struct intel_display_device_info gm45_display = { - GEN4_DISPLAY, - .supports_tv = 1, +static const struct platform_desc gm45_desc = { + .info = &(const struct intel_display_device_info) { + GEN4_DISPLAY, + .supports_tv = 1, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; #define ILK_DISPLAY \ @@ -340,112 +372,128 @@ static const struct intel_display_device_info gm45_display = { BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ -static const struct intel_display_device_info ilk_d_display = { - ILK_DISPLAY, +static const struct platform_desc ilk_d_desc = { + .info = &(const struct intel_display_device_info) { + ILK_DISPLAY, + }, }; -static const struct intel_display_device_info ilk_m_display = { - ILK_DISPLAY, +static const struct platform_desc ilk_m_desc = { + .info = &(const struct intel_display_device_info) { + ILK_DISPLAY, - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info snb_display = { - .has_hotplug = 1, - I9XX_PIPE_OFFSETS, - I9XX_CURSOR_OFFSETS, - ILK_COLORS, +static const struct platform_desc snb_desc = { + .info = &(const struct intel_display_device_info) { + .has_hotplug = 1, + I9XX_PIPE_OFFSETS, + I9XX_CURSOR_OFFSETS, + ILK_COLORS, - .__runtime_defaults.ip.ver = 6, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), - .__runtime_defaults.cpu_transcoder_mask = + .__runtime_defaults.ip.ver = 6, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info ivb_display = { - .has_hotplug = 1, - IVB_PIPE_OFFSETS, - IVB_CURSOR_OFFSETS, - IVB_COLORS, +static const struct platform_desc ivb_desc = { + .info = &(const struct intel_display_device_info) { + .has_hotplug = 1, + IVB_PIPE_OFFSETS, + IVB_CURSOR_OFFSETS, + IVB_COLORS, - .__runtime_defaults.ip.ver = 7, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = + .__runtime_defaults.ip.ver = 7, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info vlv_display = { - .has_gmch = 1, - .has_hotplug = 1, - .mmio_offset = VLV_DISPLAY_BASE, - I9XX_PIPE_OFFSETS, - I9XX_CURSOR_OFFSETS, - I9XX_COLORS, - - .__runtime_defaults.ip.ver = 7, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), - .__runtime_defaults.cpu_transcoder_mask = +static const struct platform_desc vlv_desc = { + .info = &(const struct intel_display_device_info) { + .has_gmch = 1, + .has_hotplug = 1, + .mmio_offset = VLV_DISPLAY_BASE, + I9XX_PIPE_OFFSETS, + I9XX_CURSOR_OFFSETS, + I9XX_COLORS, + + .__runtime_defaults.ip.ver = 7, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */ + }, }; -static const struct intel_display_device_info hsw_display = { - .has_ddi = 1, - .has_dp_mst = 1, - .has_fpga_dbg = 1, - .has_hotplug = 1, - .has_psr = 1, - .has_psr_hw_tracking = 1, - HSW_PIPE_OFFSETS, - IVB_CURSOR_OFFSETS, - IVB_COLORS, - - .__runtime_defaults.ip.ver = 7, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = +static const struct platform_desc hsw_desc = { + .info = &(const struct intel_display_device_info) { + .has_ddi = 1, + .has_dp_mst = 1, + .has_fpga_dbg = 1, + .has_hotplug = 1, + .has_psr = 1, + .has_psr_hw_tracking = 1, + HSW_PIPE_OFFSETS, + IVB_CURSOR_OFFSETS, + IVB_COLORS, + + .__runtime_defaults.ip.ver = 7, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info bdw_display = { - .has_ddi = 1, - .has_dp_mst = 1, - .has_fpga_dbg = 1, - .has_hotplug = 1, - .has_psr = 1, - .has_psr_hw_tracking = 1, - HSW_PIPE_OFFSETS, - IVB_CURSOR_OFFSETS, - IVB_COLORS, - - .__runtime_defaults.ip.ver = 8, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = +static const struct platform_desc bdw_desc = { + .info = &(const struct intel_display_device_info) { + .has_ddi = 1, + .has_dp_mst = 1, + .has_fpga_dbg = 1, + .has_hotplug = 1, + .has_psr = 1, + .has_psr_hw_tracking = 1, + HSW_PIPE_OFFSETS, + IVB_CURSOR_OFFSETS, + IVB_COLORS, + + .__runtime_defaults.ip.ver = 8, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info chv_display = { - .has_hotplug = 1, - .has_gmch = 1, - .mmio_offset = VLV_DISPLAY_BASE, - CHV_PIPE_OFFSETS, - CHV_CURSOR_OFFSETS, - CHV_COLORS, - - .__runtime_defaults.ip.ver = 8, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = +static const struct platform_desc chv_desc = { + .info = &(const struct intel_display_device_info) { + .has_hotplug = 1, + .has_gmch = 1, + .mmio_offset = VLV_DISPLAY_BASE, + CHV_PIPE_OFFSETS, + CHV_CURSOR_OFFSETS, + CHV_COLORS, + + .__runtime_defaults.ip.ver = 8, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */ + }, }; static const struct intel_display_device_info skl_display = { @@ -467,13 +515,29 @@ static const struct intel_display_device_info skl_display = { .__runtime_defaults.has_hdcp = 1, .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), .__runtime_defaults.cpu_transcoder_mask = - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), }; -#define GEN9_LP_DISPLAY \ +static const struct platform_desc skl_desc = { + .info = &skl_display, +}; + +static const struct platform_desc kbl_desc = { + .info = &skl_display, +}; + +static const struct platform_desc cfl_desc = { + .info = &skl_display, +}; + +static const struct platform_desc cml_desc = { + .info = &skl_display, +}; + +#define GEN9_LP_DISPLAY \ .dbuf.slice_mask = BIT(DBUF_S1), \ .has_dp_mst = 1, \ .has_ddi = 1, \ @@ -496,19 +560,23 @@ static const struct intel_display_device_info skl_display = { BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) -static const struct intel_display_device_info bxt_display = { - GEN9_LP_DISPLAY, - .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ +static const struct platform_desc bxt_desc = { + .info = &(const struct intel_display_device_info) { + GEN9_LP_DISPLAY, + .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ - .__runtime_defaults.ip.ver = 9, + .__runtime_defaults.ip.ver = 9, + }, }; -static const struct intel_display_device_info glk_display = { - GEN9_LP_DISPLAY, - .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ - GLK_COLORS, +static const struct platform_desc glk_desc = { + .info = &(const struct intel_display_device_info) { + GEN9_LP_DISPLAY, + .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ + GLK_COLORS, - .__runtime_defaults.ip.ver = 10, + .__runtime_defaults.ip.ver = 10, + }, }; #define ICL_DISPLAY \ @@ -552,10 +620,12 @@ static const struct intel_display_device_info glk_display = { BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) -static const struct intel_display_device_info icl_display = { - ICL_DISPLAY, +static const struct platform_desc icl_desc = { + .info = &(const struct intel_display_device_info) { + ICL_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), + }, }; static const struct intel_display_device_info jsl_ehl_display = { @@ -564,6 +634,14 @@ static const struct intel_display_device_info jsl_ehl_display = { .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), }; +static const struct platform_desc jsl_desc = { + .info = &jsl_ehl_display, +}; + +static const struct platform_desc ehl_desc = { + .info = &jsl_ehl_display, +}; + #define XE_D_DISPLAY \ .abox_mask = GENMASK(2, 1), \ .dbuf.size = 2048, \ @@ -607,44 +685,52 @@ static const struct intel_display_device_info jsl_ehl_display = { BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) -static const struct intel_display_device_info tgl_display = { - XE_D_DISPLAY, +static const struct platform_desc tgl_desc = { + .info = &(const struct intel_display_device_info) { + XE_D_DISPLAY, - /* - * FIXME DDI C/combo PHY C missing due to combo PHY - * code making a mess on SKUs where the PHY is missing. - */ - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | + /* + * FIXME DDI C/combo PHY C missing due to combo PHY + * code making a mess on SKUs where the PHY is missing. + */ + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6), + }, }; -static const struct intel_display_device_info dg1_display = { - XE_D_DISPLAY, +static const struct platform_desc dg1_desc = { + .info = &(const struct intel_display_device_info) { + XE_D_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2), + }, }; -static const struct intel_display_device_info rkl_display = { - XE_D_DISPLAY, - .abox_mask = BIT(0), - .has_hti = 1, - .has_psr_hw_tracking = 0, +static const struct platform_desc rkl_desc = { + .info = &(const struct intel_display_device_info) { + XE_D_DISPLAY, + .abox_mask = BIT(0), + .has_hti = 1, + .has_psr_hw_tracking = 0, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2), + }, }; -static const struct intel_display_device_info adl_s_display = { - XE_D_DISPLAY, - .has_hti = 1, - .has_psr_hw_tracking = 0, +static const struct platform_desc adl_s_desc = { + .info = &(const struct intel_display_device_info) { + XE_D_DISPLAY, + .has_hti = 1, + .has_psr_hw_tracking = 0, - .__runtime_defaults.port_mask = BIT(PORT_A) | + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), + }, }; #define XE_LPD_FEATURES \ @@ -703,6 +789,10 @@ static const struct intel_display_device_info xe_lpd_display = { BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), }; +static const struct platform_desc adl_p_desc = { + .info = &xe_lpd_display, +}; + static const struct intel_display_device_info xe_hpd_display = { XE_LPD_FEATURES, .has_cdclk_squash = 1, @@ -714,6 +804,10 @@ static const struct intel_display_device_info xe_hpd_display = { BIT(PORT_TC1), }; +static const struct platform_desc dg2_desc = { + .info = &xe_hpd_display, +}; + #define XE_LPDP_FEATURES \ .abox_mask = GENMASK(1, 0), \ .color = { \ @@ -795,54 +889,54 @@ static bool has_no_display(struct pci_dev *pdev) return pci_match_id(ids, pdev); } -#define INTEL_DISPLAY_DEVICE(_id, _info) { .devid = (_id), .info = (_info) } +#define INTEL_DISPLAY_DEVICE(_id, _desc) { .devid = (_id), .desc = (_desc) } static const struct { u32 devid; - const struct intel_display_device_info *info; + const struct platform_desc *desc; } intel_display_ids[] = { - INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_display), - INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_display), - INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_display), - INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_display), - INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_display), - INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_display), - INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_display), - INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_display), - INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_display), - INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_display), - INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_display), - INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_display), - INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_display), - INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_display), - INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_display), - INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_display), - INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_display), - INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_display), - INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_display), - INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_display), - INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_display), - INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_display), - INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_display), - INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_display), - INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_display), - INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display), - INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display), - INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_display), - INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_display), - INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_display), - INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display), - INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display), - INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), - INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), - INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), - INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), - INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &xe_hpd_display), + INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_desc), + INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_desc), + INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_desc), + INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_desc), + INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_desc), + INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_desc), + INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_desc), + INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_desc), + INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_desc), + INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_desc), + INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_desc), + INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_desc), + INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_desc), + INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_desc), + INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_desc), + INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_desc), + INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_desc), + INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_desc), + INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_desc), + INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_desc), + INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_desc), + INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_desc), + INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_desc), + INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_desc), + INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_desc), + INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &kbl_desc), + INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), + INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), + INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &cml_desc), + INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_desc), + INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &ehl_desc), + INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_desc), + INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_desc), + INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_desc), + INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_desc), + INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), + INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), + INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), + INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), + INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), + INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), + INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc), /* * Do not add any GMD_ID-based platforms to this list. They will @@ -909,7 +1003,7 @@ probe_display(struct drm_i915_private *i915) for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { if (intel_display_ids[i].devid == pdev->device) - return intel_display_ids[i].info; + return intel_display_ids[i].desc->info; } drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", From patchwork Wed May 22 17:33:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63365C25B7A for ; Wed, 22 May 2024 17:34:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FD4C10E265; Wed, 22 May 2024 17:34:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ULRuIyN8"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE56E10E1C7; Wed, 22 May 2024 17:34:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399266; x=1747935266; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d9SGfLjftlPKuEdb0upzIfHACrM4n0eC3taiiBy4sjU=; b=ULRuIyN8IBlego8Dxypbz7E1eIe1Sg6DKHvwqOey8S3ipsqIPtOCPhjC QmvPX/KFVuZCot6Dk6ef/ucCnArOZYZ9OeaqZvnPhZNyHkWTuXTK0WKlC ip2qt8S714ImwLAhoLmGEng1bLunTLfV56RTSofE+NfXnWfeB2UlZO0k7 ETfjCLLlN3keEpd5Xil0nCfqwxj+FUXsLaaDaxdczXmnlX1A/ppJaNrgz 1K25UV8dqxBncMTM9WaPkAlOJK7QtjhaOQLXFkuhNTwASQGDsl4RSm+vj yIkqo/MfjlmWWu5m1ReoQPXYMwBlajonMK1a0ipOf2fYg0rlwOdH54LEa Q==; X-CSE-ConnectionGUID: 8d6NoAzgT2WVivezjvTytw== X-CSE-MsgGUID: td0Ljm2kTcajQdpfQYPi8g== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="12611425" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="12611425" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:25 -0700 X-CSE-ConnectionGUID: smTK43ALSOmVdzk+3QZzHw== X-CSE-MsgGUID: ux07AAm5SRCVaefa21fSWg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33474965" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:23 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 06/10] drm/i915: add LNL PCI IDs Date: Wed, 22 May 2024 20:33:43 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Although not supported by i915 core, the display code needs to know the LNL PCI IDs. Long term, xe and i915 should probably share the file defining PCI IDs. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- include/drm/i915_pciids.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 3e39d644ebaa..7ae7ee11ef38 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -783,4 +783,10 @@ MACRO__(0x7DD1, ## __VA_ARGS__), \ MACRO__(0x7DD5, ## __VA_ARGS__) +/* LNL */ +#define INTEL_LNL_IDS(MACRO__, ...) \ + MACRO__(0x6420, ## __VA_ARGS__), \ + MACRO__(0x64A0, ## __VA_ARGS__), \ + MACRO__(0x64B0, ## __VA_ARGS__) + #endif /* _I915_PCIIDS_H */ From patchwork Wed May 22 17:33:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0981C41513 for ; Wed, 22 May 2024 17:34:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EDDCB10E3A1; Wed, 22 May 2024 17:34:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="N8euzcq1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 16EF310E1C7; Wed, 22 May 2024 17:34:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399271; x=1747935271; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RHnFvv0CK6gRd+D5iWu/Ot1vTgYVq94Y5H7BGx3wr4k=; b=N8euzcq1zSOfRWuHcsZY6HTqkMu3LqezYD9WxgOExaWvrZetMpPupjdP R4D7lF5azD0EknYbchMd73nwvQXn3POSHm4gcDX2fdBPOcKzzItnvbBug 28zZuZ7yfnGlQ/8/AY9WrnZk8jcpjcIZLDcFYX1Euo5Uv+7V9nDioNXdU WoLPf7AR4I6f5AXh+ZJRxdg+34AFFYHovpVo5IByU8HZi2Z+f35Lvbp6V yejemOdboxg4K8OCZD1IzHVEb5cD9pqqnM8v896Kfh8Tk677mOmPEKHIY 394Hi0qaP3qqHO35KQ8LW8AO7jPowIRr4DWu9grmQXtF5El0WTYX8mURD Q==; X-CSE-ConnectionGUID: eRal80QoQPiRK0xo8soTNQ== X-CSE-MsgGUID: ujyCP71TRMOF/UHrirhOOw== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="12611432" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="12611432" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:31 -0700 X-CSE-ConnectionGUID: fPdbXEmjTgC0Oj0d52HacQ== X-CSE-MsgGUID: pL3aChGFT5G+t0iQKiuGhg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33474986" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:28 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 07/10] drm/i915/display: change display probe to identify GMD ID based platforms Date: Wed, 22 May 2024 20:33:44 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We'll need to identify all platforms, including the ones that have display defined by GMD ID. Add MTL and LNL. Their display info will still be probed via GMD ID. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- .../drm/i915/display/intel_display_device.c | 44 +++++++++++-------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index d1e03437abb3..416853ed50df 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -21,7 +21,7 @@ __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); struct platform_desc { - const struct intel_display_device_info *info; + const struct intel_display_device_info *info; /* NULL for GMD ID */ }; static const struct intel_display_device_info no_display = {}; @@ -871,6 +871,17 @@ static const struct intel_display_device_info xe2_hpd_display = { BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), }; +/* + * Do not initialize the .info member of the platform desc for GMD ID based + * platforms. Their display will be probed automatically based on the IP version + * reported by the hardware. + */ +static const struct platform_desc mtl_desc = { +}; + +static const struct platform_desc lnl_desc = { +}; + __diag_pop(); /* @@ -937,12 +948,8 @@ static const struct { INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc), - - /* - * Do not add any GMD_ID-based platforms to this list. They will - * be probed automatically based on the IP version reported by - * the hardware. - */ + INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc), + INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc), }; static const struct { @@ -995,20 +1002,15 @@ probe_gmdid_display(struct drm_i915_private *i915, struct intel_display_ip_ver * return NULL; } -static const struct intel_display_device_info * -probe_display(struct drm_i915_private *i915) +static const struct platform_desc *find_platform_desc(struct pci_dev *pdev) { - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); int i; for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { if (intel_display_ids[i].devid == pdev->device) - return intel_display_ids[i].desc->info; + return intel_display_ids[i].desc; } - drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", - pdev->device); - return NULL; } @@ -1017,6 +1019,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) struct pci_dev *pdev = to_pci_dev(i915->drm.dev); const struct intel_display_device_info *info; struct intel_display_ip_ver ip_ver = {}; + const struct platform_desc *desc; /* Add drm device backpointer as early as possible. */ i915->display.drm = &i915->drm; @@ -1028,12 +1031,17 @@ void intel_display_device_probe(struct drm_i915_private *i915) goto no_display; } - if (HAS_GMD_ID(i915)) - info = probe_gmdid_display(i915, &ip_ver); - else - info = probe_display(i915); + desc = find_platform_desc(pdev); + if (!desc) { + drm_dbg_kms(&i915->drm, "Unknown device ID %04x; disabling display.\n", + pdev->device); + goto no_display; + } + info = desc->info; if (!info) + info = probe_gmdid_display(i915, &ip_ver); + if (!info) goto no_display; DISPLAY_INFO(i915) = info; From patchwork Wed May 22 17:33:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6570BC25B78 for ; Wed, 22 May 2024 17:34:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E6E510E34A; Wed, 22 May 2024 17:34:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bBeTO/5u"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id EDBFC10E1C7; Wed, 22 May 2024 17:34:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399276; x=1747935276; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EKW2u2ipwQd14XoBxNJ3aKNtAp1YaRFfyIXbs1dWBuk=; b=bBeTO/5uZiKrprH/1cXJE37fmhnSVXsEx/kwdZWGfAUdf+y9Fjiff6Fy wGWD9zBAlS/rOGWIv/6sXB+VMYeIjMvvD1YDuqc9XE0LbMWERqnts/iJr PO3BAg3JEwtG62g1oKDzxYnW6o1GOxf0gnCg6cADgZ/mE3C/ofQbc/6q1 4w8RO5ZCprwKqp6ODrd8D1Bk4/pYORLE2eob+M9R/apEJ+L1AtuwBS/wW W8dieHKe8Lc20s2rNAxG1FIoB050iB3Eu9CDTVjvKsWdgJrwqBGjX4AW2 sCz53CUalvfjA7JhUqEfM34q33QPBKergVJLLgH8OBFMF7dBgdzwwxBnw Q==; X-CSE-ConnectionGUID: g8F/a6jLTd+IX3waGnHLGA== X-CSE-MsgGUID: zybbRjLPSyO9xUzx3FztZA== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="12611449" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="12611449" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:35 -0700 X-CSE-ConnectionGUID: TLOVw+noRCSONxd2wHEQwQ== X-CSE-MsgGUID: JsBqndUDQBOVBp47wACvHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33475015" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:33 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 08/10] drm/i915/display: identify platforms with enum and name Date: Wed, 22 May 2024 20:33:45 +0300 Message-Id: <5dec70931217cd93e3ef34f7a57f949f6683f048.1716399081.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add enum intel_display_platform and add that and name to all platform descriptors. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- .../drm/i915/display/intel_display_device.c | 48 +++++++++++++++ .../drm/i915/display/intel_display_device.h | 58 +++++++++++++++++++ 2 files changed, 106 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 416853ed50df..7c5cead1fe15 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -21,9 +21,15 @@ __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); struct platform_desc { + enum intel_display_platform platform; + const char *name; const struct intel_display_device_info *info; /* NULL for GMD ID */ }; +#define PLATFORM(_platform) \ + .platform = (INTEL_DISPLAY_##_platform), \ + .name = #_platform + static const struct intel_display_device_info no_display = {}; #define PIPE_A_OFFSET 0x70000 @@ -205,6 +211,7 @@ static const struct intel_display_device_info no_display = {}; .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) static const struct platform_desc i830_desc = { + PLATFORM(I830), .info = &(const struct intel_display_device_info) { I830_DISPLAY, @@ -213,6 +220,7 @@ static const struct platform_desc i830_desc = { }; static const struct platform_desc i845_desc = { + PLATFORM(I845G), .info = &(const struct intel_display_device_info) { I845_DISPLAY, @@ -221,6 +229,7 @@ static const struct platform_desc i845_desc = { }; static const struct platform_desc i85x_desc = { + PLATFORM(I85X), .info = &(const struct intel_display_device_info) { I830_DISPLAY, @@ -230,6 +239,7 @@ static const struct platform_desc i85x_desc = { }; static const struct platform_desc i865g_desc = { + PLATFORM(I865G), .info = &(const struct intel_display_device_info) { I845_DISPLAY, @@ -251,6 +261,7 @@ static const struct platform_desc i865g_desc = { .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */ static const struct platform_desc i915g_desc = { + PLATFORM(I915G), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I845_COLORS, @@ -260,6 +271,7 @@ static const struct platform_desc i915g_desc = { }; static const struct platform_desc i915gm_desc = { + PLATFORM(I915GM), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I9XX_COLORS, @@ -272,6 +284,7 @@ static const struct platform_desc i915gm_desc = { }; static const struct platform_desc i945g_desc = { + PLATFORM(I945G), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I845_COLORS, @@ -282,6 +295,7 @@ static const struct platform_desc i945g_desc = { }; static const struct platform_desc i945gm_desc = { + PLATFORM(I915GM), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I9XX_COLORS, @@ -295,6 +309,7 @@ static const struct platform_desc i945gm_desc = { }; static const struct platform_desc g33_desc = { + PLATFORM(G33), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I845_COLORS, @@ -303,6 +318,7 @@ static const struct platform_desc g33_desc = { }; static const struct platform_desc pnv_desc = { + PLATFORM(PINEVIEW), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I9XX_COLORS, @@ -323,6 +339,7 @@ static const struct platform_desc pnv_desc = { BIT(TRANSCODER_A) | BIT(TRANSCODER_B) static const struct platform_desc i965g_desc = { + PLATFORM(I965G), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, .has_overlay = 1, @@ -332,6 +349,7 @@ static const struct platform_desc i965g_desc = { }; static const struct platform_desc i965gm_desc = { + PLATFORM(I965GM), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, .has_overlay = 1, @@ -343,6 +361,7 @@ static const struct platform_desc i965gm_desc = { }; static const struct platform_desc g45_desc = { + PLATFORM(G45), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, @@ -351,6 +370,7 @@ static const struct platform_desc g45_desc = { }; static const struct platform_desc gm45_desc = { + PLATFORM(GM45), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, .supports_tv = 1, @@ -373,12 +393,14 @@ static const struct platform_desc gm45_desc = { .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ static const struct platform_desc ilk_d_desc = { + PLATFORM(IRONLAKE), .info = &(const struct intel_display_device_info) { ILK_DISPLAY, }, }; static const struct platform_desc ilk_m_desc = { + PLATFORM(IRONLAKE), .info = &(const struct intel_display_device_info) { ILK_DISPLAY, @@ -387,6 +409,7 @@ static const struct platform_desc ilk_m_desc = { }; static const struct platform_desc snb_desc = { + PLATFORM(SANDYBRIDGE), .info = &(const struct intel_display_device_info) { .has_hotplug = 1, I9XX_PIPE_OFFSETS, @@ -403,6 +426,7 @@ static const struct platform_desc snb_desc = { }; static const struct platform_desc ivb_desc = { + PLATFORM(IVYBRIDGE), .info = &(const struct intel_display_device_info) { .has_hotplug = 1, IVB_PIPE_OFFSETS, @@ -419,6 +443,7 @@ static const struct platform_desc ivb_desc = { }; static const struct platform_desc vlv_desc = { + PLATFORM(VALLEYVIEW), .info = &(const struct intel_display_device_info) { .has_gmch = 1, .has_hotplug = 1, @@ -436,6 +461,7 @@ static const struct platform_desc vlv_desc = { }; static const struct platform_desc hsw_desc = { + PLATFORM(HASWELL), .info = &(const struct intel_display_device_info) { .has_ddi = 1, .has_dp_mst = 1, @@ -458,6 +484,7 @@ static const struct platform_desc hsw_desc = { }; static const struct platform_desc bdw_desc = { + PLATFORM(BROADWELL), .info = &(const struct intel_display_device_info) { .has_ddi = 1, .has_dp_mst = 1, @@ -480,6 +507,7 @@ static const struct platform_desc bdw_desc = { }; static const struct platform_desc chv_desc = { + PLATFORM(CHERRYVIEW), .info = &(const struct intel_display_device_info) { .has_hotplug = 1, .has_gmch = 1, @@ -522,18 +550,22 @@ static const struct intel_display_device_info skl_display = { }; static const struct platform_desc skl_desc = { + PLATFORM(SKYLAKE), .info = &skl_display, }; static const struct platform_desc kbl_desc = { + PLATFORM(KABYLAKE), .info = &skl_display, }; static const struct platform_desc cfl_desc = { + PLATFORM(COFFEELAKE), .info = &skl_display, }; static const struct platform_desc cml_desc = { + PLATFORM(COMETLAKE), .info = &skl_display, }; @@ -561,6 +593,7 @@ static const struct platform_desc cml_desc = { .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) static const struct platform_desc bxt_desc = { + PLATFORM(BROXTON), .info = &(const struct intel_display_device_info) { GEN9_LP_DISPLAY, .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ @@ -570,6 +603,7 @@ static const struct platform_desc bxt_desc = { }; static const struct platform_desc glk_desc = { + PLATFORM(GEMINILAKE), .info = &(const struct intel_display_device_info) { GEN9_LP_DISPLAY, .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ @@ -621,6 +655,7 @@ static const struct platform_desc glk_desc = { .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) static const struct platform_desc icl_desc = { + PLATFORM(ICELAKE), .info = &(const struct intel_display_device_info) { ICL_DISPLAY, @@ -635,10 +670,12 @@ static const struct intel_display_device_info jsl_ehl_display = { }; static const struct platform_desc jsl_desc = { + PLATFORM(JASPERLAKE), .info = &jsl_ehl_display, }; static const struct platform_desc ehl_desc = { + PLATFORM(ELKHARTLAKE), .info = &jsl_ehl_display, }; @@ -686,6 +723,7 @@ static const struct platform_desc ehl_desc = { .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) static const struct platform_desc tgl_desc = { + PLATFORM(TIGERLAKE), .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, @@ -699,6 +737,7 @@ static const struct platform_desc tgl_desc = { }; static const struct platform_desc dg1_desc = { + PLATFORM(DG1), .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, @@ -708,6 +747,7 @@ static const struct platform_desc dg1_desc = { }; static const struct platform_desc rkl_desc = { + PLATFORM(ROCKETLAKE), .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, .abox_mask = BIT(0), @@ -723,6 +763,7 @@ static const struct platform_desc rkl_desc = { }; static const struct platform_desc adl_s_desc = { + PLATFORM(ALDERLAKE_S), .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, .has_hti = 1, @@ -790,6 +831,7 @@ static const struct intel_display_device_info xe_lpd_display = { }; static const struct platform_desc adl_p_desc = { + PLATFORM(ALDERLAKE_P), .info = &xe_lpd_display, }; @@ -805,6 +847,7 @@ static const struct intel_display_device_info xe_hpd_display = { }; static const struct platform_desc dg2_desc = { + PLATFORM(DG2), .info = &xe_hpd_display, }; @@ -877,9 +920,11 @@ static const struct intel_display_device_info xe2_hpd_display = { * reported by the hardware. */ static const struct platform_desc mtl_desc = { + PLATFORM(METEORLAKE), }; static const struct platform_desc lnl_desc = { + PLATFORM(LUNARLAKE), }; __diag_pop(); @@ -1050,6 +1095,9 @@ void intel_display_device_probe(struct drm_i915_private *i915) &DISPLAY_INFO(i915)->__runtime_defaults, sizeof(*DISPLAY_RUNTIME_INFO(i915))); + drm_WARN_ON(&i915->drm, !desc->platform || !desc->name); + DISPLAY_RUNTIME_INFO(i915)->platform = desc->platform; + if (ip_ver.ver || ip_ver.rel || ip_ver.step) DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index fd2d03bfe8a6..8accd680a61e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -14,6 +14,62 @@ struct drm_i915_private; struct drm_printer; +/* Keep in gen based order, and chronological order within a gen */ +enum intel_display_platform { + INTEL_DISPLAY_PLATFORM_UNINITIALIZED = 0, + /* Display ver 2 */ + INTEL_DISPLAY_I830, + INTEL_DISPLAY_I845G, + INTEL_DISPLAY_I85X, + INTEL_DISPLAY_I865G, + /* Display ver 3 */ + INTEL_DISPLAY_I915G, + INTEL_DISPLAY_I915GM, + INTEL_DISPLAY_I945G, + INTEL_DISPLAY_I945GM, + INTEL_DISPLAY_G33, + INTEL_DISPLAY_PINEVIEW, + /* Display ver 4 */ + INTEL_DISPLAY_I965G, + INTEL_DISPLAY_I965GM, + INTEL_DISPLAY_G45, + INTEL_DISPLAY_GM45, + /* Display ver 5 */ + INTEL_DISPLAY_IRONLAKE, + /* Display ver 6 */ + INTEL_DISPLAY_SANDYBRIDGE, + /* Display ver 7 */ + INTEL_DISPLAY_IVYBRIDGE, + INTEL_DISPLAY_VALLEYVIEW, + INTEL_DISPLAY_HASWELL, + /* Display ver 8 */ + INTEL_DISPLAY_BROADWELL, + INTEL_DISPLAY_CHERRYVIEW, + /* Display ver 9 */ + INTEL_DISPLAY_SKYLAKE, + INTEL_DISPLAY_BROXTON, + INTEL_DISPLAY_KABYLAKE, + INTEL_DISPLAY_GEMINILAKE, + INTEL_DISPLAY_COFFEELAKE, + INTEL_DISPLAY_COMETLAKE, + /* Display ver 11 */ + INTEL_DISPLAY_ICELAKE, + INTEL_DISPLAY_JASPERLAKE, + INTEL_DISPLAY_ELKHARTLAKE, + /* Display ver 12 */ + INTEL_DISPLAY_TIGERLAKE, + INTEL_DISPLAY_ROCKETLAKE, + INTEL_DISPLAY_DG1, + INTEL_DISPLAY_ALDERLAKE_S, + /* Display ver 13 */ + INTEL_DISPLAY_ALDERLAKE_P, + INTEL_DISPLAY_DG2, + /* Display ver 14 (based on GMD ID) */ + INTEL_DISPLAY_METEORLAKE, + /* Display ver 20 (based on GMD ID) */ + INTEL_DISPLAY_LUNARLAKE, +}; + #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ @@ -111,6 +167,8 @@ struct drm_printer; (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) struct intel_display_runtime_info { + enum intel_display_platform platform; + struct intel_display_ip_ver { u16 ver; u16 rel; From patchwork Wed May 22 17:33:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44E32C25B78 for ; Wed, 22 May 2024 17:34:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 85CAE10E31A; Wed, 22 May 2024 17:34:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="D7OMCJX1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7803910E427; Wed, 22 May 2024 17:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399280; x=1747935280; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0IR2H8PeaFBYIIyBMbQx4UaMpDaA7ICbLIRO78BwJLk=; b=D7OMCJX13FMFCHMg695wU9dsutFobDfJ7r6brXvtLi0QfBJeOU0cEIqJ GNZHkPyUjmcGCg7px6pjg4Kz8WhbdRgKaTegupxEBLGgVstvrJFJaPOVB F0MDKgD3lrz8o5lUmyIddj3zkm6OTinIiU2g1gL+l0vbcRgWEza7Xkzg7 dX/TGhkJg/f941VSepGTXvjnnC0tG0FMk8zMdf0ckb6R25Ftb7jPNjxhA LFZxTMReL38o9dcvm+zLsRStpMPJj9bV3wKhCh94o7KSbV7gwdDTdnt5i OJr6XfI3IGCTo1RBTOnrqlrDscjLSPtQA24W5NI/bxXLU47zGj2/YzvWD g==; X-CSE-ConnectionGUID: h91l0Mt0SGaseqfXC5jQwg== X-CSE-MsgGUID: TBZSpUObRlK8V9JWRFYITA== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="12611453" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="12611453" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:40 -0700 X-CSE-ConnectionGUID: 5PQGM2v+Tz2G/28VVVwAmw== X-CSE-MsgGUID: mSzLAbToTfK95UZcXdZyWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33475046" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:38 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 09/10] drm/i915/display: add support for subplatforms Date: Wed, 22 May 2024 20:33:46 +0300 Message-Id: <8c04e32648395c0b745bc31a1edd4ef6f574bb70.1716399081.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add support for subplatforms. This is similar to what the xe driver is doing. The subplatform is an enum and it's exclusive, i.e. only one subplatform can match, and it completely identifies the platform and subplatform. This is different from i915 core, and is notable in the handling of ULT/ULX and RPL/RPL-U. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- .../drm/i915/display/intel_display_device.c | 204 ++++++++++++++++++ .../drm/i915/display/intel_display_device.h | 26 +++ 2 files changed, 230 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 7c5cead1fe15..59b8ca174ef8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -20,9 +20,16 @@ __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); +struct subplatform_desc { + enum intel_display_subplatform subplatform; + const char *name; + const u16 *pciidlist; +}; + struct platform_desc { enum intel_display_platform platform; const char *name; + const struct subplatform_desc *subplatforms; const struct intel_display_device_info *info; /* NULL for GMD ID */ }; @@ -30,6 +37,8 @@ struct platform_desc { .platform = (INTEL_DISPLAY_##_platform), \ .name = #_platform +#define ID(id) (id) + static const struct intel_display_device_info no_display = {}; #define PIPE_A_OFFSET 0x70000 @@ -460,8 +469,26 @@ static const struct platform_desc vlv_desc = { }, }; +static const u16 hsw_ult_ids[] = { + INTEL_HSW_ULT_GT1_IDS(ID), + INTEL_HSW_ULT_GT2_IDS(ID), + INTEL_HSW_ULT_GT3_IDS(ID), + 0 +}; + +static const u16 hsw_ulx_ids[] = { + INTEL_HSW_ULX_GT1_IDS(ID), + INTEL_HSW_ULX_GT2_IDS(ID), + 0 +}; + static const struct platform_desc hsw_desc = { PLATFORM(HASWELL), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_HASWELL_ULT, "ULT", hsw_ult_ids }, + { INTEL_DISPLAY_HASWELL_ULX, "ULX", hsw_ulx_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { .has_ddi = 1, .has_dp_mst = 1, @@ -483,8 +510,29 @@ static const struct platform_desc hsw_desc = { }, }; +static const u16 bdw_ult_ids[] = { + INTEL_BDW_ULT_GT1_IDS(ID), + INTEL_BDW_ULT_GT2_IDS(ID), + INTEL_BDW_ULT_GT3_IDS(ID), + INTEL_BDW_ULT_RSVD_IDS(ID), + 0 +}; + +static const u16 bdw_ulx_ids[] = { + INTEL_BDW_ULX_GT1_IDS(ID), + INTEL_BDW_ULX_GT2_IDS(ID), + INTEL_BDW_ULX_GT3_IDS(ID), + INTEL_BDW_ULX_RSVD_IDS(ID), + 0 +}; + static const struct platform_desc bdw_desc = { PLATFORM(BROADWELL), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_BROADWELL_ULT, "ULT", bdw_ult_ids }, + { INTEL_DISPLAY_BROADWELL_ULX, "ULX", bdw_ulx_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { .has_ddi = 1, .has_dp_mst = 1, @@ -549,23 +597,89 @@ static const struct intel_display_device_info skl_display = { .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), }; +static const u16 skl_ult_ids[] = { + INTEL_SKL_ULT_GT1_IDS(ID), + INTEL_SKL_ULT_GT2_IDS(ID), + INTEL_SKL_ULT_GT3_IDS(ID), + 0 +}; + +static const u16 skl_ulx_ids[] = { + INTEL_SKL_ULX_GT1_IDS(ID), + INTEL_SKL_ULX_GT2_IDS(ID), + 0 +}; + static const struct platform_desc skl_desc = { PLATFORM(SKYLAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_SKYLAKE_ULT, "ULT", skl_ult_ids }, + { INTEL_DISPLAY_SKYLAKE_ULX, "ULX", skl_ulx_ids }, + {}, + }, .info = &skl_display, }; +static const u16 kbl_ult_ids[] = { + INTEL_KBL_ULT_GT1_IDS(ID), + INTEL_KBL_ULT_GT2_IDS(ID), + INTEL_KBL_ULT_GT3_IDS(ID), + 0 +}; + +static const u16 kbl_ulx_ids[] = { + INTEL_KBL_ULX_GT1_IDS(ID), + INTEL_KBL_ULX_GT2_IDS(ID), + INTEL_AML_KBL_GT2_IDS(ID), + 0 +}; + static const struct platform_desc kbl_desc = { PLATFORM(KABYLAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_KABYLAKE_ULT, "ULT", kbl_ult_ids }, + { INTEL_DISPLAY_KABYLAKE_ULX, "ULX", kbl_ulx_ids }, + {}, + }, .info = &skl_display, }; +static const u16 cfl_ult_ids[] = { + INTEL_CFL_U_GT2_IDS(ID), + INTEL_CFL_U_GT3_IDS(ID), + INTEL_WHL_U_GT1_IDS(ID), + INTEL_WHL_U_GT2_IDS(ID), + INTEL_WHL_U_GT3_IDS(ID), + 0 +}; + +static const u16 cfl_ulx_ids[] = { + INTEL_AML_CFL_GT2_IDS(ID), + 0 +}; + static const struct platform_desc cfl_desc = { PLATFORM(COFFEELAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_COFFEELAKE_ULT, "ULT", cfl_ult_ids }, + { INTEL_DISPLAY_COFFEELAKE_ULX, "ULX", cfl_ulx_ids }, + {}, + }, .info = &skl_display, }; +static const u16 cml_ult_ids[] = { + INTEL_CML_U_GT1_IDS(ID), + INTEL_CML_U_GT2_IDS(ID), + 0 +}; + static const struct platform_desc cml_desc = { PLATFORM(COMETLAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_COMETLAKE_ULT, "ULT", cml_ult_ids }, + {}, + }, .info = &skl_display, }; @@ -654,8 +768,17 @@ static const struct platform_desc glk_desc = { BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) +static const u16 icl_port_f_ids[] = { + INTEL_ICL_PORT_F_IDS(ID), + 0 +}; + static const struct platform_desc icl_desc = { PLATFORM(ICELAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_ICELAKE_PORT_F, "Port F", icl_port_f_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { ICL_DISPLAY, @@ -722,8 +845,17 @@ static const struct platform_desc ehl_desc = { BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) +static const u16 tgl_uy_ids[] = { + INTEL_TGL_GT2_IDS(ID), + 0 +}; + static const struct platform_desc tgl_desc = { PLATFORM(TIGERLAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_TIGERLAKE_UY, "UY", tgl_uy_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, @@ -762,8 +894,17 @@ static const struct platform_desc rkl_desc = { }, }; +static const u16 adls_rpls_ids[] = { + INTEL_RPLS_IDS(ID), + 0 +}; + static const struct platform_desc adl_s_desc = { PLATFORM(ALDERLAKE_S), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, .has_hti = 1, @@ -830,8 +971,29 @@ static const struct intel_display_device_info xe_lpd_display = { BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), }; +static const u16 adlp_adln_ids[] = { + INTEL_ADLN_IDS(ID), + 0 +}; + +static const u16 adlp_rplu_ids[] = { + INTEL_RPLU_IDS(ID), + 0 +}; + +static const u16 adlp_rplp_ids[] = { + INTEL_RPLP_IDS(ID), + 0 +}; + static const struct platform_desc adl_p_desc = { PLATFORM(ALDERLAKE_P), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids }, + { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids }, + { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids }, + {}, + }, .info = &xe_lpd_display, }; @@ -846,8 +1008,29 @@ static const struct intel_display_device_info xe_hpd_display = { BIT(PORT_TC1), }; +static const u16 dg2_g10_ids[] = { + INTEL_DG2_G10_IDS(ID), + 0 +}; + +static const u16 dg2_g11_ids[] = { + INTEL_DG2_G11_IDS(ID), + 0 +}; + +static const u16 dg2_g12_ids[] = { + INTEL_DG2_G12_IDS(ID), + 0 +}; + static const struct platform_desc dg2_desc = { PLATFORM(DG2), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_DG2_G10, "G10", dg2_g10_ids }, + { INTEL_DISPLAY_DG2_G11, "G11", dg2_g11_ids }, + { INTEL_DISPLAY_DG2_G12, "G12", dg2_g12_ids }, + {}, + }, .info = &xe_hpd_display, }; @@ -1059,12 +1242,27 @@ static const struct platform_desc *find_platform_desc(struct pci_dev *pdev) return NULL; } +static const struct subplatform_desc * +find_subplatform_desc(struct pci_dev *pdev, const struct platform_desc *desc) +{ + const struct subplatform_desc *sp; + const u16 *id; + + for (sp = desc->subplatforms; sp && sp->subplatform; sp++) + for (id = sp->pciidlist; *id; id++) + if (*id == pdev->device) + return sp; + + return NULL; +} + void intel_display_device_probe(struct drm_i915_private *i915) { struct pci_dev *pdev = to_pci_dev(i915->drm.dev); const struct intel_display_device_info *info; struct intel_display_ip_ver ip_ver = {}; const struct platform_desc *desc; + const struct subplatform_desc *subdesc; /* Add drm device backpointer as early as possible. */ i915->display.drm = &i915->drm; @@ -1098,6 +1296,12 @@ void intel_display_device_probe(struct drm_i915_private *i915) drm_WARN_ON(&i915->drm, !desc->platform || !desc->name); DISPLAY_RUNTIME_INFO(i915)->platform = desc->platform; + subdesc = find_subplatform_desc(pdev, desc); + if (subdesc) { + drm_WARN_ON(&i915->drm, !subdesc->subplatform || !subdesc->name); + DISPLAY_RUNTIME_INFO(i915)->subplatform = subdesc->subplatform; + } + if (ip_ver.ver || ip_ver.rel || ip_ver.step) DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 8accd680a61e..e1d9947394dc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -70,6 +70,31 @@ enum intel_display_platform { INTEL_DISPLAY_LUNARLAKE, }; +enum intel_display_subplatform { + INTEL_DISPLAY_SUBPLATFORM_UNINITIALIZED = 0, + INTEL_DISPLAY_HASWELL_ULT, + INTEL_DISPLAY_HASWELL_ULX, + INTEL_DISPLAY_BROADWELL_ULT, + INTEL_DISPLAY_BROADWELL_ULX, + INTEL_DISPLAY_SKYLAKE_ULT, + INTEL_DISPLAY_SKYLAKE_ULX, + INTEL_DISPLAY_KABYLAKE_ULT, + INTEL_DISPLAY_KABYLAKE_ULX, + INTEL_DISPLAY_COFFEELAKE_ULT, + INTEL_DISPLAY_COFFEELAKE_ULX, + INTEL_DISPLAY_COMETLAKE_ULT, + INTEL_DISPLAY_COMETLAKE_ULX, + INTEL_DISPLAY_ICELAKE_PORT_F, + INTEL_DISPLAY_TIGERLAKE_UY, + INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, + INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, + INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, + INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, + INTEL_DISPLAY_DG2_G10, + INTEL_DISPLAY_DG2_G11, + INTEL_DISPLAY_DG2_G12, +}; + #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ @@ -168,6 +193,7 @@ enum intel_display_platform { struct intel_display_runtime_info { enum intel_display_platform platform; + enum intel_display_subplatform subplatform; struct intel_display_ip_ver { u16 ver; From patchwork Wed May 22 17:33:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74402C25B7E for ; Wed, 22 May 2024 17:34:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C98A810E427; Wed, 22 May 2024 17:34:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="HvxH0OTG"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 37E9410E1C7; Wed, 22 May 2024 17:34:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716399285; x=1747935285; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dsdCXZVo5dDZnXKWIb8GoEarsCHcPxhJO89VB9NiTE4=; b=HvxH0OTGSLoCp1qNIwI/J2Dd6RSiqaDEMxg3nhtSTIeYeDbVxTVVbYFs g2mAxdBGy5YD0+y41m/wAMjO1TYgmuj1/hJbwbwLKi+xyOQldTq876ATw SoRl4PCQlUqgYIzwfXCZQph4lt4t91FfrAp0ghQc6yJLmVMsZp3s98kpl GpMI4479KBiFJxTOI1s/q1tF3O7OEyaN2c106ej6IzgFRLXPRIFX1shgw oD9kQkWjM3KsR2wrqzZaKtsTRD34S9f92f4RkcKayr6PWWmqJG0U7vmCs gpIjdBQ6zjVRmOfuTh89asM0A2aU+hLmq0OPwoJl3v8vHN0e7CM5mBvIw Q==; X-CSE-ConnectionGUID: Zob6JYNPRTWVptZ5Bc2utw== X-CSE-MsgGUID: oRySzi5+T/qCupqvXlihyQ== X-IronPort-AV: E=McAfee;i="6600,9927,11080"; a="12611460" X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="12611460" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:45 -0700 X-CSE-ConnectionGUID: H+Hmb9kJRnunZK4DsqS4GQ== X-CSE-MsgGUID: j3C3Kr5mRQ+A3zOlYxFjyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,181,1712646000"; d="scan'208";a="33475061" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 May 2024 10:34:43 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Subject: [PATCH 10/10] drm/i915/display: add probe message Date: Wed, 22 May 2024 20:33:47 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add an info message about which display device was probed. Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 59b8ca174ef8..5b6dfb5032e7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1305,6 +1305,11 @@ void intel_display_device_probe(struct drm_i915_private *i915) if (ip_ver.ver || ip_ver.rel || ip_ver.step) DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; + drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u\n", + desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", + pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver, + DISPLAY_RUNTIME_INFO(i915)->ip.rel); + return; no_display: