From patchwork Thu May 23 10:33:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 13671600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3995DC25B75 for ; Thu, 23 May 2024 10:34:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=cQYTd9Gk6r6I2qN3e+Jbh3Sg45muDK7tLl16KnvEEWE=; b=P2bj83fwsEivAd 5firDpio9EHsETHfNqacxEA2LlpaDneuaNFLhimqkHB5NzYTj7D2s4JUYwgv7z93IlkiFWpsGFMc8 37y0s9I2wvazapmOS1x1+GvZvk7ElE5WIWHf2WcDpr9IpDcKjcmolh0SV3r0Bup9HyHhX8MXu4uM5 NI/V9cGE41MMbfHEZ4YeBjpIR4tUrzb1Lq1NCp03DwRQVPTnuh7Ebz6kArc8goBXddrZCXgl6EQEl AQyKQtqNDHuU0knkcWdEqAWSSGPoSTtJ6Cm+B0hn6eT2q10DiDW80oWjJ3KKxcfJYz0d0/8AbC4y7 qkaJmwprR+3Chw9fKnGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sA5lg-00000005tfh-0KoO; Thu, 23 May 2024 10:33:52 +0000 Received: from metis.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::104]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sA5la-00000005td3-2s1j for linux-arm-kernel@lists.infradead.org; Thu, 23 May 2024 10:33:49 +0000 Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1sA5lK-0007kH-Ly; Thu, 23 May 2024 12:33:30 +0200 Received: from [2a0a:edc0:0:900:1d::77] (helo=ptz.office.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sA5lI-002eDf-Q5; Thu, 23 May 2024 12:33:28 +0200 Received: from ukl by ptz.office.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1sA5lI-00AfcR-2K; Thu, 23 May 2024 12:33:28 +0200 From: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= To: Alain Volmat , Mark Brown , Ben Wolsieffer Cc: Maxime Coquelin , Alexandre Torgue , linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, =?utf-8?q?Leon?= =?utf-8?q?ard_G=C3=B6hrs?= Subject: [PATCH] spi: stm32: Revert change that enabled controller before asserting CS Date: Thu, 23 May 2024 12:33:25 +0200 Message-ID: <20240523103326.792907-2-u.kleine-koenig@pengutronix.de> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3022; i=u.kleine-koenig@pengutronix.de; h=from:subject; bh=6tuNnoLkJ2tXDCxIpUaYwWLi21/Zzu/baG1ufTacAHE=; b=owEBbQGS/pANAwAKAY+A+1h9Ev5OAcsmYgBmTxt2iwSlG4f6TMyHvH9Enp+HExKclnaGmgUv5 sT2/d4d1iaJATMEAAEKAB0WIQQ/gaxpOnoeWYmt/tOPgPtYfRL+TgUCZk8bdgAKCRCPgPtYfRL+ TrlmB/4gV8s2Y7NT/84tO/LJQeNFA/eP0C2EtjPHZS1/32AOwgO6TFQcrzJcpZh45yk0wPYPMHb aFTODdWZv8lTX3BfpTP7YfvWwPffd/xX2QoXNZeNFmn19qksWILTn53/v+W1LztEshxRElS42t1 C0R0HoVbnbPEOb9q7MS4GrqiyCvuh3hGsHrItLh9QCy3gISo3HAi33TyIHWUbIG6sl1nhB7z3Nq bw4UOdOKXSU7blghuSU7ZVwLBAbVJxUoKudwG3UPt3CDErvpUawdnQRmbHIPMY//vHCXhADehof Y5cdLRs/dcOLq1HXB4ZE/ljlT87kerC3elpMKT4LGN4i0JAr X-Developer-Key: i=u.kleine-koenig@pengutronix.de; a=openpgp; fpr=0D2511F322BFAB1C1580266BE2DCDD9132669BD6 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240523_033346_757709_5E5A6B85 X-CRM114-Status: GOOD ( 14.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On stm32mp157 enabling the controller before asserting CS makes the hardware trigger spurious interrupts in a tight loop and the transfers fail. Revert the commit that swapped the order of enable and CS. This reintroduces the problem that swapping was supposed to fix, which however is less grave. Reported-by: Leonard Göhrs Link: https://lore.kernel.org/all/39033ed7-3e57-4339-80b4-fc8919e26aa7@pengutronix.de/ Fixes: 52b62e7a5d4f ("spi: stm32: enable controller before asserting CS") Signed-off-by: Uwe Kleine-König --- drivers/spi/spi-stm32.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) base-commit: a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6 diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index 4a68abcdcc35..e4e7ddb7524a 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -1016,8 +1016,10 @@ static irqreturn_t stm32fx_spi_irq_event(int irq, void *dev_id) static irqreturn_t stm32fx_spi_irq_thread(int irq, void *dev_id) { struct spi_controller *ctrl = dev_id; + struct stm32_spi *spi = spi_controller_get_devdata(ctrl); spi_finalize_current_transfer(ctrl); + stm32fx_spi_disable(spi); return IRQ_HANDLED; } @@ -1185,8 +1187,6 @@ static int stm32_spi_prepare_msg(struct spi_controller *ctrl, ~clrb) | setb, spi->base + spi->cfg->regs->cpol.reg); - stm32_spi_enable(spi); - spin_unlock_irqrestore(&spi->lock, flags); return 0; @@ -1204,6 +1204,7 @@ static void stm32fx_spi_dma_tx_cb(void *data) if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { spi_finalize_current_transfer(spi->ctrl); + stm32fx_spi_disable(spi); } } @@ -1218,6 +1219,7 @@ static void stm32_spi_dma_rx_cb(void *data) struct stm32_spi *spi = data; spi_finalize_current_transfer(spi->ctrl); + spi->cfg->disable(spi); } /** @@ -1305,6 +1307,8 @@ static int stm32fx_spi_transfer_one_irq(struct stm32_spi *spi) stm32_spi_set_bits(spi, STM32FX_SPI_CR2, cr2); + stm32_spi_enable(spi); + /* starting data transfer when buffer is loaded */ if (spi->tx_buf) spi->cfg->write_tx(spi); @@ -1341,6 +1345,8 @@ static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) spin_lock_irqsave(&spi->lock, flags); + stm32_spi_enable(spi); + /* Be sure to have data in fifo before starting data transfer */ if (spi->tx_buf) stm32h7_spi_write_txfifo(spi); @@ -1372,6 +1378,8 @@ static void stm32fx_spi_transfer_one_dma_start(struct stm32_spi *spi) */ stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_ERRIE); } + + stm32_spi_enable(spi); } /** @@ -1405,6 +1413,8 @@ static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier); + stm32_spi_enable(spi); + if (STM32_SPI_HOST_MODE(spi)) stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); }