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Thu, 23 May 2024 05:49:26 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 23 May 2024 14:49:14 +0200 Subject: [PATCH v4 01/15] dt-bindings: display: mediatek: aal: add compatible for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v4-1-ed82eb168fb1@baylibre.com> References: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> In-Reply-To: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1032; i=amergnat@baylibre.com; h=from:subject:message-id; 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Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Alexandre Mergnat Reviewed-by: CK Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 623cf7e37fe3..47ddba5c41af 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -36,6 +36,7 @@ properties: - mediatek,mt8188-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal + - mediatek,mt8365-disp-aal - const: mediatek,mt8183-disp-aal reg: From patchwork Thu May 23 12:49:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B820C25B75 for ; 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Thu, 23 May 2024 05:49:28 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-354faf3fa68sm1259611f8f.116.2024.05.23.05.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 05:49:27 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 23 May 2024 14:49:15 +0200 Subject: [PATCH v4 02/15] dt-bindings: display: mediatek: ccorr: add compatible for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v4-2-ed82eb168fb1@baylibre.com> References: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> In-Reply-To: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document the display Color Correction on MT8365, which is compatible with that of the MT8183. Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat Reviewed-by: CK Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 71ea277a5d8e..fca8e7bb0cbc 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -24,6 +24,9 @@ properties: - enum: - mediatek,mt8183-disp-ccorr - mediatek,mt8192-disp-ccorr + - items: + - const: mediatek,mt8365-disp-ccorr + - const: mediatek,mt8183-disp-ccorr - items: - enum: - mediatek,mt8186-disp-ccorr From patchwork Thu May 23 12:49:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44D1AC25B79 for ; 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Thu, 23 May 2024 05:49:29 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-354faf3fa68sm1259611f8f.116.2024.05.23.05.49.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 05:49:29 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 23 May 2024 14:49:16 +0200 Subject: [PATCH v4 03/15] dt-bindings: display: mediatek: color: add compatible for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v4-3-ed82eb168fb1@baylibre.com> References: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> In-Reply-To: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document the display Color on MT8365, which is compatible with that of the MT8173. Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat Reviewed-by: CK Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 61d040a10c08..6160439ce4d7 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -40,6 +40,7 @@ properties: - mediatek,mt8188-disp-color - mediatek,mt8192-disp-color - mediatek,mt8195-disp-color + - mediatek,mt8365-disp-color - const: mediatek,mt8173-disp-color reg: maxItems: 1 From patchwork Thu May 23 12:49:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFDBEC25B75 for ; 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Thu, 23 May 2024 05:49:31 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-354faf3fa68sm1259611f8f.116.2024.05.23.05.49.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 05:49:30 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 23 May 2024 14:49:17 +0200 Subject: [PATCH v4 04/15] dt-bindings: display: mediatek: dither: add compatible for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v4-4-ed82eb168fb1@baylibre.com> References: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> In-Reply-To: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document the display Dither on MT8365, which is compatible with that of the MT8183. Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat Reviewed-by: CK Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 3d4ab3f86294..abaf27916d13 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither + - mediatek,mt8365-disp-dither - const: mediatek,mt8183-disp-dither reg: From patchwork Thu May 23 12:49:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63255C25B79 for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document the Display Serial Interface on MT8365, which is compatible with that of the MT8183. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Alexandre Mergnat Reviewed-by: CK Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml index 2e9d3d23cbc1..27ffbccc2a08 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -37,6 +37,7 @@ properties: - items: - enum: - mediatek,mt8195-dsi + - mediatek,mt8365-dsi - const: mediatek,mt8183-dsi reg: From patchwork Thu May 23 12:49:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB764C25B79 for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fabien Parent DPI is part of the display / multimedia block in MediaTek SoCs, and always have a power-domain (at least in the upstream device-trees). Add the power-domains property to the binding documentation. Fixes: 9273cf7d3942 ("dt-bindings: display: mediatek: convert the dpi bindings to yaml") Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Alexandre Mergnat Reviewed-by: CK Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 6607cb1c6e0a..169d054d81ff 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -80,6 +80,9 @@ properties: - port@0 - port@1 + power-domains: + maxItems: 1 + required: - compatible - reg @@ -99,11 +102,13 @@ examples: - | #include #include + #include dpi: dpi@1401d000 { compatible = "mediatek,mt8173-dpi"; reg = <0x1401d000 0x1000>; interrupts = ; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 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Thu, 23 May 2024 05:49:35 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-354faf3fa68sm1259611f8f.116.2024.05.23.05.49.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 05:49:35 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 23 May 2024 14:49:20 +0200 Subject: [PATCH v4 07/15] dt-bindings: display: mediatek: dpi: add compatible for MT8365 MIME-Version: 1.0 Message-Id: <20231023-display-support-v4-7-ed82eb168fb1@baylibre.com> References: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> In-Reply-To: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add dt-binding documentation of dpi for MediaTek MT8365 SoC. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Alexandre Mergnat Reviewed-by: CK Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 169d054d81ff..21b93f356901 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -31,6 +31,10 @@ properties: - enum: - mediatek,mt6795-dpi - const: mediatek,mt8183-dpi + - items: + - enum: + - mediatek,mt8365-dpi + - const: mediatek,mt8192-dpi reg: maxItems: 1 From patchwork Thu May 23 12:49:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40924C25B75 for ; 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Thu, 23 May 2024 05:49:37 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-354faf3fa68sm1259611f8f.116.2024.05.23.05.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 05:49:36 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 23 May 2024 14:49:21 +0200 Subject: [PATCH v4 08/15] dt-bindings: display: mediatek: gamma: add compatible for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v4-8-ed82eb168fb1@baylibre.com> References: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> In-Reply-To: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document the display Gamma on MT8365, which is compatible with that of the MT8183. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index 17f299abda11..48542dc7e784 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt8188-disp-gamma - mediatek,mt8192-disp-gamma - mediatek,mt8195-disp-gamma + - mediatek,mt8365-disp-gamma - const: mediatek,mt8183-disp-gamma - items: - enum: From patchwork Thu May 23 12:49:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0AC77C25B7F for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document the display Overlay on MT8365, which is compatible with that of the MT8192. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index e93f0247bdcc..9ea796a033b2 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -44,6 +44,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-ovl + - mediatek,mt8365-disp-ovl - const: mediatek,mt8192-disp-ovl reg: From patchwork Thu May 23 12:49:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C94BC27C42 for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document the display Data Path Read DMA on MT8365, which is compatible with that of the MT8183. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index edb8d3b67025..878f676b581f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -45,6 +45,7 @@ properties: - enum: - mediatek,mt8186-disp-rdma - mediatek,mt8192-disp-rdma + - mediatek,mt8365-disp-rdma - const: mediatek,mt8183-disp-rdma reg: From patchwork Thu May 23 12:49:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18A0BC25B79 for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered before mtk_dsi_poweron. lanes_ready flag toggle to true during mtk_dsi_lane_ready function, and the DSI module is set up during mtk_dsi_poweron. Later, during panel driver init, mtk_dsi_lane_ready is triggered but does nothing because lanes are considered ready. Unfortunately, when the panel driver try to communicate, the DSI returns a timeout. The solution found here is to put lanes_ready flag to false after the DSI module setup into mtk_dsi_poweron to init the DSI lanes after the power / setup of the DSI module. Signed-off-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index e036d9394c23..cb546a9e9419 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -643,6 +643,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); + dsi->lanes_ready = false; + return 0; err_disable_engine_clk: clk_disable_unprepare(dsi->engine_clk); From patchwork Thu May 23 12:49:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64562C25B75 for ; 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Thu, 23 May 2024 05:49:42 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-354faf3fa68sm1259611f8f.116.2024.05.23.05.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 05:49:42 -0700 (PDT) From: amergnat@baylibre.com Date: Thu, 23 May 2024 14:49:25 +0200 Subject: [PATCH v4 12/15] drm/mediatek: add MT8365 SoC support MIME-Version: 1.0 Message-Id: <20231023-display-support-v4-12-ed82eb168fb1@baylibre.com> References: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> In-Reply-To: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat , Fabien Parent X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fabien Parent Add DRM support for MT8365 SoC. Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index ce8f3cc6e853..e1c3281651ae 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -318,6 +318,10 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .mmsys_dev_num = 2, }; +static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { + .mmsys_dev_num = 1, +}; + static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, @@ -345,6 +349,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8195_vdosys0_driver_data}, { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data}, + { .compatible = "mediatek,mt8365-mmsys", + .data = &mt8365_mmsys_driver_data}, { } }; MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); @@ -732,6 +738,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8195-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8365-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { .compatible = "mediatek,mt2701-disp-ovl", From patchwork Thu May 23 12:49:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB330C25B79 for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable this feature for the i350-evk HDMI connector support. Signed-off-by: Alexandre Mergnat --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6281975199c4..7dac8f92b0b9 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -881,6 +881,7 @@ CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m CONFIG_DRM_FSL_LDB=m +CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m From patchwork Thu May 23 12:49:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E80E6C25B7C for ; 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Thu, 23 May 2024 05:49:45 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-354faf3fa68sm1259611f8f.116.2024.05.23.05.49.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 05:49:44 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 23 May 2024 14:49:27 +0200 Subject: [PATCH v4 14/15] arm64: dts: mediatek: add display blocks support for the MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v4-14-ed82eb168fb1@baylibre.com> References: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> In-Reply-To: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" - Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 336 +++++++++++++++++++++++++++++++ 1 file changed, 336 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 24581f7410aa..9f88645141d6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -17,6 +18,19 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + aal0 = &aal0; + ccorr0 = &ccorr0; + color0 = &color0; + dither0 = &dither0; + dpi0 = &dpi0; + dsi0 = &dsi0; + gamma0 = &gamma0; + ovl0 = &ovl0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -607,6 +621,15 @@ spi: spi@1100a000 { status = "disabled"; }; + disp_pwm: pwm@1100e000 { + compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + clock-names = "main", "mm"; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -703,6 +726,15 @@ ethernet: ethernet@112a0000 { status = "disabled"; }; + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clock-output-names = "mipi_tx0_pll"; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -730,6 +762,26 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8365-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + mmsys_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_in>; + }; + }; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8365-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; }; smi_common: smi@14002000 { @@ -755,6 +807,290 @@ larb0: larb@14003000 { mediatek,larb-id = <0>; }; + ovl0: ovl@1400b000 { + compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ovl0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&mmsys_main>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + ovl0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&rdma0_in>; + }; + }; + }; + }; + + rdma0: rdma@1400d000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rdma0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + rdma0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&color0_in>; + }; + }; + }; + }; + + color0: color@1400f000 { + compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&ccorr0_in>; + }; + }; + }; + }; + + ccorr0: ccorr@14010000 { + compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ccorr0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + ccorr0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&aal0_in>; + }; + }; + }; + }; + + aal0: aal@14011000 { + compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + aal0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + aal0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&gamma0_in>; + }; + }; + }; + }; + + gamma0: gamma@14012000 { + compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + gamma0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + gamma0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dither0_in>; + }; + }; + }; + }; + + dither0: dither@14013000 { + compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dither0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dither0_out: endpoint@0 { + reg = <0>; + }; + }; + }; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + clock-names = "engine", "digital", "hs"; + clocks = <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts = ; + phy-names = "dphy"; + phys = <&mipi_tx0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rdma1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&mmsys_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + rdma1_out: endpoint@1 { + reg = <1>; + }; + }; + }; + }; + + dpi0: dpi@14018000 { + compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; + reg = <0 0x14018000 0 0x1000>; + clocks = <&mmsys CLK_MM_DPI0_DPI0>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names = "pixel", "engine", "pll"; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + status = "disabled"; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; From patchwork Thu May 23 12:49:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13671764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A250C25B7D for ; Thu, 23 May 2024 12:50:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 761EA10E570; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" MIPI DSI: - Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg", to power the pannel plugged to the DSI connector. - Setup the Display Parallel Interface. - Add the startek kd070fhfid015 pannel support. HDMI: - Add HDMI connector support. - Add the "ite,it66121" HDMI bridge support, driven by I2C1. - Setup the Display Parallel Interface. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 236 ++++++++++++++++++++++++++++ 1 file changed, 236 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 50cbaefa1a99..6e972e2c1586 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -26,6 +26,21 @@ chosen { stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + + port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_connector_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -86,6 +101,15 @@ optee_reserved: optee@43200000 { reg = <0 0x43200000 0 0x00c00000>; }; }; + + vsys_lcm_reg: regulator-vsys-lcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vsys_lcm"; + }; }; &cpu0 { @@ -108,6 +132,89 @@ &cpu3 { sram-supply = <&mt6357_vsram_proc_reg>; }; +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +&dpi0 { + pinctrl-0 = <&dpi_default_pins>; + pinctrl-1 = <&dpi_idle_pins>; + pinctrl-names = "default", "sleep"; + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dpi0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dpi0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&it66121_in>; + }; + }; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "startek,kd070fhfid015"; + reg = <0>; + enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&mt6357_vsim1_reg>; + power-supply = <&vsys_lcm_reg>; + + port { + #address-cells = <1>; + #size-cells = <0>; + panel_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_out>; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsi0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dsi0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + ðernet { pinctrl-0 = <ðernet_pins>; pinctrl-names = "default"; @@ -138,6 +245,56 @@ &i2c0 { status = "okay"; }; +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-div = <2>; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + it66121_hdmi: hdmi@4c { + #sound-dai-cells = <0>; + compatible = "ite,it66121"; + interrupt-parent = <&pio>; + interrupts = <68 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&ite_pins>; + pinctrl-names = "default"; + reg = <0x4c>; + reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>; + vcn18-supply = <&mt6357_vsim2_reg>; + vcn33-supply = <&mt6357_vibr_reg>; + vrf12-supply = <&mt6357_vrf12_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + it66121_in: endpoint@0 { + reg = <0>; + bus-width = <12>; + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + hdmi_connector_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + &mmc0 { assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; @@ -180,7 +337,55 @@ &mt6357_pmic { #interrupt-cells = <2>; }; +&mt6357_vsim1_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + &pio { + dpi_default_pins: dpi-default-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <4>; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + ethernet_pins: ethernet-pins { phy_reset_pins { pinmux = ; @@ -222,6 +427,33 @@ pins { }; }; + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + irq_ite_pins { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pwr_pins { + pinmux = , + ; + output-high; + }; + + rst_ite_pins { + pinmux = ; + output-high; + }; + }; + mmc0_default_pins: mmc0-default-pins { clk-pins { pinmux = ; @@ -377,6 +609,10 @@ &pwm { status = "okay"; }; +&rdma1_out { + remote-endpoint = <&dpi0_in>; +}; + &ssusb { dr_mode = "otg"; maximum-speed = "high-speed";