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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF00004680.mail.protection.outlook.com (10.167.243.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7611.14 via Frontend Transport; Thu, 23 May 2024 15:56:56 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 23 May 2024 10:56:56 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 1/9] x86/mce/inject: Only write MCA_MISC with user-set value Date: Thu, 23 May 2024 10:56:33 -0500 Message-ID: <20240523155641.2805411-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523155641.2805411-1-yazen.ghannam@amd.com> References: <20240523155641.2805411-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|CY5PR12MB6430:EE_ X-MS-Office365-Filtering-Correlation-Id: 70a0e361-48fc-40ba-0fe6-08dc7b40f93c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|1800799015|36860700004|376005; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2024 15:56:56.9041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70a0e361-48fc-40ba-0fe6-08dc7b40f93c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6430 The MCA_MISC register is used to control the MCA thresholding feature on AMD systems. Therefore, it is not generally part of the error state that a user would adjust when testing non-thresholding cases. However, MCA_MISC is unconditionally written even if a user does not supply a value. The default value of '0' will be used and clobber the register. Write the MCA_MISC register only if the user has given a value for it. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/inject.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 94953d749475..8d18074534ff 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -487,12 +487,16 @@ static void prepare_msrs(void *info) wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); } - wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); + + if (m.misc) + wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); } else { wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); - wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); + + if (m.misc) + wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); } } From patchwork Thu May 23 15:56:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13672015 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2080.outbound.protection.outlook.com [40.107.223.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 308BE1170F; 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Thu, 23 May 2024 10:56:56 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 2/9] x86/mce: Remove unused variable and return value in machine_check_poll() Date: Thu, 23 May 2024 10:56:34 -0500 Message-ID: <20240523155641.2805411-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523155641.2805411-1-yazen.ghannam@amd.com> References: <20240523155641.2805411-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|SN7PR12MB8769:EE_ X-MS-Office365-Filtering-Correlation-Id: 4f85c2d2-1890-40a6-96ed-08dc7b40f983 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|82310400017|36860700004|1800799015; X-Microsoft-Antispam-Message-Info: S6O4IccZTXf1Sb94INst/8QopDxlT0/KZHyVvBxGreakKTQVbokWvmrXjcr5WoJHyZ7j7+M3jR8ooCWxxy0kJOkXKqnRn4cIQu/vg19fOOKra+PcBt1ibim+i8C62AIxnq9mZl2DjuBAgJGLr6VR0reziUyJgxfX8MxqYDCjNUg1cSBbQto1d0/KSmZsalgXLjQpc/0iekhQ6TnaqZYfQX4l9AdDybNeRouKJfqQHjmI8HsZ1afrdRW4WwbpVJzvlmMbqnUfqEsBVWAbYUXnWSRL2wmNbsdLbOUjUStU3sQQdbJTF6Bly7wm3SQyGDaWU5t09rpcLt53kuH5ULv/jsCcaA6oZRfbPblU4s4b66KabgLcS1oG6RUpLFeO/n2yVoAYhz9QVwO1wK6tdi4vCpPybBxqbEe9rWSOqe4JJy/m3feQg49JgWWUGEO+efDzLDcLB0nLz2NEuFA1/iBzjFPQj4S5njk5OACvTsfoKHiOWHuknZ5RJG45v+5uUSOJnRv2urN/C2E3yAhJyh5zFHsHVxjUSdlJS82VJTT+aeFFVpDA0Ne9ibYEcNSjGn8stbl/HU1ZCsWL6dRXZShfpxHS5/QtVlVhbeyhPOp19y/J60kzfI0eh4tUb8HoFFmNNdX1TdjHVbTB5YdviFe8SGPUtMekE0gBr/ltSnyS1eFGZ0bpxz6JyUHIFsux3zZkh12DKk8zdQs6MWbEhIHwuLqXkLaqRawcHeV0I7BT06pf7mBSEKZGJFSPbdqQdIMKOoRWWcidgPFbjTehvlO6yJySWXNdf+0VlyNfMRDpAj9bI/rU2lANP4kW2QMvlvMtvFamQHJBhoS/OTQ2KXeOnCMlowGXYZcJE9+7KaqqZ4Pbac5gV0XxZ2wpj4wWbi44NF5x3QA0sjWD3uDM4uCBgCdmcv5M2Dlk9D4Q32LDU74hhmZx4mNTZqzxpvHhgpepbAY+BWFUIHtyq7fxeowoxsNkk9q7Yp7sGKZZbE47cVhpVMhnMx64J0tApdZPe2Md9G94S4XDXjhsYnsKIV8WJf9witAIDa/Sh4TwsgRgr52NG6dqgOF9AGsoNis6ol4/tp/RkAwjf0OEQs28n9HbvUzoUPldAn8lUC9JGh4NNFi2RAsx1UNef1YBvOl/Lm3iqCZJSt9tuJX5zErTdnWV/+yl0s0+eASrbXZZhtyr3OzDB4FfDOLLGrD0AYmp0ferGoDLB2PKpscn/JaKSnLJebq7Gd+qobpi+NrYFZQV01bYnFYpmM7eP8182+UFzXlfIylqCt/7fQU9xum6PermUM6a9luEpibBaak4X9Fh4goq3iUiMuiyK3FgpbIPOZLE97nf6YOkrpL5CuZPX5Ajs8LlazB2wzOAVNG9yZyIc1GN2XqV/IE5BnG3Hx5Au9GM X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(376005)(82310400017)(36860700004)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2024 15:56:57.3573 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f85c2d2-1890-40a6-96ed-08dc7b40f983 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8769 The recent CMCI storm handling rework removed the last case that checks the return value of machine_check_poll(). Therefore the "error_seen" variable is no longer used, so remove it. Fixes: 3ed57b41a412 ("x86/mce: Remove old CMCI storm mitigation code") Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 3 ++- arch/x86/kernel/cpu/mce/core.c | 7 +------ 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index de3118305838..bc3813c94c79 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -259,7 +259,8 @@ enum mcp_flags { MCP_DONTLOG = BIT(2), /* only clear, don't log */ MCP_QUEUE_LOG = BIT(3), /* only queue to genpool */ }; -bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b); + +void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); int mce_notify_irq(void); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index b5cc557cfc37..287108de210e 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -677,10 +677,9 @@ DEFINE_PER_CPU(unsigned, mce_poll_count); * is already totally * confused. In this case it's likely it will * not fully execute the machine check handler either. */ -bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) +void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); - bool error_seen = false; struct mce m; int i; @@ -754,8 +753,6 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) continue; log_it: - error_seen = true; - if (flags & MCP_DONTLOG) goto clear_it; @@ -787,8 +784,6 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) */ sync_core(); - - return error_seen; } EXPORT_SYMBOL_GPL(machine_check_poll); From patchwork Thu May 23 15:56:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13672019 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2072.outbound.protection.outlook.com [40.107.92.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCC3E1E535; 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Thu, 23 May 2024 10:56:56 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 3/9] x86/mce: Increment MCP count only for timer calls Date: Thu, 23 May 2024 10:56:35 -0500 Message-ID: <20240523155641.2805411-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523155641.2805411-1-yazen.ghannam@amd.com> References: <20240523155641.2805411-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|CYYPR12MB8940:EE_ X-MS-Office365-Filtering-Correlation-Id: 82036e87-c179-48b5-1c65-08dc7b40fbce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|82310400017|376005|36860700004; X-Microsoft-Antispam-Message-Info: eye9zthNZbAqCLW0NAzUe7xCtPtiv0fDxNLIr6SwrDIetDXusyeJyn6V4leaHWLmiWdSjHbiKHK2RIOkmdvQwoJ2W7oBREzfCykasWvFz8eobL6FufZQ2r79TcB31TKTNjfuw/N7y6jdRUW3ZNVavXzAkflj3uI23NN0R0+0DW2Tc55rxR2E2gHa4NyyPVu10myXS0ecC+dj3jK0Z4U0Yeh8tgfpUV6YX9aLy98cVD/TyyXte8ykfpq5XKHJdfaKHscN247ZWXRZ5E5R/cGX/SozcQvrS1uwVv6I1kF7ML9BgnBwXQ8SPjHyxy8lHjllhLvR6K/mYx3RJvJj804XZrGjs3esY2sqKm1sYDxteK3YV/qztuEMY1T74aHgR5MyBhA7m4BT48eg6rJtWFkWoDhgQK5c6573ERQvtmyN2Nr74Kde/1Hi1+2FaBzEXebQtBiyUmkSOE1h20jsJBQpFhpzYb+uHbQ7n3W5U/zLp0sfPlwxFMXWZxlvJ7jV029dO3TdTZFDZL4hy0/hXKK0W6bgPcYg5gikerdR1ypI/evEaaoE3rXuRXecSoZ44XynXe9v1cOx0Z4gaEzOuvMaOoFfE43fGEJf0hq/2xJjmJShlIQ01G/PfX6AFJbM3loDLz2O6rvT1+MAuQM5P01y3c3ympWVFR9eHXFC/crsaKPWI///SQraT8p3XEb/3lumav+Kz2wAjCiAO3JQrzYftl4evkHEbCFc1C/3NInQPmFSTZMJwTqipvmK6A8wL6AocJbDuLI4a9NgcrQWRfcmozaa05oWydijphm8wZFpyN0BWhpkDOOlwyW8dWnaOsARi/Pp1LN+oM49n+Un11rSjfyE+4gKgmvxve537XBt/2TWQ1HrC/MvRyc0k5IQFvNDf0h0Y9ByOZaCCTbpaAXGYAL7HytFOXquB0yCxoh2UYHudDeTdMg5E7pDJfGsIj2YontJ081xumZi24S+l1Ocu/w3o7IH7+XysLOzRzCdO84nk8oJzB/P2wCWYrlhd2cfFUiAWKb6zvXPnUpBrYqoROHGvjA7svawAiDDiBkZ7iU2w0uL5fMCpy8Pvckz5VztIDLr4s4QOakvhU4J6EL489uydjHZOxaZg9VXzSOEj7v9CG4uZDdYx9HlnkUUCbkhOizpVjptiL5NbBcIi/pfoWfqkDwUe8CiK4TZaJ6OAPYexvPgYMPwySfmtEsHuJ1rdxV4rg44zJKGL92PPIZeX5MYqDMC279GgDcEBhFIoBVztAFC6vVVAWARXBHRTGCSWe1j81opjeEkIOdPyEZoVFgB+S9OWffMvOi4X5xLntN+gmKLgjmI0nUn1K+SYiy7983cebNiXlmjt87B7iJYtQbx4YasBIUwNhPmYNGGZd0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(1800799015)(82310400017)(376005)(36860700004);DIR:OUT;SFP:1101; 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Therefore, the count includes calls from the timer, boot-time polling, and interrupt handlers. Only increment the MCP count when called from the timer so as to avoid double counting the interrupt handlers. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 287108de210e..70c8df1a766a 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -683,8 +683,6 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) struct mce m; int i; - this_cpu_inc(mce_poll_count); - mce_gather_info(&m, NULL); if (flags & MCP_TIMESTAMP) @@ -1667,8 +1665,10 @@ static void mce_timer_fn(struct timer_list *t) iv = __this_cpu_read(mce_next_interval); - if (mce_available(this_cpu_ptr(&cpu_info))) + if (mce_available(this_cpu_ptr(&cpu_info))) { + this_cpu_inc(mce_poll_count); mc_poll_banks(); + } /* * Alert userspace if needed. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF00004680.mail.protection.outlook.com (10.167.243.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7611.14 via Frontend Transport; Thu, 23 May 2024 15:57:01 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 23 May 2024 10:56:57 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 4/9] x86/mce: Move machine_check_poll() status checks to helper functions Date: Thu, 23 May 2024 10:56:36 -0500 Message-ID: <20240523155641.2805411-5-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523155641.2805411-1-yazen.ghannam@amd.com> References: <20240523155641.2805411-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|IA0PR12MB8302:EE_ X-MS-Office365-Filtering-Correlation-Id: 7950d509-007b-451e-2cc3-08dc7b40fc1f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|376005|36860700004|1800799015; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2024 15:57:01.7323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7950d509-007b-451e-2cc3-08dc7b40fc1f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8302 There are a number of generic and vendor-specific status checks in machine_check_poll(). These are used to determine if an error should be skipped. Move these into helper functions. Future vendor-specific checks will be added to the helpers. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/core.c | 79 +++++++++++++++++----------------- 1 file changed, 39 insertions(+), 40 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 70c8df1a766a..704e651203b4 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -662,6 +662,44 @@ static noinstr void mce_read_aux(struct mce *m, int i) DEFINE_PER_CPU(unsigned, mce_poll_count); +static bool ser_log_poll_error(struct mce *m) +{ + /* Log "not enabled" (speculative) errors */ + if (!(m->status & MCI_STATUS_EN)) + return true; + + /* + * Log UCNA (SDM: 15.6.3 "UCR Error Classification") + * UC == 1 && PCC == 0 && S == 0 + */ + if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S)) + return true; + + return false; +} + +static bool log_poll_error(enum mcp_flags flags, struct mce *m) +{ + /* If this entry is not valid, ignore it. */ + if (!(m->status & MCI_STATUS_VAL)) + return false; + + /* + * If we are logging everything (at CPU online) or this + * is a corrected error, then we must log it. + */ + if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC)) + return true; + + if (mca_cfg.ser) + return ser_log_poll_error(m); + + if (m->status & MCI_STATUS_UC) + return false; + + return true; +} + /* * Poll for corrected events or events that happened before reset. * Those are just logged through /dev/mcelog. @@ -709,48 +747,9 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) if (!mca_cfg.cmci_disabled) mce_track_storm(&m); - /* If this entry is not valid, ignore it */ - if (!(m.status & MCI_STATUS_VAL)) + if (!log_poll_error(flags, &m)) continue; - /* - * If we are logging everything (at CPU online) or this - * is a corrected error, then we must log it. - */ - if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) - goto log_it; - - /* - * Newer Intel systems that support software error - * recovery need to make additional checks. Other - * CPUs should skip over uncorrected errors, but log - * everything else. - */ - if (!mca_cfg.ser) { - if (m.status & MCI_STATUS_UC) - continue; - goto log_it; - } - - /* Log "not enabled" (speculative) errors */ - if (!(m.status & MCI_STATUS_EN)) - goto log_it; - - /* - * Log UCNA (SDM: 15.6.3 "UCR Error Classification") - * UC == 1 && PCC == 0 && S == 0 - */ - if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) - goto log_it; - - /* - * Skip anything else. Presumption is that our read of this - * bank is racing with a machine check. Leave the log alone - * for do_machine_check() to deal with it. - */ - continue; - -log_it: if (flags & MCP_DONTLOG) goto clear_it; From patchwork Thu May 23 15:56:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13672017 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2081.outbound.protection.outlook.com [40.107.236.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A0A91865B; Thu, 23 May 2024 15:57:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.81 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716479826; cv=fail; b=THgMVl+OifnC5VfF6hsHv55h8KA1hPMQTAOLuMO6zQ95l1cHqkP/Qr9RBf4z1goTwL5t7V1TpT4zlN8JDYJ17YkPF/OyWJ+LJV0kfwRRp8VvJIQlbbEfhnCqKrKFTCuiATKNiScGwmjhdPQnQ85UDEYOgRYF977Il7TVdTOPvYw= ARC-Message-Signature: i=2; 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This feature is discovered by checking capability bits in the MCA_MISC* registers. Currently, MCA thresholding is set up in two passes. The first is during CPU init where available banks are detected, and the "bank_map" variable is updated. The second is during sysfs/device init when the thresholding data structures are allocated and hardware is fully configured. During device init, the "threshold_banks" array is allocated even if no available banks were discovered. Furthermore, the thresholding reset flow checks if the top-level "threshold_banks" array is non-NULL, but it doesn't check if individual "threshold_bank" structures are non-NULL. This is avoided because the hardware interrupt is not enabled in this case. But this issue becomes present if enabling the interrupt when the thresholding data structures are not initialized. Check "bank_map" to determine if the thresholding structures should be allocated and initialized. Also, remove "mce_flags.amd_threshold" which is redundant when checking "bank_map". Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 2 +- arch/x86/kernel/cpu/mce/core.c | 1 - arch/x86/kernel/cpu/mce/internal.h | 5 +---- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9a0133ef7e20..d7dee59cc1ca 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -1395,7 +1395,7 @@ int mce_threshold_create_device(unsigned int cpu) struct threshold_bank **bp; int err; - if (!mce_flags.amd_threshold) + if (!this_cpu_read(bank_map)) return 0; bp = this_cpu_read(threshold_banks); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 704e651203b4..58b8efdcec0b 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1984,7 +1984,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 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Thu, 23 May 2024 10:56:58 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 6/9] x86/mce: Unify AMD THR handler with MCA Polling Date: Thu, 23 May 2024 10:56:38 -0500 Message-ID: <20240523155641.2805411-7-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523155641.2805411-1-yazen.ghannam@amd.com> References: <20240523155641.2805411-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|SA1PR12MB7269:EE_ X-MS-Office365-Filtering-Correlation-Id: e1cacdfa-3ddf-49ff-b28c-08dc7b40fc85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|1800799015|82310400017; X-Microsoft-Antispam-Message-Info: 1M3/sJJcJG7491UycX2ydrf7difyx5Z3QG4LxkUhUKDTmyMztmAN8pMiPPTizXfFcckT8ku3K3OSfTfmU3q9xdF6z29ExegGGiGO+GBJuBgo/ZcHGfEdStrxDyUsx4sLkCzIizFFsJ6GySB9YMPKE2NXgs37Wh/oXjEELKC2IgVAWEsDFAPTZ97fPVVIllUPWOOeGnpV/5+jNLq7cCFrAoCVV1L2aksHF7UCd4Hp9nUDw30rE3G3AF5YLd/30Ui/NsebLz9nxejfBRTXd0Z+YZ/ojgWcQ7s576nsF51G1OjlRthCJKufdyvSbf6mAS0d0xzqZUoIAo3AQllNJ6jOLmNhm6o1bmRkHnPlc163EK6G3dB1zAY9ey+MN6KdJU+Ue0PGpgdHmTDLvpKGoHW6b1wWRh/jgwawQKOcUgm1m5nTWN5gL/M8qBLOgnrq0BWc4LyjbhDTAxZebtgwSnbluEcSGW6E/bCRWq19aC8Jzy4bvsIFXUPD2r8tYjvtF+Q3Lxrzn9MxXibAwK1FQXeyr2rDXn0PWi07MkAhR+4dgvntq4sg4JZS1OeWwou+njx+AB+id8G0aImc5cdYJydHHX+YhAajtPMV5H7cRL3W+JgL1HoR16MDww7zuvXhWgPI8JuDk+veICdjOCfw+mARmL3cBSmEooGxynpWoFPF3OTzxrVWNsHYXikoqYMuY2Tj8hn7SN70Zav5J0iqbpMoJi1ZzwnoCJkddtj4OlM9y6gmZ11apzVX4gy1e2p7crFIb9MQYTftWmfxvh4GZwij4irKoJG+cc/ZdSQDBqHxr2pNnWBLjJQK2gY9PqgZOZBsxpsiQfnLZqcg42Ei7Uhd75yfady+PAM+n+lwHiVTyTMLYa5BJtpLAaVBKG/HbXtzXy7fVf8v9SybFKF8aZPRMfWu3Ei2wxDgD3TKhQkcZy/h7qUb4PKeg6IFJY+FyQQAgoxMNIVgofAhpDCDTHO09ZIedapNcjQ1RZNnlXzfwEQywbizJN/GrkHutlq7GR7rnFrQJ5ztKvA4LeJtv/4c8z46REjNWtdDdfYpv2FnOj2CbAcmGqlEpas8prjd339C5eLEtNtbO43TB9YE5HIYfF459fhMLYOlyyswA3mUOtU3NesWo9w94UL0pqnHm13LvYAJVBWB7h3lYwPCPMc7DpVAf0XnA3e4qBRlRS/S4FkTwqWFHF8REvSQ3yQSaw3mWmW5fQcNKbcM1sP6GxPojOGvDjeD6YjXO2m1rrd49SzlCcFqXtRNfuuKTstUBm9VH/PBKxTC5k5Q8aCQXxjJj/zBKipSwcN1sppjBt2nfwuKk1UJb8Ngm1BAkSaR2NEXEh+cjewvLJeVx0lX6RD/T/xZhfhXplR6Kv+7LmM2MRY6te7EjIKaKiRgaVASFxKO X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(376005)(36860700004)(1800799015)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2024 15:57:02.4042 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1cacdfa-3ddf-49ff-b28c-08dc7b40fc85 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7269 AMD systems optionally support an MCA thresholding interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how the Intel Corrected Machine Check interrupt (CMCI) is handled. AMD MCA thresholding is managed using the MCA_MISC registers within an MCA bank. The OS will need to modify the hardware error count field in order to reset the threshold limit and rearm the interrupt. Management of the MCA_MISC register should be done as a follow up to the basic MCA polling flow. It should not be the main focus of the interrupt handler. Furthermore, future systems will have the ability to send an MCA thresholding interrupt to the OS even when the OS does not manage the feature, i.e. MCA_MISC registers are Read-as-Zero/Locked. Call the common MCA polling function when handling the MCA thresholding interrupt. This will allow the OS to find any valid errors whether or not the MCA thresholding feature is OS-managed. Also, this allows the common MCA polling options and kernel parameters to apply to AMD systems. Add a callback to the MCA polling function to check and reset any threshold blocks that have reached their threshold limit. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 54 +++++++++++++----------------- arch/x86/kernel/cpu/mce/core.c | 8 +++++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 33 insertions(+), 31 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index d7dee59cc1ca..1ac445a0dc12 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -56,6 +56,7 @@ #define SMCA_THR_LVT_OFF 0xF000 static bool thresholding_irq_en; +static DEFINE_PER_CPU_READ_MOSTLY(mce_banks_t, mce_thr_intr_banks); static const char * const th_names[] = { "load_store", @@ -578,6 +579,7 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, if (!b.interrupt_capable) goto done; + __set_bit(bank, this_cpu_ptr(mce_thr_intr_banks)); b.interrupt_enable = 1; if (!mce_flags.smca) { @@ -883,12 +885,7 @@ static void amd_deferred_error_interrupt(void) log_error_deferred(bank); } -static void log_error_thresholding(unsigned int bank, u64 misc) -{ - _log_error_deferred(bank, misc); -} - -static void log_and_reset_block(struct threshold_block *block) +static void reset_block(struct threshold_block *block) { struct thresh_restart tr; u32 low = 0, high = 0; @@ -902,49 +899,44 @@ static void log_and_reset_block(struct threshold_block *block) if (!(high & MASK_OVERFLOW_HI)) return; - /* Log the MCE which caused the threshold event. */ - log_error_thresholding(block->bank, ((u64)high << 32) | low); - - /* Reset threshold block after logging error. */ memset(&tr, 0, sizeof(tr)); tr.b = block; threshold_restart_bank(&tr); } -/* - * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt - * goes off when error_count reaches threshold_limit. - */ -static void amd_threshold_interrupt(void) +void amd_reset_thr_limit(unsigned int bank) { struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; struct threshold_bank **bp = this_cpu_read(threshold_banks); - unsigned int bank, cpu = smp_processor_id(); /* * Validate that the threshold bank has been initialized already. The * handler is installed at boot time, but on a hotplug event the * interrupt might fire before the data has been initialized. */ - if (!bp) + if (!bp || !bp[bank]) return; - for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { - if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) - continue; + first_block = bp[bank]->blocks; + if (!first_block) + return; - first_block = bp[bank]->blocks; - if (!first_block) - continue; + /* + * The first block is also the head of the list. Check it first + * before iterating over the rest. + */ + reset_block(first_block); + list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) + reset_block(block); +} - /* - * The first block is also the head of the list. Check it first - * before iterating over the rest. - */ - log_and_reset_block(first_block); - list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) - log_and_reset_block(block); - } +/* + * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt + * goes off when error_count reaches threshold_limit. + */ +static void amd_threshold_interrupt(void) +{ + machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_thr_intr_banks)); } /* diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 58b8efdcec0b..d6517b93c903 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -660,6 +660,12 @@ static noinstr void mce_read_aux(struct mce *m, int i) } } +static void reset_thr_limit(unsigned int bank) +{ + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) + return amd_reset_thr_limit(bank); +} + DEFINE_PER_CPU(unsigned, mce_poll_count); static bool ser_log_poll_error(struct mce *m) @@ -769,6 +775,8 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) mce_log(&m); clear_it: + reset_thr_limit(i); + /* * Clear state for this bank. */ diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 08571b10bf3f..3e062cf01d4d 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -262,6 +262,7 @@ extern bool filter_mce(struct mce *m); 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Thu, 23 May 2024 10:56:58 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 7/9] x86/mce: Unify AMD DFR handler with MCA Polling Date: Thu, 23 May 2024 10:56:39 -0500 Message-ID: <20240523155641.2805411-8-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523155641.2805411-1-yazen.ghannam@amd.com> References: <20240523155641.2805411-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|CYYPR12MB8853:EE_ X-MS-Office365-Filtering-Correlation-Id: 55cf9f9f-85bb-4ec5-0fd0-08dc7b40fd04 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|1800799015|376005|36860700004; X-Microsoft-Antispam-Message-Info: +Ojn1+fhx5JPhpFxBvVy44MaHiWpg7SLU0MIn6dcq8hS8UjHoRev1DKdDetvPkMo4i+OP620yJhr8lzzXCOe0x1LJ9NmVOntFYKM3xsBuyNt0FOSdOCOdN0yA6/xycZwWF6AK2ZIqs9gLPDhCHO2oCBrzA23tZN19LyQIYgbku0PTuQ/N9Wo1ATGhiHbJHolGA6+qAcwM12oUW0/wF/WA5JqwO5LoNipl/n3pj6kCHwMcErY7R/H+0h3lnJm/tZhcTBSLvjuOtRv/RPwFqjTWnOGedW20653vAOz6Q7rrA2ZIcKrsFsJGljZk1hOcNxTAM5B3AQH6z4XBH5AoXV3joMQky3Gr33QUL9Yujpbsg39VWHbFuzl3UHc/VF/Vg+SElb0TxKp7qsJlw0Y2vswQUgOPsEqoaHLNg8DuTXqoX/0vlhNWiyRP/L9hAcc0Xh5v3DKNXWu0bTaUjJzcSmXgG3FETxRgrlualmAbfCi/tfujd19dyKgFdjyET7pXPvyEdbbmXy03DUOHivv48WpIhPu40vKDPLPSqFPbbbsAZBiwZfvTIZLnJFZKLTHxgPiw/DJXI4GKzXJ+lQ188pUOVi3vlUJMDtSt4BGd7cc22JAGtKYTC96ZZ1HkXI+Iq4zElj+ILtCM3722wyI7grU9vvVisaVemGpUg99DqwSE5pl2puVwD6cuRlb0dLOmq1NgJPUyD7p4FhU4hNYdKdR8NguAiSULRlS4h+ed92d73FSfKy3z9kZnmrJzvGlJWNtEfRT97AShlV9mGkNUJ+SdDR85kVfxoSKwgvXtLWVaUi1CUJQIdPNyagdJPX9uKtCcG3jkbv5kgX8Ba0rG/EMVCa4UBrnMaMXp6OQXqJ0/DjbX33bu0c2AR+S4Osm6WRhVdjHpR81DjToW1hyH5UzWVcYIZ1ZmSVMyC1Fd0geg5rrDUdpSd4hQVivJ4XF6JYUr6x4q5XZ3fj7ebYnJqU2XZxH3/qn56sjZU5yHjwPaT0WwUKObGQ2iIvR+IZO9/sftr8kVrMDSz0d5o9Ick0t3qJ6hNq8qzYrkp0N2Zyq3LLRPjIZsUxSO7CKi9u1UwAmlod3mLTXxI7NpH2UCIRxYud9PXNnGIb3fvFyWtXAoVpXYZymBzCM4ESz+zLYsUmSOYJ3Kyzq4ER+4AOfOmkqH+vSjbNEFXC77nh2Yhql/pFmMMRGtKTFw3pGKUl9d2q67O9ii74fKSnAe6vDIJ5TzZxyegeo8k7/5sUi7OGox6x1/z1Yv/wszXi30JjfaQETHrleEaZ7oz2RRZGbf/6GaV5lX1/HO9cOR3ZvJbfn3cTP+A/CWJgD47PG6R9rFkZApofb2lVwsWD3Qx4xWUUbFH5ULK9YsUaeZbOg1hbdl86ZNHG29cqgsuqmpjEht8ou X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(82310400017)(1800799015)(376005)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2024 15:57:03.2324 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55cf9f9f-85bb-4ec5-0fd0-08dc7b40fd04 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8853 AMD systems optionally support a deferred error interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how other MCA interrupts are handled. Deferred errors do not require any special handling related to the interrupt, e.g. resetting or rearming the interrupt, etc. However, Scalable MCA systems include a pair of registers, MCA_DESTAT and MCA_DEADDR, that should be checked for valid errors. This check should be done whenever MCA registers are polled. Currently, the deferred error interrupt does this check, but the MCA polling function does not. Call the MCA polling function when handling the deferred error interrupt. This keeps all "polling" cases in a common function. Call the polling function only for banks that have the deferred error interrupt enabled. Add an SMCA status check helper. This will do the same status check and register clearing that the interrupt handler has done. And it extends the common polling flow to find AMD deferred errors. Remove old code whose functionality is already covered in the common MCA code. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 99 ++-------------------------------- arch/x86/kernel/cpu/mce/core.c | 46 ++++++++++++++-- 2 files changed, 46 insertions(+), 99 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 1ac445a0dc12..c6594da95340 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -57,6 +57,7 @@ static bool thresholding_irq_en; static DEFINE_PER_CPU_READ_MOSTLY(mce_banks_t, mce_thr_intr_banks); +static DEFINE_PER_CPU_READ_MOSTLY(mce_banks_t, mce_dfr_intr_banks); static const char * const th_names[] = { "load_store", @@ -296,8 +297,10 @@ static void smca_configure(unsigned int bank, unsigned int cpu) * APIC based interrupt. First, check that no interrupt has been * set. */ - if ((low & BIT(5)) && !((high >> 5) & 0x3)) + if ((low & BIT(5)) && !((high >> 5) & 0x3)) { + __set_bit(bank, this_cpu_ptr(mce_dfr_intr_banks)); high |= BIT(5); + } this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); @@ -778,33 +781,6 @@ bool amd_mce_usable_address(struct mce *m) return false; } -static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) -{ - struct mce m; - - mce_setup(&m); - - m.status = status; - m.misc = misc; - m.bank = bank; - m.tsc = rdtsc(); - - if (m.status & MCI_STATUS_ADDRV) { - m.addr = addr; - - smca_extract_err_addr(&m); - } - - if (mce_flags.smca) { - rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); - - if (m.status & MCI_STATUS_SYNDV) - rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); - } - - mce_log(&m); -} - DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) { trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); @@ -814,75 +790,10 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) apic_eoi(); } -/* - * Returns true if the logged error is deferred. False, otherwise. - */ -static inline bool -_log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) -{ - u64 status, addr = 0; - - rdmsrl(msr_stat, status); - if (!(status & MCI_STATUS_VAL)) - return false; - - if (status & MCI_STATUS_ADDRV) - rdmsrl(msr_addr, addr); - - __log_error(bank, status, addr, misc); - - wrmsrl(msr_stat, 0); - - return status & MCI_STATUS_DEFERRED; -} - -static bool _log_error_deferred(unsigned int bank, u32 misc) -{ - if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), - mca_msr_reg(bank, MCA_ADDR), misc)) - return false; - - /* - * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. - * Return true here to avoid accessing these registers. - */ - if (!mce_flags.smca) - return true; - - /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); - return true; -} - -/* - * We have three scenarios for checking for Deferred errors: - * - * 1) Non-SMCA systems check MCA_STATUS and log error if found. - * 2) SMCA systems check MCA_STATUS. If error is found then log it and also - * clear MCA_DESTAT. - * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and - * log it. - */ -static void log_error_deferred(unsigned int bank) -{ - if (_log_error_deferred(bank, 0)) - return; - - /* - * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check - * for a valid error. - */ - _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), - MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); -} - /* APIC interrupt handler for deferred errors */ static void amd_deferred_error_interrupt(void) { - unsigned int bank; - - for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) - log_error_deferred(bank); + machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_dfr_intr_banks)); } static void reset_block(struct threshold_block *block) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index d6517b93c903..16c999b2cc1f 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -637,7 +637,8 @@ static noinstr void mce_read_aux(struct mce *m, int i) if (m->status & MCI_STATUS_MISCV) m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); - if (m->status & MCI_STATUS_ADDRV) { + /* Don't overwrite an address value that was saved earlier. */ + if (m->status & MCI_STATUS_ADDRV && !m->addr) { m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR)); /* @@ -668,6 +669,35 @@ static void reset_thr_limit(unsigned int bank) DEFINE_PER_CPU(unsigned, mce_poll_count); +static bool smca_log_poll_error(struct mce *m, u32 *status_reg) +{ + /* + * If this is a deferred error found in MCA_STATUS, then clear + * the redundant data from the MCA_DESTAT register. + */ + if (m->status & MCI_STATUS_VAL) { + if (m->status & MCI_STATUS_DEFERRED) + mce_wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); + + return true; + } + + /* + * If the MCA_DESTAT register has valid data, then use + * it as the status register. + */ + *status_reg = MSR_AMD64_SMCA_MCx_DESTAT(m->bank); + m->status = mce_rdmsrl(*status_reg); + + if (!(m->status & MCI_STATUS_VAL)) + return false; + + if (m->status & MCI_STATUS_ADDRV) + m->addr = mce_rdmsrl(MSR_AMD64_SMCA_MCx_DEADDR(m->bank)); + + return true; +} + static bool ser_log_poll_error(struct mce *m) { /* Log "not enabled" (speculative) errors */ @@ -684,8 +714,11 @@ static bool ser_log_poll_error(struct mce *m) return false; } -static bool log_poll_error(enum mcp_flags flags, struct mce *m) +static bool log_poll_error(enum mcp_flags flags, struct mce *m, u32 *status_reg) { + if (mce_flags.smca) + return smca_log_poll_error(m, status_reg); + /* If this entry is not valid, ignore it. */ if (!(m->status & MCI_STATUS_VAL)) return false; @@ -724,6 +757,7 @@ static bool log_poll_error(enum mcp_flags flags, struct mce *m) void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + u32 status_reg; struct mce m; int i; @@ -736,12 +770,14 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) if (!mce_banks[i].ctl || !test_bit(i, *b)) continue; + status_reg = mca_msr_reg(i, MCA_STATUS); + m.misc = 0; m.addr = 0; m.bank = i; barrier(); - m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 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Thu, 23 May 2024 10:56:59 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 8/9] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Date: Thu, 23 May 2024 10:56:40 -0500 Message-ID: <20240523155641.2805411-9-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523155641.2805411-1-yazen.ghannam@amd.com> References: <20240523155641.2805411-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|CH3PR12MB8849:EE_ X-MS-Office365-Filtering-Correlation-Id: d6ce2a04-4caf-40d7-200c-08dc7b40fd55 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|1800799015|82310400017|36860700004; X-Microsoft-Antispam-Message-Info: cH5cxJcj0mbjuhS2cx0GVFBAq535RqFuKcfJk9VoX8uSovTRoEZ/JjVMXBUB8fWtu2I1xMXkSkkVxhbxEU5ILUpSMBEf3FWexr8RZ8jkEXjPE6MOy9F3V1DQADyFmSvv6FXzMRscTK/IDMQtMV02fZCW4HXdFpt15oqiiluciHgVIFvNDqnxI22WnGIeXoZgiV3/XWxcKDzqfWslDVeZqcppFXjUvrxEPbfPsbzqGdq+Kms0bbB13WFMtdnappv0hrkUTYX4VOJMGDyXhqkLHIxp2fyFKppYxsiK68oQlxX0FvlUoP9+1zqgu9dsHmzuUouDZC5ocRRUJ0Wu65/8Hl3h50/XZaJlaZ068/Etcwy3BfWn5suivzXQrqq2qpHnrwhLQ+gk3Oe1D5MinqiJP3/gKXWS9680CqV3JoyCat9u0vSn+p2X12Aya+RH6zkPX5EIPzuNynxZY3BxNsWwoIrGFKfaamzkNfI6gLcJW3P9BO5SvCSMiJXhYNOxxckq9vmIv5DuiXGSlskzCnKk9Nk6juIMoJ353nUbiVM3gw4fkPcQ4HCDSlsBH8littLTQm4451fN20cIc0Uo8NfDIb0jHDuuEEhZ66wMNH0Gb6Fed2I1kNSZdwPZXqprpO4CXVWmV1ac/WE3NjspGTduOzhetR5rx+u371h086X/DwZhBsNwz2CkL10HTCHBBYlxChJ7mNhaIYk5J4vja4AGEVLXaYeYMhD38/T+xK8ABvmhJRPD3njdJGENGJDyxsacs/V7MicGlX1mJEnCR8eTgJl55ANpCZvDUjaVo0Gy9ss3YXK+05uJGlCU1mfOBwb3oHcgJjqDiLldtU1DO/yFry4unMe9RdwjiZh7y36f51jmfgZ7k/uYlKLhZo2J1oEmA6KkCkzE0TiY6e4+YRwoibZrBqz1VLjQECinz6D8DeApqnXWjOktJUKFvAbslZerjaocrzxDRjZ/8haJ0O94TRmuoyfBk8JZWoLSYAEFLwyuI/qOyVE9Ur/ZlWVPaHwQWQekT70C1xbjFPVZYRB+AKiV5/Q+DrZX6U2KnIilL2G9hRffWK5nQwzxATBaXRtbxUyo3/bC4Jj6zNTiDgHOxNsngTes7UrZH2aunKwRCTpkvXf1gxLcT3vJISVBQF6G0geUWsX0YpEvgTAMtcYktvdq8Gd75GKxTkYIrOoVL1rotnWU3uVuxloI/9dXARjEwK17Px8vMsYkaFcybEIzX3LdAM0z67NUk4ntd49FxJny2pQxjHnfbBRD2DLexgB0KQtkOQwE6x7gtFcr9YavYmqIJT4fbPkBIW1fLOpjpBBcx6saXwhPd5+v/14ILFAgNDdWbVDJ2NKFZSInO/oda2J06rDlfEHAyJc18GFBp3k3Wr4WKccDgNO6u884muaL X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(376005)(1800799015)(82310400017)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2024 15:57:03.7636 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6ce2a04-4caf-40d7-200c-08dc7b40fd55 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8849 Scalable MCA systems have a per-CPU register that gives the APIC LVT offset for the thresholding and deferred error interrupts. Currently, this register is read once to set up the deferred error interrupt and then read again for each thresholding block. Furthermore, the APIC LVT registers are configured each time, but they only need to be configured once per-CPU. Move the APIC LVT setup to the early part of CPU init, so that the registers are set up once. Also, this ensures that the kernel is ready to service the interrupts before the individual error sources (each MCA bank) are enabled. Apply this change only to SMCA systems to avoid breaking any legacy behavior. The deferred error interrupt is technically advertised by the SUCCOR feature. However, this was first made available on SMCA systems. Therefore, only set up the deferred error interrupt on SMCA systems and simplify the code. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 116 +++++++++++++++------------------- 1 file changed, 52 insertions(+), 64 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index c6594da95340..7acaa21e11e1 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -46,9 +46,6 @@ /* Deferred error settings */ #define MSR_CU_DEF_ERR 0xC0000410 #define MASK_DEF_LVTOFF 0x000000F0 -#define MASK_DEF_INT_TYPE 0x00000006 -#define DEF_LVT_OFF 0x2 -#define DEF_INT_TYPE_APIC 0x2 /* Scalable MCA: */ @@ -58,6 +55,8 @@ static bool thresholding_irq_en; static DEFINE_PER_CPU_READ_MOSTLY(mce_banks_t, mce_thr_intr_banks); static DEFINE_PER_CPU_READ_MOSTLY(mce_banks_t, mce_dfr_intr_banks); +static DEFINE_PER_CPU_READ_MOSTLY(bool, smca_thr_intr_enabled); +static DEFINE_PER_CPU_READ_MOSTLY(bool, smca_dfr_intr_enabled); static const char * const th_names[] = { "load_store", @@ -297,7 +296,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu) * APIC based interrupt. First, check that no interrupt has been * set. */ - if ((low & BIT(5)) && !((high >> 5) & 0x3)) { + if ((low & BIT(5)) && !((high >> 5) & 0x3) && + this_cpu_read(smca_dfr_intr_enabled)) { __set_bit(bank, this_cpu_ptr(mce_dfr_intr_banks)); high |= BIT(5); } @@ -389,6 +389,14 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) { int msr = (hi & MASK_LVTOFF_HI) >> 20; + /* + * On SMCA CPUs, LVT offset is programmed at a different MSR, and + * the BIOS provides the value. The original field where LVT offset + * was set is reserved. Return early here: + */ + if (mce_flags.smca) + return 0; + if (apic < 0) { pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, @@ -397,14 +405,6 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) } if (apic != msr) { - /* - * On SMCA CPUs, LVT offset is programmed at a different MSR, and - * the BIOS provides the value. The original field where LVT offset - * was set is reserved. Return early here: - */ - if (mce_flags.smca) - return 0; - pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); @@ -485,41 +485,6 @@ static int setup_APIC_mce_threshold(int reserved, int new) return reserved; } -static int setup_APIC_deferred_error(int reserved, int new) -{ - if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, - APIC_EILVT_MSG_FIX, 0)) - return new; - - return reserved; -} - -static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) -{ - u32 low = 0, high = 0; - int def_offset = -1, def_new; - - if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) - return; - - def_new = (low & MASK_DEF_LVTOFF) >> 4; - if (!(low & MASK_DEF_LVTOFF)) { - pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); - def_new = DEF_LVT_OFF; - low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); - } - - def_offset = setup_APIC_deferred_error(def_offset, def_new); - if ((def_offset == def_new) && - (deferred_error_int_vector != amd_deferred_error_interrupt)) - deferred_error_int_vector = amd_deferred_error_interrupt; - - if (!mce_flags.smca) - low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; - - wrmsr(MSR_CU_DEF_ERR, low, high); -} - static u32 smca_get_block_address(unsigned int bank, unsigned int block, unsigned int cpu) { @@ -565,7 +530,6 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, int offset, u32 misc_high) { unsigned int cpu = smp_processor_id(); - u32 smca_low, smca_high; struct threshold_block b; int new; @@ -585,18 +549,10 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, __set_bit(bank, this_cpu_ptr(mce_thr_intr_banks)); b.interrupt_enable = 1; - if (!mce_flags.smca) { - new = (misc_high & MASK_LVTOFF_HI) >> 20; - goto set_offset; - } - - /* Gather LVT offset for thresholding: */ - if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) - goto out; - - new = (smca_low & SMCA_THR_LVT_OFF) >> 12; + if (mce_flags.smca) + goto done; -set_offset: + new = (misc_high & MASK_LVTOFF_HI) >> 20; offset = setup_APIC_mce_threshold(offset, new); if (offset == new) thresholding_irq_en = true; @@ -604,7 +560,6 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, done: mce_threshold_block_init(&b, offset); -out: return offset; } @@ -673,6 +628,37 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) wrmsrl(MSR_K7_HWCR, hwcr); } +/* + * Enable the APIC LVT interrupt vectors once per-CPU. This should be done before hardware is + * ready to send interrupts. + * + * Individual error sources are enabled later during per-bank init. + */ +static void smca_enable_interrupt_vectors(struct cpuinfo_x86 *c) +{ + u8 thr_offset, dfr_offset; + u64 mca_intr_cfg; + + if (!mce_flags.smca || !mce_flags.succor) + return; + + if (c == &boot_cpu_data) { + mce_threshold_vector = amd_threshold_interrupt; + deferred_error_int_vector = amd_deferred_error_interrupt; + } + + if (rdmsrl_safe(MSR_CU_DEF_ERR, &mca_intr_cfg)) + return; + + thr_offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12; + if (!setup_APIC_eilvt(thr_offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, 0)) + this_cpu_write(smca_thr_intr_enabled, true); + + dfr_offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4; + if (!setup_APIC_eilvt(dfr_offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0)) + this_cpu_write(smca_dfr_intr_enabled, true); +} + /* cpu init entry point, called from mce.c with preempt off */ void mce_amd_feature_init(struct cpuinfo_x86 *c) { @@ -680,11 +666,16 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low = 0, high = 0, address = 0; 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Thu, 23 May 2024 10:56:59 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 9/9] x86/mce/amd: Support SMCA Corrected Error Interrupt Date: Thu, 23 May 2024 10:56:41 -0500 Message-ID: <20240523155641.2805411-10-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523155641.2805411-1-yazen.ghannam@amd.com> References: <20240523155641.2805411-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|DS0PR12MB8785:EE_ X-MS-Office365-Filtering-Correlation-Id: a117dfb4-6b72-4545-58cf-08dc7b40fd8e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|1800799015|36860700004|376005; X-Microsoft-Antispam-Message-Info: /JslQUYhkV8M6PK+vPMSHGCQGluNiigNWEvm/uI+FO8VXcmPHu/vUyLfqz1VXJIiu+Eujm88e9BLyuoeBTR+gM5OKXe9/xsAZp6Z1oVVz+1s35tOD7Ka7xRWUz3TK71TH+7ENJUYUCOIScjGLIS+Kyjdq71RTqoF0s0sw0IF40DUWoi6JuGLjLBZ8kBM9OnbBfFgP+wKzOSJq6z2OWYjR2i4tT0oE3Vvmx6p4J83ZzjKSQgla42Ci7a0xcQvj5BwaBkc72cdwLoQUMH0rbMGpO77KxIhlDNswezlRRBX+aSC4OqlpfMGBpVWDrilbEyxKvSeY0KduB2M6dgBlmqHDpW6HDLoKAPqZ8DtyB61VjHS/dntGT+Q1c7/jsDJL7S2/0BjNOULhb2Od8S7ZDXycFkfSZu55WEmNXX9UGDoevNNlgRuwQkXRoiedjLlC2N2cY2V0DtfDztRkLcuCe476w79KwTpiqbHDKymO37yXjD5Gkfz/7tQrcQ1Lyvems8JdAC3jKB6slMO78WtfEYR6/OX4MYpczYXbpA/5uJG+UinFjng5EXiaDMvO6HJ94WitMBlXUbeVcpX0uI50+bGOS4pZGCfEvu4HmHUzsf/Hd0wn7B7n5tj0jLwS6sa1Sk3swYCIxSdrQkPCwGjeUg11RpwwJqJuLPgjOSunz/9+Egi7LCU/tREOsELEyXdhn+vTz75vo194IAEsCdm6K8AjzpOd0UZ20yaO0UtvUl5Tun5Q66TCxkivvTtc5YgA8ACrlLjuL/dhdXlZ/qk8HELtDDNfDr2MFmaObvrghFJ/3eBoMSP2TeB3VdBH3LHei7zFAJD4a9kLv5gQr+gf6IwObi9jJtGsaV4zuYJ4xHrMVW3LR8rs+33DiWpIh2PAqkF1OLMRpLexgC1rPhM/mllmBFR526zK7+DnZIiKC5C1oPbHP58KKQk6HpZVMgXELM6hpL8eyEevttzlO0DC3Nbgz/9VPqDXtEBEexbohmrphsaTW0AfmRySe7gvL29orcx2wjXO2djDF0TF76flQyqq5cf+SI3frz1q6fxtl9lNXCvh8EScg0JhkH0GuM1ONPk0IQQ93FNYieoA0YDdL5LbIqIReTw/Qjc36yaJ1/HUcP1TPOQoXlcoCQ7LLAoVbgaJRBgBMwPYEIJefvS7fq0xQUi7+gRt9XQLSUQ5Po4pX8pk5ze5sHOWuW3li7f51FWysI0Yp0ZMp5OnntRzJtmn/cJAroDnAwGM5DRuvWPAlXuPoVgvlmfMSJzWVMxOTGdVNoyN05nMAOGwH7AP7GaexSWPlTZrbF11yMYnfUaYuv3h2yUztLqjMjMdwueHcIg0CJuAANu3MfoYpDdTvglR5kU58L9+qJeELsQHRYkmrSRn+xgXV41WBfrfr35dkyR X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(82310400017)(1800799015)(36860700004)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2024 15:57:04.1386 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a117dfb4-6b72-4545-58cf-08dc7b40fd8e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8785 AMD systems optionally support MCA thresholding which provides the ability for hardware to send an interrupt when a set error threshold is reached. This feature counts errors of all severities, but it is commonly used to report correctable errors with an interrupt rather than polling. Scalable MCA systems allow the Platform to take control of this feature. In this case, the OS will not see the feature configuration and control bits in the MCA_MISC* registers. The OS will not receive the MCA thresholding interrupt, and it will need to poll for correctable errors. A "corrected error interrupt" will be available on Scalable MCA systems. This will be used in the same configuration where the Platform controls MCA thresholding. However, the Platform will now be able to send the MCA thresholding interrupt to the OS. Check for the feature bit in the MCA_CONFIG register and confirm that the MCA thresholding interrupt handler is already enabled. If successful, set the feature enable bit in the MCA_CONFIG register to indicate to the Platform that the OS is ready for the interrupt. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 7acaa21e11e1..cc1527ff76fc 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -302,6 +302,11 @@ static void smca_configure(unsigned int bank, unsigned int cpu) high |= BIT(5); } + if ((low & BIT(10)) && this_cpu_read(smca_thr_intr_enabled)) { + __set_bit(bank, this_cpu_ptr(mce_thr_intr_banks)); + high |= BIT(8); + } + this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); wrmsr(smca_config, low, high);