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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:21 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Mayuresh Chitale , Samuel Holland , Samuel Ortiz , Evan Green , Xiao Wang , Alexandre Ghiti , Andrew Morton , Kemeng Shi , "Mike Rapoport (IBM)" , Jisheng Zhang , "Matthew Wilcox (Oracle)" , Charlie Jenkins , Leonardo Bras , linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 1/5] RISC-V: Detect and Enable Svadu Extension Support Date: Fri, 24 May 2024 18:33:01 +0800 Message-Id: <20240524103307.2684-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240524_033323_315035_1E3AAA68 X-CRM114-Status: GOOD ( 13.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Svadu is a RISC-V extension for hardware updating of PTE A/D bits. In this patch we detect Svadu extension support from DTB and enable it with SBI FWFT extension. Also we add arch_has_hw_pte_young() to enable optimization in MGLRU and __wp_page_copy_user() if Svadu extension is available. Co-developed-by: Jinyu Tang Signed-off-by: Jinyu Tang Signed-off-by: Yong-Xuan Wang Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/pgtable.h | 8 +++++++- arch/riscv/kernel/cpufeature.c | 11 +++++++++++ 5 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index be09c8836d56..30fa558ee284 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -34,6 +34,7 @@ config RISCV select ARCH_HAS_PMEM_API select ARCH_HAS_PREPARE_SYNC_CORE_CMD select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_HW_PTE_YOUNG select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..2ac270ad4acd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -194,6 +194,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_ADUE (_AC(1, ULL) << 61) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..8d539e3f4e11 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,7 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SVADU 75 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 9f8ea0e33eb1..1f1b326ccf63 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -117,6 +117,7 @@ #include #include #include +#include #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) @@ -285,7 +286,6 @@ static inline pte_t pud_pte(pud_t pud) } #ifdef CONFIG_RISCV_ISA_SVNAPOT -#include static __always_inline bool has_svnapot(void) { @@ -621,6 +621,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) return __pgprot(prot); } +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); +} + /* * THP functions */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ed2359eae35..b023908c5932 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -93,6 +93,16 @@ static bool riscv_isa_extension_check(int id) return false; } return true; + case RISCV_ISA_EXT_SVADU: + if (sbi_probe_extension(SBI_EXT_FWFT) > 0) { + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_SET, SBI_FWFT_PTE_AD_HW_UPDATING, + 1, 0, 0, 0, 0); + + return ret.error == SBI_SUCCESS; + } + return false; case RISCV_ISA_EXT_INVALID: return false; } @@ -301,6 +311,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_SUPERSET(svadu, RISCV_ISA_EXT_SVADU, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), From patchwork Fri May 24 10:33:02 2024 Content-Type: text/plain; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:26 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 2/5] dt-bindings: riscv: Add Svadu Entry Date: Fri, 24 May 2024 18:33:02 +0800 Message-Id: <20240524103307.2684-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240524_033329_285943_3C1A4996 X-CRM114-Status: UNSURE ( 7.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add an entry for the Svadu extension to the riscv,isa-extensions property. Signed-off-by: Yong-Xuan Wang Acked-by: Conor Dooley Reviewed-by: Andrew Jones --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..598a5841920f 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -153,6 +153,12 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware updating + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request + #25 from ved-rivos/ratified") of riscv-svadu. + - const: svinval description: The standard Svinval supervisor-level extension for fine-grained From patchwork Fri May 24 10:33:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13673054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA255C25B79 for ; Fri, 24 May 2024 10:33:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bdSwZXexAU25k0u6xFdiGLFcMJCiDn5mhmgmcBfk2jw=; b=abLkouIMqIQTF3 LxJKX0+v6Fnopl56Vz/fm4FleLMHEtTbIMrduVP/t2+CyDDW8K0gi6QhGhfBsDMsWLunBPjlNsB16 eLLbGdbtPZ1P7OeKoDM/mtgDttpKK87/h1L77A8m+5t2cZOekheQ5mCLMG460OttvPnF/rq9UiWk6 8qVHeuRvrISbvNkb9F3S8AvZm409SRdF1DZJknwVj1I+uB/6dv9pxnhLY/jhI8p4gvNOnaXScn/ts 9G86/w1eZaUTaq4dgdnPANEf4zZjdKfyOJmzyzHJLan5Rw7GIQsa+MLRvOAT0X2zxnxhhGFihbVfK o+hHbkFjTpZRKKNMNv4w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sASF0-00000008gBu-2nY5; Fri, 24 May 2024 10:33:38 +0000 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sASEv-00000008g7O-0SZS for linux-riscv@lists.infradead.org; Fri, 24 May 2024 10:33:34 +0000 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2bdd8968dabso1443123a91.3 for ; Fri, 24 May 2024 03:33:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1716546811; x=1717151611; darn=lists.infradead.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=jd1Ys62vbvg6Kc0O0Y86nMWaJ5oNcjAjjfmW/HddUAI=; b=OmuKI8AkHOmXCfocmfrc2Pn484eU3Wr0pCUlROmyZHZyOHWtbZW30fDd+VdcvMWEwj mRlpWLSqdqHvUFTpcwe6fUBYX7elCPR9k4MG4CnooREl6IDVYi/FkdN2F+lZ6kyqIr8b +sL7SOgRVFInk1uKacgYpqwl2p6bFFmmhCDoxFxv81gJghTbPn1rLTw7jFzdbrHHc6if Ud19yZcG+HDY25It5JMRuYXsDU5lMe9gy9xtkHlqyZsOUJQjxD3QViPZkb+7kXeBZG24 fCci7BEx+ggQvp+sSIqmMk7CDLSC+22IZBkZOkUgU07oled/6qkcM0blae2hMPvJ/RKQ SVnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716546811; x=1717151611; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jd1Ys62vbvg6Kc0O0Y86nMWaJ5oNcjAjjfmW/HddUAI=; b=NviMy/yj70avsZWl5AIQSWK1kKGeqVLl0nlmDAtrIxENLG+eE9MblyKFLeSUVPEv28 5OuaUEol0tRKvGqYfq3WrA8EhfMtxpbFW2QLX2WoJJtQjN8PJoZ7BsXZiDFvm2YHnWrR H1SZLqISxEKhqQxaK8+JtnMhurAMuwSgbmXepxd3DB8eU/Xo2hGh3+qQwlXFdidw+fW/ WDpGptja7uFgCLYxwErVY2V6hMZHKsR07qXRZ9j/mwrsXj9G2+J8xKDNu8ztkc0YELS/ u+g1Ob5WmRSjq4gHVqosjjA0SzamE+8JMrvmZ/vJdmlq1QPuA/lWP5vZEbC68ATLRfZa 1zsQ== X-Gm-Message-State: AOJu0YxYhZb7IA5Cs6WpIdSRmplRfnciUUoI99JTdpr4nj8W+YqW7qqz Kd+BMQZmdMKiJ6AQqH3jMQCgPfHZuq1tQuBune62d3cm+cMeSCE5efUBBLDIAxH5iYzJfmq606E yEPBgz3l1KSDlsOx8vbaM7UmL3YZY3hRMBRl/r0S6ICgfEb26eivOt/5eZbT3opOTJ5DoFTouCZ cFPCZ8A7vzq80sLfCxRb/NtmOxMILMhZiurm2sEGKfZC8wcUdOPQoYH7Y= X-Google-Smtp-Source: AGHT+IEqHFEgIIblN+tGvoPCOSPByLGwZDHSVVvoF8yH7h0Gq/GADB1ishTF2VIIM9YemQrEgoARmQ== X-Received: by 2002:a17:90a:db54:b0:2be:d1:e7e1 with SMTP id 98e67ed59e1d1-2bf5e173c71mr1678283a91.10.1716546811417; Fri, 24 May 2024 03:33:31 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:31 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 3/5] RISC-V: KVM: Add Svadu Extension Support for Guest/VM Date: Fri, 24 May 2024 18:33:03 +0800 Message-Id: <20240524103307.2684-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240524_033333_192507_2796692A X-CRM114-Status: UNSURE ( 9.20 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svadu extension for Guest/VM. The ADUE bit in henvcfg is cleared by default for backward-compatibility. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index a59a8448deea..bcf99264560d 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZFA, KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, + KVM_RISCV_ISA_EXT_SVADU, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 994adc26db4b..4166665e215d 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -37,6 +37,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), From patchwork Fri May 24 10:33:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13673055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 804E1C25B74 for ; Fri, 24 May 2024 10:33:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SdSe3q2APdz/I2YxKW+PuLyNx0eV4XSOTZ9b6zut8sI=; b=U/BVZXMtT52tRA EFk3PyUdSOGssUzgJ6Z2I921K6pzAhqFyGnfbkL3JMm70lx757yfbW4Sm2bN90H1vp+a5rNWMalsK EiikKxztgCTSpTN+ALzppQWyPXrsVIpGth7BV34pbhMc3S44gn53zTG29qar44n2JCTGlbHzZlTDu sTTjsEijW3F1n1OlKdqSAZwjj4aeb1kNmZI+DSFtApecKWLa3Zu1C0/A0/JCOk16Z1/i6mDssrA6Z Jms+QcxO1IjANUyzI9vQ8sGmeRA2J+o2p2bvh9JjMDpThndQPwZrJmC6tpcYcTq2dCkRGdOAwslry 8kmjw4f6Q+YQ99hqnghQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sASF5-00000008gGN-1NfP; Fri, 24 May 2024 10:33:43 +0000 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sASF0-00000008gAk-3AIR for linux-riscv@lists.infradead.org; Fri, 24 May 2024 10:33:40 +0000 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-681ad26f277so567413a12.3 for ; Fri, 24 May 2024 03:33:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1716546816; x=1717151616; darn=lists.infradead.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=WZ6BYwn5mOMy3jrtkhWqLvXB1lQ/8oP4LPFGWsTQioU=; b=IiULeMMRGg8zjilqNzS6E+dCMzTQ4bO3/tm5U3JRbAluh5TkjBjLBFfLP2wUqheBgw YfLzWwiHGz4P1IYdDUfdPe9/ZkOVv3xXTL6tV7Ti6zr/LQsUFS+YrNYtWjDE8YMHP+Fw 6JOwYsJtOyskhp9iE+uYuU7x30JBQ5v0qGX900haKuP/fTKrFg92ivVl2T2YdLt4VZxw jMs8/MqzwR7Mo2DAd/E5TmB9MMpHKnSdx0aycEjrga3rMtrvPQzxW4ksG6OeRIKcBTif 2DLCjZ7QOKIY8zuQiYmLzAPT7QPwR93B0JoI3MuWkBjak/gHSUSqPHmy5hOlNu1cVyl8 6Alg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716546816; x=1717151616; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WZ6BYwn5mOMy3jrtkhWqLvXB1lQ/8oP4LPFGWsTQioU=; b=AFw6lG/VMCFDnGaPAz2WKq8v0BnN07rAPPR7b+74A4nPSrEYkLzxXYKajYIqevJHQu DP0z6zQKgQf0X6dNet4ncZfIh+dz/RCKFIxQ+L2gGvI7Dfmnq8Ub8c4khc9lBFX+kMHM 2daXZKbFQWuzCvBtBApB4FD0wh43swTOFG37Ek3cnDsxaSDLSzrNwvvJ6NQUxUZm24dM RVH2uP9vzeB7xX7voWwF6vx4tEGF3PuKY1Qcg2Yf2KjiKGt3mZuFe74GyfUTk/7jiMZL dWYLL1UTtHTtu26Io+rZApYcyskDrgT+x7c75T2flfzm+6JpmhRi37fEjM+kdxREWI4Y uyhw== X-Gm-Message-State: AOJu0YzC7d4uMy1y7neEvnjrDA2wwOK8a+jejN3KGSpyLDIXr9lrCAxT SdZtuiWAV8DEQGdwdicQQckjy7cI6L7ve5qSuZYB9C1VHaopTyfO7F2moB3p7QSLdN7MTknvVHh 3TVW7OOcQs26W8JzCZU+xwmCZH6xtkngT+AdwbzDvbytDe8YFWrbtNa7D3gVxDxvpe17j0yJgVn 8oU7UxV22TZPl3rXj1U++o0r8JY+bZxP1c9hq0ndFkKdsoCpd0tpIMyDM= X-Google-Smtp-Source: AGHT+IHwYRl01Pr85mA3t2HEOvg+sKlaLLf3SKTeqlscw+r+oqPR6B2j0Lab23cBYZRY16JbGWy4mw== X-Received: by 2002:a05:6a20:6a2c:b0:1af:f23c:804a with SMTP id adf61e73a8af0-1b212e20716mr2197510637.38.1716546815854; Fri, 24 May 2024 03:33:35 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:35 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 4/5] RISC-V: KVM: add support for SBI_FWFT_PTE_AD_HW_UPDATING Date: Fri, 24 May 2024 18:33:04 +0800 Message-Id: <20240524103307.2684-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240524_033338_845994_290BC292 X-CRM114-Status: GOOD ( 12.97 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add support for SBI_FWFT_PTE_AD_HW_UPDATING to set the PTE A/D bits updating behavior for Guest/VM. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 2 +- arch/riscv/kvm/vcpu_sbi_fwft.c | 38 +++++++++++++++++++++- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h index 7b7bcc5c8fee..3614a44e0a4a 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h @@ -11,7 +11,7 @@ #include -#define KVM_SBI_FWFT_FEATURE_COUNT 1 +#define KVM_SBI_FWFT_FEATURE_COUNT 2 struct kvm_sbi_fwft_config; struct kvm_vcpu; diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 89ec263c250d..14ef74023340 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -71,6 +71,36 @@ static int kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, return SBI_SUCCESS; } +static int kvm_sbi_fwft_adue_supported(struct kvm_vcpu *vcpu) +{ + if (!riscv_isa_extension_available(vcpu->arch.isa, SVADU)) + return SBI_ERR_NOT_SUPPORTED; + + return 0; +} + +static int kvm_sbi_fwft_set_adue(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + unsigned long value) +{ + if (value) + vcpu->arch.cfg.henvcfg |= ENVCFG_ADUE; + else + vcpu->arch.cfg.henvcfg &= ~ENVCFG_ADUE; + + return SBI_SUCCESS; +} + +static int kvm_sbi_fwft_get_adue(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + unsigned long *value) +{ + if (!riscv_isa_extension_available(vcpu->arch.isa, SVADU)) + return SBI_ERR_NOT_SUPPORTED; + + *value = !!(vcpu->arch.cfg.henvcfg & ENVCFG_ADUE); + + return SBI_SUCCESS; +} + static struct kvm_sbi_fwft_config * kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t feature) { @@ -177,7 +207,13 @@ static const struct kvm_sbi_fwft_feature features[] = { .supported = kvm_sbi_fwft_misaligned_delegation_supported, .set = kvm_sbi_fwft_set_misaligned_delegation, .get = kvm_sbi_fwft_get_misaligned_delegation, - } + }, + { + .id = SBI_FWFT_PTE_AD_HW_UPDATING, + .supported = kvm_sbi_fwft_adue_supported, + .set = kvm_sbi_fwft_set_adue, + .get = kvm_sbi_fwft_get_adue, + }, }; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:40 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 5/5] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt Date: Fri, 24 May 2024 18:33:05 +0800 Message-Id: <20240524103307.2684-6-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240524_033342_398395_9C03F04D X-CRM114-Status: UNSURE ( 8.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Update the get-reg-list test to test the Svadu Extension is available for guest OS. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index b882b7b9b785..3e71b7e40dbf 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -44,6 +44,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT: @@ -409,6 +410,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -932,6 +934,7 @@ KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D); KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); +KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); @@ -987,6 +990,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_h, &config_smstateen, &config_sstc, + &config_svadu, &config_svinval, &config_svnapot, &config_svpbmt,