From patchwork Fri May 24 20:00:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Zide" X-Patchwork-Id: 13673606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD9E5C25B79 for ; Fri, 24 May 2024 20:02:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sAb6J-0002Ir-EF; Fri, 24 May 2024 16:01:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sAb63-00025z-2V; Fri, 24 May 2024 16:01:05 -0400 Received: from mgamail.intel.com ([192.198.163.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sAb5v-00051T-BG; Fri, 24 May 2024 16:00:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716580851; x=1748116851; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TxxJnHMBaLnho+/05QzctY86Y8OJz5CyPdX6d6Cev54=; b=mpc7+m/xQcJ6WPiCT51isNdMEuCxTL4UxaC0YY3gkwZIx7dvZBul7Yy/ mTgKbMliNpxJONpwDb3fTlgRAmldT4Mo2f/rghn5FS37TyGq87wKjBdOt kc1p9BwCPrWSBeR0BqremjPS+XLPBK3pYjYFeemX5ZeQj2gAfAHTUONxc AvdO5O7j5sBMgQQKhA3Qg/h1TdKIZIZELYofw4ZwR+Zutx9lSfjvRpOox BM1eSVP35KqBdq7szE5VT5zj1OIAzf/6GX2R9h1PuZidye/P/YWvrUJmn WXO1Nobucpd7w9oZmxtoydcKLrlrpWILUx508SrwZSxHtrsyLEMM7l6zC w==; X-CSE-ConnectionGUID: fDUc9Ub2T8GW/KyPXa54dA== X-CSE-MsgGUID: TUBMBPzISOm312cGEK8guQ== X-IronPort-AV: E=McAfee;i="6600,9927,11082"; a="15918263" X-IronPort-AV: E=Sophos;i="6.08,186,1712646000"; d="scan'208";a="15918263" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 13:00:46 -0700 X-CSE-ConnectionGUID: PG9RzVkzT4We7qa5u0gq5A== X-CSE-MsgGUID: i5LmdFabSFm3uuxpa4R3OA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,186,1712646000"; d="scan'208";a="39108906" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.100]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 13:00:46 -0700 From: Zide Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mst@redhat.com, thuth@redhat.com, cfontana@suse.de, xiaoyao.li@intel.com, qemu-trivial@nongnu.org, Zide Chen Subject: [PATCH V2 1/3] vl: Allow multiple -overcommit commands Date: Fri, 24 May 2024 13:00:15 -0700 Message-Id: <20240524200017.150339-2-zide.chen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240524200017.150339-1-zide.chen@intel.com> References: <20240524200017.150339-1-zide.chen@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Both cpu-pm and mem-lock are related to system resource overcommit, but they are separate from each other, in terms of how they are realized, and of course, they are applied to different system resources. It's tempting to use separate command lines to specify their behavior. e.g., in the following example, the cpu-pm command is quietly overwritten, and it's not easy to notice it without careful inspection. --overcommit mem-lock=on --overcommit cpu-pm=on Fixes: c8c9dc42b7ca ("Remove the deprecated -realtime option") Suggested-by: Thomas Huth Signed-off-by: Zide Chen Reviewed-by: Thomas Huth Reviewed-by: Zhao Liu --- v2: Thanks to Thomas' suggestion, changed to this better approach, which is more generic and can handle situations like: "enabled the option in the config file, and now you'd like to disable it on the command line again". system/vl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/system/vl.c b/system/vl.c index a3eede5fa5b8..dfa6cdd9283b 100644 --- a/system/vl.c +++ b/system/vl.c @@ -3545,8 +3545,8 @@ void qemu_init(int argc, char **argv) if (!opts) { exit(1); } - enable_mlock = qemu_opt_get_bool(opts, "mem-lock", false); - enable_cpu_pm = qemu_opt_get_bool(opts, "cpu-pm", false); + enable_mlock = qemu_opt_get_bool(opts, "mem-lock", enable_mlock); + enable_cpu_pm = qemu_opt_get_bool(opts, "cpu-pm", enable_cpu_pm); break; case QEMU_OPTION_compat: { From patchwork Fri May 24 20:00:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Zide" X-Patchwork-Id: 13673604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBB3FC41513 for ; Fri, 24 May 2024 20:02:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sAb6H-0002Gb-7g; Fri, 24 May 2024 16:01:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sAb67-0002AO-VX; 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a="15918266" X-IronPort-AV: E=Sophos;i="6.08,186,1712646000"; d="scan'208";a="15918266" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 13:00:46 -0700 X-CSE-ConnectionGUID: R987icKQR22Acv/yRV1Dkg== X-CSE-MsgGUID: 8ohV8JULSo+ZYahDIuu+ag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,186,1712646000"; d="scan'208";a="39108910" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.100]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 13:00:46 -0700 From: Zide Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mst@redhat.com, thuth@redhat.com, cfontana@suse.de, xiaoyao.li@intel.com, qemu-trivial@nongnu.org, Zide Chen Subject: [PATCH V2 2/3] target/i386: call cpu_exec_realizefn before x86_cpu_filter_features Date: Fri, 24 May 2024 13:00:16 -0700 Message-Id: <20240524200017.150339-3-zide.chen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240524200017.150339-1-zide.chen@intel.com> References: <20240524200017.150339-1-zide.chen@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org cpu_exec_realizefn which calls the accel-specific realizefn may expand features. e.g., some accel-specific options may require extra features to be enabled, and it's appropriate to expand these features in accel- specific realizefn. One such example is the cpu-pm option, which may add CPUID_EXT_MONITOR. Thus, call cpu_exec_realizefn before x86_cpu_filter_features to ensure that it won't expose features not supported by the host. Fixes: 662175b91ff2 ("i386: reorder call to cpu_exec_realizefn") Suggested-by: Xiaoyao Li Signed-off-by: Zide Chen --- target/i386/cpu.c | 24 ++++++++++++------------ target/i386/kvm/kvm-cpu.c | 1 - 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bc2dceb647fa..a1c1c785bd2f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7604,6 +7604,18 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) } } + /* + * note: the call to the framework needs to happen after feature expansion, + * but before the checks/modifications to ucode_rev, mwait, phys_bits. + * These may be set by the accel-specific code, + * and the results are subsequently checked / assumed in this function. + */ + cpu_exec_realizefn(cs, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { @@ -7625,18 +7637,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) x86_cpu_set_sgxlepubkeyhash(env); - /* - * note: the call to the framework needs to happen after feature expansion, - * but before the checks/modifications to ucode_rev, mwait, phys_bits. - * These may be set by the accel-specific code, - * and the results are subsequently checked / assumed in this function. - */ - cpu_exec_realizefn(cs, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { g_autofree char *name = x86_cpu_class_get_model_name(xcc); error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index f76972e47e61..3adcedf0dbc3 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -50,7 +50,6 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) * nothing else has been set by the user (or by accelerators) in * cpu->ucode_rev and cpu->phys_bits, and updates the CPUID results in * mwait.ecx. - * This accel realization code also assumes cpu features are already expanded. * * realize order: * From patchwork Fri May 24 20:00:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Zide" X-Patchwork-Id: 13673605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F8E1C25B7D for ; Fri, 24 May 2024 20:02:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sAb6K-0002JB-02; Fri, 24 May 2024 16:01:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sAb67-0002AN-VX; Fri, 24 May 2024 16:01:05 -0400 Received: from mgamail.intel.com ([192.198.163.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sAb65-00050y-8Q; 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24 May 2024 13:00:47 -0700 X-CSE-ConnectionGUID: 8eAWJbomQI6p/IR+TlvkVA== X-CSE-MsgGUID: pS5GDOZTTWK8qgYDfYh2nA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,186,1712646000"; d="scan'208";a="39108914" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.100]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 13:00:47 -0700 From: Zide Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, mst@redhat.com, thuth@redhat.com, cfontana@suse.de, xiaoyao.li@intel.com, qemu-trivial@nongnu.org, Zide Chen Subject: [PATCH V2 3/3] target/i386: Move host_cpu_enable_cpu_pm into kvm_cpu_realizefn() Date: Fri, 24 May 2024 13:00:17 -0700 Message-Id: <20240524200017.150339-4-zide.chen@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240524200017.150339-1-zide.chen@intel.com> References: <20240524200017.150339-1-zide.chen@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.198.163.13; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org It seems not a good idea to expand features in host_cpu_realizefn, which is for host CPU only. Additionally, cpu-pm option is KVM specific, and it's cleaner to put it in kvm_cpu_realizefn(), together with the WAITPKG code. Fixes: f5cc5a5c1686 ("i386: split cpu accelerators from cpu.c, using AccelCPUClass") Signed-off-by: Zide Chen --- target/i386/host-cpu.c | 12 ------------ target/i386/kvm/kvm-cpu.c | 11 +++++++++-- 2 files changed, 9 insertions(+), 14 deletions(-) diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c index 280e427c017c..8b8bf5afeccf 100644 --- a/target/i386/host-cpu.c +++ b/target/i386/host-cpu.c @@ -42,15 +42,6 @@ static uint32_t host_cpu_phys_bits(void) return host_phys_bits; } -static void host_cpu_enable_cpu_pm(X86CPU *cpu) -{ - CPUX86State *env = &cpu->env; - - host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, - &cpu->mwait.ecx, &cpu->mwait.edx); - env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; -} - static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu) { uint32_t host_phys_bits = host_cpu_phys_bits(); @@ -83,9 +74,6 @@ bool host_cpu_realizefn(CPUState *cs, Error **errp) X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; - if (cpu->max_features && enable_cpu_pm) { - host_cpu_enable_cpu_pm(cpu); - } if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { uint32_t phys_bits = host_cpu_adjust_phys_bits(cpu); diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 3adcedf0dbc3..197c892da89a 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -64,9 +64,16 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) * cpu_common_realizefn() (via xcc->parent_realize) */ if (cpu->max_features) { - if (enable_cpu_pm && kvm_has_waitpkg()) { - env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG; + if (enable_cpu_pm) { + if (kvm_has_waitpkg()) { + env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG; + } + + host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, + &cpu->mwait.ecx, &cpu->mwait.edx); + env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; } + if (cpu->ucode_rev == 0) { cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,