From patchwork Mon May 27 23:51:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pengfei Li X-Patchwork-Id: 13674743 Received: from EUR02-VI1-obe.outbound.protection.outlook.com (mail-vi1eur02on2057.outbound.protection.outlook.com [40.107.241.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1AAC2E403; Mon, 27 May 2024 07:50:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.241.57 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796227; cv=fail; b=D34uI6y4EXuooU6AZUW+/4jsPue4hicfM8PLIuStSo1aTVnJC3oMBCYc2YqF6QDdDo4yXzLPU174Xyokvjm1BPlxWHH+4hp5d6AEk6KRFGEejBUuMPv1SwLzlKJkSM1d1L1vZrtKe4frToFjUTWNpawiwOOFy7DD0JsKp5Pl4M0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796227; c=relaxed/simple; bh=WR0NNIeUX8GHVKJcjOaokqTy/DiyjvUNxKymcBOOY1g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=KShF1nnLO9WXxhhoHoWKl0j1gJ3S5HiJmxbTjjDY65rGPymalMJAIvL8iz5ADThn/YFC7FfxjQj//DXmdpGBdXJGYLozF1vDxcYLhCVZ/gpV1xenVZrTitj799C7JownXi8Hy/NeIIJ50RIPK/qyJQ6OhW2AFJaYJekde0i1GWQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=g0yZpjnQ; arc=fail smtp.client-ip=40.107.241.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="g0yZpjnQ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Qlf5cQtNmGm/vUcibD3RMxVFjwHfVONAO/zWS87Rzb1XIoRKYVV2P4n5xkUmKggB4odo/Ieq+apB8rwYefnQOYJAHuf1EUgILMzDZR2ROhFBbli3nOt8uDwx/5pAZTnL1LoFB1gHjJfhK7NOYwLbqjtEdWd6L+Ii/tW1Irk+GrZ+YahYK9ELSEt9VzuJM77ekdFOBEMydwsTcXIxIrkfz9NKR3uSWddI8PlJSiqt/ofSCP1oqEtNizGmtIDCfaFOY1cOKb6oyOwcZwOsoYJ9vF9pbNxdi2mKLzJNYVWEwx7ZyZtSfiwvRTxaWewyRV8cTvFSjcdtLfTB8TgOefBTRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IuwIN6qRtf7KJGto7VvZ0CDP/XVS0gIl4Kbb06ilxg0=; b=fBymHh7Jmz6aC8H7SSMLFjg4jNxeKyuJZVzUdGfoftG0do04YcaXfVWC9oukM6n8dfF8VVongv28k8M8j1KnD1ODWr2GXTNypkurn8lab3BrRwtSkK+U0YzpbnfXPrBswuJIx73x+E5V7iGB2g7wT4lw6dkurtFUo/Wj1eiiNpNSPNuwazatzrYB14ousQbXpZCf805f6T+/FCkt1iPOTUF4ws8kt+58KPFnHIiwI7RJYbv8YousKxyyk9OxMJc+PeTcWIpYrG8WHzlDegO7p2YNKi1AfpFEnieG3dXZVhS0bjCSShDxCK8edzkS9FTopkWHfOrryUpXuvQ690+jxw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IuwIN6qRtf7KJGto7VvZ0CDP/XVS0gIl4Kbb06ilxg0=; b=g0yZpjnQq+FhfHdqb5rpXvKcTU+vEo1V4ILFiT8rHeKJSr6Q7ydzY+ZtpepcmopjDH29ycdlCG5RvjsMLuGykMiiZ2jrH71Eceva0lZZ7TBUx50MNE+wUaeWAzZ+bggg4ojSnyMnujDBl+x3xOql9cgZsZ4exLa4ee7nBttMkWg= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) by PAXPR04MB8781.eurprd04.prod.outlook.com (2603:10a6:102:20c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.29; Mon, 27 May 2024 07:50:22 +0000 Received: from DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84]) by DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84%4]) with mapi id 15.20.7611.025; Mon, 27 May 2024 07:50:21 +0000 From: Pengfei Li To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, ye.li@nxp.com, peng.fan@nxp.com, aisheng.dong@nxp.com, frank.li@nxp.com Cc: tharvey@gateworks.com, alexander.stein@ew.tq-group.com, gregor.herburger@ew.tq-group.com, hiago.franco@toradex.com, joao.goncalves@toradex.com, hvilleneuve@dimonoff.com, Markus.Niebel@ew.tq-group.com, m.felsch@pengutronix.de, m.othacehe@gmail.com, bhelgaas@google.com, leoyang.li@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, pengfei.li_1@nxp.com Subject: [PATCH 1/5] dt-bindings: clock: Add i.MX91 clock support Date: Mon, 27 May 2024 16:51:54 -0700 Message-Id: <20240527235158.1037971-2-pengfei.li_1@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240527235158.1037971-1-pengfei.li_1@nxp.com> References: <20240527235158.1037971-1-pengfei.li_1@nxp.com> X-ClientProxiedBy: SG2PR01CA0118.apcprd01.prod.exchangelabs.com (2603:1096:4:40::22) To DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB8PR04MB7065:EE_|PAXPR04MB8781:EE_ X-MS-Office365-Filtering-Correlation-Id: ee18c940-50e7-4a0a-b944-08dc7e21a891 X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|52116005|376005|7416005|1800799015|38350700005|921011; X-Microsoft-Antispam-Message-Info: 4/RFZBW3JT8OIXktEfd0uv5g+Q059Fp/ONoLSeBZv44T2X7H3TA+pfYjg8BEYDMxjPkXSoDghE2qb8XcjB1D2N7K//7vfSbV+XW6BSfU4MZCyH8vG4D+pGd6MgqjZ/StAOe9b6DZcyHu2sXBA5Oetwox9W9mWrVAh9OM0tZ5dGlv7myeSMXNHWyNnSSvRFRUzJP/w0SyRNg/GW/sgmzTIdigpBJjKrAHiiqXzGbYeoniTbxeDra7YJvWpwOhqIJAL+/XLiKKzH4l1atsr+oMhoaKqRiYqHjCgcIbB+4HZOpaF9CbWwHXo5j2qhm5E/325uIKWjN19NMS0WnV+zAwghy/gUwxHpE0TgKz3rbkvAdMES86UGPJmGYex1ITefxGKwMDrzUFVoQUgRxrnCc+xYeTa62JRKl9QSDcPpKpHi3MNCYG5eEDyDGWFOZdqZ+p8LUvd/Uktsxr2Z+R9yqlJLsJ0+q9ZcPIffzKcXVnxrviwV+nk3x6TGp0bcthMslmTtv3dhE+k3TgTE25h8Q6/eDPwHQdoOZGmvezcfmYg/UQ4Dpf01s3+ctIfN9wIGYvBx5abPMv0w7xVxZ+S/oosJ5duWBNuC4vYGibDyJHd9PnSCSxYGydDLxO8OunFLWqi1lhdifunXBeMM5PJIJnvuHiQYUJ5BJOOjy57lm4dRddbs1zqIaqPKhjEDoIsp6c62F+lbSg3H/51Vhebh5fV9watKqsQNCj4s2k7UgSSICnDiaR6ITuVzDxgQh0DwuQkUlNl0/yhd7S+g45xtQ4KbKtMn8BYmoNDnPm8Ao2alcK3hX9k61kq2L2b4+UdoVnuWt+pD0bNxglhzhXOJHsFMD+ldSFMDBZqRIKV54zD9Qll2REfbDeBMIczCoAYqf8FMXBosc4UCAU/PPq7i8IyrW9bLHwpO8AjSZNV9GnzEh5LAicnAwg2KIhFAzqh+tL3NDkUG3vXYLTpipWCTnXosue6hzW8hH+nox/+CBjs78er5lI5MWk+re823ajN5bA91o6kKY0AFSrnPlBeEhm7tSE48T4hLpVVUuaXyOVA8up0wRZheJ7ED6LHpE6FOcmFh8itVl3Qy0eMhR5SCqgyZkYUd/5ZRGCAGNtV28mf5UEou1DLt9YeTplp4v5pRh9XmDjjNx7MIq41vmFpW4gZMG8FjPgWcVYZ10aj0WPbmhh7mIED/e7+urgP/LNoX/Avc3xDfxxNVFOn/pYMv+b17gUFXrNWcKqRB+DCfGG31r6pYTegPQ5Q7TuLs4txZFq61CjYINxs+Vk9W7OzdyK0hEnFu8Gd6j3G1QAV0a5ZvN8qm+iw1kWsNne+hTQAxa5cMIZWDIk9TWqehNeHxCchnaJuLm/MrnvIqvEJr6ZoeU= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB8PR04MB7065.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366007)(52116005)(376005)(7416005)(1800799015)(38350700005)(921011);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BQr/o33rPQQbe1H9juUFowpQ9F89dChIgWDQ9qIKz2DyMcT0eTi7wcezZ8JSpADwmiOjQ+qYwF+ZSawX+qRFT6eXqh2OjAzYV3FSrGvnNOt7Eh30MtUtvsahQOAincuJb+rUkTnXFxU4W4w4cHWJ+2iNBsZxTT3skNcLV710jRAl5AYYzlDGLlvCfFRr9vF9ZR5xqa9l+tuhYMLTmxRPQYx7nLia4ClfrgfwRq962DzZlCCN9luCo4Y/5QI+jSizZ4q0jGPA+6MdMMuAONJiExZXSi3lAAMUP7oTIs+YE4Kp0UrjW/QWKwmhdJ+BD3W8Pa/tfZdGnnusDIS04Et7hQYjBaiinw+ljKHt47ZsMzmB9KjEafci1ZRMblRk4P6lRiEfqBCHl2pbEuhDtIEOBNb9cySIPW0Z4Y8IPyrQ9TJR2XkJNTAuJkmCVTFMTDe4hBRzoRpHE4DAqaXLg/X0akupzXSmzl10Ik1zfvWI3ri0ja8kRja5rgKbzpdgD1oDpwEfvpAPhJRbO1wYY/3b+iX2bhZlMkssnkbmC55aL4dzhBNqt1E7b+oALctKv7wlavPbQpNH3JxlNCbAiXBGSA/TpOpXHtTrzHTVpi87JR/VTkKYZuERlGVUW+n0c/skzrTVh200mhEF7s2TBfIDASJ6gCRi01B+7KDMGDqfRu2U0yIdRhpotDjWXUgf2DdCuvYfVqTurlyMU3OJMzXXJcPLzepG8CXUPGZRdGFqagaiJOpjPR8beoWnQAUOv9hn5QWnPiQMCrtUlyM/7JDU/oNoEzw8wDdUdeeoKunMTGHk/mBBd3wjxUuq/nK+KWtCWMkkNFxyZ4YPbCPoZtNzEjcfoAvdgLRqjzPhZg5paSQgOW9tHw4cmBR1dSVGcK5MXkrg0mWCl/J15svlmkvpEMhQeu/QqDB7jVyU3haZbP+hZnvgMOYFIwR77jSTygST6eURpBJb8aq8prPtjBco9HydRLDQAqOoWcYrxjzGjcun3oydr8tO612ZKBSbhMsrPE8B4tmcusf4Bd5SpSFAS7v/DJVsjDfWWDQwHqyWH0NX1OItqY4FmIu9AJBA8wzbcEWNuqEUXEvyKVhqPPjIYNe6uxGtEuBmxBuYLLN9zyi71WyLR0DpY3mkOrL0xvxXyqPPy/Y9SpAtMRjr6KkNDBEDSUxCvm7gNmHQ9fE5q+SM82gvN4PlKcRL4vVDEvnGqv7tCkfjUJZyzzcq9ErpCwXviz/9sihSU9GvTxraoLMwwH0rHqhFUVgQ+I758LNQh99+xRfVhvLYDPbK/0NVkGeTTN1X4lQEoOkkSgvGciPlLunTRXI3OJl0dimkSxupqmZHDPhKGSrBy+lCdU6h83rHPNUbedudFL8ad5Y7f+N1wQzxg4haAXyNo4ABVbCBKf0sR6SeoSjqganvmEjINzrHkExD/tahmsTVsXN6Xf+wBb6tKCaSb7zBDSM9Ieh1z8YBxy7FG9K4f6Mz/MkZU7d4kczEyKEKgAnCaahgEya5lE7nYjKF0FkrcgdfrsNeuj6O5SGw6bEWjU5NCJNzDhKO2ooOS2qLOM8mB8Q6QlNIfrqIGw9NS89NAoS9gjT4 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ee18c940-50e7-4a0a-b944-08dc7e21a891 X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB7065.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2024 07:50:21.0335 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4GhWM7/F2tLFv6OT17ZaFiIiAEodaQo5ftpLR79JEZOLlhxjutv+32N4AB215YbTsNJqMADq4qwsN5wYqEPkSw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8781 i.MX91 has similar Clock Control Module(CCM) design as i.MX93. Add a new compatible string for i.MX91. Signed-off-by: Pengfei Li Reviewed-by: Frank Li --- Documentation/devicetree/bindings/clock/imx93-clock.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/imx93-clock.yaml b/Documentation/devicetree/bindings/clock/imx93-clock.yaml index ccb53c6b96c1..98c0800732ef 100644 --- a/Documentation/devicetree/bindings/clock/imx93-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx93-clock.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - fsl,imx91-ccm - fsl,imx93-ccm reg: From patchwork Mon May 27 23:51:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pengfei Li X-Patchwork-Id: 13674744 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2067.outbound.protection.outlook.com [40.107.6.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED56222079; Mon, 27 May 2024 07:50:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.67 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796239; cv=fail; b=oUbX92HHNCpKIGZvdCh0TCQOnI8aemkLYotDNDTC2Q4E8HQQJMZA/Vc+jJjk0fDfN20iTtU6A/vPVfejC+EfByQ1w2BFiDF0pg2RuA59Yiaq1HLS/KsdOoujGuTGiJq7MbQi0oN70E98dwckKrGYOcIe3Bw2OA8nycsdvgbAEXs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796239; c=relaxed/simple; bh=phBvGcHMIgyfL6loc9p7Vw2mZ4WAuVHd753qu1uoV10=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=jp2BAB856vMJ/qLqSUiNbxAC/BexfNmZ7ftzacnXC6HG7gH9ysckaFXi39lpDk7MJUllVChUThVNJoRezf1bLciso5GKdjOCuX+9m5kKURX5aIxJWr3HKp7mazQuGyF6taHydP1NbgARitHAH1OLmU7m8vLeCPGvvtrsg1YMltw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=ISgry/iV; arc=fail smtp.client-ip=40.107.6.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="ISgry/iV" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CFUrpMu4WzOgoVvpGqZGsCeSON1uaAYNFivDYct64Tk2Ob6cIYgX0Scoo0iVGNdLzab+eGxnYY5HXZ6wIQmyhmYGSQoSWBvic4y/kCHBrZxRmlj8LZInX8NEb3FNvmFltTF+LjndTLnd/rcRvoePbDO5Ho2lk8M6VuKkArvTN+1eYhYhaP2IudjGN+obGzmR1I+E1BJDrlvRSrw8T3meYL9A0QQ+jFUHQYcyX/mNNSlV2O2PcKNFgb1fr7g6FWncpIYSVOJcBAsnZnJ6nO7jlDqOxA5H8HmyhJ1BkjoklhSxc/GiNF4lAPUVztI4ElDiCqKojfgDJt57T4oMBBUO8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=63XEgxlPo9CFNy65p+vhwz62dlHiQMICvm+I35mUGAY=; b=bhT8eRa6poT0cqsHy5CfKmaUoGN7tt5V3LKPxhHpJyWuw68xIZlq+mUaP9jZ5TZFPWVKiHmDsUbLke8WWnODjW3j+b3szUiPs9+vx1vZSZ+ItBq1eqxw0ldMguXH6uoTwabK76iQOaC07ktZbjdogb5vBMXsvs/7NW7NrTPBUQkySixIotVu99DfnK826WrMA657JJqEFHjU5ek+ZmYkOaNyM8ga1CclUZyUCRNHXuFvKeKxBc6j5E8rjpkXlElNH5GAvz7MPTocZmN7DVrMDCHm9SIbsB/X/8E1S4UgDOli5hnGgO78XdIIzrvLC7NUwF32pprPfEK1bjLLYSlcpg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=63XEgxlPo9CFNy65p+vhwz62dlHiQMICvm+I35mUGAY=; b=ISgry/iVDSpfYKpyEq6H4I0D1lYq6d9d2qi1vJONOGnFegvzxwgoarczgbwILvURkOv6srD2Pxf+8LnPhfbd8KCBKMcjg9K6fGpPvikK5cFJOUNiSS6tMVHBjYPiIw2pTt5Si4S3MymK5ExSlFv7uqUW2cL0gmf0RsX7FuTXuuE= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) by PAXPR04MB8781.eurprd04.prod.outlook.com (2603:10a6:102:20c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.29; Mon, 27 May 2024 07:50:34 +0000 Received: from DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84]) by DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84%4]) with mapi id 15.20.7611.025; Mon, 27 May 2024 07:50:34 +0000 From: Pengfei Li To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, ye.li@nxp.com, peng.fan@nxp.com, aisheng.dong@nxp.com, frank.li@nxp.com Cc: tharvey@gateworks.com, alexander.stein@ew.tq-group.com, gregor.herburger@ew.tq-group.com, hiago.franco@toradex.com, joao.goncalves@toradex.com, hvilleneuve@dimonoff.com, Markus.Niebel@ew.tq-group.com, m.felsch@pengutronix.de, m.othacehe@gmail.com, bhelgaas@google.com, leoyang.li@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, pengfei.li_1@nxp.com Subject: [PATCH 2/5] dt-bindings: clock: Add i.MX91 clock definition Date: Mon, 27 May 2024 16:51:55 -0700 Message-Id: <20240527235158.1037971-3-pengfei.li_1@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240527235158.1037971-1-pengfei.li_1@nxp.com> References: <20240527235158.1037971-1-pengfei.li_1@nxp.com> X-ClientProxiedBy: SG2PR01CA0118.apcprd01.prod.exchangelabs.com (2603:1096:4:40::22) To DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB8PR04MB7065:EE_|PAXPR04MB8781:EE_ X-MS-Office365-Filtering-Correlation-Id: 24c029a4-7b7d-487c-09ca-08dc7e21b04d X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|52116005|376005|7416005|1800799015|38350700005|921011; X-Microsoft-Antispam-Message-Info: hWWjAmZjPuheMLuQv4R/GO7XGxQnwh6xBmxSmb69oB0j1uh0JxxIVpRXhx5oSY8KuJFZqeFfvpCoO9rbmChAGfTOMpfzBoXWXznhrO5PdgisT8a3pLI/jB5+289A51nCEMkW6qo6XiDIyy8g5ZSTTrTz6PUQYcv4f9QZe/ql2EDiOmojnwMn1XLT37kC37Ur5EoyzdPdfNLVShMO0cSzpy7+t8vrqCzn+1Th4Rr/oKeiHqgEDO9Klr6xKODDGNj+zIPGwVbhyGhCra2rFl8uIZeEbKUKlPWyhr+wB0JbvXSWx1oCqPRjlDl5NJKo1dhM5+YoGMszNiWSP7I1BGkYcNy7BfKB1cYzYKuOECht2FgwxoGfLm+XGzuto1tpOPDUb8LpCFA5Veag94foDQdJETCjV7YSwJbLZJc1KgLhPv+zbAJtbqsq61Tr/P66bkvrH/vFMiXea9M3nYqyuiadWYm1OjWpXxz7L2yy1WaaZzn6LqfXEkSj1kJvCOHT9ZP8XUNit8X/9NdHzHlGk2KmzosIEWZjyiBq4jKuqwV1iPNxKsLg98WPLmXGdbcX2dNCH2cm8Iw5QdsB9QzeN1FJAuPrNhl0uVM5yenBrW22Jvfv/TVOunMyTkd+fgWi4Yr/Sd+ZdSnSaJdGBSxx29skT2Ezf8VU7BS4VgmXVI/+xLgHXmm7VqQpvn2YQ4sp6YjXFMh+OGuk3pxxNRLb+czEmx/JxRtH133tlCffpdvxjha14rbtYVbjBffQIJEAtRo2usWXyVV/dI6hxOzKZIecsp/4qBwgUtG96Gt9bzbc8PBEt1V02LuMJCRPt2TkPk8xdMjaG0z0XKItUHpRBgRYA0g/J/kvCNMnHiCjusUCUkn7wjert9f2s7XUB1v0T8ObSm02LieSHC3plPCBkH1TuMojIGX7ijvAgoOdQyQE2ob2J+rilk6LrCXpacJMTgnQzz1BualAPfH2+n5U9KtAhfIp3Mx4cV842mdMoQZ62vHCR0WnIy+m0tjBHvILPPCKgVgSJvsSDJo1FcLlQhBvE5OlkOQcd3L5ATS6fLZpdWInxBFw4FO6JmPZLgseUnfLTBR1pVCNOrROwyk9Wv9sS4FHdJ2z1UFpUT0zwV28GwESOksT1oIH0TIBFVCTqLqmZE17Z4/MBRMYaXpZ+OHMysIjDMxhT5tKnoRx8xsrpy02jCBiBuMZ53II47lHan/wgLgMxDH5qUn7mN4tYb7LFMZ8wilMMzpIGS4neVVFEy69dvnZ+JryAV9q34VTkmN4Pzj/zsoD2u55ZymLZcgAXtWIxV8nN19hu/WZGddWg8p8ghFsvAx3lgMk6H6zaFiAYyP4XaJfoeBOs71ESQDDMGF+ZD46RW0dNow25AxU7z0= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB8PR04MB7065.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366007)(52116005)(376005)(7416005)(1800799015)(38350700005)(921011);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5IyLGxMvoNzEFg0VRJj9BuwZar71fomeSdrNw0Khm/1qrwmmkjjIibYGAQZowtYG+hbPMDCy+H1CSyFcnzVCd7CSNKTTu8cCPYHkWGxc1Qhiu3XLiLHIMrVycMX/w3JrRWqYy4pnCMS3WrgkHJ5bjfNp02hZCrOOlr9oE6QMKpBJd3QLZXx2zOEcqF1IuhFPSQAvVB8THm1rkUZ2RLtAcQrxFeKFF7EOWoT1+m1jY7XgZhnhWkbC3GcJMqR/4m9m9wnkkw1gmYSV7xWR3UenO8QKn7by2WSpttKSZI/XbhNbgtmn/yC2CKMqhILnzPKDUfPgDEqpRnYyWUeY7C/mHyxMC4RVyQuoo7Bg2uobNVNP+zBsRtLaCaQsb5mgPoEWQech129Bhzj4miuT1jzS62utjfsQYIJ2Nl3KFASKSg+ITrGHBYDHDCtMascxjqcK4/fwdJS+cKnpxhrBnlEWNspyjSweng9gaQsurSJvRRNouLF3MIcBfmFcEFUG+g1uMuR48zFF9I/NQUx37ulCH+tY7bgyYWk1bTW+d72GEQD+WrOI78vDi53zJGA9UPKkYbMr9FMvijcChxgvCRKALLFbtlNsLUXtclUQzkIFxr/6Te7d1ECdfco2WqKxXnNLEr2hs1H0MkIVf101SmlWbBTtiCLPhDbdSi/iTrGYKI54pn8z5ZIDG3wZZs+Zfbhw0hyyDB4eY4lNQWd7efePJzmlByBe8tGfeM5errwV93u/NQnSBQWI3KnrSJ3tG888Ptf5/1xSOaB0R8zrsWv405cXLBSGg1zOKoJ/GfO7oK5JQM8lJZtrdOJKu4145pITTg3ftFZW7e7r+f4Aba7dc9fTVKrfgBWICkafiY4CQlW4SWFR1jUr57tn65Da79hwYt4yWOgN+RmHwT0shHkb/ej1kmdC5BekYDUvNpEQbzupB81hbqYmC6bX+pauaFsAkxbSYBZ8M1xdi88Wop0LFftdd5BWRC33xejTzuEYI8xjsbGB7/vl8sDi0UDBCXM9kCKLOvwRtNJJvFrjnTjuGAJAf3PGXpEW7htiLDrpu/2pPce96xiO/ws53Cy58TrhRtnx5/EIosuOmlg600I3EVwNXTVZQWo1WfIG0iOkRDuZeMYsKFRnds0Vo2zbq3dqgRgCX0UnQOoCcWGW6tKO3eUg4MncZuI0f5YNZO2ZPHVhtlSJBH4fVMg69fZuhgvhYk2RVDQWkShUPbDjkrpzXxUucz37JlTv6ZAK1PPrI3JHt58gwzX45nKTN0AkV1ksGl5RoEVfWt0m+Y0L3Aj2UCy4CVD3RNR5s6Z77z8naUjiWaIUZNXtOwbb4HPYk2hknZ3m7dWdA33QRxF253vU+eFthy/EPjyD4zt0BBVVzjeEIWqnnjF1HPt9r9dehs3PBV+GdC+iZMfQWXr8olqO+68HDI9HtZEIHHU5VFoIgl4DrzNafWgONYhU3366zsXSOpiPBVIt41DIervWclvdwAyPsMzNcY3cDZlfctYAmPS9hep7woRFKQlEuQYHfbL3/mYqdu34RHjE/R5P96uAQwNj7fuxgprK/7hDMpLxUuCRlH8zCzzqSDex/ndr5iVT X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 24c029a4-7b7d-487c-09ca-08dc7e21b04d X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB7065.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2024 07:50:34.3622 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dL7bZzcutz44qMQTyaSDNv66Co/irWFc0dU+3Xv8FxgReDwQLWEmQblm1Lv6yRaY/HIcwQlMIr4Y0vdYasWZQQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8781 i.MX91 is similar with i.MX93, only add few new clock compared to i.MX93. Add i.MX91 related clock definition. Signed-off-by: Pengfei Li Reviewed-by: Frank Li --- include/dt-bindings/clock/imx93-clock.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 787c9e74dc96..ca0785f35a46 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -204,6 +204,11 @@ #define IMX93_CLK_A55_SEL 199 #define IMX93_CLK_A55_CORE 200 #define IMX93_CLK_PDM_IPG 201 -#define IMX93_CLK_END 202 +#define IMX91_CLK_ENET1_QOS_TSN 202 +#define IMX91_CLK_ENET_TIMER 203 +#define IMX91_CLK_ENET2_REGULAR 204 +#define IMX91_CLK_ENET2_REGULAR_GATE 205 +#define IMX91_CLK_ENET1_QOS_TSN_GATE 206 +#define IMX93_CLK_END 207 #endif From patchwork Mon May 27 23:51:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pengfei Li X-Patchwork-Id: 13674745 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2053.outbound.protection.outlook.com [40.107.6.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D4C3C152; Mon, 27 May 2024 07:50:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.53 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796257; cv=fail; b=EEZXP3RAdSZgM1WIK9nMu++OmXC3z0OX5EDE9rOHMBHjVlHUbJouMaRia1BegFpFZHLY2fQkR8iMwpJYrdi6HGTLOyPvLjNfOSnE+YOXLDZilOR5nxyusKgKwE1oDx3/3aMvJBY0Fnd6jLw+72QrOxOb8EXKHii170NMl8K4Gv4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796257; c=relaxed/simple; bh=p0zaNyWIASX1eBvBTVKdDewfg9VnZpbPEW5CdLIMFZw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=o+1/1/hUfm9pxo8/+VUEtS0Uj946T8sjKZsOAqpmxxCEcjrYvl7tprK3fXSB0ZOJb4DOuTWzDld2qCCnYi7ktvKk5BkW0Q+G4NLyLcI6lSofdoAeKiD7Cqlh6mqUMbTo9BsXu8ZjR8dB/0hSlRrTOqN2L5Yonnk/OCK527rvXCI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=QgIowMg/; arc=fail smtp.client-ip=40.107.6.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="QgIowMg/" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nr5hFdqlQCuMDz18hfJClKVwbbSjWwSSlNYu7nINpRxv0XkYSpl5C0QnzJgF3mwGFczSff1qULnkxhBhZBOhHOQFpAz2NP+kVyWHCWLFBYjTaJvWbRuQdH+YzYMCFGbXMtyfWrCzP9xbIX9OcmXL/01mEQTHF1vm5JED5AKfcWh5KgA3uoHdJSfYF14uEoIo2Dx0WSN6vzBdyRsu95LU61S++VIif6FdUWt0NjROlGRNdKfcOwQmaHbDqw1Q/6nfC0Z6da8ArSwAyLatdo6wlxOZ/BWooVc2kSILFaNBbYeW5pTKxD6NuEOFmqeEXbj9V5d424bUYfUhKu5+pjML0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TrjjQiGk/FiINAcAhebkUitqW0s4AiT9B5rah/L2gxs=; b=h+eMaa09GTNpctl1ynr7g4rFbG7yvsNLpQa6LTAADhjff3gJypfkrKnmPyNH+hXf1S50W8t33eVa/tx5lkrG+o1MX5VjJ01q4X34M91rErjyuiyJvC9/TPQYbcBhFSCj9Zn5baXwAN+Zi4NHryu8ahZ7smG8tgsZh9hTMJ9Do3gjWAKemP+9BtXQU6umkNkIIjyIh8+cPTUGeDlyPNOAGpYFDECQ/kBXZ90ZlcoLBHEAwjjtsu1WssSv2xlnLNR2pC/3G2TyC5FGLxa9pwsh4BJYQwxbbJN7gkC5hKXPDdJLc7Kpzoh72DROaUW399ztHDvVgqQxRbRcrtn5olR1Ww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TrjjQiGk/FiINAcAhebkUitqW0s4AiT9B5rah/L2gxs=; b=QgIowMg/nc4hUTOTsd1ow6DpIy2D4uD9Vcvr54k0LycoFYcgbkUP25BuBxZ8XHPzVDBkefCCyAI0Xhl2iVNEG6dTNeDevGmL1QbcOV1Hk6a0UoMkQVBC6MRBMW6eHF/zSvt+eLRocILHDKk7ZL6Zcuudor4zRsq6WobR6lZYAS4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) by PAXPR04MB8781.eurprd04.prod.outlook.com (2603:10a6:102:20c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.29; Mon, 27 May 2024 07:50:50 +0000 Received: from DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84]) by DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84%4]) with mapi id 15.20.7611.025; Mon, 27 May 2024 07:50:49 +0000 From: Pengfei Li To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, ye.li@nxp.com, peng.fan@nxp.com, aisheng.dong@nxp.com, frank.li@nxp.com Cc: tharvey@gateworks.com, alexander.stein@ew.tq-group.com, gregor.herburger@ew.tq-group.com, hiago.franco@toradex.com, joao.goncalves@toradex.com, hvilleneuve@dimonoff.com, Markus.Niebel@ew.tq-group.com, m.felsch@pengutronix.de, m.othacehe@gmail.com, bhelgaas@google.com, leoyang.li@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, pengfei.li_1@nxp.com Subject: [PATCH 3/5] arm64: dts: freescale: Add i.MX91 dtsi support Date: Mon, 27 May 2024 16:51:56 -0700 Message-Id: <20240527235158.1037971-4-pengfei.li_1@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240527235158.1037971-1-pengfei.li_1@nxp.com> References: <20240527235158.1037971-1-pengfei.li_1@nxp.com> X-ClientProxiedBy: SG2PR01CA0118.apcprd01.prod.exchangelabs.com (2603:1096:4:40::22) To DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB8PR04MB7065:EE_|PAXPR04MB8781:EE_ X-MS-Office365-Filtering-Correlation-Id: fd781f41-c2b5-44d6-8a1f-08dc7e21b97c X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|52116005|376005|7416005|1800799015|38350700005|921011; X-Microsoft-Antispam-Message-Info: S/eUyqJ6oNkW3bcqwInefh/f+eGSpkHoSIXffrD3DBh8C/A96oAIirYD2H6S1bfkqQwz0OuCHWV/2pnSEN/6TXaopY7KMB9yLP2q2X5TTdeojRKH+WSZBBRPM3wPelyaF3xPfMu/JzeEXN5o5kQBt8JXD2IiVKKuw+/lP9kC4GnCaIVFq+X0IgyqvwfLOHCwVjoE8zNegtwSDyN4lt8AMEBC5yoQE1Pc32jSBeZEtIPhT4vTF103UfkY2xLRqQR4IrsfnzdL2pI5fXoR3uLKokHzQGbK8PksaazNum2Dz/2ncRIpPQ4AP6q3GZXIHVE3HqWqdSfs60sNsMP5OY4wvXW5xisxu7z/reu0M+Vw6s1qI3b86YaxWjUeKilTHLQhyK+IX+cd2o/BghN3ZFdepfp2/iGDN7m32cucOaL3kczJ+MizcRSMIpqMNTtokytmTvPl8Wsszuw/S5sdXfomsp4GulvFS8Cj+1rIhJH29kXMvfkaU7KE5QMYm/xZNi20u6QvcLd/fYn1Dl/gOKySSNQbiCmEsGuhNpG+XuVphUeywyZy5pVbwec4TIBoKcm+yZ9tXNLEr+td5W7VfwhyuNJ/8b5BPPjJgYNqM5GL4IR2/bfkYJZ2utSDbEyOROapJE2l4lhg+twlSlSvP12FBj2/bSlhaLodyfwCbanctRHx4YTJsmjJZfLXJ1Q7Ye14rJWI/ohA/hl12M4r3SyRotJgeKmE2zN6FkZFoavfvAEH5T4QRe2GAUyltQjqEgEGO9X234Rd6k23Vjgi3iO4X3rwHur5o5lFHUsoY5V5A8TYX1N3jqmGLKxo9iL/o3LOWStxjSNfLoBX1NWPBMcJz8rhEh3V+vTtrJx2jCey6dI02X5kaVuqUEosDSkoz0L8cpdtMVEy9lB/CjKcaMR9wJgrGLQfKpdjsRdQbq7Bi9Gut8tXT+7nVwZnpsDpnPIfyv05tHq6c/bgzM0RE9c9Nq5RGWGeW/nUW20y7fgM2zRmsKrTmR9IGt26Hv0kJC9kssrL1HNQvfqtW36dm/fgn/aALXMfNrJWxWqSVkM7ImyozWYyZlvplJIZDsMVPlu/AFDWqT+nRsWhz6HjxsjQqmxjJRreOkIeDeoRk/lSogGyhWzTOMefbkjOXKKGJxnjngzADCquHYIqnzOVSDyWR/xeYp3Ve21pMLZKnavjrJL+d83om1UgULeR3XyYHETuzve5AhOX2M+7LYCS0elY+SDiwPFzdSyOFwfEAxFu4DD3P4eV12AFYYxje0jm0hBa0UQXBER57p6CBPY43kzYwfFNwEA75uKQJrJ9uCWiQR3TDwDgLgKVB5h+LRLMpWLdFpPPDmJ+vG5qD1Z+8HbJXw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB8PR04MB7065.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366007)(52116005)(376005)(7416005)(1800799015)(38350700005)(921011);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vdj0jZzNRlJWoof8iZmVTNE9DN/qBF1pS6mm0UHFgHMq+pon43cz1zARpS/sOG1swOKEmzLDRvUHfGH2DnoPlaVfQb2ALi8hp2ONTbuNC3MzCVT/B/Pp94DWhU4eaEBLCe3oB5XBKh319ikgZFV7bnuoOsLAZyHQ5AWXCROjCXishDrqBiqpz5aBVTHXCs3Q35uXZQRp6Z4z2zCO1f3+ZE95x7f5qNuoY8zQ/dQSLaqx3PGiXV9OKkkXf7LytZwzk+2a79UrlriEUsongD0aq0RSYNc8KMOpPeMgIzpbsp4DGtnbW3ih6VAFd9ie+gbyjzNER0Ep8WY8B7u6q80tfM8Ek4+KW4smXNRSmQjGypPgmovk4PLOyFmrtVMVCA6Q9K61x5HV2wR8e3hZeUMH6JKbH4WA36qW3DL+lfWuhBCvgnN589vwzOry2fw4n33Y7YI9vfNitbSgNdaAvyPjgiIpabrVdKlsTPe0PiIeTWH9qmMMLcJExJh8NMJcsNtWTs2hJD5obyeWBzqKACs/Pl6I+Xs5L/IC/zrG5ncYjGawAE1llS8omBSn8O4fN+h1x3/XhH0XV2byjRW3PBfhBw4bCgZ4NMm1TNZ8/N9ly5mjSAQqrX/nRQKxpdnbgpttktXef7IOQ2aqKZqyHjWM1FT6OlejkfIzW0iMww7tCkaj6Om2yz6g2/UrcBWBW2cmc+iskaQtOqATssCQ8k2oAFmNSNVzg8aqFl1qaAzN+DEbdDTo2oO/N+RwS+PW6LVADk3FSFHspWbEojr/n3aKxwA0WkrSiDPg+17rA42dgmZoaD+039pgle1EdE1iqLFOMVw0bIFkf2VtwEbYQ1ghxS6QHU5uoeuQwsDgFhUs4NMbNX+S98F72di1GUEPOATl6/kJLJ0s0StInatiUSV2K8HaDq2C95Pw74DSv/Y/Ilsxsp1KjAaspESW4N0mTcKwdhSkPyWSddmjqJLMK/pNem7cLvT7tQyoXx8R+76MrsKqbGdlJMyqvvMjOTD+2EqJhxZPwLAC5h4r6lPuRNdPHBnCQlHCYrgEyG3mUtyWiAWor6AsL0KCuGarDIRZ/yspMtrbn7BgvzrEIfCWKyuEvBOBO1IRNDAxQQCeBSpEFrAP+PJ9bZRjIZ64dWsk0GHDtFos8zzYw7MKebYpo1faFRx2y6PBfkl0+FXymlICofCbHYVGdY6BMG0lTP4jRBjeY7npu1QlRuPTiQLJo2foYe7Y/JplOwPMVeH/hzlnFCoWZuT5jkYt5FI/KfVc6SE4mMe5FxkXY6pYE/BcVnlt4NzIFwqb6liJo+iexEFE5fSOA2mr6BKhDBiLIAmC6Ym6DULYVy41tZ21aURJNXoOu6WBP0saKmEyAS588S43vZa4raAlhsUgwblX8qgfpvKQwsF9fS3OfTYdbNe55uls8hEIGr/i3VvDK+qdIMCNNLsgyDIjV2A8uQ2BiTuC8Mn7mHeMfKoqHRcn9tjH/dqP/sEQUG+xtPCZQwMgj+PtwaaJp+yia7ogIlN5pdPpZlWq2UNoH46EEoaPAfRwPblUZlRdoh22M9R5DOXKHszoZvddKQXYBevnHOWXxzWv8gvL X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: fd781f41-c2b5-44d6-8a1f-08dc7e21b97c X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB7065.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2024 07:50:49.8861 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: j4w2EsOCz2ciBd0Cj/WAFAQI5Y3l4go6EdNx8WO5W9xTc9a47CoPMqwjrL3/csw8aFs7ERKgbgR/QbDGZI5dGQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8781 The i.MX 91 family features an Arm Cortex-A55 running at up to 1.4GHz, support for modern LPDDR4 memory to enable platform longevity, along with a rich set of peripherals targeting medical, industrial and consumer IoT market segments. Signed-off-by: Pengfei Li --- arch/arm64/boot/dts/freescale/imx91-pinfunc.h | 770 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx91.dtsi | 66 ++ 2 files changed, 836 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx91.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx91-pinfunc.h b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h new file mode 100644 index 000000000000..bc58ce2102b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h @@ -0,0 +1,770 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2024 NXP + */ + +#ifndef __DTS_IMX91_PINFUNC_H +#define __DTS_IMX91_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x00 0x00 +#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x03 0x00 +#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0488 0x06 0x00 + +#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x00 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x06 0x00 + +#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x00 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x0484 0x06 0x00 + +#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x00 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x03 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x048C 0x06 0x00 + +#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01C0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03F4 0x01 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x04BC 0x02 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x048C 0x05 0x01 +#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x0404 0x06 0x00 +#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01C0 0x036C 0x07 0x00 + +#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01C4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03F0 0x01 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01C4 0x0490 0x02 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0488 0x05 0x01 +#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x0400 0x06 0x00 +#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01C4 0x0370 0x07 0x00 + +#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01C8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x03FC 0x01 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x04C0 0x02 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x0484 0x05 0x01 +#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x040C 0x06 0x00 +#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01C8 0x0374 0x07 0x00 + +#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001C 0x01CC 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x03F8 0x01 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x04B8 0x02 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x0408 0x06 0x00 +#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001C 0x01CC 0x0378 0x07 0x00 + +#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01D0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01D0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x040C 0x06 0x01 +#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01D0 0x037C 0x07 0x00 + +#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01D4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01D4 0x04C4 0x02 0x00 +#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01D4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x0408 0x06 0x01 +#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01D4 0x0380 0x07 0x00 + +#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01D8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01D8 0x04C8 0x02 0x00 +#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01D8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x0414 0x06 0x00 +#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01D8 0x0384 0x07 0x00 + +#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002C 0x01DC 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002C 0x01DC 0x0494 0x02 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002C 0x01DC 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x0410 0x06 0x00 +#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002C 0x01DC 0x0388 0x07 0x00 + +#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01E0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01E0 0x0498 0x02 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01E0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x0414 0x06 0x01 +#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01E0 0x038C 0x07 0x00 + +#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01E4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01E4 0x049C 0x02 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01E4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x0410 0x06 0x01 +#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01E4 0x0390 0x07 0x00 + +#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01E8 0x04A0 0x02 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01E8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x041C 0x06 0x00 +#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x07 0x00 + +#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003C 0x01EC 0x04A4 0x02 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003C 0x01EC 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0418 0x06 0x00 +#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x07 0x00 + +#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01F0 0x04CC 0x02 0x00 +#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01F0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x041C 0x06 0x01 +#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x04DC 0x07 0x00 + +#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01F4 0x04D0 0x02 0x00 +#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01F4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0418 0x06 0x01 +#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x07 0x00 + +#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x0474 0x01 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01F8 0x04A8 0x02 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0480 0x06 0x00 +#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x07 0x00 + +#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0470 0x01 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004C 0x01FC 0x04AC 0x02 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x047C 0x06 0x00 +#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x07 0x00 + +#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04CC 0x02 0x01 +#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046C 0x04 0x00 +#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00 +#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x07 0x00 + +#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04B0 0x02 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x07 0x00 + +#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04D8 0x01 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04B4 0x02 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x07 0x00 + +#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x04DC 0x01 0x01 +#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005C 0x020C 0x04D0 0x02 0x01 +#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005C 0x020C 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04C4 0x02 0x01 +#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x07 0x00 + +#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04D8 0x07 0x01 + +#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04E8 0x01 0x00 +#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04E4 0x02 0x00 +#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01 +#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x07 0x00 + +#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x04EC 0x01 0x00 +#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x0400 0x06 0x01 +#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x07 0x00 + +#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04F0 0x01 0x00 +#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x07 0x00 + +#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04F4 0x01 0x00 +#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x05 0x01 +#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x07 0x00 + +#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04F8 0x01 0x00 +#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04C8 0x02 0x01 +#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x05 0x01 +#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04E0 0x07 0x00 + +#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x04FC 0x01 0x00 +#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x02 0x01 +#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x05 0x01 +#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x07 0x00 + +#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03F4 0x01 0x01 +#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03F0 0x01 0x01 +#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00 +#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00 + +#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x05 0x00 +#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x04 0x01 + +#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x02 0x00 +#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03E0 0x06 0x00 + +#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x02 0x00 +#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009C 0x024C 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009C 0x024C 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009C 0x024C 0x03E4 0x06 0x00 + +#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00A0 0x0250 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD3__GPIO4_IO3 0x00A0 0x0250 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00A0 0x0250 0x03E8 0x06 0x00 + +#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00A4 0x0254 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x02 0x02 +#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00A4 0x0254 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00A4 0x0254 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00A4 0x0254 0x03EC 0x06 0x00 + +#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00A8 0x0258 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00A8 0x0258 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00A8 0x0258 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x06 0x00 + +#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x0474 0x01 0x01 +#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00AC 0x025C 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00AC 0x025C 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00B0 0x0260 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00B0 0x0260 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00B0 0x0260 0x043C 0x02 0x00 + +#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00B4 0x0264 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00B4 0x0264 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00B4 0x0264 0x0440 0x02 0x00 + +#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00B8 0x0268 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00B8 0x0268 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00B8 0x0268 0x0434 0x02 0x00 + +#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00BC 0x026C 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00BC 0x026C 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00BC 0x026C 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00BC 0x026C 0x0444 0x02 0x00 + +#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0470 0x01 0x01 +#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x046C 0x01 0x01 +#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0448 0x03 0x00 +#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x044C 0x03 0x00 +#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0450 0x03 0x00 +#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x05 0x00 + +#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00D0 0x0280 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00D0 0x0280 0x04BC 0x06 0x01 + +#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00D4 0x0284 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00D4 0x0284 0x0490 0x06 0x01 + +#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00D8 0x0288 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00D8 0x0288 0x04C0 0x06 0x01 +#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00D8 0x0288 0x0000 0x00 0x00 + +#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00DC 0x028C 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00DC 0x028C 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00DC 0x028C 0x04B8 0x06 0x01 + +#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00E0 0x0290 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00E0 0x0290 0x0494 0x06 0x01 + +#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00E4 0x0294 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0480 0x01 0x01 +#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00E4 0x0294 0x0498 0x06 0x01 + +#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00E8 0x0298 0x049C 0x06 0x01 + +#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00EC 0x029C 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00EC 0x029C 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00EC 0x029C 0x04A0 0x06 0x01 + +#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00F0 0x02A0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00F0 0x02A0 0x04A4 0x06 0x01 + +#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00F4 0x02A4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00F4 0x02A4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00F4 0x02A4 0x04A8 0x06 0x01 + +#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00F8 0x02A8 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x047C 0x01 0x01 +#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00F8 0x02A8 0x04AC 0x06 0x01 + +#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00FC 0x02AC 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x04E4 0x01 0x01 +#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00FC 0x02AC 0x04B0 0x06 0x01 + +#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02B0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0478 0x01 0x01 +#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02B0 0x04B4 0x06 0x01 + +#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02B4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x04E4 0x02 0x02 +#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x05 0x00 + +#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02B8 0x038C 0x04 0x01 +#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02B8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02B8 0x043C 0x03 0x01 + +#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010C 0x02BC 0x0390 0x04 0x01 +#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010C 0x02BC 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010C 0x02BC 0x0440 0x03 0x01 + +#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x04 0x01 +#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02C0 0x0434 0x03 0x01 + +#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x04 0x01 +#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02C4 0x0444 0x03 0x01 + +#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x04 0x00 +#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02C8 0x0438 0x03 0x00 + +#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x04 0x01 +#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011C 0x02CC 0x0424 0x03 0x00 + +#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02D0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x04 0x01 +#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02D0 0x0420 0x03 0x00 + +#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02D4 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x04 0x01 +#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02D4 0x042C 0x03 0x00 + +#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02D8 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x04 0x01 +#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02D8 0x0428 0x03 0x00 + +#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012C 0x02DC 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x04 0x01 +#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012C 0x02DC 0x0430 0x03 0x00 + +#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x04 0x01 +#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x00 0x00 +#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x01 0x00 +#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0450 0x02 0x01 +#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x04 0x00 +#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x05 0x00 +#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x06 0x00 + +#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x04E8 0x00 0x01 +#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02E8 0x0454 0x02 0x00 +#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x04 0x01 +#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x04EC 0x00 0x01 +#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013C 0x02EC 0x0000 0x02 0x00 +#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x04 0x00 +#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x04F0 0x00 0x01 +#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02F0 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02F0 0x0460 0x02 0x00 +#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x04 0x01 +#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x04F4 0x00 0x01 +#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02F4 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02F4 0x0000 0x02 0x00 +#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x04 0x01 +#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x04F8 0x00 0x01 +#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02F8 0x03FC 0x02 0x01 +#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02F8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x04 0x01 +#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x04FC 0x00 0x01 +#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014C 0x02FC 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014C 0x02FC 0x03F8 0x02 0x01 +#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x04 0x01 +#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x02 0x01 +#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036C 0x04 0x01 +#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03E0 0x03 0x01 + +#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x02 0x01 +#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01 +#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00 +#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03E4 0x03 0x01 + +#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01 +#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015C 0x030C 0x0378 0x04 0x01 +#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015C 0x030C 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015C 0x030C 0x045C 0x03 0x00 +#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03 +#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037C 0x04 0x01 +#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00 +#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01 +#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00 +#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01 +#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01 +#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00 +#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x00 0x00 +#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x044C 0x01 0x01 +#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016C 0x031C 0x0388 0x04 0x01 +#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016C 0x031C 0x0000 0x05 0x00 +#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x06 0x00 + +#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03E0 0x00 0x02 +#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00 + +#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03E4 0x00 0x02 +#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00 + +#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03E8 0x00 0x01 +#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00 +#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SCL__GPIO1_IO3 0x0178 0x0328 0x0000 0x05 0x00 +#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00 + +#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x03EC 0x00 0x01 +#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017C 0x032C 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01 +#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00 +#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02 +#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00 +#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045C 0x00 0x01 +#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00 +#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02 +#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00 +#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01 +#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01 +#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02 +#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00 +#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04D4 0x04 0x00 +#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0468 0x00 0x01 +#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x01 0x00 +#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x043C 0x02 0x02 +#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x03 0x00 +#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018C 0x033C 0x0000 0x05 0x00 +#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018C 0x033C 0x04E0 0x07 0x02 + +#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00 +#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00 +#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00 +#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00 +#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00 + +#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04C4 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01 + +#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04C8 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01 + +#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019C 0x034C 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0420 0x02 0x01 +#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0460 0x01 0x01 +#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x042C 0x02 0x01 +#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x04 0x02 +#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01A4 0x0354 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0428 0x02 0x01 +#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x05 0x00 +#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01A4 0x0354 0x04D4 0x06 0x01 + +#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01A8 0x0358 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x04D4 0x01 0x02 +#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0430 0x02 0x01 +#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x05 0x00 + +#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x00 0x00 +#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x05 0x00 +#endif /* __DTS_IMX91_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi new file mode 100644 index 000000000000..a9f4c1fe61cc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx91-pinfunc.h" +#include "imx93.dtsi" + +&{/thermal-zones/cpu-thermal/cooling-maps/map0} { + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&clk { + compatible = "fsl,imx91-ccm"; +}; + +&eqos { + clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; +}; + +&fec { + clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>, + <&clk IMX93_CLK_DUMMY>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; +}; + +&i3c1 { + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&i3c2 { + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&tmu { + status = "disabled"; +}; + +/* i.MX91 only has one A core */ +/delete-node/ &A55_1; + +/* i.MX91 not has cm33 */ +/delete-node/ &cm33; + +/* i.MX91 not has power-domain@44461800 */ +/delete-node/ &mlmix; From patchwork Mon May 27 23:51:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pengfei Li X-Patchwork-Id: 13674746 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2086.outbound.protection.outlook.com [40.107.6.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D8CB44C68; Mon, 27 May 2024 07:51:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.86 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796267; cv=fail; b=RQ5kXsx63GQdf3ZF2SxJK49cYME4/fZgq8X3f4O+ldNA+bHNSUVDx2CyqKP1QUyZjfTlZrUFGO9U3Q5ysll2WFSulnk36byLmmsJXGyd4Ansjj5BEd5CjwZ/d3HJjAGEN1DpU3JdUTuhR0WuTuHLWSCGPP1fujQkw6k+KsiQuho= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796267; c=relaxed/simple; bh=n7VoF4Rjjm/r/SArEpBsCSFx8Rl4IQSW/q2KApckpkg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=syLXnTTGHFY4hvSivTGEmO5hvVmbxUEKzUYPTLqsa1Y/jHHuFekCeOr5WhIF1Tr91wOzA25nFOxVvB0qrGUP/J7vK7timUzrShn44z/ueT7aBo3XPAKrpMeMTa2Ms99F3+e6eC52onQfbvXsDtUcB1johqCJcR2dk2fIywUgsBI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=UVjHouIo; arc=fail smtp.client-ip=40.107.6.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="UVjHouIo" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bzfJ3bQBn4sHzL0rZfujdQGDQZ3JGn2bbRV/EwmXWRpd5QiGqX4CPchRvln7iEvyD2+B2BhXHS+5hAHw6uEQLrO8g0F8iszAp6WJfZiWtIsfmLuZCZpKAO3+5RhR0AJ/zoQMlhkTFfY6PWyGSXOsciE8oNk5VMWx0Y2BzOEV2UfMj49cWP3D4naU7E7kdW3yUZ6pSgeI400SD4Ugqqapm+PXvg1QQ/JIaUU+IwbvFqFapUFHbpJgQ82yPPn850pCeWhapUBoNGLnP1T88ohYLG2Q7qzXjjpvW80ygMoba83o84S+1D4Lp5XIsp463ZfncNSuGD2qhFDgRHfKa5cpzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EG/qZtVKtO0uDw77N6cSzsCXRaRSyEPip4JXRowEIOE=; b=btlJqQZ6WbotXKEsJC3HMtqumCBpksRHEHU+m8YD2Z/JbwzH5w/cr531wmqki9jIsr7oqUaJRcAqQyVLlsnLjKGvgBfGMrSuTcr3gZjOFD7AzkHq2pOF7s0hyUXEbXrwXsfEMASY3bQJz4v30e0t+1edOAeY2vsP6Y/Pwbqyc6MdTZHAebDMR2oKqjRfqk+MsDzgjkxu1ZFRI0fQxPcJD3tcn8ID+HC38P0yzc0grlwytzzZUXMI20nggUKGQX9izwrjbqmleayy4jzQEFUB1rxQxBWgZfVAF/ZReYvZVyjbhacp2LN7wCkOEvrDOmtQwltR5lGbxDA3dA7TQfP5qg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EG/qZtVKtO0uDw77N6cSzsCXRaRSyEPip4JXRowEIOE=; b=UVjHouIoucadEsE7CJmrYJEIBt8bjTZPapRE8V9vy9BbR9Yru+Bh7buCTmLG7cC7Tw5RW6F1xtk97v3TZyTSyuMlr0XDQxFrM931aWqtaghIzon0jUAF5mJAi1XaUWaClr5EyAqu3aC7j7SnzYDbRJNIcmMcGV7P32PivMAmrpg= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) by PAXPR04MB8781.eurprd04.prod.outlook.com (2603:10a6:102:20c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.29; Mon, 27 May 2024 07:51:03 +0000 Received: from DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84]) by DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84%4]) with mapi id 15.20.7611.025; Mon, 27 May 2024 07:51:03 +0000 From: Pengfei Li To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, ye.li@nxp.com, peng.fan@nxp.com, aisheng.dong@nxp.com, frank.li@nxp.com Cc: tharvey@gateworks.com, alexander.stein@ew.tq-group.com, gregor.herburger@ew.tq-group.com, hiago.franco@toradex.com, joao.goncalves@toradex.com, hvilleneuve@dimonoff.com, Markus.Niebel@ew.tq-group.com, m.felsch@pengutronix.de, m.othacehe@gmail.com, bhelgaas@google.com, leoyang.li@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, pengfei.li_1@nxp.com Subject: [PATCH 4/5] dt-bindings: arm: fsl: Add i.MX91 11x11 evk board Date: Mon, 27 May 2024 16:51:57 -0700 Message-Id: <20240527235158.1037971-5-pengfei.li_1@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240527235158.1037971-1-pengfei.li_1@nxp.com> References: <20240527235158.1037971-1-pengfei.li_1@nxp.com> X-ClientProxiedBy: SG2PR01CA0118.apcprd01.prod.exchangelabs.com (2603:1096:4:40::22) To DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB8PR04MB7065:EE_|PAXPR04MB8781:EE_ X-MS-Office365-Filtering-Correlation-Id: 05546b35-28fa-473b-a4ea-08dc7e21c1c9 X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|52116005|376005|7416005|1800799015|38350700005|921011; X-Microsoft-Antispam-Message-Info: +rsa81Pj5sGsghbY8Ll6wBzNKuT41INhWs3xQ1kNQLgpznt2jBcQcTdW7ZFWk+WHX+FAP1Us+89jdfDxknwNwA8oEmtEswST+TFA8Z1CGG5xRox3ywcZHniY3DECsplmYAKyVVzGtkKxolG8ZCpnW+3WKlrV3lYa4KSyze0HX5b9osRlckMgh2xBTTykUS0lcN8YhRH1UbEGpA4YwqDMPZM+lFRscSVsmIYitI52UWD+CD0JYcpC34xyfnvFCNLs1KSM3rZLKtPlDTIWv2O3ae3F+rEt9b4eHIH7/Xf7MMZSoVNjvF/lr/xwvFcplia8Xr97eW5dMxFjBDOs/x/HmxaD84ibk5N6xv+MftnWIEScKKOlkIoitwckXMNc4/aCO/de1XEosXIBQ2LALvGCtl8fX617qufaLn9DQly3pQFQ4tME2dV6XhTxmN/JHsOgqJePKLeJtrtA2e4uR3fpbcijbRxEPq0BPAmrJnSWiwkOAiGcyMXAA1Bcht+ilJ6EoDVgwvvVLr4wjj0sgIAHZoZQib8cOjP7gtIrIOuQ1+1QDFqPT+NgwQQKDrjpx2t9KmJryjY4dKb17/UkXC813Y2+DkGudc2cWGK3T4TtQIkI65lzmH9M4zOK//q9kfueLJVrBwv1khBW7jE8ATy9UluZF4OP8qj8iCC9QDZFsRAfEY41ZD6gJFvEzMYKl58gN7P17ZvdJ5RYY+wQxhQnqvHlgrDD9CvG9vEZg6yFeVexT23l+jWY9I9SPhKF1I5EaG+c1oEGKts6xheIN0MhR1rCwT9Ve0A1zyL8pVTG/TKrIruZANxM0LMAWPYVTVAfs9T4S/bVfTDrHd1ws6y2xEdjk7qjMSCyptuqzDXUP7K+M9efCgvLPmfPH6bIX3+r+3cBPvtl7LWbUP3UJPdsAihPOpwxuni3xrFcWaleoVnNCrJyLxGUj75ZSSULkDHPaeMTXAMj2U+gYbzz3zrc+Eo/AtjCGpKF/zo2Sqozw6zqMuggjI+ez6ZhXYkDnhgNBbc6NqfuUDI2fLPe7WYRKbxfCji89ptWkGne4xELwzhEl//qga6eeRK5XyL0aTY+TdlnNOvY2G3gaVmu3EMpF8T1urKbc+r/cpnxZEvBzhd//3cUrmTBYKSQAHHfLfjmpTZ1i3gxSwF6ZQ5aIbkB/Ug7WWwIBOe/JljTJpCq9JxxiGN8Ut29c4vZpbOpyGg84JfJtwykIoyv8ix+CUFQjv+pHjE5I9FbfQZ5TxqeeForTZotgfeJ5y544mU5WdVBWCifZ4VI1Zq11reyDI5hfVfr9HpazrkjwQuVpHkovcfytTr8g+XZg6YJLnByk/eByvYn5nyYqix0y3UwRV2NfsYvJqLFB3Hkkxq2Bo2y+y8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB8PR04MB7065.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366007)(52116005)(376005)(7416005)(1800799015)(38350700005)(921011);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WOYzk5Y9rmwP1l9qoA9hPY5N71+GAT5Q/Bd0T8wSW4Z7JpVE5TxsWRfr5Ad+z+5A6fOGy5QJGhgESPBOtyQ7LIvm2gUtfVC72uiBybD4Kx8EI4fLgvnvA6Ugjm4vxcuvJSWjy1jGzw6VlbuUCZOYRh5X2unT47TLzLFF1xuWXFoiNg1bRm6A6o9qmiXQjb25FhgLyl3lX62WsP7Y9v/G+74o2fTWVaAtL6Jk649k9r+sKM12BHW74tK0k3Kku3TL+eQReTA9Ci7pMBGB12Xn+4lUWbGlbr7HietskmZK9pDYQMfspqCoIVfEDbh0wm6bONm7mQsdq8b8s8W8O/xreucOTvn2w9pTKD+HdFhDWmUbWTdRmSF5rtgQv9pFUlICJ2MRlDGZk4HuxJff0TLSEW6r3MjGbvt8wOyL/Y04mLpKh9MPDe2jMRJkLcrqUm6u2g0jKFI77JIGPNQRrp8ZF/D03/EhYIvGFMod2XmE7hKJe+SQShSlqD7KiezSRdWtTKHrSt4JXwGUiB5Zlb5CT1qWj0aRcZ2xYFey47OG6RI1t/iQieyQZ1O3q77gNUhJzaR1Mox0nfvGsu5VcNAV0TQEDCfvXkiWUNTvF8uffexN0XHAPXlSMrEtwWC6Zcl4IC35pe23mgazjdrfFFMobGjRvy6ffVVA5w2/dqlsVPeB/grpiChfODMm3IYSrueJtLFYzPyvpMJ+amRa0QLHc1eyhgBAR0VFzSg6fxYlgsEfU3SMT2E2xxfNN3AwQTaM68E2jnA+njqEOShfbiSgV76ZdrSAMe+fSEr/kPHm5IbphFIA7EP6x8Dyu+SdlMFF6izEDbeyavPGyUyEi0jxKx8LzxZpG6VKeIAlJDc4DC88T3PPYgSzNo7Bmdm6LRctfZ3RPiqJUX8aUdet829BR7L91Ri08ieYfzEccpnQEtRyb+5cv3MQMXgZ8nSFy/FGeqANaGyA+uYGqqnBdNj/gwmnuSG5rTcsoBQ8JXiLwT9o8hpBoaToEvg74szVdXEHyqqPO8USO4/oXiRKsoHUcrBl7EbVEs5Zj/aBt+PSPyFd6DgkHwSZCnSsSX+iLq0Hd5afaJX9pGu03WgMtGwrzBrCMgv5bg9ULQSxeBx0+cBWYsWIX/zGFD405cEMAwF6X4H9kOixGOa1asvNiPHEo4QxlI1H9FiD805qQ+ehv3pd7zlw6t0C/ccGBHgH1haBd9oGT88c9qBiJAqm+3yQJBdbnDtWqgELtRTXtcqpwEA9WAl/L1JyMkJMqmcr7hWBY8uV/sMTKr4JvSmeWoQtxi1z7TioerXlEYuh56+vmoaJHooai0V8d4avmBeVU25A8DinnXzhrjUv2U6PtMHYsKf1Y5beq3ayiwjiVVsjzHxZu5WnJOqHSDv2XtWS0Q4lUtcokxsG+3rQ3kqN0+cKqcg9Wou2kvE5DzaqG2R6G2B9/GIR8tRqYqgPByBpaYwNQ3ltIo1QZeTEDWmndebuhwzDRbOHxWSPEcVUN6JvlTogff8sHWY0i2XnkagfdSPjAsLmGcHBCD4YAPRzOFcP4M9Nkp3pHmbGSMniTmasi+rn42n+nClxWugrKWoWp7xr X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 05546b35-28fa-473b-a4ea-08dc7e21c1c9 X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB7065.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2024 07:51:03.3217 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: egfRnZvPA8d+DJiSwiu+vt6i9WUSzg2umZsLNgx593/wWOx6hxnn5gWG9S3i91Z1GBZ+faReh2iyIqtIj1I90g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8781 Add the board imx91-11x11-evk in the binding docuemnt. Signed-off-by: Pengfei Li Reviewed-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6d185d09cb6a..41b487ed27fd 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1275,6 +1275,12 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 + - description: i.MX91 based Boards + items: + - enum: + - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board + - const: fsl,imx91 + - description: i.MXRT1050 based Boards items: - enum: From patchwork Mon May 27 23:51:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pengfei Li X-Patchwork-Id: 13674747 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2056.outbound.protection.outlook.com [40.107.6.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07777C152; Mon, 27 May 2024 07:51:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.56 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796282; cv=fail; b=TmRKB5J55GOHij4Ru9yVg/4jCsCkKII+Z81axxq9CkP9Prj6abEBwT8a2mbvJDCtEeTLahUpdtz8VMjqVrIESZ9DY6igVFhh9Yl0ZIkmZCf3Ar7iPDWcO4/+HSiz4zW8qi5P2Cn3ErwEEs8ZEJFlnKQJAbC+jdWwbS1ZM4Bwp9g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716796282; c=relaxed/simple; bh=+pBxwZAqPQ3SK4b612CyX8t1QYcB73cHWtbwrjqRPyc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=HzE3/FPa+Bz5mR7Jte4WmBhO5NdJkegtXZU/6Q2/dnU8x68ZEFfU1TKqfY1LOwq5C9VCjwdo9lfkqwrSzpLJjCwhO0CzVfoNI6v/HSInxnDgdFKaw4rJvGnLz/djWorBRUS054KRLsbz7C0ksKuCaYET/+FVV4B0GxIDj8HNATY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=OtKe6ly9; arc=fail smtp.client-ip=40.107.6.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="OtKe6ly9" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jM4u2YNcuIjYNUTOkBcYlsh8Cw2cO/uXNZcxcvozt3UTSbtVdgmqCdbnXz0mZx0JHVnYIptW+OyLPlCe84ssPD+AyBv/EJJ7qc1H2d3T+zhpyT/i8/utvnQ+AnuTKB11Qu0Z0HsA7IELs8tTa/g7NfdVrbQzR8hgrVJgRgdgR3vvCSgeLYbPe38wEhoPtuG/gFntNpxlshLSLHul4Yzjc1Lx6kmejjbTY1zx39WnzW5sFIjum/TtdjBgI6taBZ+s96XTKPpaSB4c4ejoX/Vu4L0oDJ/kVI7OzlHYUEwkPdPLlsxgFX6yk2yxR6SKgHBVyrG6t+dsWM+Kuazqt5HMig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HudrFMow0R44osU7anh5TVxsfUuJ6HAykQeIvB+Q2io=; b=XmME6E2Mo1BCeNxk9ByQYUzdGHvwhbqBx6xONHkIgvW4DL7gPEAop9NExWyazvIQdSozJeTRcx/rLRFwpr4iPBczAgGUp1hCcm6pgpMDIRJEFmy1n+/N03a3rDqTr6VmoMJKzf9ob6xlWnloKVPz/5H8UVkyB5of2ykrQ3npkpvbmqm6zonmEoPFiFhJB2y3F0k+Hn7nQeVnEH1H2PmMPJBDy/eCAOLCJmDZoCRDMAXPJ+0+LgFzKa3pSQjU0AXMV6x2wHTEU1lnCh7OL+Y7JcIwcg7cKtIYG2NQo3PRTS4Pt5mq/gP5m38yafcuGoDYFMuOGQwKoNGnh7Ldp8ABzg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HudrFMow0R44osU7anh5TVxsfUuJ6HAykQeIvB+Q2io=; b=OtKe6ly9MyNtJjobIFzq7KPNKYMR/nQQ4Vi4eRUarRiOlNaBBZ4RbHEaXZR0gd0tcVaWE8gVwrd16Kpo7mdH3qJGwPSYlE3Z0U0I2RjRAHDAk+1iq2Qx+dPvhUCMZiZMQOXzRm0Yf713Z2RFX44ZIZXtp3U7RuZgYIDnVTI32rY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) by PAXPR04MB8781.eurprd04.prod.outlook.com (2603:10a6:102:20c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.29; Mon, 27 May 2024 07:51:17 +0000 Received: from DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84]) by DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84%4]) with mapi id 15.20.7611.025; Mon, 27 May 2024 07:51:17 +0000 From: Pengfei Li To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, ye.li@nxp.com, peng.fan@nxp.com, aisheng.dong@nxp.com, frank.li@nxp.com Cc: tharvey@gateworks.com, alexander.stein@ew.tq-group.com, gregor.herburger@ew.tq-group.com, hiago.franco@toradex.com, joao.goncalves@toradex.com, hvilleneuve@dimonoff.com, Markus.Niebel@ew.tq-group.com, m.felsch@pengutronix.de, m.othacehe@gmail.com, bhelgaas@google.com, leoyang.li@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, pengfei.li_1@nxp.com Subject: [PATCH 5/5] arm64: dts: freescale: Add i.MX91 11x11 EVK basic support Date: Mon, 27 May 2024 16:51:58 -0700 Message-Id: <20240527235158.1037971-6-pengfei.li_1@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240527235158.1037971-1-pengfei.li_1@nxp.com> References: <20240527235158.1037971-1-pengfei.li_1@nxp.com> X-ClientProxiedBy: SG2PR01CA0118.apcprd01.prod.exchangelabs.com (2603:1096:4:40::22) To DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB8PR04MB7065:EE_|PAXPR04MB8781:EE_ X-MS-Office365-Filtering-Correlation-Id: 70473c41-d542-4d24-870f-08dc7e21c9df X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|52116005|376005|7416005|1800799015|38350700005|921011; X-Microsoft-Antispam-Message-Info: m86e+EtSn2CV0hTNryV+2WoJjsUyzA5ya8c4nqr3AcsFTDCqmI+FBS3ujqat/i4rZHNSrQGVsQTR5ot3J5GXgBoKmtbVeMPGnRDdoGASpZpX7o0wbnOMrPIDfC+ZEnuGgDoeZNTQxKkR1LbOEhaqOye5D7ZwP+MucxQuG/6e+9bYN2n/eWAu3ZpP3nutyw6mTJylceNHHxq3WEG/pwga8OyVzpzZi9RAUwGp2XWZlNrJOJzfv5IqL03DC7Uz90OQ8i8YVW4znCwa7U/TaxkOUGSA4l82a7mryaXzPFkK+LGoSowxf/wB+ci1bkJSSnEcSeR8mH3Cz7Afg/cTrRth7nXuFiitA9JqHRSHJB1ievcpM1z8+0cyQ3kIP1j0pfSKZx5p5k9Ra0BwJobqBl+OXAH9suMrIFVz1VxnMoo2O36dxi1saOsSCpQZ5TYApwXwWu/g4EAEdF0az0niPhbm7eogcwTwgfiNJGYSWTeP0Xpe1dct1aN9B5N2gqZ710hRcxSFUY4tPuiZ9qqcbWKA43bVWV5IZmXuV4LN0f5EtjO6EsYXvc0NbHnmuTJsyFzpcVm2vk1pYRpqIJt1G7+mOAUgjwzH1FlUFQdrDFiCjB+7Y8Lh0h80lojtTY++sjRBWbaUpCqs0rfyfAbsO2wfGMmeEWTFjrcHLTRVq00Qbc+v2gnwo7mcD2YajVKvoUHz+g0kH4U6B1bY6ovtujdMHPAY/GWPlBY5ozInkyY7SCVLLdIHeARZoKW7CFWVsHgUoCIsMxxvm2vqlb60eMAHLzABCyBiajSn4GhoTaVfxHNX8xh5DOTWWmnCS3Uppgey0fLSBDuMQC7UrJ3fmgbNbJgG6/cP+9JpCmeQ0iEHZy3QLiq9ZhOW1TDFEod9wYm+UbrNmYx3k8euAIQDELAnUjnIQtCfXsIBR0orYGwN3Begdg42ViON/uIkcJjb7hno2i6fVsPqyJcoiSGrPGCL4epKPPtfLKJpzgf4jRcQYHlQaYY72/Da4co3bq/S9iuGIUxwuVSFDLViJuD1W0F7CvUQhIRJhSzdzia5oql5yuPorCeGrO+OGL6lDCcvT666OZDzMvnGpPjMG0J9HAbu/oCBd6IE6KP+Lh/NK5TAd6zxCaKhKQAHzbGz8eEssDE++QYfh8fDtVU7QtvawyVKsrD/1MyYKJlPaxQZNDWBTGxhsYkmBfEGzk2qdbfpNxmRc3qn8Lu0H5b/6rJ8zuWmlcFPxxeGzzFeCYJwfidWAKa6xOsYoci93utqq69rhLbL22HfjBXROG9RbTx27951jbrFq/i4zPK4MBM8Qbq/ZVrv87aMXIqteVFNQp57OpVLiXtQh8nlCE0k+qc5dfXNPZUT8kEMBKmvGnZMN1cP69U= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB8PR04MB7065.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366007)(52116005)(376005)(7416005)(1800799015)(38350700005)(921011);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Hsz3w6lHPZKNqZVGvUA7mfDI1AuVhptqdumAxOzY4E4lqzdy/NdYjnVyLwNNrv65pv7drLo0ZJq8dHIIKd8Qc7lWp26XIXuNdQ2kQEy5/vQEf63+/7UMeA1K1DoATnme9YMI//qV8p6v2IIn/qyVMRT64mDmPkB/Nxu0uFx61Qbk3X6798o4UYPxsy4JnjC3o49k8zt0hO7CB43iajLmDEyWExB1ReIDhauNMujcE9uPZBg2euovacpLKNRuZ7GNfL9BPVYOqhAUWMgRNdWPYPjdyzL9yp8kSbnfpjN0oPq5B/a4wVd9bUR7DEVD5/36oxe2sNR8woNir+2RDqndy503u7k7+bc7BraR5iXQZecRfj44OBW3NMvi4GyWjeNt5cSyGLuR7eCLq52BjzJ2WM0HNYXn3lssDoG7AqZNVy3OMqXF/4/uXKyLyWVyW/uMtTpgcNy8siKFBNhHZEk386eCtxU0+ilUOvSs8kP8xzicgIffX3x0979xNP3yTMvlT3WvK3zJgGGmW1WQ+iEDSeCH9svdntv26z713JrJ+bdZRg8XT+xc/1gRRUhy4aGkMwgkpr+frc+nfU7Z6Jy2zKAiUHbhHOq0skZl9VaW8PJcblWgGdudweeG4N+FWFc5hE30lQQR6tyaI5YN8K1+Z4TBgAF0E3Q/sEvQnyXN1egy3ZRZppFEZ9bkXTtle0WOQ6dHBEM3SF2lC5JlRKZHHjQP7i+YJ3gN1rm43vsrGNjNXp8Vme3FDxhn8tKaEvvQCKs+0l7ATNAp9uBgsBAIBAQnKCFg/SJoJa7UautDlgDJ26RYL3MIycW5WBeea8J9pRlFiotsa4pmki+Dj5o6ZJLxQBc0wnwi2f0lnZTDsD6LszpfeOPEM+oGScn+EkkjiUgX8DZZiviaZ+SAW0RHjHFYqPyXU3qYkJ1sKoZ56PtdRXXeld2oBS6L4mlxG5N+UYt8rehBknkTc0hkalP+IMA0lUusYAFb8TCQLsi0iY/UjM/I1lnZP0C2vVZZvJhPL1ks0EQIgauFLOyyQ0FgasnFKPf6jzvE6yOCTFMPsmte7HBMaPjvDVic4fhxKNi5uADY6qRZL1kvtUMDGSlIHNt7sL3aj8DZNr0tQE5TkGQEHu25qIUAjf9KjMIYRmGB9pM8mBbT+k4snH7Bftse7NiEG4TSpw6l5/Nu1vg5CFT2l1/5yegK518cLVroXSS1nPVIBta7zOy8eHaASvtR690yJ5Gkt2bbJQ7wEqVO/2UubDxCj3kc85vqJODmFYlBN78w0XO8q9JbuhpIiWVvMTUnKuJZKU3iOguW1pt7S2wodEf1roFpZCAiDt88pVDsBy5dPWvVnOrJiSdA4HMgqsZHkqcwGllnltcKbweKX43pu8FkG9+4m0P6YrRQHCnRwq2GkkzUZUL7pKWIkAes+wfb1mS+EVMB3ckRyv0k5zRAvjHDHyRGKBDQQ3Th6noHnbk/Nw8QOlleYV4fr5tAXEBCiHT4MSNUlBFpxkb3CsOZhDvCvODHnV3HyMZPorPNoBsVrlj5dqJ1m/KIBmB+V22C9ZQnutFUL96H1bNlfjmgadyp4mVtdQGvdkn88uBT X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 70473c41-d542-4d24-870f-08dc7e21c9df X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB7065.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2024 07:51:17.0195 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jNkF1BA9zbmSaMK54U7RqstH5fOop/Mx5H5LTMahyp2xYXQ7CWHICXcLRi7YYY6monODu+/AofHByE6DW745DA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8781 Enable lpuart & SDHC for console and rootfs. Signed-off-by: Pengfei Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx91-11x11-evk.dts | 807 ++++++++++++++++++ 2 files changed, 808 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index bd443c2bc5a4..7083f6824e9f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -236,6 +236,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts new file mode 100644 index 000000000000..eb82a193ef72 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; + +#include +#include "imx91.dtsi" + +/ { + model = "NXP i.MX91 11X11 EVK board"; + compatible = "fsl,imx91-11x11-evk", "fsl,imx91"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + rtc0 = &bbnsm_rtc; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-name = "reg_vdd_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vrpi_3v3: regulator-vrpi-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VRPI_3V3"; + gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + vin-supply = <&buck4>; + }; + + reg_vrpi_5v: regulator-vrpi-5v { + compatible = "regulator-fixed"; + regulator-name = "VRPI_5V"; + gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + eee-broken-1000t; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110"; + reg = <0x51>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + fsl,cd-gpio-wakeup-disable; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqosgrpsleep { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX91_PAD_GPIO_IO25__CAN2_TX 0x139e + MX91_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + pinctrl_flexcan2_sleep: flexcan2sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e + MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e + MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e + MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e + MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e + MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e + MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e + MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e + MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e + MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e + MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e + MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_lcdif_gpio: lcdifgpiogrp { + fsl,pins = < + MX91_PAD_GPIO_IO00__GPIO2_IO0 0x51e + MX91_PAD_GPIO_IO01__GPIO2_IO1 0x51e + MX91_PAD_GPIO_IO02__GPIO2_IO2 0x51e + MX91_PAD_GPIO_IO03__GPIO2_IO3 0x51e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiogrpsleep { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2grpsleep { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grpsleep { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1grpsleep { + fsl,pins = < + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e + MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e + MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e + >; + }; + + pinctrl_sai3_sleep: sai3grpsleep { + fsl,pins = < + MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e + MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e + MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e + MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e + MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__PDM_CLK 0x31e + MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e + MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmgrpsleep { + fsl,pins = < + MX91_PAD_PDM_CLK__GPIO1_IO8 0x31e + MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x31e + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + + pinctrl_spdif_sleep: spdifgrpsleep { + fsl,pins = < + MX91_PAD_GPIO_IO22__GPIO2_IO22 0x31e + MX91_PAD_GPIO_IO23__GPIO2_IO23 0x31e + >; + }; +};