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Mon, 27 May 2024 09:16:21 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 1/3] clk: renesas: r8a779h0: Add VIN clocks Date: Mon, 27 May 2024 15:15:39 +0200 Message-ID: <20240527131541.1676525-2-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240527131541.1676525-1-niklas.soderlund+renesas@ragnatech.se> References: <20240527131541.1676525-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the VIN module clocks, which are used by the VIN modules on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 71f67a1c86d8..2b9c65959de6 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -188,6 +188,22 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0), DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER), DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER), + DEF_MOD("vin0", 730, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin1", 731, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin2", 800, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin3", 801, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin4", 802, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin5", 803, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin6", 804, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin7", 805, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin10", 806, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin11", 807, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin12", 808, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin13", 809, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin14", 810, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin15", 811, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin16", 812, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("vin17", 813, R8A779H0_CLK_S0D1_VIO), DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), DEF_MOD("pfc0", 915, R8A779H0_CLK_CP), DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), From patchwork Mon May 27 13:15:40 2024 Content-Type: text/plain; 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Mon, 27 May 2024 09:16:23 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 2/3] clk: renesas: r8a779h0: Add ISPCS clocks Date: Mon, 27 May 2024 15:15:40 +0200 Message-ID: <20240527131541.1676525-3-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240527131541.1676525-1-niklas.soderlund+renesas@ragnatech.se> References: <20240527131541.1676525-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the ISPCS0 and ISPCS1 module clocks, which are used by the ISPCS modules on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 2b9c65959de6..7f8e0e71a8b4 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -184,6 +184,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER), DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER), DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER), + DEF_MOD("ispcs0", 612, R8A779H0_CLK_S0D2_VIO), + DEF_MOD("ispcs1", 613, R8A779H0_CLK_S0D2_VIO), DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2), DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0), DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER), From patchwork Mon May 27 13:15:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 13675212 X-Patchwork-Delegate: geert@linux-m68k.org Received: from wfhigh1-smtp.messagingengine.com (wfhigh1-smtp.messagingengine.com [64.147.123.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6D9515E5CC; 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Mon, 27 May 2024 09:16:25 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 3/3] clk: renesas: r8a779h0: Add CSI-2 clocks Date: Mon, 27 May 2024 15:15:41 +0200 Message-ID: <20240527131541.1676525-4-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240527131541.1676525-1-niklas.soderlund+renesas@ragnatech.se> References: <20240527131541.1676525-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the CSI40 and CSI41 module clocks, which are used by the CSI-2 interfaces on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 7f8e0e71a8b4..b3cc86bb36ec 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), + DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),