From patchwork Tue May 28 02:43:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 180F8C25B74 for ; Tue, 28 May 2024 02:44:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmor-0001s3-Ud; Mon, 27 May 2024 22:44:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmoq-0001ro-1i; Mon, 27 May 2024 22:44:08 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmom-0003hC-EJ; Mon, 27 May 2024 22:44:06 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-70109d34a16so242220b3a.2; Mon, 27 May 2024 19:44:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864242; x=1717469042; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F2fI6nwAJXeFe1hxyMYDF/QLET3EtTO13tMnuGkb/Vs=; b=Rd1c3Qmgh+TuIXaz1JkQZNmIwRD27g4Z9HamwBnzl8+9154jne47jzoXRb/VJtdL1C W1Zwa9NKef8jOGGdhrTs/qDpLSyx7wuaVdJj6h2Ew99xH5H1GjiY7TMkokNFPrkPOnWw J+ILOZHucpCU+3FknNjK9b5lFeNSyGpDngWzUbxkySxKO1V+9H4BzSM6pFyVS17TIfzz dt0FZl9IdFVW4wg1OV2ZCUr12DJd5jURTyty+t4xeKXavmldhhPcRk0uR+iHllRsHqMl p3uoUSgX7Xo2CnYMxJD1FgdkKCVit4WsB3EARkWjNIBVj0xZ2i38yev8eHs2c5+8bUfV ZD1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864242; x=1717469042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F2fI6nwAJXeFe1hxyMYDF/QLET3EtTO13tMnuGkb/Vs=; b=lQ1b5STv26tDTf78m3ZM52fF/Rnklh+k+mCTNuSP0rRvSy1RHkSpgRr782hD0OSETM e5oYLRL1ALjBKWWv5fXzPjptK47jMxol6eT3h+KNzz3d7ppoJXccJWAxFxgIzzYrPZHB FTAeJ3MmXBQoApOYif7EP5rXudKYokudk6LL8aDjnGMbnDFKPEU1MSln8GoQWNzQUPCY xBko/GYQDHRxFLhPDwX+kp5gpiqpaYXu4xi4PGkievMkpKpZW+FBp6JA0R0v+tNf/Ep+ 6GkrCKYHUU6r1+DB+K3MEkulAhbIUELRSQxf+sITV7CgteXNPHEfYrHEafzpHMkQd4f5 Nslg== X-Forwarded-Encrypted: i=1; AJvYcCX6ki0tqpb45TFssZNLG9+3rGO/vvM8kjd8KQYGty34VZv0xLqPkgln2K0u6AnmSe8dpYs05Ve+PaHGlXJv/uOLUnjV8gRQ X-Gm-Message-State: AOJu0Yx/idQTmIdTdY6js1VdTHbAA/weAtbz24l9trKj9+c9+VGxbWNk 7Bp65CPQJcA79JlxXVrSghNbSxKA56/Ap1+I2pIx4yl+OyWxyCoioSkHWg== X-Google-Smtp-Source: AGHT+IEURWKJSnllvdHQtp1ADQBWCW53PlI5ryhsHlqVZgo2m3Z7/WUmlIy+cmLE5iTWf8KYXUMzhw== X-Received: by 2002:a05:6a21:27a9:b0:1b1:f7a1:df97 with SMTP id adf61e73a8af0-1b212e3aa39mr10696527637.54.1716864241914; Mon, 27 May 2024 19:44:01 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.43.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:01 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, "yang.zhang" , Daniel Henrique Barboza , qemu-stable , Alistair Francis Subject: [PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize Date: Tue, 28 May 2024 12:43:01 +1000 Message-ID: <20240528024328.246965-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: "yang.zhang" Since only root APLICs can have hw IRQ lines, aplic->parent should be initialized first. Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation") Reviewed-by: Daniel Henrique Barboza Signed-off-by: yang.zhang Cc: qemu-stable Message-ID: <20240409014445.278-1-gaoshanliukou@163.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aplic.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index fc5df0d598..32edd6d07b 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -1000,16 +1000,16 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, qdev_prop_set_bit(dev, "msimode", msimode); qdev_prop_set_bit(dev, "mmode", mmode); + if (parent) { + riscv_aplic_add_child(parent, dev); + } + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); if (!is_kvm_aia(msimode)) { sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); } - if (parent) { - riscv_aplic_add_child(parent, dev); - } - if (!msimode) { for (i = 0; i < num_harts; i++) { CPUState *cpu = cpu_by_arch_id(hartid_base + i); From patchwork Tue May 28 02:43:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60193C25B7C for ; Tue, 28 May 2024 02:44:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmox-0001zq-BG; Mon, 27 May 2024 22:44:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmot-0001sZ-7Y; Mon, 27 May 2024 22:44:11 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmoq-0003hi-2R; Mon, 27 May 2024 22:44:10 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1f44b45d6abso2988435ad.0; Mon, 27 May 2024 19:44:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864245; x=1717469045; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D8UK8uAVTnW82lBqc0PHDyOOwY4BUuAnWYWQniDrcpo=; b=gzpPVTkfDP3ENordFuovrv5fHn/u+q8WXGi1r4Om3mhuLVNZhPMnnUgmun+LKwJoEa 7PeyvtiEU2JiAa9fkPWMiRluouI6+30RdAxBAsOyJS3Qd5LvkybuJDX1v4jaX9hqOhIc 2rVXu3bDUk5T7gg5cfvijtGZHcCsZK4Mnu52dy9R6rzRKULVs0fSyJvKPpe4bziBDyoI Rs/Rbumx5PhTJ+AdwQu9fEqlfdf01ETC4gbMP2gSHYxyw0n0vBT7zfLW2IocnrHjgiDr qWAQ6EhzzqsfUiQgzcfruYhBlZqQ1qpRb6j3Xq/Acp1jni8jqMM7UtQv+PDSc2S3O4qu xOWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864245; x=1717469045; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D8UK8uAVTnW82lBqc0PHDyOOwY4BUuAnWYWQniDrcpo=; b=fEcmAIh+O/KGek59n9LIoN0tumXPW0xS/XdH4Zitdxt3GS941rnCBt+KWP2oUUW0jF UIZwwOIG0Ylx0ZdhCtgaBjvNdelLXpuAPNHZ4gsQ6UJHG4zEldBgGvDQM2JWCzIjCMXC smzveNERbfe+B435F9RSLRhjC9VEFkQVxZxeclgmlLtgmMBRjB/9STGIhPSEnx8OEG3a R7D/ys6h/ekTZRizK9T8a02/+tmVI+d6gSq7St5LGcL6hU4J7Pgg1yk8Zo7oA0uDw5Y6 oQM3MG/h9MMm4sYUpNrQ8CSbO+pwp/xGSRlI62U1KYbw+v6EPr1l/772s0BDlm1iMiGa Fa1A== X-Forwarded-Encrypted: i=1; AJvYcCWQkORBqw1faPlsaTjonHKW9RIq316nsI55BKqT9RIVV83DftNqleWY/7z3eEobWRxF/6wq0cDHFnuUC4ypg1M630zhWQFF X-Gm-Message-State: AOJu0YwmNE990vXsPfemBC/rUMlX3L4rUDXBK1gvl14Q/oOXqQS1iOT0 96ev/1v6ZP7w21zqLTaPjV7KIv8BSePOTjoVboR/UNxD7n3HoelPga/x0A== X-Google-Smtp-Source: AGHT+IGhv6X9Tw9YAcoS4jjlrHDAmQ8glmnqfh9Jx0yTE8bM8RWt3n459uoJGGnTCoHr7PwUpXLKwA== X-Received: by 2002:a17:902:ce12:b0:1f4:977e:bf with SMTP id d9443c01a7336-1f4977e13cbmr56012445ad.19.1716864245109; Mon, 27 May 2024 19:44:05 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Andrew Jones , Daniel Henrique Barboza , qemu-stable , Alistair Francis Subject: [PULL 02/28] target/riscv/kvm: Fix exposure of Zkr Date: Tue, 28 May 2024 12:43:02 +1000 Message-ID: <20240528024328.246965-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Andrew Jones The Zkr extension may only be exposed to KVM guests if the VMM implements the SEED CSR. Use the same implementation as TCG. Without this patch, running with a KVM which does not forward the SEED CSR access to QEMU will result in an ILL exception being injected into the guest (this results in Linux guests crashing on boot). And, when running with a KVM which does forward the access, QEMU will crash, since QEMU doesn't know what to do with the exit. Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8") Signed-off-by: Andrew Jones Reviewed-by: Daniel Henrique Barboza Cc: qemu-stable Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +++ target/riscv/csr.c | 18 ++++++++++++++---- target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2d0c02c35b..746efd099a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -819,6 +819,9 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +target_ulong riscv_new_csr_seed(target_ulong new_value, + target_ulong write_mask); + uint8_t satp_mode_max_from_map(uint32_t map); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 726096444f..829d8346ed 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -4267,10 +4267,8 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno, #endif /* Crypto Extension */ -static RISCVException rmw_seed(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, - target_ulong write_mask) +target_ulong riscv_new_csr_seed(target_ulong new_value, + target_ulong write_mask) { uint16_t random_v; Error *random_e = NULL; @@ -4294,6 +4292,18 @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno, rval = random_v | SEED_OPST_ES16; } + return rval; +} + +static RISCVException rmw_seed(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask) +{ + target_ulong rval; + + rval = riscv_new_csr_seed(new_value, write_mask); + if (ret_value) { *ret_value = rval; } diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index eaa36121c7..b8136c7ef8 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1418,6 +1418,28 @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) return ret; } +static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) +{ + target_ulong csr_num = run->riscv_csr.csr_num; + target_ulong new_value = run->riscv_csr.new_value; + target_ulong write_mask = run->riscv_csr.write_mask; + int ret = 0; + + switch (csr_num) { + case CSR_SEED: + run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s: un-handled CSR EXIT for CSR %lx\n", + __func__, csr_num); + ret = -1; + break; + } + + return ret; +} + int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { int ret = 0; @@ -1425,6 +1447,9 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) case KVM_EXIT_RISCV_SBI: ret = kvm_riscv_handle_sbi(cs, run); break; + case KVM_EXIT_RISCV_CSR: + ret = kvm_riscv_handle_csr(cs, run); + break; default: qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", __func__, run->exit_reason); From patchwork Tue May 28 02:43:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4753C25B7C for ; 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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:07 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Andrew Jones , =?utf-8?q?Christoph_M=C3=BCllner?= , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 03/28] target/riscv: Raise exceptions on wrs.nto Date: Tue, 28 May 2024 12:43:03 +1000 Message-ID: <20240528024328.246965-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=alistair23@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Andrew Jones Implementing wrs.nto to always just return is consistent with the specification, as the instruction is permitted to terminate the stall for any reason, but it's not useful for virtualization, where we'd like the guest to trap to the hypervisor in order to allow scheduling of the lock holding VCPU. Change to always immediately raise exceptions when the appropriate conditions are present, otherwise continue to just return. Note, immediately raising exceptions is also consistent with the specification since the time limit that should expire prior to the exception is implementation-specific. Signed-off-by: Andrew Jones Reviewed-by: Christoph Müllner Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 1 + target/riscv/op_helper.c | 11 ++++++++ target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++------- 3 files changed, 32 insertions(+), 9 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 8a63523851..451261ce5a 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -132,6 +132,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) +DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush_all, void, env) /* Native Debug */ diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f414aaebdb..2baf5bc3ca 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -380,6 +380,17 @@ void helper_wfi(CPURISCVState *env) } } +void helper_wrs_nto(CPURISCVState *env) +{ + if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) && + get_field(env->hstatus, HSTATUS_VTW) && + !get_field(env->mstatus, MSTATUS_TW)) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); + } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } +} + void helper_tlb_flush(CPURISCVState *env) { CPUState *cs = env_cpu(env); diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc index 32efbff4d5..0eef033838 100644 --- a/target/riscv/insn_trans/trans_rvzawrs.c.inc +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc @@ -16,7 +16,7 @@ * this program. If not, see . */ -static bool trans_wrs(DisasContext *ctx) +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a) { if (!ctx->cfg_ptr->ext_zawrs) { return false; @@ -40,12 +40,23 @@ static bool trans_wrs(DisasContext *ctx) return true; } -#define GEN_TRANS_WRS(insn) \ -static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a) \ -{ \ - (void)a; \ - return trans_wrs(ctx); \ -} +static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a) +{ + if (!ctx->cfg_ptr->ext_zawrs) { + return false; + } -GEN_TRANS_WRS(wrs_nto) -GEN_TRANS_WRS(wrs_sto) + /* + * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto + * should raise an exception when the implementation-specific bounded time + * limit has expired. Our time limit is zero, so we either return + * immediately, as does our implementation of wrs.sto, or raise an + * exception, as handled by the wrs.nto helper. + */ +#ifndef CONFIG_USER_ONLY + gen_helper_wrs_nto(tcg_env); +#endif + + /* We only get here when helper_wrs_nto() doesn't raise an exception. */ + return trans_wrs_sto(ctx, NULL); +} From patchwork Tue May 28 02:43:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C70B8C25B7C for ; Tue, 28 May 2024 02:47:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmp0-0002BE-9e; Mon, 27 May 2024 22:44:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmoy-00023g-NW for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:17 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmow-0003im-Mz for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:16 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1f47f07acd3so3097585ad.0 for ; Mon, 27 May 2024 19:44:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864252; x=1717469052; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BYkKX6SyHTy9ybNO6w9asZ98c6YU/EoDeMWCewzI1/4=; b=gT5vo1UZ2rPbCpph7NZKxKzaUzrRzIDU9twxPs2JsJlr6BukRag/q7MLy/I/up1PcX 89Y0P0GdA3x3b3LftE85yysVdCRXlsuQ5F3K+XsdGuezA0lQJ9FjZdmcIUM59FwOS1vw QNaBZaCIDcFUBnu6t7GRXtOnWSsMAa282E78jNh5rTOMIN+EZ1opjHen/8bsZPirJatv YLhHKwQt+IyNRq45ZKyET6mc4Q2zsIS6WhBT7ergdUmxbmEgb9kbF1jKmyX/6A6egnA4 hlArhE6xC6a70ZsfHdC5MbPGgi4ydEyebRg9Q/c2kkXU6p/deM+vbG5admpeW6IkiRNt cWbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864252; x=1717469052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BYkKX6SyHTy9ybNO6w9asZ98c6YU/EoDeMWCewzI1/4=; b=Dz1NqnfefacSycwobHfw0WNmlhl+yEP3PLMcfpudETk2KDFzkvXGnLaXAJQhVBAYX+ awSn5A6njyG56CZ6Tug8ug9GINULUk+CfXBtAyJfV/mo5H1QzzS+jT7HLDzX9pZZ8JmD NcTrPRS76YBefw4aEtSLshER++HprBNRITCe4jPx7vdLB2DVTkGoZUrrIxZ+SCQY5Wmy R05cooGeUwdGuaAQ3JAMx3lJJOAs7gSaF2zY32KEy0X894tTK51nbTMUWX0LLYTfSM6X 2vYc4YU2xxIzg5+0yLGd1A1eSsxi5fKXuTKJTY9t3I162J1wJ4JSFMbHqD3RKkPp4N5I mFLg== X-Gm-Message-State: AOJu0Yz02XvM/MJ+QJ7lBu5zJtup2KNSDsomWd8TwsXgzxtxqR0LK+q8 epX7PjKMxLS4j1OAMm/aKFJc65ZuYop7zORRRv0sgqWHt2iraY5Y9j+2zQ== X-Google-Smtp-Source: AGHT+IFBM8C4IoKQ1CwQ0ShAh58PNUrksvc42duqndOs7Xqp9IvicB1cwITkMgsWTKByWO/WcLC+pA== X-Received: by 2002:a17:902:e5ca:b0:1f4:8e4a:b781 with SMTP id d9443c01a7336-1f48e4aba48mr59157565ad.18.1716864252078; Mon, 27 May 2024 19:44:12 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:11 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls Date: Tue, 28 May 2024 12:43:04 +1000 Message-ID: <20240528024328.246965-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=alistair23@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza SBI defines a Debug Console extension "DBCN" that will, in time, replace the legacy console putchar and getchar SBI extensions. The appeal of the DBCN extension is that it allows multiple bytes to be read/written in the SBI console in a single SBI call. As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM module to userspace. But this will only happens if the KVM module actually supports this SBI extension and we activate it. We'll check for DBCN support during init time, checking if get-reg-list is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via kvm_set_one_reg() during kvm_arch_init_vcpu(). Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for SBI_EXT_DBCN, reading and writing as required. A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V host, takes around 20 seconds to boot without using DBCN. With this patch we're taking around 14 seconds to boot due to the speed-up in the terminal output. There's no change in boot time if the guest isn't using earlycon. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/sbi_ecall_interface.h | 17 +++++ target/riscv/kvm/kvm-cpu.c | 111 +++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+) diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h index 43899d08f6..7dfe5f72c6 100644 --- a/target/riscv/sbi_ecall_interface.h +++ b/target/riscv/sbi_ecall_interface.h @@ -12,6 +12,17 @@ /* clang-format off */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILED -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_NO_SHMEM -9 + /* SBI Extension IDs */ #define SBI_EXT_0_1_SET_TIMER 0x0 #define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 @@ -27,6 +38,7 @@ #define SBI_EXT_IPI 0x735049 #define SBI_EXT_RFENCE 0x52464E43 #define SBI_EXT_HSM 0x48534D +#define SBI_EXT_DBCN 0x4442434E /* SBI function IDs for BASE extension */ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 @@ -57,6 +69,11 @@ #define SBI_EXT_HSM_HART_STOP 0x1 #define SBI_EXT_HSM_HART_GET_STATUS 0x2 +/* SBI function IDs for DBCN extension */ +#define SBI_EXT_DBCN_CONSOLE_WRITE 0x0 +#define SBI_EXT_DBCN_CONSOLE_READ 0x1 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2 + #define SBI_HSM_HART_STATUS_STARTED 0x0 #define SBI_HSM_HART_STATUS_STOPPED 0x1 #define SBI_HSM_HART_STATUS_START_PENDING 0x2 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index b8136c7ef8..d2491d84e2 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -409,6 +409,12 @@ static KVMCPUConfig kvm_v_vlenb = { KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) }; +static KVMCPUConfig kvm_sbi_dbcn = { + .name = "sbi_dbcn", + .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | + KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN +}; + static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) { CPURISCVState *env = &cpu->env; @@ -1037,6 +1043,20 @@ static int uint64_cmp(const void *a, const void *b) return 0; } +static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, + KVMScratchCPU *kvmcpu, + struct kvm_reg_list *reglist) +{ + struct kvm_reg_list *reg_search; + + reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, + sizeof(uint64_t), uint64_cmp); + + if (reg_search) { + kvm_sbi_dbcn.supported = true; + } +} + static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, struct kvm_reg_list *reglist) { @@ -1142,6 +1162,8 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) if (riscv_has_ext(&cpu->env, RVV)) { kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); } + + kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist); } static void riscv_init_kvm_registers(Object *cpu_obj) @@ -1316,6 +1338,17 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) return ret; } +static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) +{ + target_ulong reg = 1; + + if (!kvm_sbi_dbcn.supported) { + return 0; + } + + return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret = 0; @@ -1333,6 +1366,8 @@ int kvm_arch_init_vcpu(CPUState *cs) kvm_riscv_update_cpu_misa_ext(cpu, cs); kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); + ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); + return ret; } @@ -1390,6 +1425,79 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs) return true; } +static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) +{ + g_autofree uint8_t *buf = NULL; + RISCVCPU *cpu = RISCV_CPU(cs); + target_ulong num_bytes; + uint64_t addr; + unsigned char ch; + int ret; + + switch (run->riscv_sbi.function_id) { + case SBI_EXT_DBCN_CONSOLE_READ: + case SBI_EXT_DBCN_CONSOLE_WRITE: + num_bytes = run->riscv_sbi.args[0]; + + if (num_bytes == 0) { + run->riscv_sbi.ret[0] = SBI_SUCCESS; + run->riscv_sbi.ret[1] = 0; + break; + } + + addr = run->riscv_sbi.args[1]; + + /* + * Handle the case where a 32 bit CPU is running in a + * 64 bit addressing env. + */ + if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { + addr |= (uint64_t)run->riscv_sbi.args[2] << 32; + } + + buf = g_malloc0(num_bytes); + + if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { + ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes); + if (ret < 0) { + error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " + "reading chardev"); + exit(1); + } + + cpu_physical_memory_write(addr, buf, ret); + } else { + cpu_physical_memory_read(addr, buf, num_bytes); + + ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes); + if (ret < 0) { + error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " + "writing chardev"); + exit(1); + } + } + + run->riscv_sbi.ret[0] = SBI_SUCCESS; + run->riscv_sbi.ret[1] = ret; + break; + case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: + ch = run->riscv_sbi.args[0]; + ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); + + if (ret < 0) { + error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " + "writing chardev"); + exit(1); + } + + run->riscv_sbi.ret[0] = SBI_SUCCESS; + run->riscv_sbi.ret[1] = 0; + break; + default: + run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; + } +} + static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) { int ret = 0; @@ -1408,6 +1516,9 @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) } ret = 0; break; + case SBI_EXT_DBCN: + kvm_riscv_handle_sbi_dbcn(cs, run); + break; default: qemu_log_mask(LOG_UNIMP, "%s: un-handled SBI EXIT, specific reasons is %lu\n", From patchwork Tue May 28 02:43:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30613C25B7E for ; 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Signed-off-by: Cheng Yang Reviewed-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- hw/riscv/boot.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 09878e722c..47281ca853 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -209,8 +209,8 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ if (fdt) { end = start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end); } } From patchwork Tue May 28 02:43:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 592ECC25B74 for ; Tue, 28 May 2024 02:47:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmp5-0002Ok-Pt; Mon, 27 May 2024 22:44:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmp4-0002Io-7b for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:22 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmp1-0003jD-Dt for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:21 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1f47db642c2so2861425ad.2 for ; Mon, 27 May 2024 19:44:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864257; x=1717469057; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UPlluaU0uKur6NZ6KKIaWWCj2wxgWKV0EN/SjQ103ro=; b=inzHFm5PgjvUzerxpCyEqauZStu/LYIrBDqQAh46HWxXehZGmw8m0B5tUELjlr3BDP K7F+andVXGbi3xKDDfV0Qb4JqWV3fMcbtEBBvy7O6nmKMJU7Zf1HOQdjG9UOKgVKgRt2 1BUAAB2iOivCa1uo/3xIHCoLisw4ugs5BWJMB0QTUQcgulsMyb+YJLSx32tVZpF/WOvV WFPUNvaJ6sm9Wg63nUXrGj99FUQhyDBSrgx0eF309UEzXvNHZ3hht0rAdIR6FdpA238a 2lSICcXrx7hW6HNRa7g4OgaJ4UUhRsRRVRSHXHSlm6l14A5llLAA32NOD59hn5DOLP1t ez5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864257; x=1717469057; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UPlluaU0uKur6NZ6KKIaWWCj2wxgWKV0EN/SjQ103ro=; b=uN+QjuF6CKaI3skHBqF+N2kP8Hiui0ArgCHdjRGaghaO1ZINmScbZm6fzP8i8MB0c2 T33a5dUZlCWcmf8W/wg3HZOjA9zN/RujlAZwh2afA4h24O2K0Nm8Zh/ystju3za48Ibn efB+S7muQ21ifhjrLz2aiOJyIWJDI+sQE5lCTvWQZ8fO2nmZbqyT7eKUc1gh+giptFLs UbxJn4YbL0Uj4Y7ssGzmH0vg1V62cgTDttSgWA6FknaarUchR6ssxdqQ3Avyhosj8CC1 lEFfDGybfLkacwC9ltduZSPS2BhsktRr2Nal6pwqi/L8hSThXjdY01qbLuN7WZm/5xXX 6jAg== X-Gm-Message-State: AOJu0YwKrN9W4zbyjEV8GpiuSR2E7IMUcrjWZbDc+RiiEhbrTlHTM66t BbLStZNh3x/uVdCOFWqS2H5ttQjHhXtVsDE71bBdi5sYADSspQBrzaKrxw== X-Google-Smtp-Source: AGHT+IE4BqkIkrCf0+yByLcMM3G781L4+L0Arn895+9fyiOkh+ZS0lOrX5+CNQXxuQSS17/5Xmy1LA== X-Received: by 2002:a17:902:f791:b0:1f4:6b1b:9439 with SMTP id d9443c01a7336-1f46b1b987bmr90892575ad.53.1716864257432; Mon, 27 May 2024 19:44:17 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:16 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Alistair Francis Subject: [PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63 Date: Tue, 28 May 2024 12:43:06 +1000 Message-ID: <20240528024328.246965-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Léger The current semihost exception number (16) is a reserved number (range [16-17]). The upcoming double trap specification uses that number for the double trap exception. Since the privileged spec (Table 22) defines ranges for custom uses change the semihosting exception number to 63 which belongs to the range [48-63] in order to avoid any future collisions with reserved exception. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fc2068ee4d..74318a925c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -670,11 +670,11 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ - RISCV_EXCP_SEMIHOST = 0x10, RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, + RISCV_EXCP_SEMIHOST = 0x3f, } RISCVException; #define RISCV_EXCP_INT_FLAG 0x80000000 From patchwork Tue May 28 02:43:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A415FC25B74 for ; Tue, 28 May 2024 02:46:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmp7-0002Yx-Kp; Mon, 27 May 2024 22:44:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmp6-0002Ry-HN; Mon, 27 May 2024 22:44:24 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmp4-0003jK-NC; Mon, 27 May 2024 22:44:24 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1f4a6a54416so2388495ad.0; Mon, 27 May 2024 19:44:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864261; x=1717469061; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PGSDVwJ0PbsAM8k/8MYYmnPwZRw9PEeElr3mXEVUI30=; b=RI1EiTh+YNL71hCrmLbIsMBV8nZ0BH5YYdBkU3Yd92xt6UsdcxdE8eyr1pEcqxaQnO +7IU+RfvE8hvYZYUlEUARW2QdUJIeohysDfWETIaSoGsdQKZRJ/1QeurGGFTR+7SEIQh BEiIQC5MQFuD+6o5lnhrSL4tPOs9H6T3fnGuo7HMDNA5l3IVAEyCZ6AioIoxgzDC5A6/ fISOhhGWEkrg2pRP3Y1k1nvtbcDBBSBnC6CaSyYL9Swg0W248KBgxoKLbgevLbTgvnVB adfDyEy4rmuJSTj4SjfiOuuDxGawOX4d19/UN1eTo6qWp/3jIMyF/eLJiLPbbVnDfedp GwmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864261; x=1717469061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PGSDVwJ0PbsAM8k/8MYYmnPwZRw9PEeElr3mXEVUI30=; b=D7FNXDuj2ti7abaGigU39+o+Xejmzk+BOePFlQD+W/GkwdGCr/c+aYgGPQp9P0/iM9 e3DPr30gxgl2gv1keS3mjwGyNOGo5XBC3JdsdL8+CcmkPdxKUzICvYIxkNE0tNYnfnus ymBTxUmZ/EgmrFhprZ1YnO8rfHTLtPVG9ujgSN8xPP5ycc91d/nLL9eAYPQN7BVYYgIA moCJfLF0yhUS9Nz2wbkIuHI0R79OJ2Z2WBmKYVeqOt6/Q6LNZ1fhIaAafftbOrvQvnup w1vsE1xtDLoTZxsWOMz9m6XcDmLwvDcH2C58Dzx+HIybQtJmnRCQ7bAJqIv3NY+kKD6x Xjxw== X-Forwarded-Encrypted: i=1; AJvYcCVdJbg1zfXkame7FV/OJS2ZLW/WexFyvHuTRyfCnKXnWh3tbiyLsvz0GqvFlJqaOeFBHDrLPUX/mVwP5itQcOz2UHyDRANV X-Gm-Message-State: AOJu0Ywx3EWVcS5tC/QHn2ueUMGq7EnerT83pLwnDTZTrdCBxkJ5MnXe pgxmuTz6RJ31F8bUFi1r26lK9Cui+6fB/RotqNppTKTe0yw6eBKl1XciHA== X-Google-Smtp-Source: AGHT+IHGAfKNgC+eh987FAw8Sl72Piu8iMc1GAsWmASL+ZlTv59TPy4ud9SnNgwFdb6kWjyXViCgkg== X-Received: by 2002:a17:902:d58c:b0:1f2:fcc0:66f with SMTP id d9443c01a7336-1f448248a0emr165604775ad.31.1716864260654; Mon, 27 May 2024 19:44:20 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:20 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , qemu-stable , Alistair Francis Subject: [PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors Date: Tue, 28 May 2024 12:43:07 +1000 Message-ID: <20240528024328.246965-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr enabled, will fail with a kernel oops SIGILL right at the start. The reason is that we can't expose zkr without implementing the SEED CSR. Disabling zkr in the guest would be a workaround, but if the KVM doesn't allow it we'll error out and never boot. In hindsight this is too strict. If we keep proceeding, despite not disabling the extension in the KVM vcpu, we'll not add the extension in the riscv,isa. The guest kernel will be unaware of the extension, i.e. it doesn't matter if the KVM vcpu has it enabled underneath or not. So it's ok to keep booting in this case. Change our current logic to not error out if we fail to disable an extension in kvm_set_one_reg(), but show a warning and keep booting. It is important to throw a warning because we must make the user aware that the extension is still available in the vcpu, meaning that an ill-behaved guest can ignore the riscv,isa settings and use the extension. The case we're handling happens with an EINVAL error code. If we fail to disable the extension in KVM for any other reason, error out. We'll also keep erroring out when we fail to enable an extension in KVM, since adding the extension in riscv,isa at this point will cause a guest malfunction because the extension isn't enabled in the vcpu. Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Cc: qemu-stable Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index d2491d84e2..473416649f 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -433,10 +433,14 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); ret = kvm_set_one_reg(cs, id, ®); if (ret != 0) { - error_report("Unable to %s extension %s in KVM, error %d", - reg ? "enable" : "disable", - multi_ext_cfg->name, ret); - exit(EXIT_FAILURE); + if (!reg && ret == -EINVAL) { + warn_report("KVM cannot disable extension %s", + multi_ext_cfg->name); + } else { + error_report("Unable to enable extension %s in KVM, error %d", + multi_ext_cfg->name, ret); + exit(EXIT_FAILURE); + } } } } From patchwork Tue May 28 02:43:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBC80C25B74 for ; Tue, 28 May 2024 02:45:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmp9-0002ju-SO; Mon, 27 May 2024 22:44:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmp8-0002fi-TO for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:26 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmp7-0003jY-3Y for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:26 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-6f8e859eb20so250631b3a.0 for ; Mon, 27 May 2024 19:44:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864263; x=1717469063; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ueu7vuYmn8RUHwOpB4gRtq7cx4bSTGY9+BukiSLE2tw=; b=IHArGdhy8HnMWBLaBDH2uq/5U/sH4dvDzqaYeqiNDsN9ZmpDGleqUdtIhw7OkuM4Tt I6pgZOxgCrj6ZpDf5IYl5W54OqNbde+E/R5OcKG8kXi8+0IQ6MmJfc6iS0P5R+6fFALf 6QC3YMkWISnM/h+Q5yTyIUG6hn1217QR72T+QmlTRHHacwCRa3e78GhkTcYB56nOi3i0 TlumyLrV2QSM9+7n8J+z/qIW4Ko3lUBlEeycdyjo8I7ktdbfFin/EEZ3JHkG/Uzna99+ vpiPMd+VuqEh+gcF3YdK8JBuEeXj2iK5WOcdKQUb3OuXrtZJ0Ogjzewq4u3oiZyXxZ+P QQ6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864263; x=1717469063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ueu7vuYmn8RUHwOpB4gRtq7cx4bSTGY9+BukiSLE2tw=; b=qAWeiy4KE9i2hs2GUbJlIf8n/YjBaEulF03SGlhqwLWvdVriZ8I+kp0+IVI4D+7vH6 4iQYtvTnbTFPdhYSamQjA62qLixnPvj4BZP32o0i2MNO7FlhyMF26TtleYUTB1Vc/fhm qwRvQlysmfJiI7ZuajoB24EZAL8m9zJ90VUIdhdsALZVVB+vT2iXyqFfQtlzhD93jtU6 4oy+lNiI81YQG6i4wvz5cxpRaKVkDWOqyBuAZXuIvR8hDFGBbChLwezqdyEEnZwbfRTX EusZsUtcSu4M5rRG3D72rAREzTN42WkfMGp+qApBMFPtRcGOiUHCMKGzXL8TxJ/eEg7w RkwA== X-Gm-Message-State: AOJu0Yzy5xKa4r0aljP/YmskREeHTJiThostelesDH+AgQ7KwgTTrkWr H9vKmajSXsDlCr/TqHd+q7dFyo+q8ehKzOE6Jgx1Uy2ZKNL2Q2ETPxMZJg== X-Google-Smtp-Source: AGHT+IHQsMDxnNUkEE816fbrBtWokGXFfoWvW/VAqBjHtNk+We9kF9dhJQBLZGFx7NmXARRjdT/GBQ== X-Received: by 2002:a05:6a20:9d8e:b0:1b1:ec00:dac8 with SMTP id adf61e73a8af0-1b212df058amr10592912637.27.1716864263583; Mon, 27 May 2024 19:44:23 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:23 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , LIU Zhiwei Subject: [PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions Date: Tue, 28 May 2024 12:43:08 +1000 Message-ID: <20240528024328.246965-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=alistair23@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza We're not setting (s/m)tval when triggering breakpoints of type 2 (mcontrol) and 6 (mcontrol6). According to the debug spec section 5.7.12, "Match Control Type 6": "The Privileged Spec says that breakpoint exceptions that occur on instruction fetches, loads, or stores update the tval CSR with either zero or the faulting virtual address. The faulting virtual address for an mcontrol6 trigger with action = 0 is the address being accessed and which caused that trigger to fire." A similar text is also found in the Debug spec section 5.7.11 w.r.t. mcontrol. Note that what we're doing ATM is not violating the spec, but it's simple enough to set mtval/stval and it makes life easier for any software that relies on this info. Given that we always use action = 0, save the faulting address for the mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is used as as scratch area for traps with address information. 'tval' is then set during riscv_cpu_do_interrupt(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 1 + target/riscv/debug.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8ad546a45a..179cf3d1a1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1718,6 +1718,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) tval = env->bins; break; case RISCV_EXCP_BREAKPOINT: + tval = env->badaddr; if (cs->watchpoint_hit) { tval = cs->watchpoint_hit->hitaddr; cs->watchpoint_hit = NULL; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index e30d99cc2f..b110370ea6 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -798,6 +798,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) { /* check U/S/M bit against current privilege level */ if ((ctrl >> 3) & BIT(env->priv)) { + env->badaddr = pc; return true; } } @@ -810,11 +811,13 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ if ((ctrl >> 23) & BIT(env->priv)) { + env->badaddr = pc; return true; } } else { /* check U/S/M bit against current privilege level */ if ((ctrl >> 3) & BIT(env->priv)) { + env->badaddr = pc; return true; } } From patchwork Tue May 28 02:43:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81E3CC25B7C for ; Tue, 28 May 2024 02:45:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpF-0002yP-29; Mon, 27 May 2024 22:44:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpD-0002w1-Nq for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:31 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpB-0003jr-EN for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:31 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-2bdefdeb545so262586a91.2 for ; Mon, 27 May 2024 19:44:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864267; x=1717469067; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ql0FgN5uAYwS4fjD417MxORch4Nog+b+HrGavXDYZwI=; b=H2GqarPhN0kqpLMmWqjVdNsC55+kNkjIwXAeUTpq777S0m4XtMQznwFp0/BuxwgQpt H5GjCObpTnu7LAkn7rMo1PrH+7rUynqM10JlZDQry61rpOyEkusBGuvyztuabQIraGJ3 8e8WJRDJkXERgcANJ1PKlhJvgdGjbgOFvR+vCzBObQSpZVbucPz6mmWONJPMZFY/eZBd QCn4FtFnx0GCMzYc2BQaaHNusU09Udb6pI3M/eMx/j2C7CcZ0A0oJq+p7yiiH2y3bS0/ dCSVZl7CELAziWNjELkat6KdcL25lUswjdw4stiWoF+g2Zn4quSs50xQO/CFZWYY5Wtt 1dNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864267; x=1717469067; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ql0FgN5uAYwS4fjD417MxORch4Nog+b+HrGavXDYZwI=; b=krIixk4IKFX3goAlupEHKUBBRDkC1/1xpkJXTBBPRf5vTUWrWR0pkgosbsTNfmFjx4 EhV8sGqmDktz8ISMtnQa/u7xgCYD1z77lRUDj9AyYvyvfCsmgqcO7JAeV8VPXDnAMxS+ rRYnj4ugCoR7gj3gQEgsh4TrAmfbdzKh2AYF5PNBSfTMIhx0APjg+HMOc33hIky8xeIx qejArcWanOEzbyEUsWvc8/9bP69mU8GmE6WYIF8Y+UiaTp7r/oDg9jeApXun5L7Tc1rN Zq/+PA7lNyiY7JvtNo1cqXsZA47HWounzMjR8utZ+9g2tqVduLGyCksvPblIx+SrCnxt BTPw== X-Gm-Message-State: AOJu0Yy8A2OhEv0laTrjO8cmauTTgoQEPDzFiPqzG6bvITeUvHjliqaP l8mmC8ZjzD2A6Xt2a4zutX7oamwwbNT2F4hsupjuMSz/G1k8xA+cOjXm/A== X-Google-Smtp-Source: AGHT+IFZbKQEfLwaWE7UGaUvdtw6KhORrld8W9I60HoCXD5SqbPydenu8wCfDRn08LNvkum6C4Zm/g== X-Received: by 2002:a17:90a:c257:b0:2bd:edbe:4e1 with SMTP id 98e67ed59e1d1-2bf5f2080b5mr10244051a91.31.1716864266759; Mon, 27 May 2024 19:44:26 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:26 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , LIU Zhiwei , Richard Henderson Subject: [PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint Date: Tue, 28 May 2024 12:43:09 +1000 Message-ID: <20240528024328.246965-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza Privileged spec section 4.1.9 mentions: "When a trap is taken into S-mode, stval is written with exception-specific information to assist software in handling the trap. (...) If stval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then stval will contain the faulting virtual address." A similar text is found for mtval in section 3.1.16. Setting mtval/stval in this scenario is optional, but some softwares read these regs when handling ebreaks. Write 'badaddr' in all ebreak breakpoints to write the appropriate 'tval' during riscv_do_cpu_interrrupt(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_privileged.c.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 620ab54eb0..bc5263a4e0 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -62,6 +62,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { generate_exception(ctx, RISCV_EXCP_SEMIHOST); } else { + tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, + offsetof(CPURISCVState, badaddr)); generate_exception(ctx, RISCV_EXCP_BREAKPOINT); } return true; From patchwork Tue May 28 02:43:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08F91C25B7C for ; Tue, 28 May 2024 02:45:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpS-0003vd-Oe; Mon, 27 May 2024 22:44:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpQ-0003nf-Qi for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:44 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpD-0003k6-TU for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:44 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1f44b42e9a6so3053135ad.0 for ; Mon, 27 May 2024 19:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864270; x=1717469070; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ObFEgQY5wZEWImSu4eT6GUcuwz9M2wSSVb6vxWt0eME=; b=JsUYtWcOQiD8DajQgp4IBPiw0fTZiW9iwolRmWkH8IPozGws/L/gWijK5RyjnpsrBO COBRD/tI2gI7sbkkEw1Q+s6lscq2P/Vzih556RMijzSB0dFzOoWySO8B4u1/aNIpTSpr OVn0gvKqtnZe9DT9ZQ5Nr7b65xP7w0u5PArr4i/pMpLZGpjJe4Vj1JSga0KvHBVXu9XC nlsgU+M8O7uBEKlbfNFMlb3HV+Cqox+5FVxVSF712RBx0zqRqEpz+A92ApEYjweFIaXj XH7OF3+JcZbUrWuXeXL7hcEPbs31eZ6aeeA6UGPIFomudLiyKmVfE8swFglA74CoofzY 4xug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864270; x=1717469070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ObFEgQY5wZEWImSu4eT6GUcuwz9M2wSSVb6vxWt0eME=; b=Sz8UMn0bojR1JuKKSL7xoVyFsiqENhbAsy14uXRSFyCdm5oHVkMULQz2PmU4a+hv2z ivaoJBZZJl+KXdtWkQLZOASO31x/PVuLkTeYf0MXGuJTd9oRVfgpL6mZ/2W0nvRKv+5i oLoWTxbVsPwaEC228hv4HBM9xVbhXwpchHGhecGHTt4nrJWv1GrKtZsn0OFvs9NehWn8 8PVIOhzjd0P6ooRvOYwUek/KS+cDxu7FO/aM6IofVvriPB4wJhMv6vg0GxNxoqnajsY8 1UMKrB/q991YkEcMpvBDoQ9nr2aDUSm8cZav9jHa5ZIxE7Le06n7o1R7v3nLBN809XVH QjWQ== X-Gm-Message-State: AOJu0YwUUGqnTJZnVkFKwlUfej9Jcnj3wugaMVETxnydtNOZiKAl3uQO Vdlg+/9kULCDLBijJ+gpk75RPIsWUsHsNzXUh0Krm/vTjo6J96iRSCYiEQ== X-Google-Smtp-Source: AGHT+IHp+s/eat18HthQKYxjHpIDca9zMdWJzO2ELjEHvQWBCNOoj85MwpPQawb/Kc9m7YmURsH23A== X-Received: by 2002:a17:903:1211:b0:1f3:5ba:18d with SMTP id d9443c01a7336-1f4486bc775mr146414405ad.4.1716864270358; Mon, 27 May 2024 19:44:30 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:29 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jason Chien , Frank Chang , Max Chou , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 10/28] target/riscv: Add support for Zve32x extension Date: Tue, 28 May 2024 12:43:10 +1000 Message-ID: <20240528024328.246965-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jason Chien Add support for Zve32x extension and replace some checks for Zve32f with Zve32x, since Zve32f depends on Zve32x. Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou Reviewed-by: Daniel Henrique Barboza Message-ID: <20240328022343.6871-2-jason.chien@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 2 ++ target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/tcg/tcg-cpu.c | 16 ++++++++-------- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 6 files changed, 15 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index cb750154bd..dce49050c0 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -91,6 +91,7 @@ struct RISCVCPUConfig { bool ext_zhinx; bool ext_zhinxmin; bool ext_zve32f; + bool ext_zve32x; bool ext_zve64f; bool ext_zve64d; bool ext_zvbb; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb1a2e7d6d..d744594cc4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), + ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x), ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin), @@ -1472,6 +1473,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false), MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false), MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false), + MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false), MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false), MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false), diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 179cf3d1a1..d71245a8cb 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -73,7 +73,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base = 0; - if (cpu->cfg.ext_zve32f) { + if (cpu->cfg.ext_zve32x) { /* * If env->vl equals to VLMAX, we can use generic vector operation * expanders (GVEC) to accerlate the vector operations. diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 829d8346ed..58ef7079dc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -93,7 +93,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->ext_zve32f) { + if (riscv_cpu_cfg(env)->ext_zve32x) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 40054a391a..e2cf5f429d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -511,9 +511,13 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension"); - return; + /* The Zve32f extension depends on the Zve32x extension */ + if (cpu->cfg.ext_zve32f) { + if (!riscv_has_ext(env, RVF)) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true); } if (cpu->cfg.ext_zvfh) { @@ -658,13 +662,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); } - /* - * In principle Zve*x would also suffice here, were they supported - * in qemu - */ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || - cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { + cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"); return; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 7d84e7d812..eec2939e23 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -149,7 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) { TCGv s1, dst; - if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) { + if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) { return false; } @@ -179,7 +179,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) { TCGv dst; - if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) { + if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) { return false; } From patchwork Tue May 28 02:43:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E235C25B74 for ; Tue, 28 May 2024 02:47:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpN-0003Wl-BV; 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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:33 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jason Chien , Frank Chang , Max Chou , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 11/28] target/riscv: Add support for Zve64x extension Date: Tue, 28 May 2024 12:43:11 +1000 Message-ID: <20240528024328.246965-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jason Chien Add support for Zve64x extension. Enabling Zve64f enables Zve64x and enabling Zve64x enables Zve32x according to their dependency. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107 Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou Reviewed-by: Daniel Henrique Barboza Message-ID: <20240328022343.6871-3-jason.chien@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------ 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index dce49050c0..e1e4f32698 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -94,6 +94,7 @@ struct RISCVCPUConfig { bool ext_zve32x; bool ext_zve64f; bool ext_zve64d; + bool ext_zve64x; bool ext_zvbb; bool ext_zvbc; bool ext_zvkb; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d744594cc4..a74f0eb29c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -156,6 +156,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x), ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), + ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x), ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin), ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), @@ -1476,6 +1477,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false), MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false), MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), + MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false), MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false), MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false), MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e2cf5f429d..fedc035313 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -498,17 +498,22 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) /* The Zve64d extension depends on the Zve64f extension */ if (cpu->cfg.ext_zve64d) { + if (!riscv_has_ext(env, RVD)) { + error_setg(errp, "Zve64d/V extensions require D extension"); + return; + } cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); } - /* The Zve64f extension depends on the Zve32f extension */ + /* The Zve64f extension depends on the Zve64x and Zve32f extensions */ if (cpu->cfg.ext_zve64f) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); } - if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { - error_setg(errp, "Zve64d/V extensions require D extension"); - return; + /* The Zve64x extension depends on the Zve32x extension */ + if (cpu->cfg.ext_zve64x) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true); } /* The Zve32f extension depends on the Zve32x extension */ @@ -670,10 +675,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { error_setg( errp, - "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); + "Zvbc and Zvknhb extensions require V or Zve64x extensions"); return; } From patchwork Tue May 28 02:43:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9DC9C25B7E for ; Tue, 28 May 2024 02:48:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpO-0003bw-3i; Mon, 27 May 2024 22:44:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpM-0003TM-Pd for qemu-devel@nongnu.org; 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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:36 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jason Chien , Frank Chang , Max Chou , Alistair Francis Subject: [PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub Date: Tue, 28 May 2024 12:43:12 +1000 Message-ID: <20240528024328.246965-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jason Chien In current implementation, the gdbstub allows reading vector registers only if V extension is supported. However, all vector extensions and vector crypto extensions have the vector registers and they all depend on Zve32x. The gdbstub should check for Zve32x instead. Signed-off-by: Jason Chien Reviewed-by: Frank Chang Reviewed-by: Max Chou Message-ID: <20240328022343.6871-4-jason.chien@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index be7a02cd90..d0cc5762c2 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -338,7 +338,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_find_static_feature("riscv-32bit-fpu.xml"), 0); } - if (env->misa_ext & RVV) { + if (cpu->cfg.ext_zve32x) { gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs), From patchwork Tue May 28 02:43:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7831DC25B74 for ; Tue, 28 May 2024 02:45:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpR-0003s6-SK; Mon, 27 May 2024 22:44:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpQ-0003mY-3f; Mon, 27 May 2024 22:44:44 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpO-0003mH-GC; Mon, 27 May 2024 22:44:43 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-7010a7df499so266634b3a.0; Mon, 27 May 2024 19:44:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864280; x=1717469080; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rwx0SPD4bR7zPO/4n31t9fpXIatcICjktSL4UeCf/R8=; b=LkoJmDtTpSRt4rAMRV5yhE5s6eHVuAYvpG2m3e4OvqCNP4wym2BXBQe4VKobmQebay sULE8PX398iEwsd5d5dyfaPHaf4HRIKjzFIPE34NzVeu6HyfhyFUJuiQilS3+Cu9HCZh 6Udx1Cbvcf3zoPe9eyTBt7SMv0QzRu6ug8QOHATxfYtsgY0G/WYAEOWEKhfqa52NXWq8 w8fqQVgWYA2wQNsL2V5kKXZY2/rh0KvkO680LR4UmcMr4ea5VUOVl9gLScCLZ5fy5Y/1 5bayHHjzE+09JwL7lNFxTvknefOjyAixoEDXNer6lF2Y3vUCV66UEXqi/FwJ0311L29c MO0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864280; x=1717469080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rwx0SPD4bR7zPO/4n31t9fpXIatcICjktSL4UeCf/R8=; b=BRCaBgCXDqIrxEJI/xgbJc7J34Jn1TS7dCexQj381ezcnKAPA8KpkX4ByeuIglG4fr fsNEyxj2a4FcoiW29msE0rcUivD6C6rOJ91WxuA1lvrKdjJyYzEGWNp2tDLRDRWo1GlR 30vJatxx+THyUmYboIU0zp7fWL1nYpypNbFc8IyYIrDsnuxs9VJm0ugvSQJsKp4/wseN rqyZH2yMVJTpnXXCxd3YPhG2PCgePBDxnJ2Oy9tpz9g57XLOOdwQUQOTio4h7YibMCGc zxuRP4UVa2lmntFJ4yM3+WO/hPJbzWoah06hCy7hrJhcaXBmRw2sjBNXaurXA9MV6aR3 eUYw== X-Forwarded-Encrypted: i=1; AJvYcCVQMJO6wgY19iBLG4iHOLVxFSXPXEttWGcKhJWnz34kmps/4xiHphNkw+YYPBlXc8rp8PteK9mANKjFntrgTvLarhYg7olA X-Gm-Message-State: AOJu0YyqGyRTPWyE/yKdnTE2a7Ff0/1DlQqVu0uT9bkjlbzpsbl9o96i 4Wayj0a+2o038bS1vPryqlao2rCGw5Acyw8LCiJ+nb4j9ey1kszJw6rEkw== X-Google-Smtp-Source: AGHT+IH6eBidv7YqdsaxGaB5j3YAedlb8030h9AimV9AXAs8oRRO6dTF1Bipk5BCsdGk4BAHGXRuiw== X-Received: by 2002:a05:6a21:800f:b0:1af:5e48:ab59 with SMTP id adf61e73a8af0-1b212cee853mr11244696637.13.1716864280544; Mon, 27 May 2024 19:44:40 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:40 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Huang Tao , Richard Henderson , LIU Zhiwei , qemu-stable , Alistair Francis Subject: [PULL 13/28] target/riscv: Fix the element agnostic function problem Date: Tue, 28 May 2024 12:43:13 +1000 Message-ID: <20240528024328.246965-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Huang Tao In RVV and vcrypto instructions, the masked and tail elements are set to 1s using vext_set_elems_1s function if the vma/vta bit is set. It is the element agnostic policy. However, this function can't deal the big endian situation. This patch fixes the problem by adding handling of such case. Signed-off-by: Huang Tao Suggested-by: Richard Henderson Reviewed-by: LIU Zhiwei Cc: qemu-stable Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/vector_internals.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c index 996c21eb31..05b2d01e58 100644 --- a/target/riscv/vector_internals.c +++ b/target/riscv/vector_internals.c @@ -30,6 +30,28 @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, if (tot - cnt == 0) { return ; } + + if (HOST_BIG_ENDIAN) { + /* + * Deal the situation when the elements are insdie + * only one uint64 block including setting the + * masked-off element. + */ + if (((tot - 1) ^ cnt) < 8) { + memset(base + H1(tot - 1), -1, tot - cnt); + return; + } + /* + * Otherwise, at least cross two uint64_t blocks. + * Set first unaligned block. + */ + if (cnt % 8 != 0) { + uint32_t j = ROUND_UP(cnt, 8); + memset(base + H1(j - 1), -1, j - cnt); + cnt = j; + } + /* Set other 64bit aligend blocks */ + } memset(base + cnt, -1, tot - cnt); } From patchwork Tue May 28 02:43:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D562C25B74 for ; Tue, 28 May 2024 02:48:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpV-0003z1-9M; Mon, 27 May 2024 22:44:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpT-0003xz-TX; Mon, 27 May 2024 22:44:47 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpS-0003mb-Aw; Mon, 27 May 2024 22:44:47 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1f47eb21f0aso3307145ad.1; Mon, 27 May 2024 19:44:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864284; x=1717469084; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5qcQTiAdEv5FwQ27d9xmN3ZTsEtqw8BucwxaZ316zkY=; b=MBVLrormYa0ek79S6tjCV0Xc5qG0JDzPi+Ubyz0HH7IShpbTBuYg7UqgIob80wxHn0 r3Jst+F+52b/8vXUwvyT/BB7g30VVs+SItWjBvB7CqhdOejpjKdsrEsVblG88GbyG0MB UD3egAyWMFdds+7/18L7bAm6DuRe5CshpxDjna3NsO/df+/lYRkQVSuBq9F+79doYpbF 4Rb6cULMwFgeGb0fezN3/1Ez6qRX6p/RYrfIkdWyMurUjOSBkO0tq6QqqtMxfZ97ZI7z Z5xskhttmpSNLMIViHShEYlB7wxysDerThFuMbS3zIDP7jmcWaZYO+85m9OVgQTjYmmv LoEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864284; x=1717469084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5qcQTiAdEv5FwQ27d9xmN3ZTsEtqw8BucwxaZ316zkY=; b=vkGU0vOJ19NHsbN+sG5FIrnGzjc5q6LKuTUT/gqj9a5PwmeUBzh1T1WFs+97sZ3HnN X+irfkszF7RZ1EircmaifqfW/RLRYOIr66kQSBTZzG+5/rGrmY00/BR8b2P2QTv39tyJ q1woz5q6thl7tfqB5IrLBW8TfxTGPJ4txJslRz6++yiLY/Gg554841qXlxqWwHvyHltr kNRzsKjz0e40KxzoRs2h/bS2tCRE8zrc7rGGmDkAxq3IuU4VAgOo/ZH732p+Ws9qlqHh 1c19DoiUP2BzHa++q4HRkg4I/l3m1HVmv1ivll5zvCnVmNjsOdIS9mPJFxwuAzrqsd/O 4NVQ== X-Forwarded-Encrypted: i=1; AJvYcCVZeJ8Cahco15vLbHoj6q8TFV0/t9lpqOxrIE3m1bhMbREgATJxfohM3hijFnhDb4SWBpMUfTCKn9uvI/+7tJXWKH9KMjs8 X-Gm-Message-State: AOJu0Yx+tAUU16lGrcjOSTurPhI3oCZjf9bU4Rl8Jc9LzbY4WZfiED47 /korWAZa1jAGEHuIGl8EmxBwz4mgldL9y0ZFzYteIbXyEDz1PGLu0nH/Pg== X-Google-Smtp-Source: AGHT+IHFm1fuCWvdFoVEXXUeUTPN+kYWVDPfGNemupT8X29OlfDuNjEAwSQKeU/mNU+Cz9C+wXHUCg== X-Received: by 2002:a17:902:e88e:b0:1f3:39f8:7e7f with SMTP id d9443c01a7336-1f4486d1f78mr111465725ad.14.1716864284443; Mon, 27 May 2024 19:44:44 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:43 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yangyu Chen , LIU Zhiwei , Alistair Francis , Max Chou , qemu-stable Subject: [PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config Date: Tue, 28 May 2024 12:43:14 +1000 Message-ID: <20240528024328.246965-15-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Yangyu Chen This code has a typo that writes zvkb to zvkg, causing users can't enable zvkb through the config. This patch gets this fixed. Signed-off-by: Yangyu Chen Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions") Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Max Chou Reviewed-by:  Weiwei Li Message-ID: Cc: qemu-stable Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a74f0eb29c..0d6fb9b4ba 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1539,7 +1539,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { /* Vector cryptography extensions */ MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false), MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false), - MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false), + MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false), MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false), MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false), MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false), From patchwork Tue May 28 02:43:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70AB3C25B7C for ; Tue, 28 May 2024 02:46:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpb-0004BW-DL; Mon, 27 May 2024 22:44:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpY-00045D-3O for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:53 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpW-0003n4-44 for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:51 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1f480624d04so3222375ad.2 for ; Mon, 27 May 2024 19:44:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864288; x=1717469088; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5Gf09NafNEVyOO1I73va6raf97epWEC91xltk6mMdyo=; b=LfeMttMOyWGnmu5aJ6X77aMaEdlqrPSTgA8gW3edmEpHP6b8M3RTxDF2ajhPhqQ3I5 Yu14F+7cLhN0aW3/nkAn3dR+CTqxUyT27GaRVt2AZcYCmzd3Ql0BED4mEHoeMJUbO9iz ESUkrhI7P+mXFO2Cr9sbOZrKabK2wx9emMqzpmzdAwZO6BSjEdt1xhM6YMSJxmvAk/U9 4dqYngTg7OtPHZgXignlN7MTOwWIqfaHhFCf0M9+xlKHQcH+QQf/SkXp7EswFnwo1xCE U7Ckp+ZoRT//DdNLPL0lOY7ho/K1iIej+9qEnFU1aFm2L0QadqRH94mDz9s5RaQhlVT6 pRJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864288; x=1717469088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5Gf09NafNEVyOO1I73va6raf97epWEC91xltk6mMdyo=; b=rh4PpE+bw7Snd/JPS3rRYGJ5xF+lKA/XpF2y89Ec10ywoUoi6MIMXy2ackNxHvKsN1 PXq4Qq3vqYlfBOfrLE97KdGquj4F+Z5eMAaqUw4tsTZu0M+0VZPga+axIAYZQ26wh7/9 +CLfKewXJodoeNWV0joEgGqxykxz5vZpXLeRmNohDP3aZ0t/vg7J9l0fuj8vc35tlUPw 9vnsW+X/ckAY+dN+D1uWlEltZJ2Up6VcAojYN9vO8JRDVg0MeXNO7dwxgksN09rgKEPT 3MSJYCtLKFkrCSCDgWG8nNZrR50IrEWjujk9TdzcQNLKv7tVbOUT6Xv0i0fyj76YD+Il SNng== X-Gm-Message-State: AOJu0YxFbPw63PdK+saEbY1Olw3a/XjDyETYtvb5kwlZ/arDPjKpe2IG fuF8fHdsKdC9gjiLFHCTc2LGh5WRUT4cAUMqHgpn7O0+96y8EPfl6A15BQ== X-Google-Smtp-Source: AGHT+IEWLVU8hGQvvNhP8/0MUd7+ERku4j1ujDcURqlgFb/FMXLc902nACKdlTK53OcqnvPnfHujjA== X-Received: by 2002:a17:902:cecd:b0:1f3:240:253d with SMTP id d9443c01a7336-1f4486d4ea7mr133957295ad.1.1716864288562; Mon, 27 May 2024 19:44:48 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:47 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Huang Tao , Christoph Muellner , LIU Zhiwei , Richard Henderson , Alistair Francis Subject: [PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder Date: Tue, 28 May 2024 12:43:15 +1000 Message-ID: <20240528024328.246965-16-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Huang Tao In this patch, we modify the decoder to be a freely composable data structure instead of a hardcoded one. It can be dynamically builded up according to the extensions. This approach has several benefits: 1. Provides support for heterogeneous cpu architectures. As we add decoder in RISCVCPU, each cpu can have their own decoder, and the decoders can be different due to cpu's features. 2. Improve the decoding efficiency. We run the guard_func to see if the decoder can be added to the dynamic_decoder when building up the decoder. Therefore, there is no need to run the guard_func when decoding each instruction. It can improve the decoding efficiency 3. For vendor or dynamic cpus, it allows them to customize their own decoder functions to improve decoding efficiency, especially when vendor-defined instruction sets increase. Because of dynamic building up, it can skip the other decoder guard functions when decoding. 4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal overhead for users that don't need this particular vendor decoder. Signed-off-by: Huang Tao Suggested-by: Christoph Muellner Co-authored-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++ target/riscv/cpu.c | 1 + target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++ target/riscv/translate.c | 31 +++++++++++++++---------------- 5 files changed, 47 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 746efd099a..04ab0f153a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -455,6 +455,7 @@ struct ArchCPU { uint32_t pmu_avail_ctrs; /* Mapping of events to counters */ GHashTable *pmu_event_ctr_map; + const GPtrArray *decoders; }; /** diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h index f7b32417f8..ce94253fe4 100644 --- a/target/riscv/tcg/tcg-cpu.h +++ b/target/riscv/tcg/tcg-cpu.h @@ -26,4 +26,19 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp); bool riscv_cpu_tcg_compatible(RISCVCPU *cpu); +struct DisasContext; +struct RISCVCPUConfig; +typedef struct RISCVDecoder { + bool (*guard_func)(const struct RISCVCPUConfig *); + bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t); +} RISCVDecoder; + +typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t); + +extern const size_t decoder_table_size; + +extern const RISCVDecoder decoder_table[]; + +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu); + #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0d6fb9b4ba..abeb50369c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1134,6 +1134,7 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) error_propagate(errp, local_err); return; } + riscv_tcg_cpu_finalize_dynamic_decoder(cpu); } else if (kvm_enabled()) { riscv_kvm_cpu_finalize_features(cpu, &local_err); if (local_err != NULL) { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fedc035313..f59b5d7f2d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -863,6 +863,21 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) } } +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) +{ + GPtrArray *dynamic_decoders; + dynamic_decoders = g_ptr_array_sized_new(decoder_table_size); + for (size_t i = 0; i < decoder_table_size; ++i) { + if (decoder_table[i].guard_func && + decoder_table[i].guard_func(&cpu->cfg)) { + g_ptr_array_add(dynamic_decoders, + (gpointer)decoder_table[i].riscv_cpu_decode_fn); + } + } + + cpu->decoders = dynamic_decoders; +} + bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) { return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2c27fd4ce1..4cd6480558 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -35,6 +35,8 @@ #include "exec/helper-info.c.inc" #undef HELPER_H +#include "tcg/tcg-cpu.h" + /* global register indices */ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ @@ -114,6 +116,7 @@ typedef struct DisasContext { /* FRM is known to contain a valid value. */ bool frm_valid; bool insn_start_updated; + const GPtrArray *decoders; } DisasContext; static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -1123,21 +1126,16 @@ static inline int insn_len(uint16_t first_word) return (first_word & 3) == 3 ? 4 : 2; } +const RISCVDecoder decoder_table[] = { + { always_true_p, decode_insn32 }, + { has_xthead_p, decode_xthead}, + { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, +}; + +const size_t decoder_table_size = ARRAY_SIZE(decoder_table); + static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { - /* - * A table with predicate (i.e., guard) functions and decoder functions - * that are tested in-order until a decoder matches onto the opcode. - */ - static const struct { - bool (*guard_func)(const RISCVCPUConfig *); - bool (*decode_func)(DisasContext *, uint32_t); - } decoders[] = { - { always_true_p, decode_insn32 }, - { has_xthead_p, decode_xthead }, - { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, - }; - ctx->virt_inst_excp = false; ctx->cur_insn_len = insn_len(opcode); /* Check for compressed insn */ @@ -1158,9 +1156,9 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) ctx->base.pc_next + 2)); ctx->opcode = opcode32; - for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { - if (decoders[i].guard_func(ctx->cfg_ptr) && - decoders[i].decode_func(ctx, opcode32)) { + for (guint i = 0; i < ctx->decoders->len; ++i) { + riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i); + if (func(ctx, opcode32)) { return; } } @@ -1205,6 +1203,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); ctx->virt_inst_excp = false; + ctx->decoders = cpu->decoders; } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) From patchwork Tue May 28 02:43:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB08DC25B74 for ; Tue, 28 May 2024 02:46:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpd-0004OL-C9; Mon, 27 May 2024 22:44:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpb-0004Fq-QJ for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:55 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpZ-0003nT-Ed for qemu-devel@nongnu.org; Mon, 27 May 2024 22:44:55 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1f480624d04so3222565ad.2 for ; Mon, 27 May 2024 19:44:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864292; x=1717469092; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MDhqEB3afbuqQBasKQEWSnaR1QfgS0WX/aMKej21gLY=; b=gpIig6ytuyarLbgvdMNbAM5QY/ALCsfd6IIFKNG3WQE7b3vAfgRIMAmGdo6aD4sgmc 962TqbbVcOOzF9Vrxsx64umMAkUdcguUikGBQKBq/nPVAGGRefqzy15LgSQn5ODwsSvV FBdi/VmI9KFTTaiALPC0kirbXyGfDTLzbkLWrbzbiifUg1hUOAik+68bOIyDVpWuqr3R lKD+CwB7L4eH7DJUSPwdragRsyjahy1ztbueZZHMQ8okfs5BNxk037NCk6hlQxsLRDSg hGKM/aJYA1avRuxObC12WenZoyPkgQclJLWbN/bL0NDaf6bCmYw7XEXfaCcrBsstrHee YTWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864292; x=1717469092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MDhqEB3afbuqQBasKQEWSnaR1QfgS0WX/aMKej21gLY=; b=LnBfK/yfxbDWaVbwnUsEEobvIUCY8K5vvkv6d/OuoJetgOMPem2paXWpsS9pnkpXoU ZER4VT4qu1872zOTVo/W6KNtVRQnVi9N+oV9VDKx7I17OIdnmR5u9naISNr+4lXO3Duk a3c+TtgcSp8lDpcs+MqIFX1ko4t0tlA1HxFcb0VJTbqL6WtRSC3j6yl1NITikMZgodqb 6a8VzokfGd7WTJERFQ2FszSFlT23J2mZ/KmSyE8snJD5m8c9PPwmYmEzzODpHbhW52/R V6l500KY+yr2asTpVIJewG1nl1ootFAtGsa9caSnvk+5xAri4LBqDQ5JmJyASoIO6kbX AWJg== X-Gm-Message-State: AOJu0YxAM7X343k3FR5Emo2O/459Op8KWe0jiGyjahaagkLO2G76e7t3 3v4WKZNwM5HOuRcfyrUQsD9IrbqpA4uMa4dUwLcUQBWEj1ligv3pd3o80Q== X-Google-Smtp-Source: AGHT+IFYuVj7MR/PjCJhrz+1Hf/yuYWk6h2qDpi5JwoOqJulT/owCROj6pjO8MXlOe7fKvn1dFSZDw== X-Received: by 2002:a17:903:22c8:b0:1f3:6ac:fbcd with SMTP id d9443c01a7336-1f4497df62cmr141652575ad.44.1716864291632; Mon, 27 May 2024 19:44:51 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:51 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?q?Christoph_M=C3=BCllner?= , LIU Zhiwei , Alistair Francis Subject: [PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation Date: Tue, 28 May 2024 12:43:16 +1000 Message-ID: <20240528024328.246965-17-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Christoph Müllner The th.sxstatus CSR can be used to identify available custom extension on T-Head CPUs. The CSR is documented here: https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc An important property of this patch is, that the th.sxstatus MAEE field is not set (indicating that XTheadMae is not available). XTheadMae is a memory attribute extension (similar to Svpbmt) which is implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits in PTEs that are marked as reserved. QEMU maintainers prefer to not implement XTheadMae, so we need give kernels a mechanism to identify if XTheadMae is available in a system or not. And this patch introduces this mechanism in QEMU in a way that's compatible with real HW (i.e., probing the th.sxstatus.MAEE bit). Further context can be found on the list: https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis --- MAINTAINERS | 1 + target/riscv/cpu.h | 3 ++ target/riscv/cpu.c | 1 + target/riscv/th_csr.c | 79 ++++++++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 1 + 5 files changed, 85 insertions(+) create mode 100644 target/riscv/th_csr.c diff --git a/MAINTAINERS b/MAINTAINERS index 448dc951c5..e9d861e8ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -343,6 +343,7 @@ L: qemu-riscv@nongnu.org S: Supported F: target/riscv/insn_trans/trans_xthead.c.inc F: target/riscv/xthead*.decode +F: target/riscv/th_* F: disas/riscv-xthead* RISC-V XVentanaCondOps extension diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 04ab0f153a..12d8b5344a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -826,4 +826,7 @@ target_ulong riscv_new_csr_seed(target_ulong new_value, uint8_t satp_mode_max_from_map(uint32_t map); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); +/* Implemented in th_csr.c */ +void th_register_custom_csrs(RISCVCPU *cpu); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index abeb50369c..2946ac298a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -547,6 +547,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) cpu->cfg.mvendorid = THEAD_VENDOR_ID; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); + th_register_custom_csrs(cpu); #endif /* inherited from parent obj via riscv_cpu_init() */ diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c new file mode 100644 index 0000000000..6c970d4e81 --- /dev/null +++ b/target/riscv/th_csr.c @@ -0,0 +1,79 @@ +/* + * T-Head-specific CSRs. + * + * Copyright (c) 2024 VRULL GmbH + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu_vendorid.h" + +#define CSR_TH_SXSTATUS 0x5c0 + +/* TH_SXSTATUS bits */ +#define TH_SXSTATUS_UCME BIT(16) +#define TH_SXSTATUS_MAEE BIT(21) +#define TH_SXSTATUS_THEADISAEE BIT(22) + +typedef struct { + int csrno; + int (*insertion_test)(RISCVCPU *cpu); + riscv_csr_operations csr_ops; +} riscv_csr; + +static RISCVException smode(CPURISCVState *env, int csrno) +{ + if (riscv_has_ext(env, RVS)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} + +static int test_thead_mvendorid(RISCVCPU *cpu) +{ + if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) { + return -1; + } + + return 0; +} + +static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* We don't set MAEE here, because QEMU does not implement MAEE. */ + *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE; + return RISCV_EXCP_NONE; +} + +static riscv_csr th_csr_list[] = { + { + .csrno = CSR_TH_SXSTATUS, + .insertion_test = test_thead_mvendorid, + .csr_ops = { "th.sxstatus", smode, read_th_sxstatus } + } +}; + +void th_register_custom_csrs(RISCVCPU *cpu) +{ + for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) { + int csrno = th_csr_list[i].csrno; + riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops; + if (!th_csr_list[i].insertion_test(cpu)) { + riscv_set_csr_ops(csrno, csr_ops); + } + } +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a5e0734e7f..a4bd61e52a 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -33,6 +33,7 @@ riscv_system_ss.add(files( 'monitor.c', 'machine.c', 'pmu.c', + 'th_csr.c', 'time_helper.c', 'riscv-qmp-cmds.c', )) From patchwork Tue May 28 02:43:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03B91C25B74 for ; Tue, 28 May 2024 02:46:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpg-0004cp-Q6; Mon, 27 May 2024 22:45:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpe-0004Ro-GN; Mon, 27 May 2024 22:44:58 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpc-0003nk-RD; Mon, 27 May 2024 22:44:58 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1f449f09476so20388965ad.1; Mon, 27 May 2024 19:44:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864295; x=1717469095; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oUhlj8L9io8L8IzXZjt++oPcFPCpbs/15osdPGsfaYk=; b=J6VEwH1tXNMICH7kkpvIyMRrf5z2v06PSYNfjIcc39Q0WJm6A2qRQvdxqvjlyYtg7l N4l8MRTW3KADN39i2EIXK6v/rupB2Ph8fgIW7LSw8ZCeuxKPFwb/xl0VDBY68ABczrKG m3WKTtlfL/byj/XkL9avzvghhvmmZIn7mGvN6s9kbIDCrR1UUZFG9PhBSNqqyl7RBaIA QNf8El1iL09p/wJ5Uztinh9vhncI9wBHhq9XsmiFfilB6Pq0eXE74oRm/GuhCN2NgaOB DyiCk2OFPTI8hmEJHJzeFwReUX4n8qvXZS8FUQ9Q87DaCq4Pmq2eiayk0cjLkj9/wMAH HtFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864295; x=1717469095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oUhlj8L9io8L8IzXZjt++oPcFPCpbs/15osdPGsfaYk=; b=E4/6LZAqUiGxasIJzxjOGnB2LRXgYkXE7ok4xLFcXpbY8P8fRrQ4PEsRQ/oAQ6Pzt3 75inR52U/1ZNYZTcnwqaXgSprkgmJ/ttu/E7sEASqHa25jZwo+5DLWGXhiAaB3MYMe/M yotMw5T8pWAUb+fe3BOKCOCO10JIltr692u5SF6meByRsOUN8MI7Qq/BB0tFPDNkNqaW v2nUsVr35tldBlUVC47O2VCo/b4SY/JV3wf5hXDUpbpoLqR6+Xb+YblhoDmXFFdieaeg XJ6Ij+jOn2/Tw1sG5JBDFsLLe1PKMPFrtAIlY1PSDOwrmM7Np0QjCeg8hi8vVmZNhv9j JS6Q== X-Forwarded-Encrypted: i=1; AJvYcCXj7497d33isGxWZleyL9F/ZTjibwKjtJ9AIiTTkfJIIS8+36riaqwJVz5vjCZhfWBoul0npyjpRZOQutgQI4qv+nlh0Bxc X-Gm-Message-State: AOJu0YzEHh9kxrdXLA23OL5TUwIhq5sBMakt5tm+ozeAcpNMwBjCdHXG rNNnr+homECWhhsJsJuNGfj5bQs3+0IVa3XsDHX1njHL7tfKKuWPDYF5QQ== X-Google-Smtp-Source: AGHT+IFtuwI0vUERUGblnPGpA6xV+XeJbcgbERG3oYNjIgq5VkM71uWOeaybRTIkQNMakUSNNSS7qw== X-Received: by 2002:a17:903:24e:b0:1f3:62c:247f with SMTP id d9443c01a7336-1f339f0a2afmr176940955ad.11.1716864294837; Mon, 27 May 2024 19:44:54 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:54 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou , Daniel Henrique Barboza , qemu-stable , Alistair Francis Subject: [PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions Date: Tue, 28 May 2024 12:43:17 +1000 Message-ID: <20240528024328.246965-18-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Max Chou According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w instructions will be affected by Zvfhmin extension. And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the conversions of * From 1*SEW(16/32) to 2*SEW(32/64) * From 2*SEW(32/64) to 1*SEW(16/32) Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza Cc: qemu-stable Message-ID: <20240322092600.1198921-2-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index eec2939e23..678b34b759 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -50,6 +50,22 @@ static bool require_rvf(DisasContext *s) } } +static bool require_rvfmin(DisasContext *s) +{ + if (s->mstatus_fs == EXT_STATUS_DISABLED) { + return false; + } + + switch (s->sew) { + case MO_16: + return s->cfg_ptr->ext_zvfhmin; + case MO_32: + return s->cfg_ptr->ext_zve32f; + default: + return false; + } +} + static bool require_scale_rvf(DisasContext *s) { if (s->mstatus_fs == EXT_STATUS_DISABLED) { @@ -75,8 +91,6 @@ static bool require_scale_rvfmin(DisasContext *s) } switch (s->sew) { - case MO_8: - return s->cfg_ptr->ext_zvfhmin; case MO_16: return s->cfg_ptr->ext_zve32f; case MO_32: @@ -2685,6 +2699,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a) static bool opffv_widen_check(DisasContext *s, arg_rmr *a) { return opfv_widen_check(s, a) && + require_rvfmin(s) && require_scale_rvfmin(s) && (s->sew != MO_8); } @@ -2790,6 +2805,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && + require_rvfmin(s) && require_scale_rvfmin(s) && (s->sew != MO_8); } From patchwork Tue May 28 02:43:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31D90C25B74 for ; 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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:44:57 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou , Daniel Henrique Barboza , qemu-stable , Alistair Francis Subject: [PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions Date: Tue, 28 May 2024 12:43:18 +1000 Message-ID: <20240528024328.246965-19-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Max Chou The require_scale_rvf function only checks the double width operator for the vector floating point widen instructions, so most of the widen checking functions need to add require_rvf for single width operator. The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width integer to double width float, so the opfxv_widen_check function doesn’t need require_rvf for the single width operator(integer). Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza Cc: qemu-stable Message-ID: <20240322092600.1198921-3-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 678b34b759..a7217aed4e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2331,6 +2331,7 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8) && vext_check_isa_ill(s) && @@ -2370,6 +2371,7 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8) && vext_check_isa_ill(s) && @@ -2402,6 +2404,7 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8) && vext_check_isa_ill(s) && @@ -2441,6 +2444,7 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8) && vext_check_isa_ill(s) && @@ -2941,6 +2945,7 @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_widen_check(s, a) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8); } From patchwork Tue May 28 02:43:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66B48C25B7C for ; Tue, 28 May 2024 02:46:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmpo-00058u-7j; Mon, 27 May 2024 22:45:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpl-0004wX-FS; Mon, 27 May 2024 22:45:05 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpj-0003pH-N2; Mon, 27 May 2024 22:45:05 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1f449f09476so20389285ad.1; Mon, 27 May 2024 19:45:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864301; x=1717469101; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yJgBJ0EmldlUzQtT/aivgrSis6Y1lAdujHeTStRACnA=; b=gwyg9vjLrV21ag4JK7GHCRYS+SUAIxGzrDpXOCqEH1q3kW+snvA+VHi4Ltd140b4CK xtjaoMi6y0Ruhp4pUvrvvHj9SOxYeTDzhtmS1m1OUmT4EpQb20fnKQfmknBILlXDzewr KRawTQgTcWTglf7U5bU8BfoIC9+1PPsN9TVlwpIFLBbegrkodhVPEHqDVBJM/aQ8auAv 9+xcN1qjo24CRJElgUWLooNbRPzOfs/SImvSqUbZKf6ULx+Iey00x+N1iQ+DB/6dpoIW cZJvyVvsc7/iHLKOm7csqimS8SLdl8c+Abe8cME+GPrhq/a+rY8mFR1LU57jSqp+M1H2 x/Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864301; x=1717469101; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yJgBJ0EmldlUzQtT/aivgrSis6Y1lAdujHeTStRACnA=; b=crXiwPcjrsRzZ90vT5F5AIOjCInD47znjWopTgwXwDfIPSl8ch90uE6hbyUtikORHd HzWXppMeko353KSZODIVujALHIyJ3EeGzW4F46A6KLyNZQQXTd+P0LpKtC0vR9L6PZGJ h1hmSxQT1S8crXLwI2ogLogN9Njbssgv5UNZU5LxLEV7gdP1/L2RAcIdeDeBhLb8xfDJ tLHVdrXyWJEtzGdtaDyfAxBpr+U+WO5C8Asi9derIFzXftqvXvAS7ffsaeRSPvQ0U3vP MUm3kRPqm6ZbHIxLCSbTHLbJ5VZS+KCKpkfzDQNecCrOwbqDOFQi+GvaH4WM3SpgbDx2 QA/Q== X-Forwarded-Encrypted: i=1; AJvYcCWLTlgpWcid9JR6itPEGqTTuoGa1M2qxPY87PKWc2FmHTYKvRyMs01MHBGw5AX4h7vXRHBgxEvKw37I/jlWjLJjeY+7CpLp X-Gm-Message-State: AOJu0YwLHqPLAB/2CLlpokGFtOkLxL5WovnEaTHfZ+vHEXhnbjmc6QMy LFDETcF/sx+EBA37LJHggu4ruDj4AqVelcEYkl3rtFZ/r+/iLY6tbkDJXg== X-Google-Smtp-Source: AGHT+IHn60gsBnT6ZIzzdaop9U7RdNHhltTiCjMjytUlyRyn1NxFBRotBfWuzYR3/fp7ZVjGf7ZI4Q== X-Received: by 2002:a17:903:2445:b0:1eb:5222:7b8e with SMTP id d9443c01a7336-1f448160c7amr159536825ad.17.1716864301376; Mon, 27 May 2024 19:45:01 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:00 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou , Daniel Henrique Barboza , qemu-stable , Alistair Francis Subject: [PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w Date: Tue, 28 May 2024 12:43:19 +1000 Message-ID: <20240528024328.246965-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Max Chou The opfv_narrow_check needs to check the single width float operator by require_rvf. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza Cc: qemu-stable Message-ID: <20240322092600.1198921-4-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index a7217aed4e..c3af38af80 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2817,6 +2817,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8); } From patchwork Tue May 28 02:43:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFE04C25B74 for ; Tue, 28 May 2024 02:47:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmr2-0007Rv-Tq; Mon, 27 May 2024 22:46:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmq2-0005kK-3G; Mon, 27 May 2024 22:45:23 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpo-00041N-Cr; Mon, 27 May 2024 22:45:21 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1f4a5344ec7so2540145ad.1; Mon, 27 May 2024 19:45:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864305; x=1717469105; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BljNjeMaZO3XaNf0tppv2lCKaXtzum6yJ/eCc7gYwjE=; b=C+73i1uZHmyhlx/h9o8cFBSCl2kzjA5HsXdpNoocMHSFs+CJ156tMrVkk4NpNezW9Y CuNeI4YNhMkVQiBDGMf87t2T0f9aDrNx83d6+NtluU+6AxgHD/6259tuYWtUzNPjKowY 7f+bZgu67hnkLTKCih/AKW67B8jb8KEp6oGVKmY0RFZABKhHLke+zzE4aHxoXK/2Uckb fYT+/GerzuRpkQsfIQH7LtL83V9pHhEO/yyqrf2QGFPxQ2o9F+RMTFgC5dO36+qMlst7 xW440GnWNsPypoxG3hygnGsG2hfqmAflFX+QyX6AMSk249idMPbbqgf7r77Rlt/bJQ8V BHLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864305; x=1717469105; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BljNjeMaZO3XaNf0tppv2lCKaXtzum6yJ/eCc7gYwjE=; b=YzzguGX18X5U6b5LJZ/d2zFg8KBfmpwYwKYa7+d6/cbTICArW8GbGXA9iESlraLtY7 ZhKZUnL50HxesgiccsVLJD3BDiXFAmSMpN4zDAYBoeDPp+p2iBUjb3N6wS2w9Ze2wky4 yJU5QC6CH2dpoUCE+7nC67GAd3O8q4VgafOA5XC7ESTIlNuCM0aQs5lcmArKJRCYR3ZZ Dz3yADdA9Xl5KgcAyRwrzR9WZlrsfIOYzi5UG03yZ9Xb+4M9SIKeJoue2NkzoPB9dKjT TtzlHEtIuHMyAQH86BNZlIiJZu9t2j7SE5C15ZYmGTUQgjJV8LJ4Hhv/3qk5exRiRTMO jApg== X-Forwarded-Encrypted: i=1; AJvYcCVhjbibivKKo0fb2sLjPcOGfjGpOQDJ7xT8I57wk6VPEXLlh4iReUgu7yOj7qJ05dDpTtQ2HsT1hEZmsTw0uTzLJdsUCwjp X-Gm-Message-State: AOJu0YwWJP3IipkGAr3SD8aESoPpSKBhX0RRswxyT6FACbQmljVOBpnc IGvmDso+IqcpeMSqY+4mv56Hv96eRAUKe8TiFTZtUss/D2mGgbqbgAcTHw== X-Google-Smtp-Source: AGHT+IHIWMkzcC2taA0xL7S4iJiF04uT/yBLd9R6pYldNAqU75SFzGHDGOiJ1VA7OFc4KD3a7VrgsQ== X-Received: by 2002:a17:902:fc8e:b0:1f4:a04e:8713 with SMTP id d9443c01a7336-1f4a04e8cd4mr65536155ad.28.1716864304559; Mon, 27 May 2024 19:45:04 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.45.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou , Daniel Henrique Barboza , qemu-stable , Alistair Francis Subject: [PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions Date: Tue, 28 May 2024 12:43:20 +1000 Message-ID: <20240528024328.246965-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Max Chou If the checking functions check both the single and double width operators at the same time, then the single width operator checking functions (require_rvf[min]) will check whether the SEW is 8. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza Cc: qemu-stable Message-ID: <20240322092600.1198921-5-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index c3af38af80..3a3896ba06 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2333,7 +2333,6 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2373,7 +2372,6 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_ds(s, a->rd, a->rs2, a->vm); } @@ -2406,7 +2404,6 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2446,7 +2443,6 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dd(s, a->rd, a->rs2, a->vm); } @@ -2704,8 +2700,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a) { return opfv_widen_check(s, a) && require_rvfmin(s) && - require_scale_rvfmin(s) && - (s->sew != MO_8); + require_scale_rvfmin(s); } #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \ @@ -2810,16 +2805,14 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && require_rvfmin(s) && - require_scale_rvfmin(s) && - (s->sew != MO_8); + require_scale_rvfmin(s); } static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && require_rvf(s) && - require_scale_rvf(s) && - (s->sew != MO_8); + require_scale_rvf(s); } #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ @@ -2947,8 +2940,7 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_widen_check(s, a) && require_rvf(s) && - require_scale_rvf(s) && - (s->sew != MO_8); + require_scale_rvf(s); } GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check) From patchwork Tue May 28 02:43:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC1CCC25B74 for ; Tue, 28 May 2024 02:47:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmq1-0005gV-Qw; Mon, 27 May 2024 22:45:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpt-0005Wd-Hj; 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[2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:07 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Joseph Chan , Alistair Francis , qemu-stable Subject: [PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception() Date: Tue, 28 May 2024 12:43:21 +1000 Message-ID: <20240528024328.246965-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=alistair23@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza raise_mmu_exception(), as is today, is prioritizing guest page faults by checking first if virt_enabled && !first_stage, and then considering the regular inst/load/store faults. There's no mention in the spec about guest page fault being a higher priority that PMP faults. In fact, privileged spec section 3.7.1 says: "Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception. Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception. Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception." So, in fact, we're doing it wrong - PMP faults should always be thrown, regardless of also being a first or second stage fault. The way riscv_cpu_tlb_fill() and get_physical_address() work is adequate: a TRANSLATE_PMP_FAIL error is immediately reported and reflected in the 'pmp_violation' flag. What we need is to change raise_mmu_exception() to prioritize it. Reported-by: Joseph Chan Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com> Cc: qemu-stable Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d71245a8cb..574886a694 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1177,28 +1177,30 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, switch (access_type) { case MMU_INST_FETCH: - if (env->virt_enabled && !first_stage) { + if (pmp_violation) { + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; + } else if (env->virt_enabled && !first_stage) { cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; } else { - cs->exception_index = pmp_violation ? - RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT; + cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; } break; case MMU_DATA_LOAD: - if (two_stage && !first_stage) { + if (pmp_violation) { + cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } else if (two_stage && !first_stage) { cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; } else { - cs->exception_index = pmp_violation ? - RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT; + cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; } break; case MMU_DATA_STORE: - if (two_stage && !first_stage) { + if (pmp_violation) { + cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + } else if (two_stage && !first_stage) { cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; } else { - cs->exception_index = pmp_violation ? - RISCV_EXCP_STORE_AMO_ACCESS_FAULT : - RISCV_EXCP_STORE_PAGE_FAULT; + cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; } break; default: From patchwork Tue May 28 02:43:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 370C1C25B74 for ; Tue, 28 May 2024 02:48:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmqO-0006Fb-5v; Mon, 27 May 2024 22:45:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpw-0005ZR-0e; Mon, 27 May 2024 22:45:16 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpu-000423-7x; Mon, 27 May 2024 22:45:15 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-6f8e859eb20so250856b3a.0; Mon, 27 May 2024 19:45:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864311; x=1717469111; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hxijtPcNuNAmolOxSVas1wwngjgg5P1pW7tz7cm2XA8=; b=gz3x2a7zGIEidmK1aW+gOfAusDipcKbEZWvpSIMhyOG0rO5T+zKWfiMY3QVXpWqu5x 2U4EVmBuul2zlQasSHuRV/DynyBZsKwBVOgQnRwZNOXfus5YWLSwOrgTijkjk2EGvZCG vMLRujoq0+3wTxK896g/ha8REtMfJLNHDwq0WjaGfE28tqeMxnm4wyz/Nu49Ot44Wgyt lfTOqReNlBZ9Aiz8AYtW01o4FWSTFuLFlFshF5dUzalj41n6ggJdyryUka52uqvvHe3x nh6E4F5Wqu9k3vnz7DfVcv4FjZjwdBSS5iimVAJ48tIfRRXzK5QIRIN2J1EP8KzB8JdQ B2/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864311; x=1717469111; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hxijtPcNuNAmolOxSVas1wwngjgg5P1pW7tz7cm2XA8=; b=lfoZGqQfrossswLSEfLsacc6NA5z8Dm27sITbEWtz/H9PdgDiq6vjsIkNBXexMygfM b0Dod6jd/TIYDKmpnm194rN6b0082z+q8WVKI+ZYO0TuTM7/vrMqlnRFP66vFaxxj2ve 4cCKcSDAC4gnF96iL1sWJfBeDupZxeb1sPj+/QlZy6y2TX2x/6t3R3KH/V+Y46QADVW4 BPaPKD5JsJUcjhJOilYvx4i+iqNMA/IY/r0pbU/tL9Nr1qBZ4Ob5rtKIKksm8wtnEzuK 6g/Ip81QAH94EHU5uG7e/CHuXSGuAwGUupRpZfsdhDdGDktM20m7+WqgGihwx4Ns31U2 +thA== X-Forwarded-Encrypted: i=1; AJvYcCU2HGjmGVSU29M26rLW4Bkc600az5hbzYkIpDaQU45AiG0JYCkgk+ChQDF5+kY3iKdKjsLUiGQYcCx6L6BtXwCzjD7qF/6Z X-Gm-Message-State: AOJu0YyIDieoYqKmsGQ9M+IPYC9f+wwDxRJelNBS9WSpbpbryq4uRsMb DBSBDW9CAanOZqm8S5KHhIfWQv5yO0bJ+/6qd8KfnsuEJAmRa7ZEyiSldw== X-Google-Smtp-Source: AGHT+IEho5U/SZCPN7r7+9RmZVKYTBsEx/Zx153SQbcEnc2A89sys3PY5Hyhn1K+zqIZfteqoileZA== X-Received: by 2002:a05:6a20:3ca2:b0:1b0:19d5:f400 with SMTP id adf61e73a8af0-1b212dd4446mr12146567637.23.1716864311019; Mon, 27 May 2024 19:45:11 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.45.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:10 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexei Filippov , Daniel Henrique Barboza , Alistair Francis , qemu-stable Subject: [PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults Date: Tue, 28 May 2024 12:43:22 +1000 Message-ID: <20240528024328.246965-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexei Filippov Previous patch fixed the PMP priority in raise_mmu_exception() but we're still setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage translation part, mtval2 will be set in case of successes 2 stage translation but failed pmp check. In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest page-fault is taken into M-mode, mtval2 is written with either zero or guest physical address that faulted, shifted by 2 bits. *For other traps, mtval2 is set to zero...* Signed-off-by: Alexei Filippov Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com> Cc: qemu-stable Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 574886a694..a02497d778 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1376,17 +1376,17 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, __func__, pa, ret, prot_pmp, tlb_size); prot &= prot_pmp; - } - - if (ret != TRANSLATE_SUCCESS) { + } else { /* * Guest physical address translation failed, this is a HS * level exception */ first_stage_error = false; - env->guest_phys_fault_addr = (im_address | - (address & - (TARGET_PAGE_SIZE - 1))) >> 2; + if (ret != TRANSLATE_PMP_FAIL) { + env->guest_phys_fault_addr = (im_address | + (address & + (TARGET_PAGE_SIZE - 1))) >> 2; + } } } } else { From patchwork Tue May 28 02:43:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F5A7C25B7C for ; Tue, 28 May 2024 02:47:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmqP-0006TW-La; Mon, 27 May 2024 22:45:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmpx-0005d0-Uc for qemu-devel@nongnu.org; Mon, 27 May 2024 22:45:19 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpw-00042O-59 for qemu-devel@nongnu.org; Mon, 27 May 2024 22:45:17 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-68185f92bfdso251207a12.0 for ; Mon, 27 May 2024 19:45:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864314; x=1717469114; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w6AzoFo8JUHoIoVJzS9JZAaDEbHq/fZUj2l7V7rYL/A=; b=QP0cU1jVAzH8PWWfB1EMpFXE90o83NVkfE+7bRRlw551Ql4jYJjAuXLSHWNiF73fHc wL8s2DQvHquJxUIBvBhoQS+T4ZDtls3QZAOUfH7stMWo6mrEaRdaWR13yxVMdRmRXtCp hizbmx3rbcWAM7fUxMld1kzryx5J6RVKyEer0VZzUOYJ70sCWOM0guI/Xlrsyw8flQoU sbf60oKv+0/PF7U+tHd6pSV/5U1RpYqim98K8rqFg3o1rAYjznZnOLZs0UCtcpYGD2f1 fpFrJ9eK7mdCBmRpIXMcxMUytj10XFNQGpsZ8EepYikDHZJ20yIahDJthR4myIB4p1y4 r3Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864314; x=1717469114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w6AzoFo8JUHoIoVJzS9JZAaDEbHq/fZUj2l7V7rYL/A=; b=ImznSdoGpdVFPA6MmWTjUHGTBzAHyozF+Ue4VXbzHd46E5mfRtiIydFsXO09onay1F 2iCqHUW2P9gA8ndIe30DEyZQlzHcY6hDOI810sylOkRP9M0pR8FY0BOB9a/NtxrlsnSS uhBc0N0Lasnli1eyDPOnASlDJY/9N4nV6R5PUB1xiQGSVZYr1CzZyFKAQNl63fUsnJSD fQmzXbzNqTtHU8cZ2oDRLANZVkuapay+6Ca26uIjhc2xz4kD3hZUwaxyQA6hsE2xnXY9 NG6jr9fOTQLL4suLS5BCZfJAPBaYoGaAfrmLoDQ2qdsSMPdwwy15F35B70gMdY3FKRmX ozyA== X-Gm-Message-State: AOJu0YwUvMD4AijOM1Ks1WJQdjQLYHBOVRSbf9aANbwtTSE9szH94yvX N5N8oVHuMB4kaYwaiCQGWYamoU3LeJqyP+PW45vrugx2TShvwtTUMEOH8Q== X-Google-Smtp-Source: AGHT+IEMjkSkq7OD8Ut5c2F3mGQxtpTmFwGgmVHfToyBFud2Q9HNqb/25Z1NWCIpEsAYVRnHWwf49w== X-Received: by 2002:a05:6a20:3d8a:b0:1a7:7ac1:a3ba with SMTP id adf61e73a8af0-1b212e2c397mr11877294637.53.1716864314503; Mon, 27 May 2024 19:45:14 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.45.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:14 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Rob Bradford , Andrew Jones , Alistair Francis , Daniel Henrique Barboza , LIU Zhiwei Subject: [PULL 23/28] target/riscv: Remove experimental prefix from "B" extension Date: Tue, 28 May 2024 12:43:23 +1000 Message-ID: <20240528024328.246965-24-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Rob Bradford This extension has now been ratified: https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be removed. Since this is now a ratified extension add it to the list of extensions included in the "max" CPU variant. Signed-off-by: Rob Bradford Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2946ac298a..cee6fc4a9a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1400,7 +1400,7 @@ static const MISAExtInfo misa_ext_info_arr[] = { MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), MISA_EXT_INFO(RVV, "v", "Vector operations"), MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), - MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") + MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)") }; static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f59b5d7f2d..683f604d9f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1301,7 +1301,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) const RISCVCPUMultiExtConfig *prop; /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); + riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); From patchwork Tue May 28 02:43:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C53AC25B74 for ; Tue, 28 May 2024 02:46:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmqf-0006oG-3F; Mon, 27 May 2024 22:46:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmq2-0005kM-F3; Mon, 27 May 2024 22:45:25 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmpz-00042d-Gx; Mon, 27 May 2024 22:45:21 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1f47eb2354bso2405445ad.3; Mon, 27 May 2024 19:45:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864318; x=1717469118; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tj+xbQPw1aTPPkVQS9cYzQUJajn8RHcrOCksv3MTYMs=; b=KOehGwjsf+U6bOgzN/xi10jTGikrVJjM8QOmVhybPN0l7ad5/LHR83pSxHZZVkXvcy yBfoZyKKjhplIQD95bjEnIGXlMYQHTJIKHgCH6kwAu24n+VjXaVLYHMweehyroq4+bNy A7abHRbx7PrYYbQuptuQZqdZUfZYfSfQetmBUblkhCILRVMGzUnqB3urm8VWnio/GuWn SFtfcYJ8ZZ+WJYdo3oJTsAP7tsPPlaU8u8q+DOxLi5DRA8H2K1kCkH3Hd3JAlP7RfYMu n+Em2pVHVkz3RNpYdZepDREj76/gbsEUgFSVr8nIapsZ8JkSAOr0fNczrY4SCpiURm0k mYug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864318; x=1717469118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tj+xbQPw1aTPPkVQS9cYzQUJajn8RHcrOCksv3MTYMs=; b=uTOh3bTvx32WjKT/di+U9fTmAL6N6gYEHwwwWLQ6ir656QJ0s53GP8iIcvP/lBJFPV zRt2gH9wzBrNqa6MdCzgDd971U2jtgDlxAi8uTwVEBlpBjlHz5x/JuJ/9r1aUaz1SO0l LmbwR4vtHfDlh7451OcficGxKL1pJ1YRGYFFHO92Ns5UTLPh/GgcR2ef3G3HMhJlab1G eBQidrB3DU5dmDIPg+tyweMpUMYg39wvI4TSfbn/eUBEiIEa0O6GYV/wud/OFL4eoR8d axfjtEdUFfFg51GxeXIfqSSQBy6qmghdTHqW6clAOEcQ1zS0HDSFynAazOzoOtoTQaoe 9+Fw== X-Forwarded-Encrypted: i=1; AJvYcCUScBgwyIqayrMqkgQdec6jEvCYvwuTGiWfyd1vHN07u1mtXjHo8RZ38YZRv47t4kk2XDj0I8srbyjzY5JspofGHo30CHVx X-Gm-Message-State: AOJu0YycOZ4Ji9HpHeBGWAJbowgbtqolUn2OqQLLEQK+5ZcXOub1Qnq9 LhimqcGHsMZ3I3evEbtnpE/dkVrGl4ex1OKnLUZR57sTHm1Wpr9qcx0Cvg== X-Google-Smtp-Source: AGHT+IHNY3mxTsO4GD2NNhPfEfODwh8OY9wim5AAeReOnQOeVOX+bhORTPA04dSr7Ub7EGIto9QyOw== X-Received: by 2002:a17:903:184:b0:1f4:bcef:e962 with SMTP id d9443c01a7336-1f4bceff50cmr23240845ad.52.1716864317698; Mon, 27 May 2024 19:45:17 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:17 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis , Fabian Thomas , Richard Henderson , qemu-stable Subject: [PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation Date: Tue, 28 May 2024 12:43:24 +1000 Message-ID: <20240528024328.246965-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alistair Francis When running the instruction ``` cbo.flush 0(x0) ``` QEMU would segfault. The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0] allocated. In order to fix this let's use the existing get_address() helper. This also has the benefit of performing pointer mask calculations on the address specified in rs1. The pointer masking specificiation specifically states: """ Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz """ So this is the correct behaviour and we previously have been incorrectly not masking the address. Signed-off-by: Alistair Francis Reported-by: Fabian Thomas Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension") Reviewed-by: Richard Henderson Cc: qemu-stable Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc index d5d7095903..15711c3140 100644 --- a/target/riscv/insn_trans/trans_rvzicbo.c.inc +++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc @@ -31,27 +31,35 @@ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a) { REQUIRE_ZICBOM(ctx); - gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]); + TCGv src = get_address(ctx, a->rs1, 0); + + gen_helper_cbo_clean_flush(tcg_env, src); return true; } static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a) { REQUIRE_ZICBOM(ctx); - gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]); + TCGv src = get_address(ctx, a->rs1, 0); + + gen_helper_cbo_clean_flush(tcg_env, src); return true; } static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a) { REQUIRE_ZICBOM(ctx); - gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]); + TCGv src = get_address(ctx, a->rs1, 0); + + gen_helper_cbo_inval(tcg_env, src); return true; } static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a) { REQUIRE_ZICBOZ(ctx); - gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]); + TCGv src = get_address(ctx, a->rs1, 0); + + gen_helper_cbo_zero(tcg_env, src); return true; } From patchwork Tue May 28 02:43:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14CBEC25B7C for ; Tue, 28 May 2024 02:47:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmr3-0007dy-4B; Mon, 27 May 2024 22:46:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmq5-0005qo-Er; Mon, 27 May 2024 22:45:28 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmq3-00042x-Oj; Mon, 27 May 2024 22:45:25 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1f48bd643a0so2797845ad.3; Mon, 27 May 2024 19:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864322; x=1717469122; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=okL/u9Yr4I1gdpYP+OUmz0dGlxU1P8AIMDXGmwEB0cY=; b=VV4PA+A1kGIf0qvLu82f0he8KlTL+MtyggCi4Voztj7CFQAymbYBP1JZVbd1XG0j+G loamb9dHfb6LLQeS0+hEbpGBUX0PUwDBXegsuZU84C6AZLQWroJO3vbXrgJCyOTXjDsx 2rkUigr0K1nzdjaor6btO15f8J15ZwHVvqnsQkeO+M62yKlVb4VrrfWn1cm2Szo5nls6 jkUk4/iLhf4SUJT/9A/8dcvvjMVu7kKtYKt/nzOEV6AOnEYqlJka1lhxzJ44hklP954z rp2OONjz5IH1KefodLlkKHn+ntUjYPiUdPfbecKlTkHGRXddEv6521YWrbzPmr48tKYP mseQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864322; x=1717469122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=okL/u9Yr4I1gdpYP+OUmz0dGlxU1P8AIMDXGmwEB0cY=; b=Hdjfo+v/9bBQCniDIKddFYWSoI+FqlLxF9cZe9Qn8MK1HjNPs7KGbu9spbDtXuMwCn MyfRzg8hG/pERaOiXO/DmnvDrFydEnbkbIuJum0uA84co8a67mw6mhZpPvUBrZtUlQkM v8FFm4T5DDXclTgMLod2SyzfbZPxDxc52pYQNYQdQWFYIELmmPvHxTOkBJDWGSS2l6VV cOnqG8i2PcVdw8lAP+7kpQSHfd+2swUWoEtlaM0rnB94rfkUbPvl4qwitfpV8AufrpG6 AhMAWrtpOyuKOANE5UziQzG66fzwsyrvYHWlPwpAbO66NH8xbBrzkcVtOhEIxItQY9Ut Ocqw== X-Forwarded-Encrypted: i=1; AJvYcCUw5IXu/8Iwwzt1J4mW71M9fq+00waG04pv7qmNvdeKgT1iaXGK+LcOhPH9RJzTlvjCjtBD0PDLpxHZSFYNQB6KmGu0Sdsj X-Gm-Message-State: AOJu0Ywp6H7iygOKhnAME9rx5IPAHbL7g9k3Ch+klIVlzUyceCLgvaX3 Vm03fT6LjdQsCfCEUPKQzSIkrcyuC4Gcbu46VRdjHrxgoEAZCVDp0RhTsw== X-Google-Smtp-Source: AGHT+IGk18WLY6sPTaDfBrZsmGrDkLA+eHUSZI9mH1XG/bLQa+ZavDBolfSnVhKoh5pr0aNuDe7b2A== X-Received: by 2002:a17:902:7847:b0:1f4:9e85:9d4f with SMTP id d9443c01a7336-1f49e85a120mr38295485ad.11.1716864321680; Mon, 27 May 2024 19:45:21 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:20 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yong-Xuan Wang , Andrew Jones , qemu-stable , Alistair Francis Subject: [PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA Date: Tue, 28 May 2024 12:43:25 +1000 Message-ID: <20240528024328.246965-26-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Yong-Xuan Wang In AIA spec, each hart (or each hart within a group) has a unique hart number to locate the memory pages of interrupt files in the address space. The number of bits required to represent any hart number is equal to ceil(log2(hmax + 1)), where hmax is the largest hart number among groups. However, if the largest hart number among groups is a power of 2, QEMU will pass an inaccurate hart-index-bit setting to Linux. For example, when the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient to represent 4 harts, but we passes 3 to Linux. The code needs to be updated to ensure accurate hart-index-bit settings. Additionally, a Linux patch[1] is necessary to correctly recover the hart index when the guest OS has only 1 hart, where the hart-index-bit is 0. [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/ Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones Cc: qemu-stable Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 473416649f..235e2cdaca 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, } } - hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; + + if (max_hart_per_socket > 1) { + max_hart_per_socket--; + hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; + } else { + hart_bits = 0; + } + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, &hart_bits, true, NULL); From patchwork Tue May 28 02:43:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13503C25B7E for ; Tue, 28 May 2024 02:47:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmqP-0006Rt-Hr; Mon, 27 May 2024 22:45:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmqA-0005vL-HC; Mon, 27 May 2024 22:45:32 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmq8-00043J-OF; Mon, 27 May 2024 22:45:30 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1f4c7b022f8so2375945ad.1; Mon, 27 May 2024 19:45:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864326; x=1717469126; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yN3SL80ZeNYtdgHnSA4EmYhdmlHM54QOJLaD6qM4+6Q=; b=Exg18F5tMK73OaxP3bNlTlhrnSNuifOaypvwpimkoXwWTfi/vK5EeTsoVb107dV03W 2fEV+b5Fw0z5oruh/mFSW3FzCnZ//+jPWvuB+5vcDxqgNS8nODYew+gVTmLZxEkOJ8d1 9Li0Yl7LQq9YDcT9JL5tORJXZN0lwON+B07tSAag87kEAn6OhR/lMF1tEUocLBzlyVfp GGpaaKWWphZ2FnfmRU8SP76RHujMEbhi2giBs384x0MRmBDKsYPgsHkqSdxuMYbKjws2 TTmKWmU9vvpPqL3ARr8957nuboV7fNN5mGlbmqocUzMwa2NF+yIsBE8eCqjDPT7ZaXnX ipBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864326; x=1717469126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yN3SL80ZeNYtdgHnSA4EmYhdmlHM54QOJLaD6qM4+6Q=; b=UoSruCLoIZZJ69kpaRg29x0fliTNSuucjjDMSM7T7TI9qsY/FtyVBo4QWQF57MydTv O7l6MZkp07G5XxUjdfKOwmK9gLobTYbUOFXURUpUVwNLq7Mcr0877AgQ/qQxaNOq9GIz BRH2t6cnay2PSCQfrgls7jkBEzeXWnO9j9/qUpcKw6LFdCp+y5ONeZgq0jaI8H7U/XlB ridvBlbQYDr79DnKqmcjck2vrdDi1HTVc99E52hb5xudS5z7zakAcOlTzW0dEIlsmpGW qhkELgowmSIf9mqN/RjRSSyvGT5cjHbtO301rb8VJ5cO9Otb63fTIbMZy42dJZjcSnU9 O0Dg== X-Forwarded-Encrypted: i=1; AJvYcCWsGNDFSOhnxqFctu90I8VhtxyfpCraiPdY9A3FlhRXypcVeftYl6rFE6RRLm+KOA4EYhrkVokv2QAiKbZsdP7eYzZvmQCi X-Gm-Message-State: AOJu0YwD3o/JNyLDWlcFxG7h9hdXtSX5uxO5+jHA3DEPyb6tVlOeH3D9 PKBLNkKB5yEgSfLZzfd77nsuSu2fxkWEFA5GN0c0OF+xAfDC5znklF5UMQ== X-Google-Smtp-Source: AGHT+IE2sA0VgTzSkcni8oDsYxKZiM5vXKZauNaaAQl2WAGLA7Dfo1+LuYCXjx32GnkLfSOyA75bkA== X-Received: by 2002:a17:902:d50c:b0:1f4:b313:3e9a with SMTP id d9443c01a7336-1f4b3134380mr31282465ad.65.1716864325829; Mon, 27 May 2024 19:45:25 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:25 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Akihiko Odaki , =?utf-8?q?Alex_Benn=C3=A9e?= , Robin Dapp , LIU Zhiwei , Alistair Francis , qemu-stable Subject: [PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() Date: Tue, 28 May 2024 12:43:26 +1000 Message-ID: <20240528024328.246965-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length in bytes, when in this context we want 'reg_width' as the length in bits. Fix 'reg_width' back to the value in bits like 7cb59921c05a ("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set beforehand. While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more clarity about what the variable represents. 'bitsize' is also used in riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to gdb_feature_builder_append_reg(). Cc: Akihiko Odaki Cc: Alex Bennée Reported-by: Robin Dapp Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML") Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Acked-by: Alex Bennée Reviewed-by: Akihiko Odaki Reviewed-by: Alistair Francis Cc: qemu-stable Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/gdbstub.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index d0cc5762c2..c07df972f1 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -288,7 +288,7 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg) static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) { RISCVCPU *cpu = RISCV_CPU(cs); - int reg_width = cpu->cfg.vlenb; + int bitsize = cpu->cfg.vlenb << 3; GDBFeatureBuilder builder; int i; @@ -298,7 +298,7 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - int count = reg_width / vec_lanes[i].size; + int count = bitsize / vec_lanes[i].size; gdb_feature_builder_append_tag( &builder, "", vec_lanes[i].id, vec_lanes[i].gdb_type, count); @@ -316,7 +316,7 @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) /* Define vector registers */ for (i = 0; i < 32; i++) { gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i), - reg_width, i, "riscv_vector", "vector"); + bitsize, i, "riscv_vector", "vector"); } gdb_feature_builder_end(&builder); From patchwork Tue May 28 02:43:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B18FAC25B74 for ; Tue, 28 May 2024 02:47:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmr7-0008Ni-3O; Mon, 27 May 2024 22:46:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmqE-000610-Po; Mon, 27 May 2024 22:45:36 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBmqB-00043X-8J; Mon, 27 May 2024 22:45:34 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-681bee6bb13so2319631a12.1; Mon, 27 May 2024 19:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716864329; x=1717469129; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J5jhBOyEYmtoTJBDh000o1EH0VVoye2sH2+Q4KCgR/U=; b=RAbWoRJHCj95iZgADV193LMOE+7Y8BCIxZaPaW9EXmB9kAPYjNNYVwdv0p4T76zeGz XOvYaEfxnl0NO9syjqGIENOI7NC5TXhZfgartWrMr3u/bo/zHYLX3kY/1eyoE35PLFsR xtBWjEo70IKR7JYb7h7UQym1w/W2SvBIpLBYwblrZE+A90VcMUzsGQg5vFMawNpRl0SZ 2z3HtDZSFkyRkNYWw8uSwVT0ux9LoCGe/Gdlax2sKQ7AJpovWFYbOxujr3rgNbNmcS2o bCUyPCpc6lDOCb11A66MSZB4Zl6rPRUMpps61O2xWUu5G5tgdchdoVL0wGjnwSfrg7hC +A/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716864329; x=1717469129; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J5jhBOyEYmtoTJBDh000o1EH0VVoye2sH2+Q4KCgR/U=; b=w8jnEw46/hfwAiNmIxuyV7xuFGLU7ZwSYLjgBC9jxSjYfrDpyIz+uzMhb03hZuxuEt +aTdkWzKs3NyNwcPWTU7rzBQNjz4r+XA5qO6O3RPF2c/F0Fl0cNWx2WQ7gzLvoeITd/k I+nQYF9PRIbUbRPb0KoMMuCOsv9I8nwPkJaLgyTB1fPnQbZ5LPSuXLzilIYvVqv4gF6K Co+lbRGVYt0D5XUuGdhuEgkOsEWPrHa643nyXxoYkUvHrXltLB1X9zVs5o/HK6UPSjls 3Loozt2bp7dhBqVD5FeSqoIZ/TbujfLLsyD1RYj6CncMwRYgmw327JZ5RlHXhxChyXKU HrqA== X-Forwarded-Encrypted: i=1; AJvYcCX1MZVGqonqod5Z5gTv0xck7aNhLYHnyZK4EZvEvG79rR+ObZUa1/puTMx85B9cGiXzrFp/0sQP18rnSU3Fc5NHlwqBV6mn X-Gm-Message-State: AOJu0YzecSbqJnJ2YzNpzoGk8HsV3PLeMi95ASLrFCy1WdfTJXrUrTzR v/uKhYlRkwyJuGmIRIQDcrDT+o3Amt8r9pM7bTExTaQrMq+zhznglsElOg== X-Google-Smtp-Source: AGHT+IGMtkHie2+p7yc4Q1tiVjUxxUGzzd2HPR9bp5uQkxDSTAgDpOHkmT8N5DvuF21AuC1VvdYtnA== X-Received: by 2002:a17:90a:888:b0:2bd:efc4:a9b with SMTP id 98e67ed59e1d1-2bdefc40ad6mr17075822a91.8.1716864329102; Mon, 27 May 2024 19:45:29 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:28 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Eric DeVolder , Alistair Francis , Daniel Henrique Barboza , qemu-stable Subject: [PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs Date: Tue, 28 May 2024 12:43:27 +1000 Message-ID: <20240528024328.246965-28-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alistair Francis Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr CSRs are part of the disassembly. Reported-by: Eric DeVolder Signed-off-by: Alistair Francis Fixes: ea10325917 ("RISC-V Disassembler") Reviewed-by: Daniel Henrique Barboza Cc: qemu-stable Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com> Signed-off-by: Alistair Francis --- disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index e236c8b5b7..297cfa2f63 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2190,7 +2190,22 @@ static const char *csr_name(int csrno) case 0x0383: return "mibound"; case 0x0384: return "mdbase"; case 0x0385: return "mdbound"; - case 0x03a0: return "pmpcfg3"; + case 0x03a0: return "pmpcfg0"; + case 0x03a1: return "pmpcfg1"; + case 0x03a2: return "pmpcfg2"; + case 0x03a3: return "pmpcfg3"; + case 0x03a4: return "pmpcfg4"; + case 0x03a5: return "pmpcfg5"; + case 0x03a6: return "pmpcfg6"; + case 0x03a7: return "pmpcfg7"; + case 0x03a8: return "pmpcfg8"; + case 0x03a9: return "pmpcfg9"; + case 0x03aa: return "pmpcfg10"; + case 0x03ab: return "pmpcfg11"; + case 0x03ac: return "pmpcfg12"; + case 0x03ad: return "pmpcfg13"; + case 0x03ae: return "pmpcfg14"; + case 0x03af: return "pmpcfg15"; case 0x03b0: return "pmpaddr0"; case 0x03b1: return "pmpaddr1"; case 0x03b2: return "pmpaddr2"; @@ -2207,6 +2222,54 @@ static const char *csr_name(int csrno) case 0x03bd: return "pmpaddr13"; case 0x03be: return "pmpaddr14"; case 0x03bf: return "pmpaddr15"; + case 0x03c0: return "pmpaddr16"; + case 0x03c1: return "pmpaddr17"; + case 0x03c2: return "pmpaddr18"; + case 0x03c3: return "pmpaddr19"; + case 0x03c4: return "pmpaddr20"; + case 0x03c5: return "pmpaddr21"; + case 0x03c6: return "pmpaddr22"; + case 0x03c7: return "pmpaddr23"; + case 0x03c8: return "pmpaddr24"; + case 0x03c9: return "pmpaddr25"; + case 0x03ca: return "pmpaddr26"; + case 0x03cb: return "pmpaddr27"; + case 0x03cc: return "pmpaddr28"; + case 0x03cd: return "pmpaddr29"; + case 0x03ce: return "pmpaddr30"; + case 0x03cf: return "pmpaddr31"; + case 0x03d0: return "pmpaddr32"; + case 0x03d1: return "pmpaddr33"; + case 0x03d2: return "pmpaddr34"; + case 0x03d3: return "pmpaddr35"; + case 0x03d4: return "pmpaddr36"; + case 0x03d5: return "pmpaddr37"; + case 0x03d6: return "pmpaddr38"; + case 0x03d7: return "pmpaddr39"; + case 0x03d8: return "pmpaddr40"; + case 0x03d9: return "pmpaddr41"; + case 0x03da: return "pmpaddr42"; + case 0x03db: return "pmpaddr43"; + case 0x03dc: return "pmpaddr44"; + case 0x03dd: return "pmpaddr45"; + case 0x03de: return "pmpaddr46"; + case 0x03df: return "pmpaddr47"; + case 0x03e0: return "pmpaddr48"; + case 0x03e1: return "pmpaddr49"; + case 0x03e2: return "pmpaddr50"; + case 0x03e3: return "pmpaddr51"; + case 0x03e4: return "pmpaddr52"; + case 0x03e5: return "pmpaddr53"; + case 0x03e6: return "pmpaddr54"; + case 0x03e7: return "pmpaddr55"; + case 0x03e8: return "pmpaddr56"; + case 0x03e9: return "pmpaddr57"; + case 0x03ea: return "pmpaddr58"; + case 0x03eb: return "pmpaddr59"; + case 0x03ec: return "pmpaddr60"; + case 0x03ed: return "pmpaddr61"; + case 0x03ee: return "pmpaddr62"; + case 0x03ef: return "pmpaddr63"; case 0x0780: return "mtohost"; case 0x0781: return "mfromhost"; case 0x0782: return "mreset"; From patchwork Tue May 28 02:43:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13676030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02E4FC25B74 for ; Tue, 28 May 2024 02:47:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBmqs-00075l-Qu; Mon, 27 May 2024 22:46:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBmqF-00062A-CY for qemu-devel@nongnu.org; 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Mon, 27 May 2024 19:45:31 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-82ce-f179-8a79-69f4.ip6.aussiebb.net. [2403:580b:97e8:0:82ce:f179:8a79:69f4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c970ca0sm70733225ad.142.2024.05.27.19.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 19:45:31 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yu-Ming Chang , Alistair Francis Subject: [PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR Date: Tue, 28 May 2024 12:43:28 +1000 Message-ID: <20240528024328.246965-29-alistair.francis@wdc.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528024328.246965-1-alistair.francis@wdc.com> References: <20240528024328.246965-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Yu-Ming Chang Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies a register holding a zero value, an illegal instruction exception should be raised. Signed-off-by: Yu-Ming Chang Reviewed-by: Alistair Francis Message-ID: <20240403070823.80897-1-yumin686@andestech.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++++ target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++---- target/riscv/op_helper.c | 6 ++--- 3 files changed, 53 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 12d8b5344a..1501868008 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -709,6 +709,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, void riscv_cpu_update_mask(CPURISCVState *env); bool riscv_cpu_is_32bit(RISCVCPU *cpu); +RISCVException riscv_csrr(CPURISCVState *env, int csrno, + target_ulong *ret_value); RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); @@ -741,6 +743,8 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, target_ulong new_value, target_ulong write_mask); +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, + Int128 *ret_value); RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, Int128 *ret_value, Int128 new_value, Int128 write_mask); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58ef7079dc..57f831fedc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -4322,7 +4322,7 @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno, static inline RISCVException riscv_csrrw_check(CPURISCVState *env, int csrno, - bool write_mask) + bool write) { /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ bool read_only = get_field(csrno, 0xC00) == 3; @@ -4344,7 +4344,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, } /* read / write check */ - if (write_mask && read_only) { + if (write && read_only) { return RISCV_EXCP_ILLEGAL_INST; } @@ -4431,11 +4431,22 @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +RISCVException riscv_csrr(CPURISCVState *env, int csrno, + target_ulong *ret_value) +{ + RISCVException ret = riscv_csrrw_check(env, csrno, false); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + return riscv_csrrw_do64(env, csrno, ret_value, 0, 0); +} + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVException ret = riscv_csrrw_check(env, csrno, write_mask); + RISCVException ret = riscv_csrrw_check(env, csrno, true); if (ret != RISCV_EXCP_NONE) { return ret; } @@ -4483,13 +4494,45 @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, + Int128 *ret_value) +{ + RISCVException ret; + + ret = riscv_csrrw_check(env, csrno, false); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + if (csr_ops[csrno].read128) { + return riscv_csrrw_do128(env, csrno, ret_value, + int128_zero(), int128_zero()); + } + + /* + * Fall back to 64-bit version for now, if the 128-bit alternative isn't + * at all defined. + * Note, some CSRs don't need to extend to MXLEN (64 upper bits non + * significant), for those, this fallback is correctly handling the + * accesses + */ + target_ulong old_value; + ret = riscv_csrrw_do64(env, csrno, &old_value, + (target_ulong)0, + (target_ulong)0); + if (ret == RISCV_EXCP_NONE && ret_value) { + *ret_value = int128_make64(old_value); + } + return ret; +} + RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, Int128 *ret_value, Int128 new_value, Int128 write_mask) { RISCVException ret; - ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask)); + ret = riscv_csrrw_check(env, csrno, true); if (ret != RISCV_EXCP_NONE) { return ret; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 2baf5bc3ca..84fb2a35e5 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -51,7 +51,7 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) } target_ulong val = 0; - RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0); + RISCVException ret = riscv_csrr(env, csr, &val); if (ret != RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); @@ -84,9 +84,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, target_ulong helper_csrr_i128(CPURISCVState *env, int csr) { Int128 rv = int128_zero(); - RISCVException ret = riscv_csrrw_i128(env, csr, &rv, - int128_zero(), - int128_zero()); + RISCVException ret = riscv_csrr_i128(env, csr, &rv); if (ret != RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC());