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This will add a compatible for it. Acked-by: Conor Dooley Signed-off-by: Xu Yang --- Changes in v2: - no changes Changes in v3: - let imx95 compatilbe with imx93 Changes in v4: - add Acked-by tag Changes in v5: - no changes Changes in v6: - no changes Changes in v7: - no changes Changes in v8: - no changes Changes in v9: - no changes Changes in v10: - no changes Changes in v11: - no changes --- Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml index 6c96a4204e5d..37e8b98f2cdc 100644 --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml @@ -30,6 +30,9 @@ properties: - items: - const: fsl,imx8dxl-ddr-pmu - const: fsl,imx8-ddr-pmu + - items: + - const: fsl,imx95-ddr-pmu + - const: fsl,imx93-ddr-pmu reg: maxItems: 1 From patchwork Tue May 28 16:05:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13676242 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2077.outbound.protection.outlook.com [40.107.6.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3B647347D for ; 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Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by AS5PR04MB10019.eurprd04.prod.outlook.com (2603:10a6:20b:67f::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.30; Tue, 28 May 2024 07:57:31 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::4e24:c2c7:bd58:c5c7]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::4e24:c2c7:bd58:c5c7%4]) with mapi id 15.20.7611.025; Tue, 28 May 2024 07:57:31 +0000 From: Xu Yang To: frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v11 2/8] perf: imx_perf: add macro definitions for parsing config attr Date: Wed, 29 May 2024 00:05:17 +0800 Message-Id: <20240528160523.1695953-2-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240528160523.1695953-1-xu.yang_2@nxp.com> References: <20240528160523.1695953-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI1PR02CA0027.apcprd02.prod.outlook.com (2603:1096:4:1f4::18) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS5PR04MB10019:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a20b8b7-22ee-4c5a-dbaf-08dc7eebd3a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|1800799015|52116005|7416005|376005|38350700005|921011; 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This will add macro definitions to avoid hard-code in driver. Reviewed-by: Frank Li Signed-off-by: Xu Yang --- Changes in v4: - new patch Changes in v5: - move this patch earlier Changes in v6: - no changes Changes in v7: - use FIELD_* Changes in v8: - add Rb tag Changes in v9: - add Rb tag Changes in v10: - no changes Changes in v11: - no changes --- drivers/perf/fsl_imx9_ddr_perf.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 72c2d3074cde..0017f2c9ef91 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -42,6 +42,9 @@ #define NUM_COUNTERS 11 #define CYCLES_COUNTER 0 +#define CONFIG_EVENT GENMASK(7, 0) +#define CONFIG_COUNTER GENMASK(15, 8) + #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) #define DDR_PERF_DEV_NAME "imx9_ddr" @@ -339,8 +342,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, int counter, bool enable) { u32 ctrl_a; + int event; ctrl_a = readl_relaxed(pmu->base + PMLCA(counter)); + event = FIELD_GET(CONFIG_EVENT, config); if (enable) { ctrl_a |= PMLCA_FC; @@ -352,7 +357,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, ctrl_a &= ~PMLCA_FC; ctrl_a |= PMLCA_CE; ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F); - ctrl_a |= FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF)); + ctrl_a |= FIELD_PREP(PMLCA_EVENT, event); writel(ctrl_a, pmu->base + PMLCA(counter)); } else { /* Freeze counter. */ @@ -366,8 +371,8 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int u32 pmcfg1, pmcfg2; int event, counter; - event = cfg & 0x000000FF; - counter = (cfg & 0x0000FF00) >> 8; + event = FIELD_GET(CONFIG_EVENT, cfg); + counter = FIELD_GET(CONFIG_COUNTER, cfg); pmcfg1 = readl_relaxed(pmu->base + PMCFG1); @@ -469,7 +474,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) int cfg2 = event->attr.config2; int counter; - counter = (cfg & 0x0000FF00) >> 8; + counter = FIELD_GET(CONFIG_COUNTER, cfg); pmu->events[counter] = event; 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b=HmsuW96hlsOc3CiBePtiK8Hnhyt8qnS3jWjGwhP0PiLwXGWDTqOl8h4v7797gkkzXuQeW+oXXtRPo0H1XSumd+NPbsbqxVCE7gLXJCUldbs/yxRR6515w+U+WZ9iSP1TPi1RCY20SDz8NMGKsR0WJHkHAA/fx8bz91j5XaOfhQc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by AS5PR04MB10019.eurprd04.prod.outlook.com (2603:10a6:20b:67f::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.30; Tue, 28 May 2024 07:57:39 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::4e24:c2c7:bd58:c5c7]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::4e24:c2c7:bd58:c5c7%4]) with mapi id 15.20.7611.025; Tue, 28 May 2024 07:57:39 +0000 From: Xu Yang To: frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v11 3/8] perf: imx_perf: let the driver manage the counter usage rather the user Date: Wed, 29 May 2024 00:05:18 +0800 Message-Id: <20240528160523.1695953-3-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240528160523.1695953-1-xu.yang_2@nxp.com> References: <20240528160523.1695953-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI1PR02CA0027.apcprd02.prod.outlook.com (2603:1096:4:1f4::18) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS5PR04MB10019:EE_ X-MS-Office365-Filtering-Correlation-Id: 9883c74f-e816-4253-9c58-08dc7eebd882 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|1800799015|52116005|7416005|376005|38350700005|921011; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AR5EVgTh4i2+5Gb65mZqzsZCvKmY7mF+BPiv506mzGbZQDj8jjkeQ7ZDmRVufu7z9Cwbhifqke9CHFIR2YvQB0Jps6krdJMzjBl8nVhQclb5/NvcK/E0MaKrNcqd5+AzUpddXC2fU6HOGP+kEWMfHAnQeBArQRCNf2sxXETUIqrAOlUow0Pm3Y5ZiQyMZx+e+KORp0kVMM07IsMWm7sQPOtlyLNxf/54yXU+E8N0K8QhZBi+jzQqvcul9+jp6wqxTN8mJprvd67NpVts/iJrU0+UxSW0s+cA6tBQPue2DbIurx0CuoNUeEc9UKFGTWdlDtDd+Hwd+Nrxyzext6udKA+1mqEL/6FbOWOuVzmn/ZOF+eK1KntK/M2+UZ5Ek9fI9IaPvPSmm1XDQHZMRQ8CjUmYhtlSY+7U5cjF+oeW05Db30R2U1FSeKF0/F7uYSNkmJFk3iVSFDFNIzI8yJ9fPr7Dm+4V2wJ0AmG29Xpi9vSi7IXq7CqnJ3MJ4ringVEtupU+eO/DuoDIrDC06b9mCQwlmv2cQWRJhQV3dcDIcfxopu9VPXDy1I6/fqsErumgGEZRa514cEDJmNqMR7VNQImpa3HZSR2orqgR/5Gu6SGYkqJoW0GXecadyu65WKMrBRMd+1ICUzB3Qk6b0GOXtLHofENikd2cNfHcDcW5ufnaASn/affY4JLH3qNZKkry03S/OX/ur9Yy7elB1AdSJfvYRH/Pw8gCczcORAhysFd3LCFEp1wxDUybxXrvaO5sU7LNR13Pa590CP7wUohOiYgg6dO+YBes+KVq3/3Qo8XziF/aFiwfHXfVzGSBOTUUnh6KL36ZrVB5U3H/ozZ5/hoEnpTymWYC/h84tJVj1uD6jovamNu9Zbeo0f/g0q+iZFtenTFNHiFOcrdOBfINlEVXZxCec6A+zWQp03PYaalJTqL1pchhS6oXi9J9XmOhDU/YsBrSNxUCmo9AkNyPdArAlQXhxwfs0SQ/GyGZP3iRn0ffWZwMyocwJdtim7Y3yjzljn7Mgn80GUgv7YO88MxlqR+SRFwilcD+GDb4mokfOq7wPoKlDz3Arzk0xctoitP7oH4e4Rtd8rcpp4K8TyJcT8XuJTYAg/gJBHAeVCAmDLYQEeOpvPCj09jWoh5rFXgXwl3ZhTaTskeLhLBJMO3GE4tBzuoBLVmAMl1llSGo4GsuvwS1x7RaJC3umUKWreXPrhzCHk8b0lS95oIi1BfCQ28taU8oSm5dnaCCms4wCTkWfbiHhSW2l4LrP/IlnQGOuKsiTHhHkO6jx/7ifdltRGh+yOjWKtEtn/WJ/MsolzvkAXthTB1A4DvG0WLGlBjPvnVmdB9uNeklaOt5TpQRjlIo55XYWo2lmRSSS/+xuHsY3zX88mT5kDm/MGWl8kriBCE+dBHAbOoG9hgc3SSbMWyoN17vDoIuhoM1AYmVm5CYEDiyvbaGomlPoSDRiva1RMqWFZUqOTrurHve16y9EmO1ywqgOQGxqj9sBPRFMRlslEnbnktuAW7kg2DOlKcykbjygNaDADA0JmiLYre4usLrbd5MbjH2Z5q+fFBXTgABS/N7UqK7L2bdBXG+ X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9883c74f-e816-4253-9c58-08dc7eebd882 X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8822.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2024 07:57:39.6360 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: CrgBACAOELehRhflORQlc0VL/AuLlqzKGmFlJTqOzgDIQ65DwaODTnFnFOC0NLSZgKbBGY0nWuSmkAmn/NariA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS5PR04MB10019 In current design, the user of perf app needs to input counter ID to count events. However, this is not user-friendly since the user needs to lookup the map table to find the counter. Instead of letting the user to input the counter, let this driver to manage the counters in this patch. This will be implemented by: 1. allocate counter 0 for cycle event. 2. find unused counter from 1-10 for reference events. 3. allocate specific counter for counter-specific events. In this patch, counter attr will be kept for back-compatible but all the value passed down by counter= will be ignored. To mark counter-specific events, counter ID will be encoded into perf_pmu_events_attr.id. Reviewed-by: Frank Li Signed-off-by: Xu Yang --- Changes in v6: - new patch Changes in v7: - no changes Changes in v8: - add Rb tag Changes in v9: - keep 'counter' attr for back-compatible Changes in v10: - add some explanation about 'counter' attr in commit message Changes in v11: - keep counter format "config:8-15" - use event format "config:0-7,16-23" as suggested by Frank --- drivers/perf/fsl_imx9_ddr_perf.c | 168 ++++++++++++++++++------------- 1 file changed, 100 insertions(+), 68 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 0017f2c9ef91..15045fbfc685 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -41,9 +41,10 @@ #define NUM_COUNTERS 11 #define CYCLES_COUNTER 0 +#define CYCLES_EVENT_ID 0 #define CONFIG_EVENT GENMASK(7, 0) -#define CONFIG_COUNTER GENMASK(15, 8) +#define CONFIG_COUNTER GENMASK(23, 16) #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) @@ -130,6 +131,9 @@ static ssize_t ddr_pmu_event_show(struct device *dev, return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); } +#define COUNTER_OFFSET_IN_EVENT 8 +#define ID(counter, id) ((counter << COUNTER_OFFSET_IN_EVENT) | id) + #define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \ (&((struct perf_pmu_events_attr[]) { \ { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\ @@ -162,81 +166,81 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_29, 63), /* counter1 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, 64), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, 65), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, 66), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, 67), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, 68), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, 69), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, 70), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, 71), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, ID(1, 64)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, ID(1, 65)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, ID(1, 66)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, ID(1, 67)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, ID(1, 68)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, ID(1, 69)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, ID(1, 70)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, ID(1, 71)), /* counter2 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, 64), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, 65), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, 66), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, 67), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, 68), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, 69), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, ID(2, 64)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, ID(2, 65)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, ID(2, 66)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, ID(2, 67)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, ID(2, 68)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, ID(2, 69)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* counter3 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, 65), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, 66), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, 67), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, 68), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, 69), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, ID(3, 65)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, ID(3, 66)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, ID(3, 67)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, ID(3, 68)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, ID(3, 69)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* counter4 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, 65), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, 66), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, 67), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, 68), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, 69), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, ID(4, 65)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, ID(4, 66)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, ID(4, 67)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, ID(4, 68)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, ID(4, 69)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* counter5 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, 65), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, 66), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, 67), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, 68), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, 69), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, 70), - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, 71), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, 72), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, ID(5, 65)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, ID(5, 66)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, ID(5, 67)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, ID(5, 68)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, ID(5, 69)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, ID(5, 70)), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, ID(5, 71)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, ID(5, 72)), /* counter6 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, 64), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, 72), + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, ID(6, 64)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, ID(6, 72)), /* counter7 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, 64), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, 65), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, ID(7, 64)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, ID(7, 65)), /* counter8 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, 64), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, 65), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, ID(8, 64)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, ID(8, 65)), /* counter9 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, 65), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, 66), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, ID(9, 65)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, ID(9, 66)), /* counter10 specific events */ - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, 65), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, 66), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, ID(10, 65)), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, ID(10, 66)), NULL, }; @@ -245,7 +249,7 @@ static const struct attribute_group ddr_perf_events_attr_group = { .attrs = ddr_perf_events_attrs, }; -PMU_FORMAT_ATTR(event, "config:0-7"); +PMU_FORMAT_ATTR(event, "config:0-7,16-23"); PMU_FORMAT_ATTR(counter, "config:8-15"); PMU_FORMAT_ATTR(axi_id, "config1:0-17"); PMU_FORMAT_ATTR(axi_mask, "config2:0-17"); @@ -366,13 +370,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, } } -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) +static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, + int counter, int axi_id, int axi_mask) { u32 pmcfg1, pmcfg2; - int event, counter; - - event = FIELD_GET(CONFIG_EVENT, cfg); - counter = FIELD_GET(CONFIG_COUNTER, cfg); pmcfg1 = readl_relaxed(pmu->base + PMCFG1); @@ -392,12 +393,12 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN; pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF); - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2); + pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask); writel(pmcfg1, pmu->base + PMCFG1); pmcfg2 = readl_relaxed(pmu->base + PMCFG2); pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF); - pmcfg2 |= FIELD_PREP(PMCFG2_ID, cfg1); + pmcfg2 |= FIELD_PREP(PMCFG2_ID, axi_id); writel(pmcfg2, pmu->base + PMCFG2); } @@ -465,6 +466,28 @@ static void ddr_perf_event_start(struct perf_event *event, int flags) hwc->state = 0; } +static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter) +{ + int i; + + if (event == CYCLES_EVENT_ID) { + // Cycles counter is dedicated for cycle event. + if (pmu->events[CYCLES_COUNTER] == NULL) + return CYCLES_COUNTER; + } else if (counter != 0) { + // Counter specific event use specific counter. + if (pmu->events[counter] == NULL) + return counter; + } else { + // Auto allocate counter for referene event. + for (i = 1; i < NUM_COUNTERS; i++) + if (pmu->events[i] == NULL) + return i; + } + + return -ENOENT; +} + static int ddr_perf_event_add(struct perf_event *event, int flags) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); @@ -472,10 +495,17 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) int cfg = event->attr.config; int cfg1 = event->attr.config1; int cfg2 = event->attr.config2; - int counter; + int event_id, counter; + event_id = FIELD_GET(CONFIG_EVENT, cfg); counter = FIELD_GET(CONFIG_COUNTER, cfg); + counter = ddr_perf_alloc_counter(pmu, event_id, counter); + if (counter < 0) { + dev_dbg(pmu->dev, "There are not enough counters\n"); + return -EOPNOTSUPP; + } + pmu->events[counter] = event; pmu->active_events++; hwc->idx = counter; @@ -485,7 +515,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) ddr_perf_event_start(event, flags); /* read trans, write trans, read beat */ - ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); + ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); return 0; } @@ -506,9 +536,11 @@ static void ddr_perf_event_del(struct perf_event *event, int flags) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); struct hw_perf_event *hwc = &event->hw; + int counter = hwc->idx; ddr_perf_event_stop(event, PERF_EF_UPDATE); + pmu->events[counter] = NULL; pmu->active_events--; hwc->idx = -1; } From patchwork Tue May 28 16:05:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13676244 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2058.outbound.protection.outlook.com [40.107.6.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49AC413B285 for ; Tue, 28 May 2024 07:57:50 +0000 (UTC) Authentication-Results: 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X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6a7f80a5-90c1-4516-6575-08dc7eebdd37 X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8822.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2024 07:57:47.5166 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cuiV2UrRQU+F3pU16HMjgmLkT5lau9MdqNawgWshoLM9YzuZ+ka5AcssB8RrkUTCGBCD+FLI8OJ+E0slst8xNQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB7229 This driver is initinally used to support imx93 Soc and now it's time to add support for imx95 Soc. However, some macro definitions and events are different on these two Socs. For preparing imx95 supports, this will refactor driver for imx93. Reviewed-by: Frank Li Signed-off-by: Xu Yang --- Changes in v4: - new patch Changes in v5: - use is_visible to hide unwanted attributes as suggested by Will Changes in v6: - improve imx93_ddr_perf_monitor_config() Changes in v7: - improve imx93_ddr_perf_monitor_config() as suggested by Frank Changes in v8: - adjust is_visable() as suggested by Frank Changes in v9: - add Rb tag Changes in v10: - no changes Changes in v11: - no changes --- drivers/perf/fsl_imx9_ddr_perf.c | 106 ++++++++++++++++++++----------- 1 file changed, 68 insertions(+), 38 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 15045fbfc685..d1c5495d5e48 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -11,14 +11,14 @@ #include /* Performance monitor configuration */ -#define PMCFG1 0x00 -#define PMCFG1_RD_TRANS_FILT_EN BIT(31) -#define PMCFG1_WR_TRANS_FILT_EN BIT(30) -#define PMCFG1_RD_BT_FILT_EN BIT(29) -#define PMCFG1_ID_MASK GENMASK(17, 0) +#define PMCFG1 0x00 +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31) +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30) +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0) -#define PMCFG2 0x04 -#define PMCFG2_ID GENMASK(17, 0) +#define PMCFG2 0x04 +#define MX93_PMCFG2_ID GENMASK(17, 0) /* Global control register affects all counters and takes priority over local control registers */ #define PMGC0 0x40 @@ -75,6 +75,11 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { .identifier = "imx93", }; +static inline bool is_imx93(struct ddr_pmu *pmu) +{ + return pmu->devtype_data == &imx93_devtype_data; +} + static const struct of_device_id imx_ddr_pmu_dt_ids[] = { {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data}, { /* sentinel */ } @@ -122,24 +127,37 @@ static const struct attribute_group ddr_perf_cpumask_attr_group = { .attrs = ddr_perf_cpumask_attrs, }; +struct imx9_pmu_events_attr { + struct device_attribute attr; + u64 id; + const void *devtype_data; +}; + static ssize_t ddr_pmu_event_show(struct device *dev, struct device_attribute *attr, char *page) { - struct perf_pmu_events_attr *pmu_attr; + struct imx9_pmu_events_attr *pmu_attr; - pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); + pmu_attr = container_of(attr, struct imx9_pmu_events_attr, attr); return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); } #define COUNTER_OFFSET_IN_EVENT 8 #define ID(counter, id) ((counter << COUNTER_OFFSET_IN_EVENT) | id) -#define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \ - (&((struct perf_pmu_events_attr[]) { \ +#define DDR_PMU_EVENT_ATTR_COMM(_name, _id, _data) \ + (&((struct imx9_pmu_events_attr[]) { \ { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\ - .id = _id, } \ + .id = _id, \ + .devtype_data = _data, } \ })[0].attr.attr) +#define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \ + DDR_PMU_EVENT_ATTR_COMM(_name, _id, NULL) + +#define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) \ + DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx93_devtype_data) + static struct attribute *ddr_perf_events_attrs[] = { /* counter0 cycles event */ IMX9_DDR_PMU_EVENT_ATTR(cycles, 0), @@ -185,7 +203,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)), IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), + IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/ /* counter3 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)), @@ -197,7 +215,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), + IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/ /* counter4 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)), @@ -209,7 +227,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), + IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/ /* counter5 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)), @@ -244,9 +262,29 @@ static struct attribute *ddr_perf_events_attrs[] = { NULL, }; +static umode_t +ddr_perf_events_attrs_is_visible(struct kobject *kobj, + struct attribute *attr, int unused) +{ + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); + struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); + struct imx9_pmu_events_attr *eattr; + + eattr = container_of(attr, typeof(*eattr), attr.attr); + + if (!eattr->devtype_data) + return attr->mode; + + if (eattr->devtype_data != ddr_pmu->devtype_data) + return 0; + + return attr->mode; +} + static const struct attribute_group ddr_perf_events_attr_group = { .name = "events", .attrs = ddr_perf_events_attrs, + .is_visible = ddr_perf_events_attrs_is_visible, }; PMU_FORMAT_ATTR(event, "config:0-7,16-23"); @@ -370,36 +408,28 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, } } -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, - int counter, int axi_id, int axi_mask) +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, + int counter, int axi_id, int axi_mask) { u32 pmcfg1, pmcfg2; + u32 mask[] = { MX93_PMCFG1_RD_TRANS_FILT_EN, + MX93_PMCFG1_WR_TRANS_FILT_EN, + MX93_PMCFG1_RD_BT_FILT_EN }; pmcfg1 = readl_relaxed(pmu->base + PMCFG1); - if (counter == 2 && event == 73) - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN; - else if (counter == 2 && event != 73) - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN; - - if (counter == 3 && event == 73) - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN; - else if (counter == 3 && event != 73) - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN; - - if (counter == 4 && event == 73) - pmcfg1 |= PMCFG1_RD_BT_FILT_EN; - else if (counter == 4 && event != 73) - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN; + if (counter >= 2 && counter <= 4) + pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] : + pmcfg1 & ~mask[counter - 2]; - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF); - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask); - writel(pmcfg1, pmu->base + PMCFG1); + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF); + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask); + writel_relaxed(pmcfg1, pmu->base + PMCFG1); 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This sequence is not correct for AXI filter events since the correct AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate. Reviewed-by: Frank Li Fixes: 55691f99d417 ("drivers/perf: imx_ddr: Add support for NXP i.MX9 SoC DDRC PMU driver") cc: Signed-off-by: Xu Yang --- Changes in v5: - new patch Changes in v6: - no changes Changes in v7: - no changes Changes in v8: - add fix tag Changes in v9: - add Rb tag Changes in v10: - no changes Changes in v11: - no changes --- drivers/perf/fsl_imx9_ddr_perf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index d1c5495d5e48..26144916dba7 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -541,12 +541,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) hwc->idx = counter; hwc->state |= PERF_HES_STOPPED; - if (flags & PERF_EF_START) - ddr_perf_event_start(event, flags); - /* read trans, write trans, read beat */ imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); + if (flags & PERF_EF_START) + ddr_perf_event_start(event, flags); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2SQwzGef1ctS11ZByG1er/50rxbDu6OHO9IWIiMc4kTmlThKbyA7Schbm8a6/4dZdD9vkypCYuxs8qP42EOVE/NuO0yTCIfxnMTjuo9Q9y11GGQ2UJ9HCTVRrn1V9rafj0ZnCsR7mbHixC1GJMsKlwSrtJST0GiMKiDiYp/ILMiZdO5VVh6fjg4d7CF2qf32HsJG7dRBbOyx8XvSeb27GjwLzD4XPCfNPuZXhBI9jinfC2XRPoKjiFVD62c2YoX6xRZkHkiQJQPP8I4HGG2EzuNv1LpARjdbyayl0p48eiATAgtIDREFqAlMnLwz0Fewlf2cbrW9Nc+HLr2P/i0v1yhTirW+8WNYQJB7Oi56oR/I/owiQdUVcs5v7P/1PEj55IZvwGmDQ7OG37gE5TwOf89pwMOFZdDXS84fmaroZJ8iAbQKb2ESKBe2KDY03rI/1AvS2RRlqPJEYPZg6UTvZ1fMKC31DEYT6wNtZoxLFJFLShfZAiD5547+e8XBmVoqby0k/Jz7QVSJz95tz7Qh0eRGBvepLkBLQAIcdRqB5Px/llOd41dtmQ/BawftEWDbjTzbQ3KIffmYHUlddcvNwgclTw2m+vg3PfoHCEixZ4D8/KNYvT/ArGxaECHSxuHWQwZ9Def1r9eGqQZ7ygTEYI6ZvpLKsIobzFkhTJ7JFxER+BvrORV4XFRV8mtJA2NQCAupr1P2OlBQr/lEMQchNbTV6HrNSipwVeRvFEWidRPUwI2iQndooN4ba010IZVK1O8oRuy2CWkqbMuT8pCoPfjhaLq12/MPTCFM2SRyf9EwBhuWOwZZwFmTvPkPQDu9A/suKUsy4ju/OYb+0Vm9xw6nrKjm3B80Jz813536PcbQ4gTyqY6A7+mwYF6rO/v15A1K3i8Bf9fA9vknCAhSQDBRB2d0aaF5hoGlAyEFGeXvQGowlIfR9y8xzEJCuPbnwbTJuanaX6Dp/2Te393Y0LF55L/ysxV9TgQEHALRQBK7dUA9GECzxwlEeboO2oZJf68v8C+mI+ZVHPYge9iuQuPLzbEZY4Dabo9cmfapdO/6nhOvwq0yvjk9ebDaD1U69Wm3tlNkUkYDU06EqaXrMzhEMTrOOoPl/0M6cKUGG45bsIr8RZLz/yQtEFseYxNxbkOXRct8/R5t6BGDSSUAbEfTms7qM8/oVwg/SCMpTDriyuVSkDG31mwlzhH+jzL3K+wqBS+LK9EX7xVwh40GLorHZmxQ/K6j74ef/PTmaz0nLpsDtM1C11xthQJXuhJkqDNp5pprg5A76gjvxkv42tvU/pGhBRHtcLelQdC2v+FbhqJKf/UThE4Azgm3yYv3KxXYV4SXxjODxNc6oOWXVEGXqRWedyVLnK0qvH0h0N1qsD3Q8w9ChmVFK9qgHBqSocNEMzjLPpb65c5nu4VS1JRC75YOFJJOr+P1T1nsU4Z1baLPnOK+pBkPDjaY/l3mHEVQMrhTdoUUyj+36ayGhLwTvhzxo3NucySpVxgI4+rp2fMHK4KQhItyZkyfRyGHcM74iqfQzveE/yhm+GWTTkqtaoqAg6+pZSf6/Exvc/7YOeqH8czdXz0GbXMTyOqb X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: cc87683c-0e39-4ba9-ae26-08dc7eebe6ee X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8822.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2024 07:58:04.2249 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: B3EBq/gMlm2D28/lnnZsZJczUZGPvBeWD0uG2pVYRXF4wdZ+EEoxKYjKE2K5ow3Ac2+cswqf4H5cYGDV4wVWtg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB7229 i.MX95 has a DDR PMU which is almostly same as i.MX93, it now supports read beat and write beat filter capabilities. This will add support for i.MX95 and enhance the driver to support specific filter handling for it. Usage: For read beat: ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt2,axi_mask=ID_MASK,axi_id=ID/ ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt1,axi_mask=ID_MASK,axi_id=ID/ ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,axi_mask=ID_MASK,axi_id=ID/ eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,axi_mask=0x00f,axi_id=0x00c/ For write beat: ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,axi_mask=ID_MASK,axi_id=ID/ eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,axi_mask=0x00f,axi_id=0x00c/ Reviewed-by: Frank Li Signed-off-by: Xu Yang --- Changes in v2: - put soc spefific axi filter events to drvdata according to Frank's suggestions. - adjust pmcfg axi_id and axi_mask config Changes in v3: - no changes Changes in v4: - only contain imx95 parts Changes in v5: - improve imx95_ddr_perf_monitor_config() - use write_relaxed to pair read_relaxed Changes in v6: - no changes Changes in v7: - no changes Changes in v8: - add definition IMX95_DDR_PMU_EVENT_ATTR Changes in v9: - add Rb tag Changes in v10: - no changes Changes in v11: - no changes --- drivers/perf/fsl_imx9_ddr_perf.c | 89 ++++++++++++++++++++++++++++++-- 1 file changed, 86 insertions(+), 3 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 26144916dba7..2077680ed39f 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -17,9 +17,19 @@ #define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) #define MX93_PMCFG1_ID_MASK GENMASK(17, 0) +#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31) +#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30) + #define PMCFG2 0x04 #define MX93_PMCFG2_ID GENMASK(17, 0) +#define PMCFG3 0x08 +#define PMCFG4 0x0C +#define PMCFG5 0x10 +#define PMCFG6 0x14 +#define MX95_PMCFG_ID_MASK GENMASK(9, 0) +#define MX95_PMCFG_ID GENMASK(25, 16) + /* Global control register affects all counters and takes priority over local control registers */ #define PMGC0 0x40 /* Global control register bits */ @@ -75,13 +85,23 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { .identifier = "imx93", }; +static const struct imx_ddr_devtype_data imx95_devtype_data = { + .identifier = "imx95", +}; + static inline bool is_imx93(struct ddr_pmu *pmu) { return pmu->devtype_data == &imx93_devtype_data; } +static inline bool is_imx95(struct ddr_pmu *pmu) +{ + return pmu->devtype_data == &imx95_devtype_data; +} + static const struct of_device_id imx_ddr_pmu_dt_ids[] = { - {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data}, + { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data }, + { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); @@ -158,6 +178,9 @@ static ssize_t ddr_pmu_event_show(struct device *dev, #define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) \ DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx93_devtype_data) +#define IMX95_DDR_PMU_EVENT_ATTR(_name, _id) \ + DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx95_devtype_data) + static struct attribute *ddr_perf_events_attrs[] = { /* counter0 cycles event */ IMX9_DDR_PMU_EVENT_ATTR(cycles, 0), @@ -204,6 +227,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)), IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/ + IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, ID(2, 73)), /* imx95 specific*/ /* counter3 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)), @@ -216,6 +240,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)), IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/ + IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, ID(3, 73)), /* imx95 specific*/ /* counter4 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)), @@ -228,6 +253,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)), IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/ + IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, ID(4, 73)), /* imx95 specific*/ /* counter5 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)), @@ -239,6 +265,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, ID(5, 70)), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, ID(5, 71)), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, ID(5, 72)), + IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, ID(5, 73)), /* imx95 specific*/ /* counter6 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, ID(6, 64)), @@ -432,6 +459,57 @@ static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, writel_relaxed(pmcfg2, pmu->base + PMCFG2); } +static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, + int counter, int axi_id, int axi_mask) +{ + u32 pmcfg1, pmcfg, offset = 0; + + pmcfg1 = readl_relaxed(pmu->base + PMCFG1); + + if (event == 73) { + switch (counter) { + case 2: + pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN; + offset = PMCFG3; + break; + case 3: + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG4; + break; + case 4: + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG5; + break; + case 5: + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG6; + break; + } + } else { + switch (counter) { + case 2: + pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN; + break; + case 3: + case 4: + case 5: + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; + break; + } + } + + writel_relaxed(pmcfg1, pmu->base + PMCFG1); + + if (offset) { + pmcfg = readl_relaxed(pmu->base + offset); + pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) | + FIELD_PREP(MX95_PMCFG_ID, 0x3FF)); + pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, axi_mask) | + FIELD_PREP(MX95_PMCFG_ID, axi_id)); + writel_relaxed(pmcfg, pmu->base + offset); + } +} + static void ddr_perf_event_update(struct perf_event *event) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); @@ -541,8 +619,13 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) hwc->idx = counter; hwc->state |= PERF_HES_STOPPED; - /* read trans, write trans, read beat */ - imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); + if (is_imx93(pmu)) + /* read trans, write trans, read beat */ + imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); + + if (is_imx95(pmu)) + /* write beat, read beat2, read beat1, read beat */ + imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); if (flags & PERF_EF_START) ddr_perf_event_start(event, flags); From patchwork Tue May 28 16:05:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13676247 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-vi1eur04on2078.outbound.protection.outlook.com [40.107.8.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 587B013C8E4 for ; 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Reviewed-by: Frank Li Signed-off-by: Xu Yang --- Changes in v7: - new patch Changes in v8: - no changes Changes in v9: - add Rb tag Changes in v10: - no changes Changes in v11: - no changes --- .../arch/arm64/freescale/imx93/sys/ddrc.json | 9 +++++++ .../arm64/freescale/imx93/sys/metrics.json | 26 +++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json new file mode 100644 index 000000000000..eeeae4d49fce --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json @@ -0,0 +1,9 @@ +[ + { + "BriefDescription": "ddr cycles event", + "EventCode": "0x00", + "EventName": "imx93_ddr.cycles", + "Unit": "imx9_ddr", + "Compat": "imx93" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json new file mode 100644 index 000000000000..4d2454ca1259 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json @@ -0,0 +1,26 @@ +[ + { + "BriefDescription": "bandwidth usage for lpddr4x evk board", + "MetricName": "imx93_bandwidth_usage.lpddr4x", + "MetricExpr": "(((( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8 ) + (( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32 )) / duration_time) / (3733 * 1000000 * 2)", + "ScaleUnit": "1e2%", + "Unit": "imx9_ddr", + "Compat": "imx93" + }, + { + "BriefDescription": "bytes all masters read from ddr", + "MetricName": "imx93_ddr_read.all", + "MetricExpr": "( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx93" + }, + { + "BriefDescription": "bytes all masters write to ddr", + "MetricName": "imx93_ddr_write.all", + "MetricExpr": "( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx93" + } +] From patchwork Tue May 28 16:05:23 2024 Content-Type: text/plain; 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b=odwupChyo7+LCRyagLUY98nH+rxDkn3jKVuXOkX13AJWRV0msbIhqd0KVEf9GucgRAg2LWtAeFM/jiEI9xU1pFwbqfciynSv6cTzJVmWzTYRK1CKp3fh7rsVPoH+yT6tGcyh6ayu8c/aDkmHsHTJY6oOPXGQ6XMH2xldNjCmHDo= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by AS5PR04MB10019.eurprd04.prod.outlook.com (2603:10a6:20b:67f::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.30; Tue, 28 May 2024 07:58:20 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::4e24:c2c7:bd58:c5c7]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::4e24:c2c7:bd58:c5c7%4]) with mapi id 15.20.7611.025; Tue, 28 May 2024 07:58:20 +0000 From: Xu Yang To: frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v11 8/8] perf vendor events arm64:: Add i.MX95 DDR Performance Monitor metrics Date: Wed, 29 May 2024 00:05:23 +0800 Message-Id: <20240528160523.1695953-8-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240528160523.1695953-1-xu.yang_2@nxp.com> References: <20240528160523.1695953-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI1PR02CA0027.apcprd02.prod.outlook.com (2603:1096:4:1f4::18) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS5PR04MB10019:EE_ X-MS-Office365-Filtering-Correlation-Id: d7767713-6e22-454e-ae9a-08dc7eebf083 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|1800799015|52116005|7416005|376005|38350700005|921011; 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Reviewed-by: John Garry Reviewed-by: Ian Rogers Reviewed-by: Frank Li Signed-off-by: Xu Yang --- Changes in v2: - fix wrong AXI_MASK setting - remove unnecessary metrics - add bandwidth_usage, camera_all, disp_all metrics Changes in v3: - no changes Changes in v4: - add Reviewed-by tag Changes in v5: - fix typo Changes in v6: - remove "counter=X" from each metric Changes in v7: - add RB tag Changes in v8: - no changes Changes in v9: - no changes Changes in v10: - no changes Changes in v11: - correct display metrics --- .../arch/arm64/freescale/imx95/sys/ddrc.json | 9 + .../arm64/freescale/imx95/sys/metrics.json | 874 ++++++++++++++++++ tools/perf/pmu-events/jevents.py | 1 + 3 files changed, 884 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json new file mode 100644 index 000000000000..4dc9d2968bdc --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json @@ -0,0 +1,9 @@ +[ + { + "BriefDescription": "ddr cycles event", + "EventCode": "0x00", + "EventName": "imx95_ddr.cycles", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json new file mode 100644 index 000000000000..126ce980f6f2 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json @@ -0,0 +1,874 @@ +[ + { + "BriefDescription": "bandwidth usage for lpddr5 evk board", + "MetricName": "imx95_bandwidth_usage.lpddr5", + "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * 4)", + "ScaleUnit": "1e2%", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all masters read from ddr", + "MetricName": "imx95_ddr_read.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all masters write to ddr", + "MetricName": "imx95_ddr_write.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 read from ddr", + "MetricName": "imx95_ddr_read.a55_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 write to ddr (part1)", + "MetricName": "imx95_ddr_write.a55_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 write to ddr (part2)", + "MetricName": "imx95_ddr_write.a55_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 read from ddr", + "MetricName": "imx95_ddr_read.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 write to ddr", + "MetricName": "imx95_ddr_write.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 read from ddr", + "MetricName": "imx95_ddr_read.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 write to ddr", + "MetricName": "imx95_ddr_write.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 read from ddr", + "MetricName": "imx95_ddr_read.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 write to ddr", + "MetricName": "imx95_ddr_write.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 read from ddr", + "MetricName": "imx95_ddr_read.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 write to ddr", + "MetricName": "imx95_ddr_write.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 4 read from ddr", + "MetricName": "imx95_ddr_read.a55_4", + "MetricExpr": "( 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"MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of camera edma read from ddr", + "MetricName": "imx95_ddr_read.camera_edma", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of camera edma write to ddr", + "MetricName": "imx95_ddr_write.camera_edma", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd read from ddr", + "MetricName": "imx95_ddr_read.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd write to ddr", + "MetricName": "imx95_ddr_write.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules read from ddr", + "MetricName": "imx95_ddr_read.camera_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part1)", + "MetricName": "imx95_ddr_write.camera_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part2)", + "MetricName": "imx95_ddr_write.camera_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part3)", + "MetricName": "imx95_ddr_write.camera_all_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer0 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x2f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer0 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer1 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer1 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer2 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x310@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer2 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x310@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer3 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x320@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer3 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x320@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer4 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x330@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer4 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x330@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer5 read from ddr", + "MetricName": "imx95_ddr_read.disp_layer5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x340@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display layer5 write to ddr", + "MetricName": "imx95_ddr_write.disp_layer5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x340@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter read from ddr", + "MetricName": "imx95_ddr_read.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x350@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter write to ddr", + "MetricName": "imx95_ddr_write.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x350@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer read from ddr", + "MetricName": "imx95_ddr_read.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x360@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer write to ddr", + "MetricName": "imx95_ddr_write.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x360@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules read from ddr", + "MetricName": "imx95_ddr_read.disp_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules write to ddr (part1)", + "MetricName": "imx95_ddr_write.disp_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules write to ddr (part2)", + "MetricName": "imx95_ddr_write.disp_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index e42efc16723e..ac9b7ca41856 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -284,6 +284,7 @@ class JsonEvent: 'hisi_sccl,hha': 'hisi_sccl,hha', 'hisi_sccl,l3c': 'hisi_sccl,l3c', 'imx8_ddr': 'imx8_ddr', + 'imx9_ddr': 'imx9_ddr', 'L3PMC': 'amd_l3', 'DFPMC': 'amd_df', 'UMCPMC': 'amd_umc',