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[87.16.233.11]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626cda60bdsm615456466b.207.2024.05.28.06.32.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 06:32:58 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v4 1/4] dt-bindings: arm: bcm: Add BCM2712 SoC support Date: Tue, 28 May 2024 15:32:38 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The BCM2712 SoC is found on Raspberry Pi 5. Add compatible string to acknowledge its new chipset. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 162a39dab218..e4ff71f006b8 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -23,6 +23,12 @@ properties: - raspberrypi,4-model-b - const: brcm,bcm2711 + - description: BCM2712 based Boards + items: + - enum: + - raspberrypi,5-model-b + - const: brcm,bcm2712 + - description: BCM2835 based Boards items: - enum: From patchwork Tue May 28 13:32:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13676738 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0305416F843 for ; Tue, 28 May 2024 13:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716903183; cv=none; b=MDXx3m/Oq8PhVvpiLYmIp8Fft8QmANdln2pdWTvaI7nJmpuJ+sxzAZZaxh5ptiJnqyI1+ehD1Ej1WZFB3uB/1oplqGx9NGHJYMT83B//uQleu+cxCOK9FHO2a5kH1VfexlrZSigtThOTO9+EPvq7YcIzWCbuM/nhCFKcDG+lXaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716903183; c=relaxed/simple; bh=IXiic31ZGn5xiaoNZvGY5NBDRfFO2Bu6aMdiRK86lmc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oviIiTstmqRu44IUs4pzkqo8a9Wz5O5V8qg0o0sp1zI2WoI/MEq79T1yhW5DJW7Ul6ixzXgvzrTlXs2qtDu1rQcQD+4j4LCgJlqKeqaWf1Jp3/jvpZcWKFSN/6/1FesHPWimOe487HSAjafiDLBa9E8k898U9k1yc2w8Y48DP14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=XNwj5Bl/; arc=none smtp.client-ip=209.85.208.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="XNwj5Bl/" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-57869599ed5so1011133a12.2 for ; Tue, 28 May 2024 06:33:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1716903179; x=1717507979; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=msFCFwiwqcyL6ZO/+kBlzRSH/Up7idI6elTyfBuDv4M=; b=XNwj5Bl/NMQVIhWsqAZV3T3uX1o1/TSuCjHmc60VpZQTVVg6j7/xA07yq6a6lfRXex 97u8/U22pCWr1vCW4rt4EjwophrblLpOUWoLOorhzfm1F8FxcpNH77NKTtxShy205h2h rfUflg5OYjgG8b30YCletaLv7eUY1pYcWPxixWQJMX9MKtPTLewpOsRjg8LANTdnaxrL mmKyGXwEyNHEtzsLGEpSeg6M9YlXsNXojlYboY0qUKRMc6GONJBmOc0wMNYVzubx6ieq ih4hfEATOIQY7pj54mK0Y1l4D1EQXrh1UmaCbhnsfGeYZnPUbGBuHPsID9yx3EqTxyFl +6WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716903179; x=1717507979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=msFCFwiwqcyL6ZO/+kBlzRSH/Up7idI6elTyfBuDv4M=; b=ZT6T0ro+E92P+qhKUKvdu02wAZUNHEc8wDP2c9BwTiceu2+y70aD89bVvrm6Hfqljr dJtDFWNGGYpII5512jSNyrx5qklPJRmj+Gb/BrmxA2R2h8opMwAmrAgE84lUc0SjWes4 uexlRuKaWU5g/Cwowa5yhG+msEW1gsiOMJTZBigISqhm82qFAJnuHCzwBfTY0N8uxr2U aOdymscBTO/h3u3kEPijC6rlUBZ1NAAkvky1PfE0VCSWPiv2WzOZLzHAdft8cxEnVdWt PxkynJS1gWhx2RZBqNDnhJ6bvOdVuRvIpnHbWM8q/Kh5m7a+yDQ0thUTlZqkuCxZaHTi Nbtg== X-Forwarded-Encrypted: i=1; AJvYcCVLCcuQjupznh84A0gAL11jtYPIm4N1I6vEyqLS3r2xEFsnUtCXF3UWtNfBJf+aK683v/opp5oBkCWSsK0Syngsuk67bvxNI64y X-Gm-Message-State: AOJu0Yx0xmPHIpsInZe+gTWpqW/GrBLLUcXXDL/pB2mDm3opOKY3zXgE i7+KMkSUw1dMQYWJnDGVaxKPC/XBGdljxXkpQVnqZKOS8EpTSNez+6lRXAmFK20= X-Google-Smtp-Source: AGHT+IHtQeY8ahqqVRpLNRs6x2IiovKEZoNZkln4ViArMLwhSpDlpLCjMNDDdGHS+xJ3s0TUu2LfjQ== X-Received: by 2002:a50:9343:0:b0:579:e7c5:1001 with SMTP id 4fb4d7f45d1cf-579e7c51a1cmr2278257a12.23.1716903179511; Tue, 28 May 2024 06:32:59 -0700 (PDT) Received: from localhost (host-87-16-233-11.retail.telecomitalia.it. [87.16.233.11]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5785241214dsm7320265a12.55.2024.05.28.06.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 06:32:59 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v4 2/4] dt-bindings: mmc: Add support for BCM2712 SD host controller Date: Tue, 28 May 2024 15:32:39 +0200 Message-ID: <0f263886c0622f43d3a2f4cccaebae0c39ba1bc5.1716899600.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The BCM2712 has an SDHCI capable host interface similar to the one found in other STB chipsets. Add the relevant compatible string. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index cbd3d6c6c77f..eee6be7a7867 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -20,6 +20,7 @@ properties: - const: brcm,sdhci-brcmstb - items: - enum: + - brcm,bcm2712-sdhci - brcm,bcm74165b0-sdhci - brcm,bcm7445-sdhci - brcm,bcm7425-sdhci From patchwork Tue May 28 13:32:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13676739 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E35D16F8FA for ; Tue, 28 May 2024 13:33:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716903184; cv=none; b=nTuoLqnef2TfnoPfzvPUll1DZxWsuOMUm2zQBq6Ar9n9Re9wdTiISEmxRgFxfO6vMy8WNBCyRDBsiQ0pLRjDvC5wTLXo/vGkI7IL8AHZwN6ada23/9aiQtfxFktIvvcRws/I6l4XfJ4hDhkIZABx21FnvLt45JUoBTYHSQkL+NQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716903184; c=relaxed/simple; bh=xCeqwsoTmryqe4S0XXkbxSFO9YkPJ05veZ6sTcrEhzE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eZmVPQoexLoI6DEgnuJqFGM1UQvaLeRYUhk7N8X7vmQiSMru945rQavfSoukW/GRdoT7xOLiiHDozcL8ob3KLm7efeqIRvBwb4T26jhFx8x8d8YIGczbcui+Z2USW7gQpuH/BSNDR1X63q6XAADqjfwPngApDmnaOzHlPZcpnOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=WvY0qC+M; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="WvY0qC+M" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a620a28e95cso92401766b.3 for ; Tue, 28 May 2024 06:33:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1716903181; x=1717507981; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vAttVQb286WgzeBs4n1LQU/SvEUwJV3m31Mwzag2RvE=; b=WvY0qC+MEModBkBo5Lp0r0MvZ7GM5P2lHYDm9Iaq131lPP8+ED6gIi7Ffkkyy7wDzN oVuqqESQotIAZpg7/WQhgODO4/SJ/WCVhIfP/1KjdVCsuuSMD4Ndy57nVY/TA/96jTas kUiY/B4J4xjb2Jym+5M4VIlyKkdF8KtyMceM9U5tNDSlqGV6fML9Wg9SlYUXoa2tVfPA /RqHy95I6i3KvzwRUVETdHKd1UGRRD8751QYMIYUBjtcvfDIWq8A2jp7RmbbKqKvLwaP UyjzOMkan7cvUNoDPUuvULin45mxbFk3yhIam9KBka1Ci5j7EMiEcJ3RlJXlvewFY/PF wudA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716903181; x=1717507981; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vAttVQb286WgzeBs4n1LQU/SvEUwJV3m31Mwzag2RvE=; b=X4sYsmgg8mCi2BjqYym0XzmxR50pn6EtOZfVa1FaRidryzOJwcVVonojvKma/pA6e6 m/WVfhgJgGXD3NysZYgt9C5UwGUPOH4rKhOMplsdaY12O9nD+WZnXbDjbYT+1Oksu8AY GUMDaAfhTaAk9ey7bxRMyuNfFAUlCbnAQjag5tIt3jbPzlrlbBnHq16p0YRrB//ZF2V9 XjAiwQkYTjJbVFt5e9LOwzUjhk+ILgYP4Ay12RBNNsLx0fZFdF3Rw55SEOEYfPEgHOZd MMi+iEkiHN92aU4Ej9rWFjtV7PcH9xmaurZ4B+Kvk9XvuIahy+XjpAGrk+UwK+jTOVjQ 3ulQ== X-Forwarded-Encrypted: i=1; AJvYcCUdgHxUC3LUACPbguG30a/79DQOWrlR6EuHZxMIbIoQ/u95k/Tj1swKAUbAIK0hYHXuUwn0itWaYjPBTAMXJCEEm39pT/wq4LPk X-Gm-Message-State: AOJu0Yw20infVDBXGPPDO67PLJcZxq16V+RwHZ4eTRDI7TQ4t+sS47Ec +BUQWfDdirzzSP0Jw2cC3ETtbVnJdmbBGtx9xKx1K6MbdoBr3ZTgITHt3a5IhRg= X-Google-Smtp-Source: AGHT+IGM94/l7QnF+H/+9xD5yqLVDdx1tOWfh2zBVOOVaQvsHCnpoeegLHgLc4A1XrQmSWUj79Za8w== X-Received: by 2002:a17:906:5a47:b0:a62:2c5f:5a64 with SMTP id a640c23a62f3a-a626407bfacmr890996866b.15.1716903180761; Tue, 28 May 2024 06:33:00 -0700 (PDT) Received: from localhost (host-87-16-233-11.retail.telecomitalia.it. [87.16.233.11]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a634b0ec497sm57631166b.116.2024.05.28.06.33.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 06:33:00 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v4 3/4] mmc: sdhci-brcmstb: Add BCM2712 support Date: Tue, 28 May 2024 15:32:40 +0200 Message-ID: <4e8fc54e87447bae7db58636a1c87e5d8baeb012.1716899600.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Broadcom BCM2712 SoC has an SDHCI card controller using the SDIO CFG register block present on other STB chips. Add support for BCM2712 SD capabilities of this chipset. The silicon is SD Express capable but this driver port does not currently include that feature yet. Based on downstream driver by raspberry foundation maintained kernel. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 60 ++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 9053526fa212..0d9c42d41376 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -30,6 +30,21 @@ #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 +#define SDIO_CFG_CQ_CAPABILITY 0x4c +#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) + +#define SDIO_CFG_CTRL 0x0 +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) + +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) + +#define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) +/* Select all SD UHS type I SDR speed above 50MB/s */ +#define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; unsigned int flags; @@ -38,6 +53,7 @@ struct sdhci_brcmstb_priv { }; struct brcmstb_match_priv { + void (*cfginit)(struct sdhci_host *host); void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); struct sdhci_ops *ops; const unsigned int flags; @@ -168,6 +184,33 @@ static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host); + u32 reg, base_clk_mhz; + + /* + * If we support a speed that requires tuning, + * then select the delay line PHY as the clock source. + */ + if ((host->mmc->caps & MMC_CAP_UHS_I_SDR_MASK) || (host->mmc->caps2 & MMC_CAP_HSE_MASK)) { + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE; + reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + } + + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { + /* Force presence */ + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; + reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + } +} + static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -200,6 +243,14 @@ static struct sdhci_ops sdhci_brcmstb_ops = { .set_uhs_signaling = sdhci_set_uhs_signaling, }; +static struct sdhci_ops sdhci_brcmstb_ops_2712 = { + .set_clock = sdhci_set_clock, + .set_power = sdhci_set_power_and_bus_voltage, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + static struct sdhci_ops sdhci_brcmstb_ops_7216 = { .set_clock = sdhci_brcmstb_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -214,6 +265,11 @@ static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = { .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, }; +static const struct brcmstb_match_priv match_priv_2712 = { + .cfginit = sdhci_brcmstb_cfginit_2712, + .ops = &sdhci_brcmstb_ops_2712, +}; + static struct brcmstb_match_priv match_priv_7425 = { .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, @@ -238,6 +294,7 @@ static struct brcmstb_match_priv match_priv_74165b0 = { }; static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { + { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 }, { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, @@ -370,6 +427,9 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) (host->mmc->caps2 & MMC_CAP2_HS400_ES)) host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; + if (match_priv->cfginit) + match_priv->cfginit(host); + /* * Supply the existing CAPS, but clear the UHS modes. This * will allow these modes to be specified by device tree From patchwork Tue May 28 13:32:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13676740 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C1DD16F91F for ; Tue, 28 May 2024 13:33:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716903185; cv=none; b=u87sYrptSpECtopDd+6kyTiQ0tO/1BWnG8x3u6K/k1MgUdM1ghNTCN4YHdqBT677p+VLUh7gCR9DIR1J+CSWLEgsuurkPzJme8yuzPj6fg78biyT1Unvt2IVVUdCcnpjd+80r9xWfFelm3duO1jgN4eVyT/DX1sMkzXmgWAtERo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716903185; c=relaxed/simple; bh=uXU5QfaH5qlqXoA4DPbAYFEaIVRvOPrHJFlST/zPwXU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iHcOmXFRonGpDgkrGraAJnlqn8WtfEkuPfiK7EvT/XN0M8BFMt2KvhGovVzN1aiKdDB/5ICH4UHNY/TbUG+T49CbyYKeVycXW92HrNsN+QhYz6EyhwJMzkOH1KIzG2Ht7zCa3lZolaKTgb0HCKgy6Zey52UMiQhc0vOHRKwcrLI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=FfohnRIU; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="FfohnRIU" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-572c65cea55so1507175a12.0 for ; Tue, 28 May 2024 06:33:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1716903182; x=1717507982; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P80V1HVAEHdvXLPhNcgfiUJ7gY/EImR+9FLANrvqAlM=; b=FfohnRIUzn1ntfyFKrSfHK9GaWyK8R//hk5wkMsxD3T45IqugRmBTbixlix8JAnv4d +OlgRyDCn3+NsbVA96aL7afK559sgsqcml2vaSADlB3qwRifniJeENCLC7S5sP+zcwKD +Md6+4QxwujmxbNGZ6UL1PHuk29VDyWN8EkAXV+nVCvxj101wlm3CeAfGUwu59hUCZ1+ QlVGaa7FR4+IwYQMwP/evod4pNJatmGij1I9xWoTuhkLb9tI2Sqnt/qBsjvX20/ovskl dzpPYRjJ6fUxp5rl5SPp/PeMTbFZGeCdQZXBmkGNpPhfJAYh8mtMiPlXKNu3yIQU2UBp 8oVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716903182; x=1717507982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P80V1HVAEHdvXLPhNcgfiUJ7gY/EImR+9FLANrvqAlM=; b=FJ1y6uFdBSC1xdTL+vHnUMMDpoYVHcYvMBlRLMqhlW+u7TVfipXZxVaPwO7ti3kVFY FWuVtdoXc+qsduh2ev+OlhrllWomlHr6EiyYPIS5zJcb9uh+nPbDTTHPb9+qp+ASWfpo ShF158fC2/9wgiXzrOOr/AtR750vGHPsdMCvynZvwKvXRQtiN+7argLtErQjHCj/h1Md h2v3o8zGL3j0zVQbfn+TWy7VfxP1SgotRFpL3aR+PyQGcdrh3sZ0qixL2lJJcXxBDFpW uztJvhcEzGoCQa71KWcLzY7OomOhnxOcFFSx2nLhY5jStxoIWa+6xgEfgRWZiXx2kh+o B+fg== X-Forwarded-Encrypted: i=1; AJvYcCWQczAbpLltEnUe+DzdvP0sU90/M7qbqKDtM1G361H/yok3PJlmZi8I6Zf6r8z/r7mtyfrskvtaKh4C3xEcIQmUmpbq0qaJZptx X-Gm-Message-State: AOJu0YzOsewuZTZ/b+rYHkZZp0LQ/q59UO51DrzB8Vl7jP6Ba56KZPmd UJR4a6Nae9pNT98RLlyw0QwuaX7LhYNSoIOejdAHZpQcbj36hybx6nTGp+KTgbg= X-Google-Smtp-Source: AGHT+IGELtEbebGcHQWaOiwWRS69S906246YVwWPZzjiKGmcQHsU1k3N+kQqdUX11OL0A0zojEZdUA== X-Received: by 2002:a05:6402:b0d:b0:579:e690:8349 with SMTP id 4fb4d7f45d1cf-579e6908e1amr2747855a12.15.1716903181893; Tue, 28 May 2024 06:33:01 -0700 (PDT) Received: from localhost (host-87-16-233-11.retail.telecomitalia.it. [87.16.233.11]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-579c2026406sm4399948a12.37.2024.05.28.06.33.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 May 2024 06:33:01 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v4 4/4] arm64: dts: broadcom: Add support for BCM2712 Date: Tue, 28 May 2024 15:32:41 +0200 Message-ID: <8dd6997394a01317747ca11b4779f586752b4947.1716899600.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The BCM2712 SoC family can be found on Raspberry Pi 5. Add minimal SoC and board (Rpi5 specific) dts file to be able to boot from SD card and use console on debug UART. Signed-off-by: Andrea della Porta --- arch/arm64/boot/dts/broadcom/Makefile | 1 + .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 64 ++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 292 ++++++++++++++++++ 3 files changed, 357 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 8b4591ddd27c..92565e9781ad 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -6,6 +6,7 @@ DTC_FLAGS := -@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ + bcm2712-rpi-5-b.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts new file mode 100644 index 000000000000..2bdbb6780242 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include +#include "bcm2712.dtsi" + +/ { + compatible = "raspberrypi,5-model-b", "brcm,bcm2712"; + model = "Raspberry Pi 5"; + + aliases { + serial10 = &uart10; + }; + + chosen: chosen { + stdout-path = "serial10:115200n8"; + }; + + /* Will be filled by the bootloader */ + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x28000000>; + }; + + sd_io_1v8_reg: sd-io-1v8-reg { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>; + states = <1800000 1>, + <3300000 0>; + }; + + sd_vcc_reg: sd-vcc-reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector + * labeled "UART", i.e. the interface with the system console. + */ +&uart10 { + status = "okay"; +}; + +/* SDIO1 is used to drive the SD card */ +&sdio1 { + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi new file mode 100644 index 000000000000..71b0fa6c9594 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +#include + +/ { + compatible = "brcm,bcm2712"; + + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gicv2>; + + axi: axi@1000000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>; + + sdio1: mmc@1000fff000 { + compatible = "brcm,bcm2712-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x10 0x00fff000 0x0 0x260>, + <0x10 0x00fff400 0x0 0x200>; + reg-names = "host", "cfg"; + interrupts = ; + clocks = <&clk_emmc2>; + clock-names = "sw_sdio"; + mmc-ddr-3_3v; + }; + + gicv2: interrupt-controller@107fff9000 { + interrupt-controller; + #interrupt-cells = <3>; + compatible = "arm,gic-400"; + reg = <0x10 0x7fff9000 0x0 0x1000>, + <0x10 0x7fffa000 0x0 0x2000>, + <0x10 0x7fffc000 0x0 0x2000>, + <0x10 0x7fffe000 0x0 0x2000>; + }; + }; + + clocks { + /* The oscillator is the root of the clock tree. */ + clk_osc: clk-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc"; + clock-frequency = <54000000>; + }; + + clk_vpu: clk-vpu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <750000000>; + clock-output-names = "vpu-clock"; + }; + + clk_uart: clk-uart { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <9216000>; + clock-output-names = "uart-clock"; + }; + + clk_emmc2: clk-emmc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + clock-output-names = "emmc2-clock"; + }; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* Source for L1 d/i cache-line-size, cache-sets, cache-size + * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en + * Source for L2 cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en + * and for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 + */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x000>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l0>; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x100>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l1>; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x200>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l2>; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x300>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l3>; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + /* Source for cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en + * Source for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 + */ + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set + cache-level = <3>; + cache-unified; + }; + }; + + psci { + method = "smc"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; + }; + + rmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf@0 { + reg = <0x0 0x0 0x0 0x80000>; + no-map; + }; + + cma: linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; + }; + }; + + soc: soc@107c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x7c000000 0x10 0x7c000000 0x04000000>; + /* Emulate a contiguous 30-bit address range for DMA */ + dma-ranges = <0xc0000000 0x00 0x00000000 0x40000000>, + <0x7c000000 0x10 0x7c000000 0x04000000>; + + system_timer: timer@7c003000 { + compatible = "brcm,bcm2835-system-timer"; + reg = <0x7c003000 0x1000>; + interrupts = , + , + , + ; + clock-frequency = <1000000>; + }; + + mailbox: mailbox@7c013880 { + compatible = "brcm,bcm2835-mbox"; + reg = <0x7c013880 0x40>; + interrupts = ; + #mbox-cells = <0>; + }; + + local_intc: local-intc@7cd00000 { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x7cd00000 0x100>; + }; + + uart10: serial@7d001000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7d001000 0x200>; + interrupts = ; + clocks = <&clk_uart>, <&clk_vpu>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + interrupt-controller@7d517000 { + compatible = "brcm,bcm7271-l2-intc"; + reg = <0x7d517000 0x10>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gio_aon: gpio@7d517c00 { + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg = <0x7d517c00 0x40>; + gpio-controller; + #gpio-cells = <2>; + // Don't use GIO_AON as an interrupt controller because it will + // clash with the firmware monitoring the PMIC interrupt via the VPU. + brcm,gpio-bank-widths = <17 6>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; +};