From patchwork Tue May 28 22:56:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13677526 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 264BB13E8B5 for ; Tue, 28 May 2024 22:56:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716937007; cv=none; b=RecILO0yd5eOHb5VZ4UjN6yZD6ZyIBC4BwMJKpPUnzVZTxz8Je4aHyCRIxU8Fky4UTDJ/uptU/f8QMkNcAMWjqwtQXfZY2jt2lGtyNN/0bDQvZ/Vha2yO5KJbKpli2EdxtqfGRAj9ko7d4PL4W69SS8hYWccG/TBhXwEUPvgkT0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716937007; c=relaxed/simple; bh=mLKZ4Tk6OaRbmpp0CDtq7YLjSHV+nhJ+kV4iqYSkBW4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g3af8A6goFOFcMWUor4nyQlRAyz6DxZmrN+FuqvGh1PPInCyXWLCd/nzZh/ING5a48NHJEAKyahoORjeBWdGeDEILWWdp2wg/KRWsWoRZfVNYvWc0Aqkc9yMU/dGbNXzdo4CLgXUlKYsyD0hKkwpJZHv4Z2j6lKCRlUNOXuyn8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=xBWDYjzI; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="xBWDYjzI" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id C5B872C02E0; Wed, 29 May 2024 10:56:42 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1716937002; bh=BRccYZsVdGxDK04PwUo4q3c1Pp+x2GNlfA7P/Dp31d8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xBWDYjzIDFZMOkbEE+JejTtA2GMnPkC1g4jvrx4r+h1bWZhNjMEMdxofXrAusgfWO C52KaylEtX19leQ/ZJWqh1CNxHUXdHQ/3aB3oPaoEZJsMjffhHdhlj6ZINf+UaejFt 7rttalJ7j8z/Fov2/YO9Sg+XYVKfzGMk3PVvA+KqaU2kWM17LTznBYJjY4qA50s6oT bf8U5u/TSGsEM22nmJMczKG6zwlPDSl1p9QE7/nG+V+SQfp+20Nx16QTiPri20Wk2A hgm1cSo/3BRvSvRLX1nMsWLWM4ZiZvfK6S7OWsD92+UjSuHWRoo32IYfUOmVQzhJds aFukd/Hs5Qt9A== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Wed, 29 May 2024 10:56:42 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A8DC913EE6D; Wed, 29 May 2024 10:56:42 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A47A7280048; Wed, 29 May 2024 10:56:42 +1200 (NZST) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ukleinek@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Chris Packham Subject: [PATCH v4 1/3] dt-bindings: hwmon: Add adt7475 fan/pwm properties Date: Wed, 29 May 2024 10:56:36 +1200 Message-ID: <20240528225638.1211676-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528225638.1211676-1-chris.packham@alliedtelesis.co.nz> References: <20240528225638.1211676-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=F9L0dbhN c=1 sm=1 tr=0 ts=6656612a a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=TpHVaj0NuXgA:10 a=nd0hpPEdzzsPhCuWCasA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add fan child nodes that allow describing the connections for the ADT7475 to the fans it controls. This also allows setting some initial values for the pwm duty cycle and frequency. Signed-off-by: Chris Packham --- Notes: I realise there is still some discussion about how to express the frequency and duty cycle. I have a personal preference for using hertz for the frequency and 0-255 for the duty cycle but if the consensus is to express these things some other way I'm fine with doing some math. Changes in v4: - 0 is not a valid frequency value Changes in v3: - Use the pwm provider/consumer bindings Changes in v2: - Document 0 as a valid value (leaves hardware as-is) .../devicetree/bindings/hwmon/adt7475.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/hwmon/adt7475.yaml b/Documentation/devicetree/bindings/hwmon/adt7475.yaml index 051c976ab711..bfef4c803bf7 100644 --- a/Documentation/devicetree/bindings/hwmon/adt7475.yaml +++ b/Documentation/devicetree/bindings/hwmon/adt7475.yaml @@ -51,6 +51,15 @@ properties: enum: [0, 1] default: 1 + "#pwm-cells": + const: 4 + description: | + Number of cells in a PWM specifier. + - 0: The pwm channel + - 1: The pwm frequency in hertz - 11, 14, 22, 29, 35, 44, 58, 88, 22500 + - 2: PWM flags 0 or PWM_POLARITY_INVERTED + - 3: The default pwm duty cycle - 0-255 + patternProperties: "^adi,bypass-attenuator-in[0-4]$": description: | @@ -81,6 +90,10 @@ patternProperties: - smbalert# - gpio + "^fan-[0-9]+$": + $ref: fan-common.yaml# + unevaluatedProperties: false + required: - compatible - reg @@ -89,11 +102,12 @@ additionalProperties: false examples: - | + #include i2c { #address-cells = <1>; #size-cells = <0>; - hwmon@2e { + pwm: hwmon@2e { compatible = "adi,adt7476"; reg = <0x2e>; adi,bypass-attenuator-in0 = <1>; @@ -101,5 +115,14 @@ examples: adi,pwm-active-state = <1 0 1>; adi,pin10-function = "smbalert#"; adi,pin14-function = "tach4"; + #pwm-cells = <4>; + + fan-0 { + pwms = <&pwm 0 22500 PWM_POLARITY_INVERTED 255>; + }; + + fan-1 { + pwms = <&pwm 2 22500 PWM_POLARITY_INVERTED 255>; + }; }; }; From patchwork Tue May 28 22:56:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13677527 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32CFF13EFEF for ; Tue, 28 May 2024 22:56:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; 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Wed, 29 May 2024 10:56:42 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id AAF4C13EE83; Wed, 29 May 2024 10:56:42 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A6614280AFC; Wed, 29 May 2024 10:56:42 +1200 (NZST) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ukleinek@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Chris Packham Subject: [PATCH v4 2/3] dt-bindings: hwmon: adt7475: Deprecate adi,pwm-active-state Date: Wed, 29 May 2024 10:56:37 +1200 Message-ID: <20240528225638.1211676-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528225638.1211676-1-chris.packham@alliedtelesis.co.nz> References: <20240528225638.1211676-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=F9L0dbhN c=1 sm=1 tr=0 ts=6656612a a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=TpHVaj0NuXgA:10 a=A1YWOaG1RMH6ymt1ZYoA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Now that we have fan child nodes that can specify flags for the PWM outputs we no longer need the adi,pwm-active-state property. Signed-off-by: Chris Packham Acked-by: Rob Herring (Arm) --- Notes: Changes in v3: - New Documentation/devicetree/bindings/hwmon/adt7475.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/hwmon/adt7475.yaml b/Documentation/devicetree/bindings/hwmon/adt7475.yaml index bfef4c803bf7..ed18984c2529 100644 --- a/Documentation/devicetree/bindings/hwmon/adt7475.yaml +++ b/Documentation/devicetree/bindings/hwmon/adt7475.yaml @@ -45,6 +45,7 @@ properties: the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm uses a logic high output for 100% duty cycle. $ref: /schemas/types.yaml#/definitions/uint32-array + deprecated: true minItems: 3 maxItems: 3 items: @@ -112,7 +113,6 @@ examples: reg = <0x2e>; adi,bypass-attenuator-in0 = <1>; adi,bypass-attenuator-in1 = <0>; - adi,pwm-active-state = <1 0 1>; adi,pin10-function = "smbalert#"; adi,pin14-function = "tach4"; #pwm-cells = <4>; From patchwork Tue May 28 22:56:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13677528 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 342AC13F006 for ; Tue, 28 May 2024 22:56:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716937008; cv=none; b=HQQZ7UqrBH6hrAAoC2YiCZhvBtCcKXExV8Mb/YuAdZwX4DLMV1mPVL+1A1xAWRwlqwYsq/IYfwLnEZc3RaPZK47wwgF7qKtMWstDr2F1C/xPJH1SGTm/ynoqKkPL+IvePbmRuRGVlbaEmSBCoFZqDcaED5FWQXo3PEdE9cMEb00= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716937008; c=relaxed/simple; bh=Mr4R4Ovc/1GYphW/4sCiClMVCQOYp+QcgAN/leUXXoU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JIqWVjiw0LHJJf4aB62aAntxuk1vz/5awqEjPafJO9PCPT8BHXeazQa/yRIN7KWmJYDzkc5xUerCnAZU2r1SpmPvZJ1DHYhnr5NZpb4zQXNLaG7s5Ei0hnQxqgQvC7+YURpZAlOWKilka5RbqDNxw4e02G5j601iEFjqdbrN+78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=bnbaLEP/; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="bnbaLEP/" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 1C1F92C083B; Wed, 29 May 2024 10:56:43 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1716937003; bh=sDg5hLIzdRqL90fe0fSd0Q9S7I111GJVwkN3eDzWGyU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bnbaLEP/q1CLAkKSbqbJz5nHx75HpfY0Tz3fDpLUQsY0a7vQr0dOc5OLfCGvvWvZv GLpNyIRO84IjcfMewkU2QJBoDebspW6SlBaN2bwAqkcq5SOsR2DV8HaNKedulWOXVH I5Wja+o9Rek7/jyZRInQi+SPv8S0pyGnJ3PI7YEZ+2YQKKX9F3DhHWPrM0SHX6xlpc GDzbPBMbivAFx7FJJurxBQj4CAf6xjgqnJUZhBjdoNsPpIMyS6PhS3caUgj+UNWtnI r7F8i/pM05glr1XmOKK7FbP3Nd9oREdR0Sal1lmpsKSJC9IJnN+I+SxgNdGdmF6EhL T2Fiq5cxe77qg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Wed, 29 May 2024 10:56:42 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id AECEC13EE84; Wed, 29 May 2024 10:56:42 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id AC2C4280A37; Wed, 29 May 2024 10:56:42 +1200 (NZST) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ukleinek@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Chris Packham Subject: [PATCH v4 3/3] hwmon: (adt7475) Add support for configuring initial PWM state Date: Wed, 29 May 2024 10:56:38 +1200 Message-ID: <20240528225638.1211676-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240528225638.1211676-1-chris.packham@alliedtelesis.co.nz> References: <20240528225638.1211676-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=F9L0dbhN c=1 sm=1 tr=0 ts=6656612a a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=TpHVaj0NuXgA:10 a=cN3pOM3YZmoqkZYst0EA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat By default the PWM duty cycle in hardware is 100%. On some systems this can cause unwanted fan noise. Add the ability to specify the fan connections and initial state of the PWMs via device properties. Signed-off-by: Chris Packham --- Notes: Changes in v4: - Support DT and ACPI fwnodes - Put PWM into manual mode Changes in v3: - Use the pwm provider/consumer bindings Changes in v2: - Use correct device property string for frequency - Allow -EINVAL and only warn on error - Use a frequency of 0 to indicate that the hardware should be left as-is drivers/hwmon/adt7475.c | 112 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/drivers/hwmon/adt7475.c b/drivers/hwmon/adt7475.c index 4224ffb30483..b5c58e3cda03 100644 --- a/drivers/hwmon/adt7475.c +++ b/drivers/hwmon/adt7475.c @@ -21,6 +21,8 @@ #include #include +#include + /* Indexes for the sysfs hooks */ #define INPUT 0 @@ -1662,6 +1664,112 @@ static int adt7475_set_pwm_polarity(struct i2c_client *client) return 0; } +struct adt7475_pwm_config { + int index; + int freq; + int flags; + int duty; +}; + +static int adt7475_pwm_properties_parse_reference_args(struct fwnode_handle *fwnode, + struct adt7475_pwm_config *cfg) +{ + int ret; + struct fwnode_reference_args args = {}; + + ret = fwnode_property_get_reference_args(fwnode, "pwms", "#pwm-cells", 0, 0, &args); + if (ret) + return ret; + + if (args.nargs != 4) { + fwnode_handle_put(args.fwnode); + return -EINVAL; + } + + cfg->index = args.args[0]; + cfg->freq = find_closest(args.args[1], pwmfreq_table, ARRAY_SIZE(pwmfreq_table)); + cfg->flags = args.args[2]; + cfg->duty = clamp_val(args.args[3], 0, 0xFF); + + fwnode_handle_put(args.fwnode); + + return 0; +} + +static int adt7475_pwm_properties_parse_args(struct fwnode_handle *fwnode, + struct adt7475_pwm_config *cfg) +{ + int ret; + u32 args[4] = {}; + + ret = fwnode_property_read_u32_array(fwnode, "pwms", args, ARRAY_SIZE(args)); + if (ret) + return ret; + + cfg->index = args[0]; + cfg->freq = find_closest(args[1], pwmfreq_table, ARRAY_SIZE(pwmfreq_table)); + cfg->flags = args[2]; + cfg->duty = clamp_val(args[3], 0, 0xFF); + + return 0; +} + +static int adt7475_fan_pwm_config(struct i2c_client *client) +{ + struct adt7475_data *data = i2c_get_clientdata(client); + struct fwnode_handle *child; + struct adt7475_pwm_config cfg = {}; + int ret; + + device_for_each_child_node(&client->dev, child) { + if (!fwnode_property_present(child, "pwms")) + continue; + + if (is_of_node(child)) + ret = adt7475_pwm_properties_parse_reference_args(child, &cfg); + else + ret = adt7475_pwm_properties_parse_args(child, &cfg); + + if (cfg.index >= ADT7475_PWM_COUNT) + return -EINVAL; + + ret = adt7475_read(PWM_CONFIG_REG(cfg.index)); + if (ret < 0) + return ret; + data->pwm[CONTROL][cfg.index] = ret; + if (cfg.flags & PWM_POLARITY_INVERTED) + data->pwm[CONTROL][cfg.index] |= BIT(4); + else + data->pwm[CONTROL][cfg.index] &= ~BIT(4); + + /* Force to manual mode so PWM values take effect */ + data->pwm[CONTROL][cfg.index] &= ~0xE0; + data->pwm[CONTROL][cfg.index] |= 0x07 << 5; + + ret = i2c_smbus_write_byte_data(client, PWM_CONFIG_REG(cfg.index), + data->pwm[CONTROL][cfg.index]); + if (ret) + return ret; + + data->pwm[INPUT][cfg.index] = cfg.duty; + ret = i2c_smbus_write_byte_data(client, PWM_REG(cfg.index), + data->pwm[INPUT][cfg.index]); + if (ret) + return ret; + + data->range[cfg.index] = adt7475_read(TEMP_TRANGE_REG(cfg.index)); + data->range[cfg.index] &= ~0xf; + data->range[cfg.index] |= cfg.freq; + + ret = i2c_smbus_write_byte_data(client, TEMP_TRANGE_REG(cfg.index), + data->range[cfg.index]); + if (ret) + return ret; + } + + return 0; +} + static int adt7475_probe(struct i2c_client *client) { enum chips chip; @@ -1778,6 +1886,10 @@ static int adt7475_probe(struct i2c_client *client) if (ret && ret != -EINVAL) dev_warn(&client->dev, "Error configuring pwm polarity\n"); + ret = adt7475_fan_pwm_config(client); + if (ret) + dev_warn(&client->dev, "Error %d configuring fan/pwm\n", ret); + /* Start monitoring */ switch (chip) { case adt7475: