From patchwork Wed May 29 08:28:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678332 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7294176FA3; Wed, 29 May 2024 08:29:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971358; cv=none; b=E6Z5VhFIXzkvXUE8Y8SAZxETyUfjllhWf5OU0zsGz7aSIJ+2m0tn1zp4ilKTHtKkIP0dfXsRa4+LHUfropf+GX1udhVNJNljO6GDE36Ri/ReHX8C53aNWJu1U5t9wkETAmI0hZGd5UJ68EQ8cRTjFUZjMLUymz3GRebnZX/wuEQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971358; c=relaxed/simple; bh=YQdBNL3lsBxDipD/xKxlprycaEEuRK+D1X2/LL0v9pk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JkIMAqm1x/q/hcTZfvLEIcRJ3W5jy3LGj8ffDsY9sp3Z3SSu2t6l9g3Lj7sWmI0wW3hylZcnn4r/PirtQZA8+Or+c8Fk+SaHDCPPC51lYHLXqX5luu59z2D31vezHIB8ewURo3j2lX31XSB9ECK4ybaBGHnJFp5mPIUGNsd+a9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tNdZg47P; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tNdZg47P" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5A3ACC4AF0D; Wed, 29 May 2024 08:29:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971358; bh=YQdBNL3lsBxDipD/xKxlprycaEEuRK+D1X2/LL0v9pk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tNdZg47PkI8DdddprTyeIZEIsV6JOQTZDDXhrcGGQVcIrp1B5ECK0HmrzIKdrQUQ7 9pcvvKhs8TX8iLJgdedT68V1l3QAkpQZdAui3ViMh94wV/VJa+jbKNi/bKfG9DuljD vwjrJETLDA8EIikBKWkM6vYIAt5Gwl1GvYE/aRFoP23KJsDjZwHMWyr8NQb2ONueaz HEVEqcaRX/S2rj8HoGTv0NLCySh9wgtYAsaofmhAfGC9Qdj9reIlz/l+M9U/cR3ctW fbK32RgZn8hK/9F3PsWMV+nvL1AmQO4/jPEaIeK2Olt05+bavyvLeymjSubpm8VXpe orx/hd3l87Z4Q== From: Niklas Cassel Date: Wed, 29 May 2024 10:28:55 +0200 Subject: [PATCH v4 01/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-1-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1296; i=cassel@kernel.org; h=from:subject:message-id; bh=YQdBNL3lsBxDipD/xKxlprycaEEuRK+D1X2/LL0v9pk=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnocaCq7Jst/wOOJeK4PSzflpL85tqVjoYCEjEcW67 9rtWE2LjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEykxIjhfyZvXInhLQfrgP6D ga8+pT1lCphp2LZmy06zuVdD5J99amdk2BIePc1O/5n4hqwNNsFHjrIbL5D46LyP96espqkpjwY 3JwA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the reg-name "apb" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use a different reg-name when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "apb" is already defined in snps,dw-pcie.yaml, add it also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index bbdb01d22848..00dec01f1f73 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -100,7 +100,7 @@ properties: for new bindings. oneOf: - description: See native 'elbi/app' CSR region for details. - enum: [ link, appl ] + enum: [ apb, link, appl ] - description: See native 'atu' CSR region for details. enum: [ atu_dma ] allOf: From patchwork Wed May 29 08:28:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678333 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52191178364; Wed, 29 May 2024 08:29:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971362; cv=none; b=Wd5ogfgmpJa2lcA2lHeJiOjRRrsNhOAsjtzDDGPnMXcCKmp8uEEk2StzfwusX2oOq79dBqQooLw/g1oabsberof6DNqvsKcb2ho0xuc3CS+SkkbxIw89RciZ2x0zwLuoJyxrr55FxnI3WjZuhtk5/Xq1oH1shp/KrWOqAF3TN/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971362; c=relaxed/simple; bh=0AsOf44k0peZ3qs9praxDDjjEV3cTdstHX1bWf4Vatw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KWp2Iy4LX1BBjZpDTzWBRAQRnAqSa9LWmEv2xuyndS4gSdzJbJaL2pvLGgjGyK+lxwi//tl68AUmxfG5aoYPYzYLcGD1pYTKY9hh1T9tfH/ByihgTQTEnRzEoEQwPBg3zTnM7nCZLd5VnBnHNDSXUpzLKh5y265khNL8jAFPbOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kltBVmHc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kltBVmHc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7E687C32781; Wed, 29 May 2024 08:29:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971362; bh=0AsOf44k0peZ3qs9praxDDjjEV3cTdstHX1bWf4Vatw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kltBVmHcR8ymdXTWZ2dryzYB1qMuJLqY5l7F/rKZzrcc49uLpWiNeZnn/O+3p011Q z+CnE/RYmVyaKluH1XxnguoEnf1C4u+2/DNFs5cfOcpzJ6hKNFgUtuPgfmlSwfwA+v 6PkKl9+ya2ozGuDHGx1dIlGM4AL0lzXH8lH1XhobmfgeG88aQXvc+qtGIwrOxwAVCx NpwrEAV9g1TY5ij07VPUV/ijv/BPz1NElU3NjXmHphhib9av/GXS5ccAdjxWP2Pqm8 k8RgQkI31CdPyg1uCKQC1UCmNTPWdXcOvfQlh7nM3cRXcbEtaRv1fQM/9Li8PDZQ28 40SudWbejOQRA== From: Niklas Cassel Date: Wed, 29 May 2024 10:28:56 +0200 Subject: [PATCH v4 02/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-2-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1267; i=cassel@kernel.org; h=from:subject:message-id; bh=0AsOf44k0peZ3qs9praxDDjjEV3cTdstHX1bWf4Vatw=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnodaZ+asi51/JWVBrUmPrPzpOs8HP//tvHJ/4mV5R sbsrFaOjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEwkcQrDX3mNvwyn188MWKdo zJUc/avFxfPAGakfS0IvyynvfskupMrIsFfgz6MvLz/Ma39iLrCk8FvttR91jld/e8QIBE+d8qk yiRkA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the interrupt-names "sys", "pmc", "msg", "err" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use different interrupt-names when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "sys", "pmc", "msg", "err" are already defined in snps,dw-pcie.yaml, add them also for snps,dw-pcie-ep.yaml. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index 00dec01f1f73..f5f12cbc2cb3 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -156,7 +156,7 @@ properties: for new bindings. oneOf: - description: See native "app" IRQ for details - enum: [ intr ] + enum: [ intr, sys, pmc, msg, err ] max-functions: maximum: 32 From patchwork Wed May 29 08:28:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678334 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D1C81791EF; Wed, 29 May 2024 08:29:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971366; cv=none; b=HbomKBzwiaPgcqN1RDdX8j7qgNGMDqdbw//PTsuf7krW69LB97Y5SCYYclaBKMrM6yeVopU3ncQcrISlGtTrh4OpLAq2oMb/C6vw/zRChonupz8sPHEwh9W5fEnRdRs8ouw1uw6vuCOagpsa0wBNJt8KNOF3p1oY2L0jXZDb8nY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971366; c=relaxed/simple; bh=qiqeHfjdk+Gj3u+QTqjs/LSs7UUp1/lyknJfxw+i+DA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ri9vNym76kxCgr1AMl5SE4LbmJdgAo7+29YG2G1U73INiaac/vrzaPwUxH7QdqZCCQP/z/+aS485k+SZG5toeAY8ZNXsObVKP3QbyiwvkPPj92sL7hdxrbBh68j8nxVh9EgsZ0/6jfjM55np64EDJCwYRn5N3lU2DvZkBwkC63k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g4ry1cqd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g4ry1cqd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A1847C4AF0E; Wed, 29 May 2024 08:29:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971366; bh=qiqeHfjdk+Gj3u+QTqjs/LSs7UUp1/lyknJfxw+i+DA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=g4ry1cqd8cEzgUN5sgycB2Tcf5R7uiP6t0Dm/q9LtF67P31IKtyflNthn2PVOdMqS om7YWdJOnopR3AsM3G4F4cnUrH3lrWVuWlMf5ZtBG51zubCwnyY5voZAQD9H1LrWjP eE+lieWeTRSgrKpY26OuQGsDjbz2GIUpF0QZsKzpgOtby3YQtW4LLqUmaDjIKRoHpn u5wmBx1OIpC89prBDN70Zp5RddterI3xUJQjMLg06TIMga6Ua5i86IXpALocmW/v9g ywO/Zm9zKnj8nPu7GuwCSKvio6RS0HRgMbeZR9EFQy+rqunO7UbyatqhWF7HAiUlPE Pduy6KCHrSGSA== From: Niklas Cassel Date: Wed, 29 May 2024 10:28:57 +0200 Subject: [PATCH v4 03/13] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-3-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1672; i=cassel@kernel.org; h=from:subject:message-id; bh=qiqeHfjdk+Gj3u+QTqjs/LSs7UUp1/lyknJfxw+i+DA=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnoc6hojfuZDwtrcj87srW2uyR1UtS1jG3q6UOYv2n vf9k7G8o5SFQYyLQVZMkcX3h8v+4m73KccV79jAzGFlAhnCwMUpABNJL2dk2P3P7CxH533tJZtt rVZEpKTXnHB8pPZWJE44KVqNIeHvd4b/7gfcp1jz96Xc4r5/7trsl29Dt+j22K24HvHj5z5Lln3 lXAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd that are triggered when the PCIe controller (when running in Endpoint mode) has sent an Assert_INTA Message to the upstream device. Some DWC controllers have these interrupt in a combined interrupt signal. Add the description of these interrupts to the device tree binding. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index f5f12cbc2cb3..f474b9e3fc7e 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -151,6 +151,15 @@ properties: Application-specific IRQ raised depending on the vendor-specific events basis. const: app + - description: + Interrupts triggered when the controller itself (in Endpoint mode) + has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to + the upstream device. + pattern: "^tx_int(a|b|c|d)$" + - description: + Combined interrupt signal raised when the controller has sent an + Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details. + const: legacy - description: Vendor-specific IRQ names. Consider using the generic names above for new bindings. From patchwork Wed May 29 08:28:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678335 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFFAE16A374; Wed, 29 May 2024 08:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971371; cv=none; b=Fp/WI0IHdUu/xBoNYDI/Bdn56dTWNON8f4+808fG4/ibMlW/Jk1FKN8SFdXKB+WuTld/5iy42xo+N8gDqDFpJL2nTbMCXm8MlB3523cYabsWaofojvBbt8zcPSxLS59Ie6akU68ZP/DZKC2qePoGX4sV9h+Q32Kxy0Twx7ei4sA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971371; c=relaxed/simple; bh=zeWgZMBKWqV0mTmt0pu9yQOlBSadlLh4PY9sjzXyna0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nmZY7qqq+WQbIoNiyueftns75bpmogQdLxdL5dAN/jRR/idT9uIF4H/lKvrFfV4yoXnBXv26PQ56s7QPLftv4sRD1yShXVk/hQQe5XFdqkQS9MJ8qCi2tq8+uP0WlCXpgV+JCpcZYdk6A3NLq+iZ1NKvumzQkJcYntOwNN4v0Uw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Z1r+/NM8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z1r+/NM8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C413EC32781; Wed, 29 May 2024 08:29:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971370; bh=zeWgZMBKWqV0mTmt0pu9yQOlBSadlLh4PY9sjzXyna0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Z1r+/NM8fEk1Qw10UHFCz8HHCJL9dMbX9LU9Dn2xm40ZEFZBOdDgaIOz/XCqkDF8V o09+Ka8lGbybr9oaNxHyYNLNUHi51XEq6vpchM8LHqJfiLPTMXPKZYst1H39ijSblD mv+SnRIyRdbzWZRQktyI5TERlZSMz+q4sUDM3GWnoZ4nTUKe8JVKLFD6qVsLPuU84T l1ZQuBmJ96WN3vi4elvKuwfhxKY8dUQ0pYOgE3vomlprR4JzgGJQCSBpPOrTH0IIn1 gockfp3bngnQ43WXXw3swPBzI8v3gen5UrTgBilQDpA9Hs2cAQsQZUiXAkrdQ7nOYv GqvkXP/HEJXjA== From: Niklas Cassel Date: Wed, 29 May 2024 10:28:58 +0200 Subject: [PATCH v4 04/13] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-4-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8069; i=cassel@kernel.org; h=from:subject:message-id; bh=zeWgZMBKWqV0mTmt0pu9yQOlBSadlLh4PY9sjzXyna0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnocuvWf/Pd121XTflr83Hvyr4IpwsVJ9+fq2UobA+ uccl/pmdZSyMIhxMciKKbL4/nDZX9ztPuW44h0bmDmsTCBDGLg4BWAiU44y/DMs5jg4uzuJ4fB7 prUM+Wpanl6H3I3XzhDn+X/iuvkOwTsMv1lDW2SWMh4qWNRwm2V14p73PAtezVSrU4w8YKR7SDi +mgEA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Refactor the rockchip-dw-pcie binding to move generic properties to a new rockchip-dw-pcie-common binding that can be shared by both RC and EP mode. No functional change intended. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 111 +++++++++++++++++++++ .../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 93 +---------------- 2 files changed, 114 insertions(+), 90 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml new file mode 100644 index 000000000000..60d190a77580 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe RC/EP controller on Rockchip SoCs + +maintainers: + - Shawn Lin + - Simon Xue + - Heiko Stuebner + +description: |+ + Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip + SoCs. + +properties: + clocks: + minItems: 5 + items: + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + - description: AHB clock for PCIe dbi + - description: APB clock for PCIe + - description: Auxiliary clock for PCIe + - description: PIPE clock + - description: Reference clock for PCIe + + clock-names: + minItems: 5 + items: + - const: aclk_mst + - const: aclk_slv + - const: aclk_dbi + - const: pclk + - const: aux + - const: pipe + - const: ref + + interrupts: + items: + - description: + Combined system interrupt, which is used to signal the following + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app + - description: + Combined PM interrupt, which is used to signal the following + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, + linkst_out_l0s, pm_dstate_update + - description: + Combined message interrupt, which is used to signal the following + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active + - description: + Combined legacy interrupt, which is used to signal the following + interrupts - inta, intb, intc, intd + - description: + Combined error interrupt, which is used to signal the following + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, + nf_err_rx, f_err_rx, radm_qoverflow + + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + oneOf: + - const: pipe + - items: + - const: pwr + - const: pipe + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - num-lanes + - phys + - phy-names + - power-domains + - resets + - reset-names + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 5f719218c472..550d8a684af3 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: DesignWare based PCIe controller on Rockchip SoCs +title: DesignWare based PCIe Root Complex controller on Rockchip SoCs maintainers: - Shawn Lin @@ -12,12 +12,13 @@ maintainers: - Heiko Stuebner description: |+ - RK3568 SoC PCIe host controller is based on the Synopsys DesignWare + RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# properties: compatible: @@ -40,61 +41,6 @@ properties: - const: apb - const: config - clocks: - minItems: 5 - items: - - description: AHB clock for PCIe master - - description: AHB clock for PCIe slave - - description: AHB clock for PCIe dbi - - description: APB clock for PCIe - - description: Auxiliary clock for PCIe - - description: PIPE clock - - description: Reference clock for PCIe - - clock-names: - minItems: 5 - items: - - const: aclk_mst - - const: aclk_slv - - const: aclk_dbi - - const: pclk - - const: aux - - const: pipe - - const: ref - - interrupts: - items: - - description: - Combined system interrupt, which is used to signal the following - interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, - hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, - edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app - - description: - Combined PM interrupt, which is used to signal the following - interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, - linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, - linkst_out_l0s, pm_dstate_update - - description: - Combined message interrupt, which is used to signal the following - interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, - pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - - description: - Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd - - description: - Combined error interrupt, which is used to signal the following - interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, - tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, - nf_err_rx, f_err_rx, radm_qoverflow - - interrupt-names: - items: - - const: sys - - const: pmc - - const: msg - - const: legacy - - const: err - legacy-interrupt-controller: description: Interrupt controller node for handling legacy PCI interrupts. type: object @@ -119,47 +65,14 @@ properties: msi-map: true - num-lanes: true - - phys: - maxItems: 1 - - phy-names: - const: pcie-phy - - power-domains: - maxItems: 1 - ranges: minItems: 2 maxItems: 3 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - oneOf: - - const: pipe - - items: - - const: pwr - - const: pipe - vpcie3v3-supply: true required: - - compatible - - reg - - reg-names - - clocks - - clock-names - msi-map - - num-lanes - - phys - - phy-names - - power-domains - - resets - - reset-names unevaluatedProperties: false From patchwork Wed May 29 08:28:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678336 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C66AE1802D8; Wed, 29 May 2024 08:29:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971374; cv=none; b=B/LgG7jgudwnHrOJNnQrdFyaAMsX7oG3++U69EihF3ff7sRe9xYh7ydDl3ofpmHbmf2dQaRZXnGcmPrSvmSvksx5agD37v9UMkCKZeX5x6t4sdApF6Y4w5kkyMHz7ug/hn/pMTaKyJXlCQvCVl1PaWhfTcr6LP+RRGbHkro1f7s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971374; c=relaxed/simple; bh=DgDwrueIemNRUbe/G47rptzZcqdtSi36/c0CqD/3bpc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k6rMUOckxAVoCSh4NRVQKz9u3qcsEjeMISgadJR+dBV38L8Tar5mA5GWWowNoO5zTQjVWyaNWvVGTzw72fsWommrYdaEgHMn5QUUWG72DIbTqhW8n3JJRC/8UsmpHqeCMaS0A6GYeuTAhC27K8H36f3pYDyiGuGXzIrb4SDiuJA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lvPQdGTU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lvPQdGTU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9A56C2BD10; Wed, 29 May 2024 08:29:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971374; bh=DgDwrueIemNRUbe/G47rptzZcqdtSi36/c0CqD/3bpc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lvPQdGTUaVlg1aqniVj6oGLXetp4BruksxRNlzdqZhWsTycgI43tlsgfYsWEJslbj uZb/1QwyF2o91i4ZfK7bU7qZmuUqSP9G9fjt2AQ25W49F50qhrApiVV82LNSllGKA7 0q3BEvK8qSNHaPPxmxClcCimaM3Ig9pm5pJL7P78Io/a1sCqW+I1zqp2t9rEhZ9KGl tvqBqG7jK8M4jO491Ev9C0mcz/NV9NCbjQVvSbgfqUJMXrr3NTlPac3yb0ydK2Ad41 OYBktfPb0/Ma77o7VwXNlZwj6GOOsYTv2cO17kCdyJ2lLQ1MRkErq7eQ/cYYtLxg4r ueNsvzrkbAH7w== From: Niklas Cassel Date: Wed, 29 May 2024 10:28:59 +0200 Subject: [PATCH v4 05/13] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-5-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1950; i=cassel@kernel.org; h=from:subject:message-id; bh=DgDwrueIemNRUbe/G47rptzZcqdtSi36/c0CqD/3bpc=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnofyPD2dFfy2tyLyxpPX9s3lddundb7ydDrQ3WTWf KdI74Z7RykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACZS4sLwv9hs4aovpT8M32wW 2qrXJLHnv/TVVx7bZQ8dU0oqtZmr0crwV0Su3Vedx+1EWVbGS+UbP/a7GDWp3VE+mbY54ZaHptk 6dgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The descriptions of the combined interrupt signals (level1) mention all the lower interrupt signals (level2) for each combined interrupt, regardless if the lower (level2) signal is RC or EP specific. E.g. the description of "Combined system interrupt" includes rbar_update, which is EP specific, and the description of "Combined message interrupt" includes obff_idle, obff_obff, obff_cpu_active, which are all EP specific. The only exception is the "Combined legacy interrupt", which for some reason does not provide an exhaustive list of the lower (level2) signals. Add the missing lower interrupt signals: tx_inta, tx_intb, tx_intc, and tx_intd for the "Combined legacy interrupt", as per the rk3568 and rk3588 Technical Reference Manuals, such that the descriptions of the combined interrupt signals are consistent. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index 60d190a77580..ec5e6a3d048e 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -56,7 +56,8 @@ properties: pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - description: Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd + interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc, + tx_intd - description: Combined error interrupt, which is used to signal the following interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, From patchwork Wed May 29 08:29:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678337 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED22416A38C; Wed, 29 May 2024 08:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971379; cv=none; b=NlZNh+LXbJKfxSI5BxIgzBV5YH10CG8mjVqm6CrU2KMwjP6MCV7W4aurSAhR+Aw2hwvQroE0yIWgHflnDA2FyPdpvEB9zzOxbR7kKRUpEmeJ9vpJBtxhENK+7mVRX0DAGtXL4vYkcmVVenftuud1RRPd1EKEb5YwyGWH3sPFL0k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971379; c=relaxed/simple; bh=nWtMO3Tq70/oK25PGlvcS03OBMjbjH2pdvYUD7wjcIo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hNoIsbtj+EfMgvUicDqMRQokEOKQXPYXheqxH8fLoDYOnF/4bvw5KbfR0aSAP0KLDNwr/Kj8UcAFKHxxGBASwaQqIWGWrVCEPuay/SbXJQOD8fwnK37evq1KsRrgqisRBR1By61SHF66VlE8gLmlbWsgW8diK9VORz/BY716Q60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=caItURaD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="caItURaD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 17907C32786; Wed, 29 May 2024 08:29:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971378; bh=nWtMO3Tq70/oK25PGlvcS03OBMjbjH2pdvYUD7wjcIo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=caItURaDaOim13+0rLMOpCIqrjMpzl+h1Cj4mOwPzjLByJATqglAhJs1TmoCSQp4X fb2MFPCqPaYdp6shprAM5Ct9dg+oZhZn7C1E+/dBwjMpHKQ2X2zlfCfDR6gT4w7YaI HgCn5gtSSAS79R5OLSKYirntMsbfsFmzPqv43lPG5eY/77XJEVtRHNEEhy+eh10Lu3 Cw3HaoxvMERBXIPPP0k0KD5+kw8WB0DNLbMurSstaVcaKcMByLLqSOfLXkdc2lMmrq I3Sf7+HjwHEeMFIhMwx3TnKEiu4ezO9ZC39l/jnVp83igVZ0D/cEh73Xki5kROJeqI Q1jewmNvmGGrw== From: Niklas Cassel Date: Wed, 29 May 2024 10:29:00 +0200 Subject: [PATCH v4 06/13] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-6-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5534; i=cassel@kernel.org; h=from:subject:message-id; bh=nWtMO3Tq70/oK25PGlvcS03OBMjbjH2pdvYUD7wjcIo=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnoc2zrrSPHn3/J3Nd/cUnZe+EDr9fdaTwsonp45sy Lss9d3mSEcpC4MYF4OsmCKL7w+X/cXd7lOOK96xgZnDygQyhIGLUwAmErmO4a+4UeWTExGxWgIL ZWM95Z7czpOL37P9+WWHrQ8rvTkWdskx/LOWu3f2xvn3gr9qvqoe/7Xi0k4OG17eL4nBQQXce/a od3ACAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 14 ++++ .../bindings/pci/rockchip-dw-pcie-ep.yaml | 95 ++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index ec5e6a3d048e..cc9adfc7611c 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -39,6 +39,7 @@ properties: - const: ref interrupts: + minItems: 5 items: - description: Combined system interrupt, which is used to signal the following @@ -63,14 +64,27 @@ properties: interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow + - description: + eDMA write channel 0 interrupt + - description: + eDMA write channel 1 interrupt + - description: + eDMA read channel 0 interrupt + - description: + eDMA read channel 1 interrupt interrupt-names: + minItems: 5 items: - const: sys - const: pmc - const: msg - const: legacy - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 num-lanes: true diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml new file mode 100644 index 000000000000..e0c8668afc01 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe Endpoint controller on Rockchip SoCs + +maintainers: + - Niklas Cassel + +description: |+ + RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# + +properties: + compatible: + enum: + - rockchip,rk3568-pcie-ep + - rockchip,rk3588-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Data Bus Interface (DBI) shadow registers + - description: Rockchip designed configuration registers + - description: Memory region used to map remote RC address space + - description: Address Translation Unit (ATU) registers + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: apb + - const: addr_space + - const: atu + +required: + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + }; + }; +... From patchwork Wed May 29 08:29:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678338 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F16416ABEB; Wed, 29 May 2024 08:29:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971383; cv=none; b=cNF87aq/sD9PdICYQz9LjXlC0RV2kcAdmxtDpjY/APZNEkV3r1ld0T5yvzsaTRX5MPorMLRXB80PBXeXHA4NOAJvolfpseFZ2XfFCQa+qlL17kOUQGwq0vuIs43SLjh8qEw5IttIsUhrDXT4I/N4zcYkB4U5WSbQ6VTn1vF3NaU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971383; c=relaxed/simple; bh=j29Odjmid02gVXIY5mRFCi+Esy8gIr9tXG/wl62J2qI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e74r9dGn/tABNxhhAKEj8lNpVt+2d79NGW4Xz2c4ZmLP+/hSMGkHjSjNXffJsSUbZNT5IJpSKOxPADv9b4FEpfa/QIDphseqyS51jyAHlk/Urms9pRAnk2xT9z1KjE6OX0b3d+gpdKF97dPVVjsEf0VGA6XxDIUTQDifXduY1T8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RFGVC93v; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RFGVC93v" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3BD3EC4AF0A; Wed, 29 May 2024 08:29:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971382; bh=j29Odjmid02gVXIY5mRFCi+Esy8gIr9tXG/wl62J2qI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=RFGVC93vi/1w7P/FWNhVdBwm1mpeCcOFUviLios9IyLqeoSSHA/D/z8wlYXVys4RC F4H2umpX32USOj8b8AaoyvuAUzuhVOs4EnxXq6mXZo6ajpluMp6KKy7+NTD+XM6pWd 78doFhIvyx7GooTRDiKxhhP0zIvqf2J9YNyuFzVJIoNyDr9pbYAlIx0maZmv9B7/Xe Pkf+RumNOZ0Ln1Q4e0Wna0FoHdkFRwjUdAjj82jaYTKOy5SDZkOk18JS3A2Cew64Ed xFFtFothCeXw/QV1IEwlgoveIsLvWSMGZYMX3mzLagQeLZIE3RtEM9xRDYgqr2mMZb Q91twdZtTvpgw== From: Niklas Cassel Date: Wed, 29 May 2024 10:29:01 +0200 Subject: [PATCH v4 07/13] PCI: dw-rockchip: Fix weird indentation Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-7-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1187; i=cassel@kernel.org; h=from:subject:message-id; bh=j29Odjmid02gVXIY5mRFCi+Esy8gIr9tXG/wl62J2qI=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnoeevvBM8P2lxolLF685d/3q2VuF7AclEhxTXOI9J 0ozdVyL6ChlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBEeBMY/mcIV9clmN7Mlnz5 stO+wPLI1YdXIq9Lvz83xaXnhrnNRX2Gv2JOG7ccyfHr1q2M5bmarJO2ZemkHSvnX5utb5JXLSD UwwYA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Fix the indentation of rockchip_pcie_{readl,writel}_apb() parameters to match the opening parenthesis. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 61b1acba7182..3dfed08ef456 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -60,14 +60,13 @@ struct rockchip_pcie { struct irq_domain *irq_domain; }; -static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, - u32 reg) +static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg) { return readl_relaxed(rockchip->apb_base + reg); } -static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, - u32 val, u32 reg) +static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val, + u32 reg) { writel_relaxed(val, rockchip->apb_base + reg); } From patchwork Wed May 29 08:29:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678339 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80265374F6; Wed, 29 May 2024 08:29:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971387; cv=none; b=Mgrj8QpRQDOEZBsa41tPt/4n/0QDa/a8bvvKw2kqQ8YjcWodzT7QAXb1bxamvE6Wb+GM6IAc2W7fx6GCJuL7Xrpwfafyb1Q9GIyyOMxJuUDWgH5czEfHItakL2e9TZ+lcgeJ7M3EEX+GZNHilUwdBqzggpPh2PQEPiRrDYRX9K0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971387; c=relaxed/simple; bh=HSVP5fO1xteYLr3eNC2G4UOEz2LEMqziZSkp+Sf41N0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Cuma0ef5gwOKrk8bI60DTamGLIqzIS6Qaw9LTmg+52lhB6kU6XKN7D01Ggrn2wGRD6A83UQC7SbZmpzLihQIh3JLTvSzyJIhqHOtmLZX1A4n7xa5CQ+HOG2GcGpDEZHu1bW/JqRSQJMGDRMu4avaVF5HUbJqbwmtW6MLs17oNZ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NRNGiRuS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NRNGiRuS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5DB7CC2BD10; Wed, 29 May 2024 08:29:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971387; bh=HSVP5fO1xteYLr3eNC2G4UOEz2LEMqziZSkp+Sf41N0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NRNGiRuSrg3XQvmSdOFqBeLUMZzgzkBW5Xz64cPyI8nrqs1N0pSHv9nDK5CHw8UOn Khbl/n25WgD+f7yVQz0a3wUCz8p6Di9WMKmlsPQR93TH9wBUK5GUsf6osBTjuRte72 3kSVjARIAQ5GiBFkKaRILNDlqDzuTp/JzYlCLLlyQuCmwVFNe6LGxSCd516/Cf6Viy zFbbx3nMychM1zH0ikxVUsYZBHJ0p12ybUKTOwiyl5Ko8AW1SfiGbb/xCoxWZ4PK/3 fzgBu77mseltWWamhU0mwKofrElyxLfLrcDDmOeRE5ljIb5lL4QcVJWcZvPbwE3l4C 5h+QiQTzpwoEw== From: Niklas Cassel Date: Wed, 29 May 2024 10:29:02 +0200 Subject: [PATCH v4 08/13] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-8-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1426; i=cassel@kernel.org; h=from:subject:message-id; bh=HSVP5fO1xteYLr3eNC2G4UOEz2LEMqziZSkp+Sf41N0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnoc68fivD7KdkMf+XcE076Rx4JLj0xfdKLRVfjP/w sUq/uB9HaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZiIQQvDPwX/QvYryeE7yo3W neM917/picEVo/uNrSHdNQxF9xZc3MnIcGufYtubLc8WGvx64berIso9TqnY7ceJyUXdKtEn6/O yWQE= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add a rockchip_pcie_ltssm() helper function that reads the LTSSM status. This helper will be used in additional places in follow-up commits. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 3dfed08ef456..1380e3a5284b 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -143,6 +143,11 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) return 0; } +static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip) +{ + return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS); +} + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, @@ -152,7 +157,7 @@ static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) static int rockchip_pcie_link_up(struct dw_pcie *pci) { struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); - u32 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS); + u32 val = rockchip_pcie_get_ltssm(rockchip); if ((val & PCIE_LINKUP) == PCIE_LINKUP && (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY) From patchwork Wed May 29 08:29:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678340 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6246D374F6; Wed, 29 May 2024 08:29:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971391; cv=none; b=ovwhX5vQEcKv9rHHBwyazM8ZO6hQLbE4yvXmMSqNENb7AVsBhYCw2DClVL8f4x7JjSvo42gAskE6EnQsK67k5gA7sSzCLgPDgJoUsPXNwAYO+dKg8BubkG2NcaEiKDnNYiQKn41KJpFGDYC6N03rdIXMdgkzLU6VpprCCj176TQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971391; c=relaxed/simple; bh=SMegS8nfoyN3eNUTsk9/OXgYZ+S9QBWigdpnPN30MN8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BPLXpPh/KNOCxZyaC1FOj5uaRj2xg5QGuae1cF6rljWWpvAH9U9izkr8EcXFEu4+5k5W2iaEF5thGmgGLFQlh4xCuLW9Rfer70smZjMGhQj+A9dm7HoZW3ahhrEr5amfDo4Hk43YnF4NwdmRotC3175ldjAkwdV2fHNHBR6fQDs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fPcIzDgm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fPcIzDgm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 816B3C32789; Wed, 29 May 2024 08:29:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971391; bh=SMegS8nfoyN3eNUTsk9/OXgYZ+S9QBWigdpnPN30MN8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fPcIzDgmpp4lG6N4O4av6+KhSpuaX0QHWg6UKDiJ/jtuHRpoHOhD8GoFf6P23dLzG J5XNmWfVgtiQCkZJP930+wb0DKt+EnyZzx607omepb0Xn6yAcuB0iPwPk67seFxm6h 1mTVjZ6jIbQ7t3S/Wx/fGk0ogPcwIZ5L0e/1hAW7C5VgsGdlooHPz+/MarPDgzW58R Iup8B7C7bJC5F0Ztgp9LKa5SEPpwPaxo8xbRKqEG5HJ8zoi9FigqGCLwictAkhzXgv YO4MrSlrfWKr51+E3aU57/FQJI1z889UUkm4dVXZhit2/SoJ+gRAunkQHtf1gTV7KZ M50u/T1lezs4g== From: Niklas Cassel Date: Wed, 29 May 2024 10:29:03 +0200 Subject: [PATCH v4 09/13] PCI: dw-rockchip: Refactor the driver to prepare for EP mode Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-9-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4770; i=cassel@kernel.org; h=from:subject:message-id; bh=SMegS8nfoyN3eNUTsk9/OXgYZ+S9QBWigdpnPN30MN8=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnoduzg+/6X+zNZ6nWS4jsjphl+WkV9t2bLJ9tM6zN PC5XANnRykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACbyS5mR4VrlIib9HnPh/NtT hA41nzFLTNsQVsS6qeSqpKCo2/rNcxj+KTN8We1rEPpw8RVjP/td6p9upjBVTlp9putvnsrV7Oi PnAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA This refactors the driver to prepare for EP mode. Add of-match data to the existing compatible, and explicitly define it as DW_PCIE_RC_TYPE. This way, we will be able to add EP mode in a follow-up commit in a much less intrusive way, which makes the follup-up commit much easier to review. No functional change intended. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 84 +++++++++++++++++++-------- 1 file changed, 60 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 1380e3a5284b..e133511692af 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -49,15 +49,20 @@ #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) struct rockchip_pcie { - struct dw_pcie pci; - void __iomem *apb_base; - struct phy *phy; - struct clk_bulk_data *clks; - unsigned int clk_cnt; - struct reset_control *rst; - struct gpio_desc *rst_gpio; - struct regulator *vpcie3v3; - struct irq_domain *irq_domain; + struct dw_pcie pci; + void __iomem *apb_base; + struct phy *phy; + struct clk_bulk_data *clks; + unsigned int clk_cnt; + struct reset_control *rst; + struct gpio_desc *rst_gpio; + struct regulator *vpcie3v3; + struct irq_domain *irq_domain; + const struct rockchip_pcie_of_data *data; +}; + +struct rockchip_pcie_of_data { + enum dw_pcie_device_mode mode; }; static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg) @@ -195,7 +200,6 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); struct device *dev = rockchip->pci.dev; - u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); int irq, ret; irq = of_irq_get_byname(dev->of_node, "legacy"); @@ -209,12 +213,6 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler, rockchip); - /* LTSSM enable control mode */ - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); - - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, - PCIE_CLIENT_GENERAL_CONTROL); - return 0; } @@ -294,13 +292,35 @@ static const struct dw_pcie_ops dw_pcie_ops = { .start_link = rockchip_pcie_start_link, }; +static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip) +{ + struct dw_pcie_rp *pp; + u32 val; + + /* LTSSM enable control mode */ + val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, + PCIE_CLIENT_GENERAL_CONTROL); + + pp = &rockchip->pci.pp; + pp->ops = &rockchip_pcie_host_ops; + + return dw_pcie_host_init(pp); +} + static int rockchip_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct rockchip_pcie *rockchip; - struct dw_pcie_rp *pp; + const struct rockchip_pcie_of_data *data; int ret; + data = of_device_get_match_data(dev); + if (!data) + return -EINVAL; + rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL); if (!rockchip) return -ENOMEM; @@ -309,9 +329,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev) rockchip->pci.dev = dev; rockchip->pci.ops = &dw_pcie_ops; - - pp = &rockchip->pci.pp; - pp->ops = &rockchip_pcie_host_ops; + rockchip->data = data; ret = rockchip_pcie_resource_get(pdev, rockchip); if (ret) @@ -347,10 +365,21 @@ static int rockchip_pcie_probe(struct platform_device *pdev) if (ret) goto deinit_phy; - ret = dw_pcie_host_init(pp); - if (!ret) - return 0; + switch (data->mode) { + case DW_PCIE_RC_TYPE: + ret = rockchip_pcie_configure_rc(rockchip); + if (ret) + goto deinit_clk; + break; + default: + dev_err(dev, "INVALID device type %d\n", data->mode); + ret = -EINVAL; + goto deinit_clk; + } + + return 0; +deinit_clk: clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); deinit_phy: rockchip_pcie_phy_deinit(rockchip); @@ -361,8 +390,15 @@ static int rockchip_pcie_probe(struct platform_device *pdev) return ret; } +static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = { + .mode = DW_PCIE_RC_TYPE, +}; + static const struct of_device_id rockchip_pcie_of_match[] = { - { .compatible = "rockchip,rk3568-pcie", }, + { + .compatible = "rockchip,rk3568-pcie", + .data = &rockchip_pcie_rc_of_data_rk3568, + }, {}, }; From patchwork Wed May 29 08:29:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678341 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D779416C6B6; Wed, 29 May 2024 08:29:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971395; cv=none; b=ok/mtYax6aOTSuN9rKsK8IEGGPHtAhjb8bRQqHt9lFHl+UMdxTD5su+hEN7jRhsUTqxQVALu/5p+8ybIQsp4q4s88n35HtvTGlDIxrGeDZVDEkLzTq3Z9QEYazLTZfjjIgRJaxoNjIWR0atAnJeZ/Wrx22XDtakX5W48NAjnKqg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971395; c=relaxed/simple; bh=q/CFBjrEalEcsNAr3tf03EY4lqdtyimcaejYq+qBky0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=X2giUfvMPA04VFir8l7Z5g/kJUJ9R6WEVvg/8SGUyKtBils5WbpJtwwFbM6Z8g6O9xFqFfoNiczEeH1QYncR6A0ZZPL59C/CvIVSfSdozFDVGfTiXtFt3Ri2gdO3VWtG4dHalsXjCu7LcMFGt2PJChd7HMYusQjBZMlRb9cye68= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cxJ9BlQT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cxJ9BlQT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A66A8C32789; Wed, 29 May 2024 08:29:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971395; bh=q/CFBjrEalEcsNAr3tf03EY4lqdtyimcaejYq+qBky0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cxJ9BlQThYrCiR5d2Klj95jPLD7VHTAA6ZQj720ULalUlAWA9GiWKV7N8mMz/fjlf cYW8/QV1K8di55g+yxux07DZBS5T5kXcjvDF7cZTg5318OdUDRFZiR/5W5cZzaZg1w IEZJzb1dpMm10VDO0qDJzrxffmEwDF6yB0DoiV48lJju9TUk34zaVceZ3LiLwN062J 5UpHp5oPtcV/U5ky+LiaZwvRYHUP4/2UiL3alsIFa/V395r4XcBs07nBYZ1Hh6hASp 4gMAT86PunXnSxTqzQBi8uhzgCO9pG4fuDlaEJYcwXSXNB9MRztMwwyJHD+zBRZfez UPTF+59Q/31cA== From: Niklas Cassel Date: Wed, 29 May 2024 10:29:04 +0200 Subject: [PATCH v4 10/13] PCI: dw-rockchip: Add endpoint mode support Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-10-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11300; i=cassel@kernel.org; h=from:subject:message-id; bh=q/CFBjrEalEcsNAr3tf03EY4lqdtyimcaejYq+qBky0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnocufWugn9A4U9V4WsD3VdXNBkIK07nqk0Oj03blb 794NNu9o5SFQYyLQVZMkcX3h8v+4m73KccV79jAzGFlAhnCwMUpABM5PpGRYd6TXXaTj7/zNsjW ldc34/QTbfR+nvh/veeppGf6jZ5SOQz/jNNmS3iYn/qrvi+cs8c+T0izds39i17bVZbZfF3xOEK bEQA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The PCIe controller in rk3568 and rk3588 can operate in endpoint mode. This endpoint mode support heavily leverages the existing code in pcie-designware-ep.c. Add support for endpoint mode to the existing pcie-dw-rockchip glue driver. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/Kconfig | 17 ++- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 210 ++++++++++++++++++++++++++ 2 files changed, 224 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 8afacc90c63b..9fae0d977271 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -311,16 +311,27 @@ config PCIE_RCAR_GEN4_EP SoCs. To compile this driver as a module, choose M here: the module will be called pcie-rcar-gen4.ko. This uses the DesignWare core. +config PCIE_ROCKCHIP_DW + bool + config PCIE_ROCKCHIP_DW_HOST - bool "Rockchip DesignWare PCIe controller" - select PCIE_DW + bool "Rockchip DesignWare PCIe controller (host mode)" select PCIE_DW_HOST depends on PCI_MSI depends on ARCH_ROCKCHIP || COMPILE_TEST depends on OF help Enables support for the DesignWare PCIe controller in the - Rockchip SoC except RK3399. + Rockchip SoC (except RK3399) to work in host mode. + +config PCIE_ROCKCHIP_DW_EP + bool "Rockchip DesignWare PCIe controller (endpoint mode)" + select PCIE_DW_EP + depends on ARCH_ROCKCHIP || COMPILE_TEST + depends on OF + help + Enables support for the DesignWare PCIe controller in the + Rockchip SoC (except RK3399) to work in endpoint mode. config PCI_EXYNOS tristate "Samsung Exynos PCIe controller" diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index e133511692af..347721207161 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -34,10 +34,16 @@ #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) #define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) #define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) +#define PCIE_CLIENT_INTR_STATUS_MISC 0x10 +#define PCIE_CLIENT_INTR_MASK_MISC 0x24 #define PCIE_SMLH_LINKUP BIT(16) #define PCIE_RDLH_LINKUP BIT(17) #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) #define PCIE_L0S_ENTRY 0x11 #define PCIE_CLIENT_GENERAL_CONTROL 0x0 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 @@ -63,6 +69,7 @@ struct rockchip_pcie { struct rockchip_pcie_of_data { enum dw_pcie_device_mode mode; + const struct pci_epc_features *epc_features; }; static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg) @@ -159,6 +166,12 @@ static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) PCIE_CLIENT_GENERAL_CONTROL); } +static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip) +{ + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM, + PCIE_CLIENT_GENERAL_CONTROL); +} + static int rockchip_pcie_link_up(struct dw_pcie *pci) { struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); @@ -195,6 +208,13 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci) return 0; } +static void rockchip_pcie_stop_link(struct dw_pcie *pci) +{ + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + + rockchip_pcie_disable_ltssm(rockchip); +} + static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -220,6 +240,82 @@ static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { .init = rockchip_pcie_host_init, }; +static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar; + + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) + dw_pcie_ep_reset_bar(pci, bar); +}; + +static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + unsigned int type, u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_IRQ_INTX: + return dw_pcie_ep_raise_intx_irq(ep, func_no); + case PCI_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + case PCI_IRQ_MSIX: + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + } + + return 0; +} + +static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = { + .linkup_notifier = true, + .msi_capable = true, + .msix_capable = true, + .align = SZ_64K, + .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, +}; + +/* + * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of + * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver, + * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by + * default.) If the host could write to BAR4, the iATU settings (for all other + * BARs) would be overwritten, resulting in (all other BARs) no longer working. + */ +static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { + .linkup_notifier = true, + .msi_capable = true, + .msix_capable = true, + .align = SZ_64K, + .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, + .bar[BAR_4] = { .type = BAR_RESERVED, }, + .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, }, +}; + +static const struct pci_epc_features * +rockchip_pcie_get_features(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + + return rockchip->data->epc_features; +} + +static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = { + .init = rockchip_pcie_ep_init, + .raise_irq = rockchip_pcie_raise_irq, + .get_features = rockchip_pcie_get_features, +}; + static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->pci.dev; @@ -290,13 +386,47 @@ static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip) static const struct dw_pcie_ops dw_pcie_ops = { .link_up = rockchip_pcie_link_up, .start_link = rockchip_pcie_start_link, + .stop_link = rockchip_pcie_stop_link, }; +static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg) +{ + struct rockchip_pcie *rockchip = arg; + struct dw_pcie *pci = &rockchip->pci; + struct device *dev = pci->dev; + u32 reg, val; + + reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); + + dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg); + dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip)); + + if (reg & PCIE_LINK_REQ_RST_NOT_INT) { + dev_dbg(dev, "hot reset or link-down reset\n"); + dw_pcie_ep_linkdown(&pci->ep); + } + + if (reg & PCIE_RDLH_LINK_UP_CHGED) { + val = rockchip_pcie_get_ltssm(rockchip); + if ((val & PCIE_LINKUP) == PCIE_LINKUP) { + dev_dbg(dev, "link up\n"); + dw_pcie_ep_linkup(&pci->ep); + } + } + + rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); + + return IRQ_HANDLED; +} + static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip) { struct dw_pcie_rp *pp; u32 val; + if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST)) + return -ENODEV; + /* LTSSM enable control mode */ val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); @@ -310,6 +440,63 @@ static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip) return dw_pcie_host_init(pp); } +static int rockchip_pcie_configure_ep(struct platform_device *pdev, + struct rockchip_pcie *rockchip) +{ + struct device *dev = &pdev->dev; + int irq, ret; + u32 val; + + if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP)) + return -ENODEV; + + irq = platform_get_irq_byname(pdev, "sys"); + if (irq < 0) { + dev_err(dev, "missing sys IRQ resource\n"); + return irq; + } + + ret = devm_request_threaded_irq(dev, irq, NULL, + rockchip_pcie_ep_sys_irq_thread, + IRQF_ONESHOT, "pcie-sys", rockchip); + if (ret) { + dev_err(dev, "failed to request PCIe sys IRQ\n"); + return ret; + } + + /* LTSSM enable control mode */ + val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE, + PCIE_CLIENT_GENERAL_CONTROL); + + rockchip->pci.ep.ops = &rockchip_pcie_ep_ops; + rockchip->pci.ep.page_size = SZ_64K; + + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + + ret = dw_pcie_ep_init(&rockchip->pci.ep); + if (ret) { + dev_err(dev, "failed to initialize endpoint\n"); + return ret; + } + + ret = dw_pcie_ep_init_registers(&rockchip->pci.ep); + if (ret) { + dev_err(dev, "failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(&rockchip->pci.ep); + return ret; + } + + dw_pcie_ep_init_notify(&rockchip->pci.ep); + + /* unmask DLL up/down indicator and hot reset/link-down reset */ + rockchip_pcie_writel_apb(rockchip, 0x60000, PCIE_CLIENT_INTR_MASK_MISC); + + return ret; +} + static int rockchip_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -371,6 +558,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev) if (ret) goto deinit_clk; break; + case DW_PCIE_EP_TYPE: + ret = rockchip_pcie_configure_ep(pdev, rockchip); + if (ret) + goto deinit_clk; + break; default: dev_err(dev, "INVALID device type %d\n", data->mode); ret = -EINVAL; @@ -394,11 +586,29 @@ static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = { .mode = DW_PCIE_RC_TYPE, }; +static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = { + .mode = DW_PCIE_EP_TYPE, + .epc_features = &rockchip_pcie_epc_features_rk3568, +}; + +static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = { + .mode = DW_PCIE_EP_TYPE, + .epc_features = &rockchip_pcie_epc_features_rk3588, +}; + static const struct of_device_id rockchip_pcie_of_match[] = { { .compatible = "rockchip,rk3568-pcie", .data = &rockchip_pcie_rc_of_data_rk3568, }, + { + .compatible = "rockchip,rk3568-pcie-ep", + .data = &rockchip_pcie_ep_of_data_rk3568, + }, + { + .compatible = "rockchip,rk3588-pcie-ep", + .data = &rockchip_pcie_ep_of_data_rk3588, + }, {}, }; From patchwork Wed May 29 08:29:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678342 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A31D16C451; Wed, 29 May 2024 08:29:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971399; cv=none; b=c9dng8pq3kwalexeIz9srQtr8GxG8nFkwL3/MwwUgcKq9BNIa/ugH+Mv7xkwZvvnqDsDkpdxQOjxz74OyctuGcsiu0Qh6hjCfptadLzC+/SgUcFn034Br9vqRlFZUUOblQO67JQo2VKUku9NDpgJtigQfOBtVpOIR9694NmxvAI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971399; c=relaxed/simple; bh=RLD5Nn+8JjuWpy1BZvj15mTHLVP0CnrW2Huj0XxmdF4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=g5X29/Qa7fL5TxKGxWUNINj1jFX3z8Y4JOPjokTo/Q+9USQ8Mdn1XAadKV7d6I2aMNx6MYvJuwo1wFMe2XPjIrrmCWjKiGJUlM1DVwW8J+rAl0CBQzDVyP7emrnhJ9lWC9c9Zf3ox764gDZGkXk9ICCEVqOV1minxhdo3RrO9fA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pOwVFbbe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pOwVFbbe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA183C32781; Wed, 29 May 2024 08:29:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971399; bh=RLD5Nn+8JjuWpy1BZvj15mTHLVP0CnrW2Huj0XxmdF4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pOwVFbbeGA2yhuzOQzBEs5rWojusiFmM6z5sC1QVRvrocGA7/kvhrcy3lHRPrHF5u mel2+xeU3zzF6HWp967e/EeTxcyhZPSnwWv2F6ifp8SA7luneQV+LdccCAykmlqjxm TmH8ApCQ81dchGVfMZYJ9WtwW4rEAucVNbopJpkRHJ1B2MsIuy1QQmI8LJFEJ5MKaS 3Wnng2VIMI/2HO2arZ3FMcbfbaUCQmUypnQTR57Xfw6zS6GataXxaqaSiZ/CKS2QYp Ehc80hB+MXn3DdxPbiaX1ubaf/YVwp1pGebS5Xl+U0LoZVoEIumDxv8heP40Jscg7P wEzox/S2VtWuA== From: Niklas Cassel Date: Wed, 29 May 2024 10:29:05 +0200 Subject: [PATCH v4 11/13] misc: pci_endpoint_test: Add support for rockchip rk3588 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-11-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2359; i=cassel@kernel.org; h=from:subject:message-id; bh=RLD5Nn+8JjuWpy1BZvj15mTHLVP0CnrW2Huj0XxmdF4=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnofmxn15sEJFrm1X1KlpVW49e49d6DUvPLFueW/Yf N35VnJ7OkpZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjCRtkxGhlUV04K/dTpa+CX0 Mlv7sHq9EM4WOsjS2uvbnb3LNS6wlpHhQOvs7Vc1td/HXXWz2n217lvZ1bq1B97MfTj7rETzESk lNgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Rockchip rk3588 requires 64k alignment. While there is an existing device_id:vendor_id in the driver with 64k alignment, that device_id:vendor_id is am654, which uses BAR2 instead of BAR0 as the test_reg_bar, and also has special is_am654_pci_dev() checks in the driver to disallow BAR0. In order to allow testing all BARs, add a new rk3588 entry in the driver. We intentionally do not add the vendor id to pci_ids.h, since the policy for that file is that the vendor id has to be used by multiple drivers. Hopefully, this new entry will be short-lived, as there is a series on the mailing list which intends to move the address alignment restrictions from this driver to the endpoint side. Add a new entry for rk3588 in order to allow us to test all BARs. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/misc/pci_endpoint_test.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 4f3ec1f2ba9f..0ffc8e02b863 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -85,6 +85,9 @@ #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025 #define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031 +#define PCI_VENDOR_ID_ROCKCHIP 0x1d87 +#define PCI_DEVICE_ID_ROCKCHIP_RK3588 0x3588 + static DEFINE_IDA(pci_endpoint_test_ida); #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ @@ -1006,6 +1009,11 @@ static const struct pci_endpoint_test_data j721e_data = { .irq_type = IRQ_TYPE_MSI, }; +static const struct pci_endpoint_test_data rk3588_data = { + .alignment = SZ_64K, + .irq_type = IRQ_TYPE_MSI, +}; + static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x), .driver_data = (kernel_ulong_t)&default_data, @@ -1043,6 +1051,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721S2), .driver_data = (kernel_ulong_t)&j721e_data, }, + { PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588), + .driver_data = (kernel_ulong_t)&rk3588_data, + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); From patchwork Wed May 29 08:29:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678343 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18CAF1667C1; Wed, 29 May 2024 08:30:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716971404; cv=none; b=o2i290FTAwYdcpdhrRF/IvA1DbVzEXjoNmZ3+SLMI002wWYtjo/aVkkJXaw1oD3lcs+hIzDDcRQTIwS7EM043KvnbMJsIi42gtW8nKb4AM+0pN+n+58D6RNJBY+9LODPSjXx0DswGcL9KdykQgcbn0XFnZvEdnwyR2o/t5j5Urk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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a=openpgp-sha256; l=2324; i=cassel@kernel.org; h=from:subject:message-id; bh=9PVV++LUhN+71aXrADyChLLN+FW6M4sy+ZWci6a3+vk=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnofurVS6PnltS12B0pmfRSrTiko78nYoPArS9noi4 2fbdftlRykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACZisZCRYXLE0fXaRcG38+dr nf/00WHXV4OUtJNvBQ2efuJv6fTbw8TwP/FL+4p4oafuJxO102PDPKpElOvl7my81Bi90nVG3Dk xLgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add a device tree node representing PCIe endpoint mode. The controller can either be configured to run in Root Complex or Endpoint node. If a user wants to run the controller in endpoint mode, the user has to disable the pcie3x4 node and enable the pcie3x4_ep node. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 5984016b5f96..6b5bf1055143 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -186,6 +186,41 @@ pcie3x4_intc: legacy-interrupt-controller { }; }; + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + }; + pcie3x2: pcie@fe160000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; From patchwork Wed May 29 08:29:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13678344 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 345C416D9BE; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cBw9VvBc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1AF23C2BD10; Wed, 29 May 2024 08:30:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716971407; bh=LO909Qkb49dF2RDbiXWZUtB58HFe23RYE1wbMe1vcLI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cBw9VvBcV1o5536nQZc+jpLoTRiQB5iWrsAWafOAX/+iRPbfpmCEevODeAijFiVFH is94eFUQkngtapUPj33iBBOa5dG2GDrM1ZYUZhfwcQNC1iNlypwGCDSfba9zyf6v/f VflaC03AdPaIXD5guCFfFF6r4R/lS4SmKBR5K7gDmlAbbFXI0faWNyOlCk5hLjK0ts 2Sz1W2GoYhQ5tDvG7HiV5gNSY+eatigFxHD0dymvuXdWxVR5i15ATFCW2GEGJGxYQH bd+jUUuHvqzy997jyv8GBc5ua68u8vZItG87JMaSd76wVBg5lTeY1HqWmj98LFDaeY JtcVMqaAeAirw== From: Niklas Cassel Date: Wed, 29 May 2024 10:29:07 +0200 Subject: [PATCH v4 13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-rockchip-pcie-ep-v1-v4-13-3dc00fe21a78@kernel.org> References: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> In-Reply-To: <20240529-rockchip-pcie-ep-v1-v4-0-3dc00fe21a78@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3452; i=cassel@kernel.org; h=from:subject:message-id; bh=LO909Qkb49dF2RDbiXWZUtB58HFe23RYE1wbMe1vcLI=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLCnoc2R3GI9XocrK5x5whJLLWw3H6w5YDYHdaFQpxun 56EfJvWUcrCIMbFICumyOL7w2V/cbf7lOOKd2xg5rAygQxh4OIUgIm4ljEybMjbMmMnU1Hikoyu dfqWC2K+fnv3mn8uVwKTp4Og13cZc0aGX7pr+0xiU+/LxKzf6pSs/m/RX28+Dln7dr+yfw6L+K7 zAgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Add rock5b overlays for PCIe endpoint mode support. If using the rock5b as an endpoint against a normal PC, only the rk3588-rock-5b-pcie-ep.dtbo needs to be applied. If using two rock5b:s, with one board as EP and the other board as RC, rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to be applied to the respective boards. Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/Makefile | 5 +++++ .../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++ .../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f42fa62b4064..df7f5103b018 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb @@ -134,3 +136,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb + +# Enable support for device-tree overlays +DTC_FLAGS_rk3588-rock-5b += -@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso new file mode 100644 index 000000000000..672d748fcc67 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode + * in the SRNS (Separate Reference Clock No Spread) configuration. + * + * NOTE: If using a setup with two ROCK 5B:s, with one board running in + * RC mode and the other board running in EP mode, see also the device + * tree overlay: rk3588-rock-5b-pcie-srns.dtso. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&pcie3x4_ep { + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso new file mode 100644 index 000000000000..1a0f1af65c43 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex + * mode in the SRNS (Separate Reference Clock No Spread) configuration. + * + * This device tree overlay is only needed (on the RC side) when running + * a setup with two ROCK 5B:s, with one board running in RC mode and the + * other board running in EP mode. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +};