From patchwork Wed May 29 09:38:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13678540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A2C1C27C43 for ; Wed, 29 May 2024 09:39:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D7AEB10E021; Wed, 29 May 2024 09:39:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Vrv5jrHa"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3247B10EF0D for ; Wed, 29 May 2024 09:39:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716975544; x=1748511544; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+T8QYM7VTAKcx8dLe7nYpDytqwXJZ01fZG17Li7rY4M=; b=Vrv5jrHaBk2Bi3G1y1gczlrUvNLidXO3LWFfDBDU4o+zYY6QpKrcsgu3 H3qrM77WWNBww2pzEdB/nJ19y81F6k2V1pIvLZDlmFBR16Q3qlDW/ygXK iNY9O/LpH04B5a0dfYAGh4L/tNcVZUAF4W/PvE9SqIb+aWpnFC5qPP9KM jGaEQWu8VFT3Jdg0FuSdJ9Y223iAY2nAmiazurb2iH+rM8m6ZYb+KiR29 Xa7q9fIaV2eVJVTshoHnahPhpoibaoaZYmDNHUyqFkBgia2US/Ph12JPa sNf1DoWG1TWx24KnN5G/ahHtkIkTsIbIT+8T2X1wYSQs0sTxHhCnc1Nan Q==; X-CSE-ConnectionGUID: hugeZzX0TDaP0XAnr/zqNA== X-CSE-MsgGUID: 1jpF+gJaSBOuRZflzi+irQ== X-IronPort-AV: E=McAfee;i="6600,9927,11085"; a="16316810" X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="16316810" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:04 -0700 X-CSE-ConnectionGUID: 7q8L8koZQe6tj1O/ISe4RQ== X-CSE-MsgGUID: O+Ui/G7zSXKsiOsjtXyRyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="40273881" Received: from romanove-mobl.ger.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.36.185]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:03 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 1/6] drm/i915/psr: Add Early Transport status boolean into intel_psr Date: Wed, 29 May 2024 12:38:44 +0300 Message-Id: <20240529093849.1016172-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240529093849.1016172-1-jouni.hogander@intel.com> References: <20240529093849.1016172-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we are purely relying on psr2_su_region_et_valid. Add new boolean value into intel_psr struct indicating whether Early Transport is enabled or not and use it instead of psr2_su_region_et_valid for getting Early Transport status information. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 6fbfe8a18f45..739baf4bb66e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1703,6 +1703,7 @@ struct intel_psr { bool sel_update_enabled; bool psr2_sel_fetch_enabled; bool psr2_sel_fetch_cff_enabled; + bool su_region_et_enabled; bool req_psr2_sdp_prior_scanline; u8 sink_sync_latency; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 19f8ac12f995..4c92e47d4fa3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -978,7 +978,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0); } - if (psr2_su_region_et_valid(intel_dp)) + if (intel_dp->psr.su_region_et_enabled) val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; /* @@ -2050,6 +2050,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, intel_dp->psr.dc3co_exit_delay = val; intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; + intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; intel_dp->psr.req_psr2_sdp_prior_scanline = crtc_state->req_psr2_sdp_prior_scanline; @@ -2206,6 +2207,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_dp->psr.panel_replay_enabled = false; intel_dp->psr.sel_update_enabled = false; intel_dp->psr.psr2_sel_fetch_enabled = false; + intel_dp->psr.su_region_et_enabled = false; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; } From patchwork Wed May 29 09:38:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13678541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2882FC25B75 for ; Wed, 29 May 2024 09:39:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5892F10EE81; Wed, 29 May 2024 09:39:08 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ax8TINm1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0AFBD10E0BB for ; Wed, 29 May 2024 09:39:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716975546; x=1748511546; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2rUYfvoM/yUIS8bq6s4igvY0Up1UA9Wh8roGrPt1JZo=; b=Ax8TINm1e4PY4MVzgMcFgk3Kja2poJBlR0WxG8mnfGrDnWx1qdIlIb/U Ul2VluIUVya0eXWLx38g/4HHHDdIFR+MA5mV8PHq6jrunqsUpNAUyEEeM NXAFgtdkrayk7/D6YX6ft+3DjDbpTDBcAGpraSTG4D4YyzChlwwmS0ImD 4+H+V61XEppP1sTLXTkHE7gY1g7Fj09aLxS4BxSc24judB5EWGQohpWXI xYt8leQvkUav1wMLE6R6C8GwTVDE2mAQqMDtDCGQ4ZUed710mVXtp9pnW znl8aOmOuLiHOzVgpJnl9d4Mf2Uw90RxbPiHE4+2K3ehzug1AEclKy5oE Q==; X-CSE-ConnectionGUID: 5SaH6PthQ4CN30z+uPWCKg== X-CSE-MsgGUID: GlLCnaENQzm9dUAdqLoJiQ== X-IronPort-AV: E=McAfee;i="6600,9927,11085"; a="16316811" X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="16316811" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:06 -0700 X-CSE-ConnectionGUID: WmR9PFQoSpOKw2mpC+yEeQ== X-CSE-MsgGUID: E4bV+cI/QxK0skg5NrTC3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="40273884" Received: from romanove-mobl.ger.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.36.185]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:05 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 2/6] drm/i915/psr: Get Early Transport status in intel_psr_pipe_get_config Date: Wed, 29 May 2024 12:38:45 +0300 Message-Id: <20240529093849.1016172-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240529093849.1016172-1-jouni.hogander@intel.com> References: <20240529093849.1016172-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We are currently not getting Early Transport status information in intel_psr_pipe_get_config. Fix this. Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4c92e47d4fa3..1e55d447481a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1757,6 +1757,8 @@ void intel_psr_get_config(struct intel_encoder *encoder, pipe_config->enable_psr2_sel_fetch = true; } + pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; + if (DISPLAY_VER(dev_priv) >= 12) { val = intel_de_read(dev_priv, TRANS_EXITLINE(dev_priv, cpu_transcoder)); From patchwork Wed May 29 09:38:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13678542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97CB5C25B75 for ; Wed, 29 May 2024 09:39:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D112910E0BB; Wed, 29 May 2024 09:39:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GDmFHQCR"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id DD38D10E0BB for ; Wed, 29 May 2024 09:39:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716975548; x=1748511548; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c9kpFuTh+5WUlEneBvfvSugvnrUclTc3/I9G7J4M7uQ=; b=GDmFHQCRQmfbwwJyHgXos3azJdOgySRlgYuWXrjXM5/AHf6/R2KUHtAI +ZNBHQamT8SP/7zjaZ8wP5sKE+8Wajs4h6w/cEYm63LgWZ4hNudDF3okI ckhi570k4P+rs/5Mrf6tPeqHNtJqW1ikIclIKmTxF3LUkEKQ9XboAivon RGENyalLRCUTWk0/v9SpOfuKMGbc3O/DBTqZkOr5cQ+D1ROyQA9E5APp3 0XfhhkjqAKH+dypyb2A+zoS6FjbhN0GuKTlWB0ipQR/DFI+YDJBmGwPO8 TVh0VfnnUw22Y89wDxxE/7CQV23ohfNMwz0kMgawXQ1uBnR2yqsuPcxS4 A==; X-CSE-ConnectionGUID: ASjqzPM3RdWKmYPQGwecuw== X-CSE-MsgGUID: 0vrdPhjzTL+fGgWrr2txXQ== X-IronPort-AV: E=McAfee;i="6600,9927,11085"; a="16316812" X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="16316812" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:08 -0700 X-CSE-ConnectionGUID: s9Sfrd/dSRmbrUu9wb42Qw== X-CSE-MsgGUID: iJadkHkbR8KMgrzTSe2/CA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="40273887" Received: from romanove-mobl.ger.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.36.185]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:06 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 3/6] drm/i915/psr: Use enable boolean from intel_crtc_state for Early Transport Date: Wed, 29 May 2024 12:38:46 +0300 Message-Id: <20240529093849.1016172-4-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240529093849.1016172-1-jouni.hogander@intel.com> References: <20240529093849.1016172-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" When enabling Early Transport use intel_crtc_state->enable_psr2_su_region_et instead of psr2_su_region_et_valid. Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1e55d447481a..605ca6b6321d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -709,7 +709,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp, DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); - if (psr2_su_region_et_valid(intel_dp)) + if (crtc_state->enable_psr2_su_region_et) dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET; } From patchwork Wed May 29 09:38:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13678544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C24CAC27C43 for ; Wed, 29 May 2024 09:39:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F016A10E3C3; Wed, 29 May 2024 09:39:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FLmpncAi"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5FD7810F5B4 for ; Wed, 29 May 2024 09:39:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716975550; x=1748511550; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B5biMBXaqHsgMjvKiabm/ekIayOo7VFPZMTKvVbv7+o=; b=FLmpncAihaLr/taBZ+bz5R0QQwCdEAOuwEujkGT9HWGJVjc/zFXL6uFj 5ckihVexFCidCS6OL2AbofBwicVWkvEZ1OiqkpKxTQhE6LEGJML1tjnBt n+fk/TIoZiPOUgOtJK9vWZKQgUAuiKAOet2RL8APwfPOsDlpXok74+Txg 8eXmivhjurh8FrI32d35Bax6k0o1n9LE5c/BOh99yW2zNEKsAnMhRdR9w QSkvJR1V6pIzUbnXaz1HA42C3n17spH5aNL87+BWjXoAE4Ql0Ge15Dik7 DNVZqsHuTaVv87uEu2ihYckiH4qNLeMfTH+crOdRGERGt4OscoPeuomZY A==; X-CSE-ConnectionGUID: 3+Icej0NRxWFI/2IJjfX3g== X-CSE-MsgGUID: gQuX2S4uSraijxZ0DwEKgA== X-IronPort-AV: E=McAfee;i="6600,9927,11085"; a="16316817" X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="16316817" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:09 -0700 X-CSE-ConnectionGUID: gjcZ90tXSMeBanhDehif+Q== X-CSE-MsgGUID: 7PGcXzLxT6226n37yCKoLg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="40273890" Received: from romanove-mobl.ger.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.36.185]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:08 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 4/6] drm/i915/display: Selective fetch Y position on Region Early Transport Date: Wed, 29 May 2024 12:38:47 +0300 Message-Id: <20240529093849.1016172-5-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240529093849.1016172-1-jouni.hogander@intel.com> References: <20240529093849.1016172-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Selective fetch Y position differs when Region Early Transport is used. Use formula from Bspec for this. Bspec: 68927 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index b7678b8a7f3d..1aa70fc35b9d 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1302,7 +1302,11 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane, clip = &plane_state->psr2_sel_fetch_area; - val = (clip->y1 + plane_state->uapi.dst.y1) << 16; + if (crtc_state->enable_psr2_su_region_et) + y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1); + else + y = (clip->y1 + plane_state->uapi.dst.y1); + val = y << 16; val |= plane_state->uapi.dst.x1; intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val); From patchwork Wed May 29 09:38:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13678545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91362C27C44 for ; Wed, 29 May 2024 09:39:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 71AF010F572; Wed, 29 May 2024 09:39:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fqLuDMMM"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5C84A10EF88 for ; Wed, 29 May 2024 09:39:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716975551; x=1748511551; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=31zHeYzB9e4MOX3QXKl+EaJqX6IRbPiJouZRBRxmz34=; b=fqLuDMMMcx5Nj/AAJoxNjoTHT/ctaRZwGZZM91a9QrH8/Q6LLhGRzrf3 RC6x70fGNicdnu3Aq7qo5hH2/32MYYEwE9kC9Phi0FavaV+Mxl+E9OLPt jiINmti550ulIiiiKvYTe64sDtzpXqVzCKVvnj4iKw/PcFvQMLfwPXOyv acLcnZHMNDMUkbd4CTn+UASPtiNXpY2Vt8l0KLYdUQReWo4mgq54Xlm1u 8TeWnR+aEW+bhLDPQnJY62HEWQ70DEDCjp64Nokd0xlO/UmqcKcs9A0M4 5xmhC2nZtZaLisUtQBxHfkbsygMpHOZMfibstuVPAByMGM/nPom+6wGj0 Q==; X-CSE-ConnectionGUID: PWsgI7+yQZyo/k8olab46g== X-CSE-MsgGUID: SzCxn1j0QRa8VNN4y4kBqQ== X-IronPort-AV: E=McAfee;i="6600,9927,11085"; a="16316832" X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="16316832" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:11 -0700 X-CSE-ConnectionGUID: WnpZNUlUR1uQsN3Cuk/vGA== X-CSE-MsgGUID: vJLrftzeQbCXWxMjgZuQdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="40273893" Received: from romanove-mobl.ger.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.36.185]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:10 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 5/6] drm/i915/psr: Allow setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE via debugfs Date: Wed, 29 May 2024 12:38:48 +0300 Message-Id: <20240529093849.1016172-6-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240529093849.1016172-1-jouni.hogander@intel.com> References: <20240529093849.1016172-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE (0x20) via psr_debug debugfs interface is not allowed. This patch allows it. v3: - ensure psr is disabled/enabled if enable_psr2_su_region_et changes - remove extra space v2: ensure that fastset is performed when the bit changes Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 605ca6b6321d..16fa70c3ae45 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2773,12 +2773,15 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, * - PSR disabled in new state * - All planes will go inactive * - Changing between PSR versions + * - Region Early Transport changing * - Display WA #1136: skl, bxt */ needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); needs_to_disable |= !new_crtc_state->has_psr; needs_to_disable |= !new_crtc_state->active_planes; needs_to_disable |= new_crtc_state->has_sel_update != psr->sel_update_enabled; + needs_to_disable |= new_crtc_state->enable_psr2_su_region_et != + psr->su_region_et_enabled; needs_to_disable |= DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled; @@ -3014,10 +3017,12 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; - u32 old_mode; + const u32 disable_bits = val & I915_PSR_DEBUG_SU_REGION_ET_DISABLE; + u32 old_mode, old_disable_bits; int ret; - if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || + if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | + I915_PSR_DEBUG_MODE_MASK) || mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); return -EINVAL; @@ -3028,6 +3033,8 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) return ret; old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; + old_disable_bits = intel_dp->psr.debug & + I915_PSR_DEBUG_SU_REGION_ET_DISABLE; intel_dp->psr.debug = val; /* @@ -3039,7 +3046,7 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) mutex_unlock(&intel_dp->psr.lock); - if (old_mode != mode) + if (old_mode != mode || old_disable_bits != disable_bits) ret = intel_psr_fastset_force(dev_priv); return ret; From patchwork Wed May 29 09:38:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13678543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B29A4C27C44 for ; Wed, 29 May 2024 09:39:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 07F7E10E63D; Wed, 29 May 2024 09:39:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="neYa/x5O"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1632A10E0BB for ; Wed, 29 May 2024 09:39:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716975554; x=1748511554; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tZ/m8pX92qX8oNx27zJTHumfkPQhl7DUVtWtcy8j59c=; b=neYa/x5O4Tz7YWBmA6EqWH7DVYI/xR5KBNVRcJudxBRZH7IYMPb3m0ep 05RJ3bEXg2nsiRr/TBLLuRxq8XQXHSrnRWBC7NSnoESkcBkLU4jl3vVRg N4VKbe+K6iaJNCNaaipXFxVUodu1Ak0jQUVSWGBbo6prBaUSiBSGvz3GU OdiAPi6czRRdW5pJewgIqXYeEZ0aBHdd5ikRZUmyqT16nGA4wL0L24R7C h5I7hVfpswY/vMtE+KbfRtsyQ0wBECbCquXXMHh+qWTkb5FxwFgeq3eYg ocV0XQ48LYAyToBK2AObTpeR2k21z48WMMZgE5lKkEIGOJr4myzxZ2jZy Q==; X-CSE-ConnectionGUID: 2uDLT80kS66+kvuVo/d+hQ== X-CSE-MsgGUID: oMsuXZi6Sci//I/IMfQLxQ== X-IronPort-AV: E=McAfee;i="6600,9927,11085"; a="16316836" X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="16316836" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:13 -0700 X-CSE-ConnectionGUID: m0fVwQcMRWaNN8lVGOK0Aw== X-CSE-MsgGUID: tPe2DpheRlSgRnBMfiXxaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,198,1712646000"; d="scan'208";a="40273896" Received: from romanove-mobl.ger.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.249.36.185]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2024 02:39:12 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH 6/6] drm/i915/psr: Add Early Transport into psr debugfs interface Date: Wed, 29 May 2024 12:38:49 +0300 Message-Id: <20240529093849.1016172-7-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240529093849.1016172-1-jouni.hogander@intel.com> References: <20240529093849.1016172-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We want to have sink Early Transport capability and usage in our psr debugfs status interface. v4: use su_region_et_enabled instead of psr2_su_region_et_valid v3: remove extra space from "PSR mode: disabled" v2: printout "Selective Update enabled (Early Transport)" instead of "Selective Update Early Transport enabled" Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 35 ++++++++++++++++++------ 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 16fa70c3ae45..c2318fb60f54 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3611,25 +3611,44 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp, if (psr->sink_support) seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); + if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) + seq_printf(m, " (Early Transport)"); seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); - seq_printf(m, ", Panel Replay Selective Update = %s\n", + seq_printf(m, ", Panel Replay Selective Update = %s", str_yes_no(psr->sink_panel_replay_su_support)); + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) + seq_printf(m, " (Early Transport)"); + seq_printf(m, "\n"); } static void intel_psr_print_mode(struct intel_dp *intel_dp, struct seq_file *m) { struct intel_psr *psr = &intel_dp->psr; - const char *status; + const char *status, *mode, *region_et; - if (psr->panel_replay_enabled) - status = psr->sel_update_enabled ? "Panel Replay Selective Update Enabled" : - "Panel Replay Enabled"; - else if (psr->enabled) - status = psr->sel_update_enabled ? "PSR2" : "PSR1"; + if (psr->enabled) + status = " enabled"; else status = "disabled"; - seq_printf(m, "PSR mode: %s\n", status); + + if (psr->panel_replay_enabled && psr->sel_update_enabled) + mode = "Panel Replay Selective Update"; + else if (psr->panel_replay_enabled) + mode = "Panel Replay"; + else if (psr->sel_update_enabled) + mode = "PSR2"; + else if (psr->enabled) + mode = "PSR1"; + else + mode = ""; + + if (psr->su_region_et_enabled) + region_et = " (Early Transport)"; + else + region_et = ""; + + seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et); } static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)