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Add a new compatible string for i.MX91. Signed-off-by: Pengfei Li Reviewed-by: Frank Li --- Documentation/devicetree/bindings/clock/imx93-clock.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/imx93-clock.yaml b/Documentation/devicetree/bindings/clock/imx93-clock.yaml index ccb53c6b96c1..98c0800732ef 100644 --- a/Documentation/devicetree/bindings/clock/imx93-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx93-clock.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - fsl,imx91-ccm - fsl,imx93-ccm reg: From patchwork Thu May 30 02:26:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pengfei Li X-Patchwork-Id: 13678664 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2053.outbound.protection.outlook.com [40.107.20.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BD7D73475; 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Received: from DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) by DB9PR04MB8393.eurprd04.prod.outlook.com (2603:10a6:10:25f::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.19; Wed, 29 May 2024 10:30:48 +0000 Received: from DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84]) by DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84%4]) with mapi id 15.20.7611.030; Wed, 29 May 2024 10:30:48 +0000 From: Pengfei Li To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, ye.li@nxp.com, peng.fan@nxp.com, aisheng.dong@nxp.com, frank.li@nxp.com Cc: tharvey@gateworks.com, alexander.stein@ew.tq-group.com, gregor.herburger@ew.tq-group.com, hiago.franco@toradex.com, joao.goncalves@toradex.com, hvilleneuve@dimonoff.com, Markus.Niebel@ew.tq-group.com, m.felsch@pengutronix.de, m.othacehe@gmail.com, bhelgaas@google.com, leoyang.li@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, pengfei.li_1@nxp.com Subject: [PATCH v2 2/5] dt-bindings: clock: Add i.MX91 clock definition Date: Wed, 29 May 2024 19:26:31 -0700 Message-Id: <20240530022634.2062084-3-pengfei.li_1@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530022634.2062084-1-pengfei.li_1@nxp.com> References: <20240530022634.2062084-1-pengfei.li_1@nxp.com> X-ClientProxiedBy: AM0PR04CA0029.eurprd04.prod.outlook.com (2603:10a6:208:122::42) To DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB8PR04MB7065:EE_|DB9PR04MB8393:EE_ X-MS-Office365-Filtering-Correlation-Id: e670d2cd-396b-4b04-f5f4-08dc7fca67b1 X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|376005|1800799015|52116005|7416005|38350700005|921011; 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Add i.MX91 related clock definition. Signed-off-by: Pengfei Li Reviewed-by: Frank Li --- include/dt-bindings/clock/imx93-clock.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 787c9e74dc96..ca0785f35a46 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -204,6 +204,11 @@ #define IMX93_CLK_A55_SEL 199 #define IMX93_CLK_A55_CORE 200 #define IMX93_CLK_PDM_IPG 201 -#define IMX93_CLK_END 202 +#define IMX91_CLK_ENET1_QOS_TSN 202 +#define IMX91_CLK_ENET_TIMER 203 +#define IMX91_CLK_ENET2_REGULAR 204 +#define IMX91_CLK_ENET2_REGULAR_GATE 205 +#define IMX91_CLK_ENET1_QOS_TSN_GATE 206 +#define IMX93_CLK_END 207 #endif From patchwork Thu May 30 02:26:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pengfei Li X-Patchwork-Id: 13678665 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2045.outbound.protection.outlook.com [40.107.22.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 966A216EBEF; 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The design of the i.MX91 platform is very similar to i.MX93. The mainly difference between i.MX91 and i.MX93 is as follows: - i.MX91 removed some clocks and modified the names of some clocks. - i.MX91 only has one A core Signed-off-by: Pengfei Li Reviewed-by: Frank Li --- Notes: Change for v2: - refine the commit msg to supplement the differences between i.MX91 and i.MX93. arch/arm64/boot/dts/freescale/imx91-pinfunc.h | 770 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx91.dtsi | 66 ++ 2 files changed, 836 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx91.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx91-pinfunc.h b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h new file mode 100644 index 000000000000..bc58ce2102b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h @@ -0,0 +1,770 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2024 NXP + */ + +#ifndef __DTS_IMX91_PINFUNC_H +#define __DTS_IMX91_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x00 0x00 +#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x03 0x00 +#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0488 0x06 0x00 + +#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x00 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x06 0x00 + +#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x00 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x0484 0x06 0x00 + +#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x00 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x03 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x048C 0x06 0x00 + +#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01C0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03F4 0x01 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x04BC 0x02 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x048C 0x05 0x01 +#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x0404 0x06 0x00 +#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01C0 0x036C 0x07 0x00 + +#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01C4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03F0 0x01 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01C4 0x0490 0x02 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0488 0x05 0x01 +#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x0400 0x06 0x00 +#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01C4 0x0370 0x07 0x00 + +#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01C8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x03FC 0x01 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x04C0 0x02 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x0484 0x05 0x01 +#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x040C 0x06 0x00 +#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01C8 0x0374 0x07 0x00 + +#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001C 0x01CC 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x03F8 0x01 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x04B8 0x02 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x0408 0x06 0x00 +#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001C 0x01CC 0x0378 0x07 0x00 + +#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01D0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01D0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x040C 0x06 0x01 +#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01D0 0x037C 0x07 0x00 + +#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01D4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01D4 0x04C4 0x02 0x00 +#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01D4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x0408 0x06 0x01 +#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01D4 0x0380 0x07 0x00 + +#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01D8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01D8 0x04C8 0x02 0x00 +#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01D8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x0414 0x06 0x00 +#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01D8 0x0384 0x07 0x00 + +#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002C 0x01DC 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002C 0x01DC 0x0494 0x02 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002C 0x01DC 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x0410 0x06 0x00 +#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002C 0x01DC 0x0388 0x07 0x00 + +#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01E0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01E0 0x0498 0x02 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01E0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x0414 0x06 0x01 +#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01E0 0x038C 0x07 0x00 + +#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01E4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01E4 0x049C 0x02 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01E4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x0410 0x06 0x01 +#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01E4 0x0390 0x07 0x00 + +#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01E8 0x04A0 0x02 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01E8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x041C 0x06 0x00 +#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x07 0x00 + +#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003C 0x01EC 0x04A4 0x02 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003C 0x01EC 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0418 0x06 0x00 +#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x07 0x00 + +#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01F0 0x04CC 0x02 0x00 +#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01F0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x041C 0x06 0x01 +#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x04DC 0x07 0x00 + +#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01F4 0x04D0 0x02 0x00 +#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01F4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0418 0x06 0x01 +#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x07 0x00 + +#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x0474 0x01 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01F8 0x04A8 0x02 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0480 0x06 0x00 +#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x07 0x00 + +#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0470 0x01 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004C 0x01FC 0x04AC 0x02 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x047C 0x06 0x00 +#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x07 0x00 + +#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04CC 0x02 0x01 +#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046C 0x04 0x00 +#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00 +#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x07 0x00 + +#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04B0 0x02 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x07 0x00 + +#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04D8 0x01 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04B4 0x02 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x07 0x00 + +#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x04DC 0x01 0x01 +#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005C 0x020C 0x04D0 0x02 0x01 +#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005C 0x020C 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04C4 0x02 0x01 +#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x07 0x00 + +#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04D8 0x07 0x01 + +#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04E8 0x01 0x00 +#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04E4 0x02 0x00 +#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01 +#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x07 0x00 + +#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x04EC 0x01 0x00 +#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x0400 0x06 0x01 +#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x07 0x00 + +#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04F0 0x01 0x00 +#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x07 0x00 + +#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04F4 0x01 0x00 +#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x05 0x01 +#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x07 0x00 + +#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04F8 0x01 0x00 +#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04C8 0x02 0x01 +#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x05 0x01 +#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04E0 0x07 0x00 + +#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x04FC 0x01 0x00 +#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x02 0x01 +#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x05 0x01 +#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x07 0x00 + +#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03F4 0x01 0x01 +#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03F0 0x01 0x01 +#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00 +#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00 + +#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x05 0x00 +#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x04 0x01 + +#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x02 0x00 +#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03E0 0x06 0x00 + +#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x02 0x00 +#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009C 0x024C 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009C 0x024C 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009C 0x024C 0x03E4 0x06 0x00 + +#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00A0 0x0250 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD3__GPIO4_IO3 0x00A0 0x0250 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00A0 0x0250 0x03E8 0x06 0x00 + +#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00A4 0x0254 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x02 0x02 +#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00A4 0x0254 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00A4 0x0254 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00A4 0x0254 0x03EC 0x06 0x00 + +#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00A8 0x0258 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00A8 0x0258 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00A8 0x0258 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x06 0x00 + +#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x0474 0x01 0x01 +#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00AC 0x025C 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00AC 0x025C 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00B0 0x0260 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00B0 0x0260 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00B0 0x0260 0x043C 0x02 0x00 + +#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00B4 0x0264 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00B4 0x0264 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00B4 0x0264 0x0440 0x02 0x00 + +#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00B8 0x0268 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00B8 0x0268 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00B8 0x0268 0x0434 0x02 0x00 + +#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00BC 0x026C 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00BC 0x026C 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00BC 0x026C 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00BC 0x026C 0x0444 0x02 0x00 + +#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0470 0x01 0x01 +#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x046C 0x01 0x01 +#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0448 0x03 0x00 +#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x044C 0x03 0x00 +#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0450 0x03 0x00 +#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x05 0x00 + +#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00D0 0x0280 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00D0 0x0280 0x04BC 0x06 0x01 + +#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00D4 0x0284 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00D4 0x0284 0x0490 0x06 0x01 + +#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00D8 0x0288 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00D8 0x0288 0x04C0 0x06 0x01 +#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00D8 0x0288 0x0000 0x00 0x00 + +#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00DC 0x028C 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00DC 0x028C 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00DC 0x028C 0x04B8 0x06 0x01 + +#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00E0 0x0290 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00E0 0x0290 0x0494 0x06 0x01 + +#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00E4 0x0294 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0480 0x01 0x01 +#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00E4 0x0294 0x0498 0x06 0x01 + +#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00E8 0x0298 0x049C 0x06 0x01 + +#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00EC 0x029C 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00EC 0x029C 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00EC 0x029C 0x04A0 0x06 0x01 + +#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00F0 0x02A0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00F0 0x02A0 0x04A4 0x06 0x01 + +#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00F4 0x02A4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00F4 0x02A4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00F4 0x02A4 0x04A8 0x06 0x01 + +#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00F8 0x02A8 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x047C 0x01 0x01 +#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00F8 0x02A8 0x04AC 0x06 0x01 + +#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00FC 0x02AC 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x04E4 0x01 0x01 +#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00FC 0x02AC 0x04B0 0x06 0x01 + +#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02B0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0478 0x01 0x01 +#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02B0 0x04B4 0x06 0x01 + +#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02B4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x04E4 0x02 0x02 +#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x05 0x00 + +#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02B8 0x038C 0x04 0x01 +#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02B8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02B8 0x043C 0x03 0x01 + +#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010C 0x02BC 0x0390 0x04 0x01 +#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010C 0x02BC 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010C 0x02BC 0x0440 0x03 0x01 + +#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x04 0x01 +#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02C0 0x0434 0x03 0x01 + +#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x04 0x01 +#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02C4 0x0444 0x03 0x01 + +#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x04 0x00 +#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02C8 0x0438 0x03 0x00 + +#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x04 0x01 +#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011C 0x02CC 0x0424 0x03 0x00 + +#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02D0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x04 0x01 +#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02D0 0x0420 0x03 0x00 + +#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02D4 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x04 0x01 +#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02D4 0x042C 0x03 0x00 + +#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02D8 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x04 0x01 +#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02D8 0x0428 0x03 0x00 + +#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012C 0x02DC 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x04 0x01 +#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012C 0x02DC 0x0430 0x03 0x00 + +#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x04 0x01 +#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x00 0x00 +#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x01 0x00 +#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0450 0x02 0x01 +#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x04 0x00 +#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x05 0x00 +#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x06 0x00 + +#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x04E8 0x00 0x01 +#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02E8 0x0454 0x02 0x00 +#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x04 0x01 +#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x04EC 0x00 0x01 +#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013C 0x02EC 0x0000 0x02 0x00 +#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x04 0x00 +#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x04F0 0x00 0x01 +#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02F0 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02F0 0x0460 0x02 0x00 +#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x04 0x01 +#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x04F4 0x00 0x01 +#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02F4 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02F4 0x0000 0x02 0x00 +#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x04 0x01 +#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x04F8 0x00 0x01 +#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02F8 0x03FC 0x02 0x01 +#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02F8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x04 0x01 +#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x04FC 0x00 0x01 +#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014C 0x02FC 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014C 0x02FC 0x03F8 0x02 0x01 +#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x04 0x01 +#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x02 0x01 +#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036C 0x04 0x01 +#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03E0 0x03 0x01 + +#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x02 0x01 +#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01 +#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00 +#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03E4 0x03 0x01 + +#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01 +#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015C 0x030C 0x0378 0x04 0x01 +#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015C 0x030C 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015C 0x030C 0x045C 0x03 0x00 +#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03 +#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037C 0x04 0x01 +#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00 +#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01 +#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00 +#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01 +#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01 +#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00 +#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x00 0x00 +#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x044C 0x01 0x01 +#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016C 0x031C 0x0388 0x04 0x01 +#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016C 0x031C 0x0000 0x05 0x00 +#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x06 0x00 + +#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03E0 0x00 0x02 +#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00 + +#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03E4 0x00 0x02 +#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00 + +#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03E8 0x00 0x01 +#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00 +#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SCL__GPIO1_IO3 0x0178 0x0328 0x0000 0x05 0x00 +#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00 + +#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x03EC 0x00 0x01 +#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017C 0x032C 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01 +#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00 +#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02 +#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00 +#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045C 0x00 0x01 +#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00 +#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02 +#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00 +#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01 +#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01 +#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02 +#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00 +#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04D4 0x04 0x00 +#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0468 0x00 0x01 +#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x01 0x00 +#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x043C 0x02 0x02 +#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x03 0x00 +#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018C 0x033C 0x0000 0x05 0x00 +#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018C 0x033C 0x04E0 0x07 0x02 + +#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00 +#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00 +#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00 +#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00 +#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00 + +#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04C4 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01 + +#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04C8 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01 + +#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019C 0x034C 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0420 0x02 0x01 +#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0460 0x01 0x01 +#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x042C 0x02 0x01 +#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x04 0x02 +#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01A4 0x0354 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0428 0x02 0x01 +#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x05 0x00 +#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01A4 0x0354 0x04D4 0x06 0x01 + +#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01A8 0x0358 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x04D4 0x01 0x02 +#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0430 0x02 0x01 +#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x05 0x00 + +#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x00 0x00 +#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x05 0x00 +#endif /* __DTS_IMX91_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi new file mode 100644 index 000000000000..a9f4c1fe61cc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx91-pinfunc.h" +#include "imx93.dtsi" + +&{/thermal-zones/cpu-thermal/cooling-maps/map0} { + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&clk { + compatible = "fsl,imx91-ccm"; +}; + +&eqos { + clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; +}; + +&fec { + clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>, + <&clk IMX93_CLK_DUMMY>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; +}; + +&i3c1 { + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&i3c2 { + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&tmu { + status = "disabled"; +}; + +/* i.MX91 only has one A core */ +/delete-node/ &A55_1; + +/* i.MX91 not has cm33 */ +/delete-node/ &cm33; + +/* i.MX91 not has power-domain@44461800 */ +/delete-node/ &mlmix; From patchwork Thu May 30 02:26:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pengfei Li X-Patchwork-Id: 13678666 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2069.outbound.protection.outlook.com [40.107.22.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 085BB17B4FB; Wed, 29 May 2024 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kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, ye.li@nxp.com, peng.fan@nxp.com, aisheng.dong@nxp.com, frank.li@nxp.com Cc: tharvey@gateworks.com, alexander.stein@ew.tq-group.com, gregor.herburger@ew.tq-group.com, hiago.franco@toradex.com, joao.goncalves@toradex.com, hvilleneuve@dimonoff.com, Markus.Niebel@ew.tq-group.com, m.felsch@pengutronix.de, m.othacehe@gmail.com, bhelgaas@google.com, leoyang.li@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, pengfei.li_1@nxp.com Subject: [PATCH v2 4/5] dt-bindings: arm: fsl: Add i.MX91 11x11 evk board Date: Wed, 29 May 2024 19:26:33 -0700 Message-Id: <20240530022634.2062084-5-pengfei.li_1@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530022634.2062084-1-pengfei.li_1@nxp.com> References: <20240530022634.2062084-1-pengfei.li_1@nxp.com> X-ClientProxiedBy: AM0PR04CA0029.eurprd04.prod.outlook.com (2603:10a6:208:122::42) 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X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5744f888-75fd-4142-6577-08dc7fca761a X-MS-Exchange-CrossTenant-AuthSource: DB8PR04MB7065.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2024 10:31:12.5900 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Tu5wlVf21ewd0JdFqd/u+Efc4QyJsXuDJsMYCjwVSForRprVimA71ElaWSG1GnYH0YCZC0IyD/ZOgKttu7IYHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8393 Add the board imx91-11x11-evk in the binding docuemnt. Signed-off-by: Pengfei Li Reviewed-by: Frank Li Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6d185d09cb6a..41b487ed27fd 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1275,6 +1275,12 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 + - description: i.MX91 based Boards + items: + - enum: + - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board + - const: fsl,imx91 + - description: i.MXRT1050 based Boards items: - enum: From patchwork Thu May 30 02:26:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pengfei Li X-Patchwork-Id: 13678670 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2042.outbound.protection.outlook.com [40.107.22.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8874F17B4FC; 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Received: from DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) by DB9PR04MB8393.eurprd04.prod.outlook.com (2603:10a6:10:25f::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7633.19; Wed, 29 May 2024 10:31:24 +0000 Received: from DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84]) by DB8PR04MB7065.eurprd04.prod.outlook.com ([fe80::8af7:8659:9d42:bd84%4]) with mapi id 15.20.7611.030; Wed, 29 May 2024 10:31:24 +0000 From: Pengfei Li To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ping.bai@nxp.com, ye.li@nxp.com, peng.fan@nxp.com, aisheng.dong@nxp.com, frank.li@nxp.com Cc: tharvey@gateworks.com, alexander.stein@ew.tq-group.com, gregor.herburger@ew.tq-group.com, hiago.franco@toradex.com, joao.goncalves@toradex.com, hvilleneuve@dimonoff.com, Markus.Niebel@ew.tq-group.com, m.felsch@pengutronix.de, m.othacehe@gmail.com, bhelgaas@google.com, leoyang.li@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, pengfei.li_1@nxp.com Subject: [PATCH v2 5/5] arm64: dts: freescale: Add i.MX91 11x11 EVK basic support Date: Wed, 29 May 2024 19:26:34 -0700 Message-Id: <20240530022634.2062084-6-pengfei.li_1@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240530022634.2062084-1-pengfei.li_1@nxp.com> References: <20240530022634.2062084-1-pengfei.li_1@nxp.com> X-ClientProxiedBy: AM0PR04CA0029.eurprd04.prod.outlook.com (2603:10a6:208:122::42) To DB8PR04MB7065.eurprd04.prod.outlook.com (2603:10a6:10:127::9) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB8PR04MB7065:EE_|DB9PR04MB8393:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e6a4836-ab39-4c28-1676-08dc7fca7d14 X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|376005|1800799015|52116005|7416005|38350700005|921011; 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Signed-off-by: Pengfei Li Reviewed-by: Frank Li --- Notes: Change for v2: - refine the commit msg to list all enabled modules. - fix dtbs_check warning arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx91-11x11-evk.dts | 820 ++++++++++++++++++ 2 files changed, 821 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index bd443c2bc5a4..7083f6824e9f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -236,6 +236,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts new file mode 100644 index 000000000000..c58dd4f1e745 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -0,0 +1,820 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; + +#include +#include "imx91.dtsi" + +/ { + model = "NXP i.MX91 11X11 EVK board"; + compatible = "fsl,imx91-11x11-evk", "fsl,imx91"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + rtc0 = &bbnsm_rtc; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-name = "reg_vdd_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vrpi_3v3: regulator-vrpi-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VRPI_3V3"; + gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + vin-supply = <&buck4>; + }; + + reg_vrpi_5v: regulator-vrpi-5v { + compatible = "regulator-fixed"; + regulator-name = "VRPI_5V"; + gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + eee-broken-1000t; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + eee-broken-1000t; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x51>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-sdio; + no-mmc; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX91_PAD_GPIO_IO25__CAN2_TX 0x139e + MX91_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + pinctrl_flexcan2_sleep: flexcan2sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e + MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e + MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e + MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e + MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e + MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e + MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e + MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e + MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e + MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e + MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e + MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_lcdif_gpio: lcdifgpiogrp { + fsl,pins = < + MX91_PAD_GPIO_IO00__GPIO2_IO0 0x51e + MX91_PAD_GPIO_IO01__GPIO2_IO1 0x51e + MX91_PAD_GPIO_IO02__GPIO2_IO2 0x51e + MX91_PAD_GPIO_IO03__GPIO2_IO3 0x51e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3sleepgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1sleepgrp { + fsl,pins = < + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e + MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e + MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e + >; + }; + + pinctrl_sai3_sleep: sai3sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e + MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e + MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e + MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e + MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__PDM_CLK 0x31e + MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e + MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmsleepgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__GPIO1_IO8 0x31e + MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x31e + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + + pinctrl_spdif_sleep: spdifsleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO22__GPIO2_IO22 0x31e + MX91_PAD_GPIO_IO23__GPIO2_IO23 0x31e + >; + }; +};