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Wed, 29 May 2024 12:53:56 +0000 (GMT) From: Minwoo Im To: Keith Busch , Klaus Jensen , Jesper Devantier Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, minwoo.im@samsung.com, gost.dev@samsung.com, Klaus Jensen Subject: [PATCH v4 1/4] hw/nvme: add Identify Endurance Group List Date: Wed, 29 May 2024 21:42:31 +0900 Message-Id: <20240529124234.1430707-2-minwoo.im@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240529124234.1430707-1-minwoo.im@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEJsWRmVeSWpSXmKPExsWy7bCmmW6qaniawZ9OZYsTU8Isbh7YyWSx /+A3VouTjXtYLSYdusZo8ez0AWaLWe/a2SyO9+5gceDwmDLtGrvHuR3n2T02repk83hybTOT R9+WVYwBrFHZNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+Abpu mTlAtygplCXmlAKFAhKLi5X07WyK8ktLUhUy8otLbJVSC1JyCswL9IoTc4tL89L18lJLrAwN DIxMgQoTsjMu/z3IXrBTpGLKwqgGxk6BLkZODgkBE4ndq/eydjFycQgJ7GGUuDnhAAuE84lR 4mLbZ0YI5xujxPa7P5hgWqZ1LYJq2csosf7ASqiW34wSX59dZgapYhNQl2iY+ooFxBYRyJHo X/mdCaSIWaCFUaL73C2wImEBJ4meV++ARnFwsAioSrzcowAS5hWwkfh77SnUNnmJ/QfPgpVz CthKdM15ww5RIyhxcuYTsPnMQDXNW2czg8yXEHjLLnGj9SMbRLOLxOeWyywQtrDEq+Nb2CFs KYnP7/ZC1ZRL/HwziRHCrpA4OOs2G8g9EgL2Eteep4CYzAKaEut36UNElSWO3ILayifRcfgv O0SYV6KjTQhihrLEx0OHmCFsSYnll15D7fGQ6Li8H+wpIYEJjBKvDtVOYFSYheSXWUh+mYWw dwEj8ypGqdSC4tz01GSjAkPdvNRyeBQn5+duYgQnTi3fHYyv1//VO8TIxMF4iFGCg1lJhPfM pNA0Id6UxMqq1KL8+KLSnNTiQ4ymwMCeyCwlmpwPTN15JfGGJpYGJmZmhuZGpgbmSuK891rn pggJpCeWpGanphakFsH0MXFwSjUwqab+C3ZzmMHRMH8h070f/CK9h07kzVkd9a2Q+6Hie4vS GIFD77eePBM0v8WsIewij1fEXlWX2rN1ppMips/fkpV3x/mM+M09j/KDgpyK5GqvPjdnUNpT wdO3Kqm3/mXb5ZTbsU6Ghq+Zdi6LlZWdzmbxd9K88MNz29auPRVdnhsm/utFqmaQmcuEkzX7 3E2W//nUdkNRfOHK7E/hvwJM9Q4F/jKeHHltH9PTDW7LHn6IvKeQ/WPut4URVXOMZgvM2KOl kHa/OOXbqjt/l181WXjgu5T5LIVjgUxJgvcOmX970KD26eIkPosLz5bu9XFc/VtBSvbVtqii b+d+rdfcYfVisuPO1Qv66nkLYpV1o5VYijMSDbWYi4oTAYeqd78lBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNLMWRmVeSWpSXmKPExsWy7bCSvG6KaniawY0mXYsTU8Isbh7YyWSx /+A3VouTjXtYLSYdusZo8ez0AWaLWe/a2SyO9+5gceDwmDLtGrvHuR3n2T02repk83hybTOT R9+WVYwBrFFcNimpOZllqUX6dglcGZf/HmQv2ClSMWVhVANjp0AXIyeHhICJxLSuRaxdjFwc QgK7GSW+Xp/JBJGQlNh3+iYrhC0scb/lCFTRT0aJ06cmgBWxCahLNEx9xQJiiwjkSVx7uYQZ pIgZaLbErItTmUESwgJOEj2v3gF1c3CwCKhKvNyjABLmFbCR+HvtKdQyeYn9B8+ClXMK2Ep0 zXnDDmILAdUsevybHaJeUOLkzCdgu5iB6pu3zmaewCgwC0lqFpLUAkamVYySqQXFuem5xYYF hnmp5XrFibnFpXnpesn5uZsYweGtpbmDcfuqD3qHGJk4GA8xSnAwK4nwnpkUmibEm5JYWZVa lB9fVJqTWnyIUZqDRUmcV/xFb4qQQHpiSWp2ampBahFMlomDU6qBaWKIrEl24YoXpR9UQ8VO 7pvs0H/sn9OsANXH58OmN8yVqGyYeuhbRuijIKnH921SZMyCwntF0naxv5/F9l4pZ//OgE9l Bcv2HHFQ2qrh7ulwz8ZEflX//A8rj2Rv3t/Jf/hVi2T0pW6zS8+2dpk2rd7rulXK593E+/vT EtNfmzywYtpj0M5Tz1p4WF6a63XdrBaGX6ppywKNW9lsRVpv3L5R1nm/6WP1q8vCgf4nuNY1 z+VMSVb2k2VeILpL8JB/UNl8hveCRf98urvnOoU/+GvvHP0+otT7Wn7QK8PlqpdKT5wyy36f +oVt+YSU+U4rFZ1K5rodmjDvpL4h3zNH+TaRX+VV99tOz7c49EVaiaU4I9FQi7moOBEAP1z/ sN4CAAA= X-CMS-MailID: 20240529125356epcas2p1f29357582a7cb7a922f950fb41f0df17 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240529125356epcas2p1f29357582a7cb7a922f950fb41f0df17 References: <20240529124234.1430707-1-minwoo.im@samsung.com> Received-SPF: pass client-ip=203.254.224.34; envelope-from=minwoo.im@samsung.com; helo=mailout4.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.036, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Commit 73064edfb864 ("hw/nvme: flexible data placement emulation") intorudced NVMe FDP feature to nvme-subsys and nvme-ctrl with a single endurance group #1 supported. This means that controller should return proper identify data to host with Identify Endurance Group List (CNS 19h). But, yes, only just for the endurance group #1. This patch allows host applications to ask for which endurance group is available and utilize FDP through that endurance group. Reviewed-by: Klaus Jensen Signed-off-by: Minwoo Im --- hw/nvme/ctrl.c | 22 ++++++++++++++++++++++ include/block/nvme.h | 1 + 2 files changed, 23 insertions(+) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 127c3d2383..18672f6619 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -5629,6 +5629,26 @@ static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n, NvmeRequest *req, return nvme_c2h(n, list, data_len, req); } +static uint16_t nvme_endurance_group_list(NvmeCtrl *n, NvmeRequest *req) +{ + uint16_t list[NVME_CONTROLLER_LIST_SIZE] = {}; + uint16_t *nr_ids = &list[0]; + uint16_t *ids = &list[1]; + uint16_t endgid = le32_to_cpu(req->cmd.cdw11) & 0xffff; + + /* + * The current nvme-subsys only supports Endurance Group #1. + */ + if (!endgid) { + *nr_ids = 1; + ids[0] = 1; + } else { + *nr_ids = 0; + } + + return nvme_c2h(n, list, sizeof(list), req); +} + static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req) { NvmeNamespace *ns; @@ -5744,6 +5764,8 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req) return nvme_identify_nslist(n, req, false); case NVME_ID_CNS_CS_NS_ACTIVE_LIST: return nvme_identify_nslist_csi(n, req, true); + case NVME_ID_CNS_ENDURANCE_GROUP_LIST: + return nvme_endurance_group_list(n, req); case NVME_ID_CNS_CS_NS_PRESENT_LIST: return nvme_identify_nslist_csi(n, req, false); case NVME_ID_CNS_NS_DESCR_LIST: diff --git a/include/block/nvme.h b/include/block/nvme.h index bb231d0b9a..7c77d38174 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -1074,6 +1074,7 @@ enum NvmeIdCns { NVME_ID_CNS_CTRL_LIST = 0x13, NVME_ID_CNS_PRIMARY_CTRL_CAP = 0x14, NVME_ID_CNS_SECONDARY_CTRL_LIST = 0x15, + NVME_ID_CNS_ENDURANCE_GROUP_LIST = 0x19, NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, NVME_ID_CNS_CS_NS_PRESENT = 0x1b, NVME_ID_CNS_IO_COMMAND_SET = 0x1c, From patchwork Wed May 29 12:42:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minwoo Im X-Patchwork-Id: 13678812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78E50C25B75 for ; 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envelope-from=minwoo.im@samsung.com; helo=mailout1.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.036, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Secondary controller list for virtualization has been managed by Identify Secondary Controller List data structure with NvmeSecCtrlList where up to 127 secondary controller entries can be managed. The problem hasn't arisen so far because NVME_MAX_VFS has been 127. This patch separated identify data itself from the actual secondary controller list managed by controller to support more than 127 secondary controllers with the following patch. This patch reused NvmeSecCtrlEntry structure to manage all the possible secondary controllers, and copy entries to identify data structure when the command comes in. Signed-off-by: Minwoo Im --- hw/nvme/ctrl.c | 21 ++++++++++----------- hw/nvme/nvme.h | 14 ++++++++------ hw/nvme/subsys.c | 8 ++++---- 3 files changed, 22 insertions(+), 21 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 18672f6619..7cf1e8e384 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -219,7 +219,6 @@ #define NVME_TEMPERATURE_CRITICAL 0x175 #define NVME_NUM_FW_SLOTS 1 #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB) -#define NVME_MAX_VFS 127 #define NVME_VF_RES_GRANULARITY 1 #define NVME_VF_OFFSET 0x1 #define NVME_VF_STRIDE 1 @@ -5480,14 +5479,14 @@ static uint16_t nvme_identify_sec_ctrl_list(NvmeCtrl *n, NvmeRequest *req) NvmeIdentify *c = (NvmeIdentify *)&req->cmd; uint16_t pri_ctrl_id = le16_to_cpu(n->pri_ctrl_cap.cntlid); uint16_t min_id = le16_to_cpu(c->ctrlid); - uint8_t num_sec_ctrl = n->sec_ctrl_list.numcntl; + uint8_t num_sec_ctrl = n->nr_sec_ctrls; NvmeSecCtrlList list = {0}; uint8_t i; for (i = 0; i < num_sec_ctrl; i++) { - if (n->sec_ctrl_list.sec[i].scid >= min_id) { - list.numcntl = num_sec_ctrl - i; - memcpy(&list.sec, n->sec_ctrl_list.sec + i, + if (n->sec_ctrl_list[i].scid >= min_id) { + list.numcntl = MIN(num_sec_ctrl - i, 127); + memcpy(&list.sec, n->sec_ctrl_list + i, list.numcntl * sizeof(NvmeSecCtrlEntry)); break; } @@ -7144,8 +7143,8 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) if (n->params.sriov_max_vfs) { if (!pci_is_vf(pci_dev)) { - for (i = 0; i < n->sec_ctrl_list.numcntl; i++) { - sctrl = &n->sec_ctrl_list.sec[i]; + for (i = 0; i < n->nr_sec_ctrls; i++) { + sctrl = &n->sec_ctrl_list[i]; nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false); } } @@ -7934,7 +7933,7 @@ static bool nvme_check_params(NvmeCtrl *n, Error **errp) static void nvme_init_state(NvmeCtrl *n) { NvmePriCtrlCap *cap = &n->pri_ctrl_cap; - NvmeSecCtrlList *list = &n->sec_ctrl_list; + NvmeSecCtrlEntry *list = n->sec_ctrl_list; NvmeSecCtrlEntry *sctrl; PCIDevice *pci = PCI_DEVICE(n); uint8_t max_vfs; @@ -7959,9 +7958,9 @@ static void nvme_init_state(NvmeCtrl *n) n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1); QTAILQ_INIT(&n->aer_queue); - list->numcntl = max_vfs; + n->nr_sec_ctrls = max_vfs; for (i = 0; i < max_vfs; i++) { - sctrl = &list->sec[i]; + sctrl = &list[i]; sctrl->pcid = cpu_to_le16(n->cntlid); sctrl->vfn = cpu_to_le16(i + 1); } @@ -8534,7 +8533,7 @@ static void nvme_sriov_post_write_config(PCIDevice *dev, uint16_t old_num_vfs) int i; for (i = pcie_sriov_num_vfs(dev); i < old_num_vfs; i++) { - sctrl = &n->sec_ctrl_list.sec[i]; + sctrl = &n->sec_ctrl_list[i]; nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false); } } diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index bed8191bd5..485b42c104 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -26,6 +26,7 @@ #define NVME_MAX_CONTROLLERS 256 #define NVME_MAX_NAMESPACES 256 +#define NVME_MAX_VFS 127 #define NVME_EUI64_DEFAULT ((uint64_t)0x5254000000000000) #define NVME_FDP_MAX_EVENTS 63 #define NVME_FDP_MAXPIDS 128 @@ -612,7 +613,8 @@ typedef struct NvmeCtrl { } features; NvmePriCtrlCap pri_ctrl_cap; - NvmeSecCtrlList sec_ctrl_list; + uint32_t nr_sec_ctrls; + NvmeSecCtrlEntry sec_ctrl_list[NVME_MAX_VFS]; struct { uint16_t vqrfap; uint16_t virfap; @@ -662,7 +664,7 @@ static inline NvmeSecCtrlEntry *nvme_sctrl(NvmeCtrl *n) NvmeCtrl *pf = NVME(pcie_sriov_get_pf(pci_dev)); if (pci_is_vf(pci_dev)) { - return &pf->sec_ctrl_list.sec[pcie_sriov_vf_number(pci_dev)]; + return &pf->sec_ctrl_list[pcie_sriov_vf_number(pci_dev)]; } return NULL; @@ -671,12 +673,12 @@ static inline NvmeSecCtrlEntry *nvme_sctrl(NvmeCtrl *n) static inline NvmeSecCtrlEntry *nvme_sctrl_for_cntlid(NvmeCtrl *n, uint16_t cntlid) { - NvmeSecCtrlList *list = &n->sec_ctrl_list; + NvmeSecCtrlEntry *list = n->sec_ctrl_list; uint8_t i; - for (i = 0; i < list->numcntl; i++) { - if (le16_to_cpu(list->sec[i].scid) == cntlid) { - return &list->sec[i]; + for (i = 0; i < n->nr_sec_ctrls; i++) { + if (le16_to_cpu(list[i].scid) == cntlid) { + return &list[i]; } } diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c index d30bb8bfd5..561ed04a53 100644 --- a/hw/nvme/subsys.c +++ b/hw/nvme/subsys.c @@ -17,13 +17,13 @@ static int nvme_subsys_reserve_cntlids(NvmeCtrl *n, int start, int num) { NvmeSubsystem *subsys = n->subsys; - NvmeSecCtrlList *list = &n->sec_ctrl_list; + NvmeSecCtrlEntry *list = n->sec_ctrl_list; NvmeSecCtrlEntry *sctrl; int i, cnt = 0; for (i = start; i < ARRAY_SIZE(subsys->ctrls) && cnt < num; i++) { if (!subsys->ctrls[i]) { - sctrl = &list->sec[cnt]; + sctrl = &list[cnt]; sctrl->scid = cpu_to_le16(i); subsys->ctrls[i] = SUBSYS_SLOT_RSVD; cnt++; @@ -36,12 +36,12 @@ static int nvme_subsys_reserve_cntlids(NvmeCtrl *n, int start, int num) static void nvme_subsys_unreserve_cntlids(NvmeCtrl *n) { NvmeSubsystem *subsys = n->subsys; - NvmeSecCtrlList *list = &n->sec_ctrl_list; + NvmeSecCtrlEntry *list = n->sec_ctrl_list; NvmeSecCtrlEntry *sctrl; int i, cntlid; for (i = 0; i < n->params.sriov_max_vfs; i++) { - sctrl = &list->sec[i]; + sctrl = &list[i]; cntlid = le16_to_cpu(sctrl->scid); if (cntlid) { From patchwork Wed May 29 12:42:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minwoo Im X-Patchwork-Id: 13678811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D785C41513 for ; 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envelope-from=minwoo.im@samsung.com; helo=mailout2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.036, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org To prevent further bumping up the number of maximum VF te support, this patch allocates a dynamic array (NvmeCtrl *)->sec_ctrl_list based on number of VF supported by sriov_max_vfs property. Signed-off-by: Minwoo Im --- hw/nvme/ctrl.c | 8 +------- hw/nvme/nvme.h | 5 ++--- hw/nvme/subsys.c | 2 ++ 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 7cf1e8e384..90a58e71bd 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -7863,12 +7863,6 @@ static bool nvme_check_params(NvmeCtrl *n, Error **errp) return false; } - if (params->sriov_max_vfs > NVME_MAX_VFS) { - error_setg(errp, "sriov_max_vfs must be between 0 and %d", - NVME_MAX_VFS); - return false; - } - if (params->cmb_size_mb) { error_setg(errp, "CMB is not supported with SR-IOV"); return false; @@ -8461,7 +8455,7 @@ static Property nvme_props[] = { DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl, params.zasl, 0), DEFINE_PROP_BOOL("zoned.auto_transition", NvmeCtrl, params.auto_transition_zones, true), - DEFINE_PROP_UINT8("sriov_max_vfs", NvmeCtrl, params.sriov_max_vfs, 0), + DEFINE_PROP_UINT16("sriov_max_vfs", NvmeCtrl, params.sriov_max_vfs, 0), DEFINE_PROP_UINT16("sriov_vq_flexible", NvmeCtrl, params.sriov_vq_flexible, 0), DEFINE_PROP_UINT16("sriov_vi_flexible", NvmeCtrl, diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 485b42c104..d8ec4bad6a 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -26,7 +26,6 @@ #define NVME_MAX_CONTROLLERS 256 #define NVME_MAX_NAMESPACES 256 -#define NVME_MAX_VFS 127 #define NVME_EUI64_DEFAULT ((uint64_t)0x5254000000000000) #define NVME_FDP_MAX_EVENTS 63 #define NVME_FDP_MAXPIDS 128 @@ -532,7 +531,7 @@ typedef struct NvmeParams { bool auto_transition_zones; bool legacy_cmb; bool ioeventfd; - uint8_t sriov_max_vfs; + uint16_t sriov_max_vfs; uint16_t sriov_vq_flexible; uint16_t sriov_vi_flexible; uint8_t sriov_max_vq_per_vf; @@ -614,7 +613,7 @@ typedef struct NvmeCtrl { NvmePriCtrlCap pri_ctrl_cap; uint32_t nr_sec_ctrls; - NvmeSecCtrlEntry sec_ctrl_list[NVME_MAX_VFS]; + NvmeSecCtrlEntry *sec_ctrl_list; struct { uint16_t vqrfap; uint16_t virfap; diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c index 561ed04a53..77deaf2c2c 100644 --- a/hw/nvme/subsys.c +++ b/hw/nvme/subsys.c @@ -61,6 +61,8 @@ int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp) if (pci_is_vf(&n->parent_obj)) { cntlid = le16_to_cpu(sctrl->scid); } else { + n->sec_ctrl_list = g_new0(NvmeSecCtrlEntry, num_vfs); + for (cntlid = 0; cntlid < ARRAY_SIZE(subsys->ctrls); cntlid++) { if (!subsys->ctrls[cntlid]) { break; From patchwork Wed May 29 12:42:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minwoo Im X-Patchwork-Id: 13678809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1CE1C25B75 for ; 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Wed, 29 May 2024 12:53:56 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20240529125356epsmtrp2d5418d6fd3b5933b0725e682d48dbe5a~T9suE5hbS1667216672epsmtrp2E; Wed, 29 May 2024 12:53:56 +0000 (GMT) X-AuditID: b6c32a48-ea7ff70000002507-e6-6657256564c3 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id 69.3A.18846.46527566; Wed, 29 May 2024 21:53:56 +0900 (KST) Received: from localhost.dsn.sec.samsung.com (unknown [10.229.54.230]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20240529125356epsmtip25bc1477f69fa5f1f32a9bb55fff374ff~T9st7Iwvf1461914619epsmtip2P; Wed, 29 May 2024 12:53:56 +0000 (GMT) From: Minwoo Im To: Keith Busch , Klaus Jensen , Jesper Devantier Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, minwoo.im@samsung.com, gost.dev@samsung.com, Klaus Jensen Subject: [PATCH v4 4/4] hw/nvme: Expand VI/VQ resource to uint32 Date: Wed, 29 May 2024 21:42:34 +0900 Message-Id: <20240529124234.1430707-5-minwoo.im@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240529124234.1430707-1-minwoo.im@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnk+LIzCtJLcpLzFFi42LZdljTXDdVNTzNYPF1QYsTU8Isbh7YyWSx /+A3VouTjXtYLSYdusZo8ez0AWaLWe/a2SyO9+5gceDwmDLtGrvHuR3n2T02repk83hybTOT R9+WVYwBrFHZNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+Abpu mTlAtygplCXmlAKFAhKLi5X07WyK8ktLUhUy8otLbJVSC1JyCswL9IoTc4tL89L18lJLrAwN DIxMgQoTsjNO/ZvAXrCMv+LYS7MGxjvcXYycHBICJhLLp05l7GLk4hAS2MEo8XnvNyjnE6NE +9FjbHDOx5Zl7DAtszY+h6raySjRfGsPO4Tzm1Fix5zvTCBVbALqEg1TX7GA2CICORL9K0Hi XBzMAi2MEt3nbjGDJIQFHCSOz9jICGKzCKhK/Fi3HCzOK2AjsfDyZDaIdfIS+w+eBYtzCthK dM15ww5RIyhxcuYTsAXMQDXNW2czQ9S/ZJfoaquEsF0kuhf1M0LYwhKvjm+BekFK4vO7vVDz yyV+vpkEVVMhcXDWbaA4B5BtL3HteQqIySygKbF+lz5EVFniyC2opXwSHYf/skOEeSU62oQg ZihLfDx0COoWSYnll15D7fGQWNC+kgkSUhMYJWYsX84+gVFhFpJfZiH5ZRbC4gWMzKsYxVIL inPTU4uNCkzg8Zucn7uJEZwytTx2MM5++0HvECMTB+MhRgkOZiUR3jOTQtOEeFMSK6tSi/Lj i0pzUosPMZoCQ3ois5Rocj4waeeVxBuaWBqYmJkZmhuZGpgrifPea52bIiSQnliSmp2aWpBa BNPHxMEp1cA08bm3wanSxqL1iQWfGaM72zcapRhUqbxhdOyV+hfYbTgvv2Pvr5eNajfv725V ExD0dC68JNvz7Mj5CHU35qU7Li98teT+yk9Sz73PSm15/ur7Z5npgSFirvuFV8je237Hsmrp vdK3q37OuiWx+PKkiROZfHxyhUsCcv88n/5U/kPC3y3r/Xc4d9cdUmOp6E7jfChcMEH2kI/+ g1+e3wvWWnlc/L+fI+ZRe7SunpD6yzg5idO2a9e/kP2/ozS/Z11fryxHwQpb4+WpAUFJF14v MWa4/3jVmQur7B+dmRJyfur59pQVRxguqUkkSU35OKk4rDb+45/uGkuX5F/sO6N+nu20VRFa O+fLL8n00wdFlFiKMxINtZiLihMB3Ibf5CIEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOLMWRmVeSWpSXmKPExsWy7bCSvG6KaniawfNfxhYnpoRZ3Dywk8li /8FvrBYnG/ewWkw6dI3R4tnpA8wWs961s1kc793B4sDhMWXaNXaPczvOs3tsWtXJ5vHk2mYm j74tqxgDWKO4bFJSczLLUov07RK4Mk79m8BesIy/4thLswbGO9xdjJwcEgImErM2PmfsYuTi EBLYzijx9tkDZoiEpMS+0zdZIWxhifstR8BsIYGfjBKfrkqB2GwC6hINU1+xgNgiAnkS114u YQYZxCzQxSgx6+JUsEHCAg4Sx2dsZASxWQRUJX6sWw4W5xWwkVh4eTIbxAJ5if0Hz4LFOQVs JbrmvGGHWGYjsejxb3aIekGJkzOfgC1jBqpv3jqbeQKjwCwkqVlIUgsYmVYxiqYWFOem5yYX GOoVJ+YWl+al6yXn525iBIe1VtAOxmXr/+odYmTiYDzEKMHBrCTCe2ZSaJoQb0piZVVqUX58 UWlOavEhRmkOFiVxXuWczhQhgfTEktTs1NSC1CKYLBMHp1QDU2XQ59aS+Dt9LffX+OQKnD+r e+uZfH9LauH9h4J3lCNmsxUtbEpkKpC4ealIOqBljv7pJhHbIwFGOZH7g9b9imHVmSOwe2PO i4W31ROO+/KfV3zG2rh+m7dD5Sy/6Wmtu24sO9WbICVkFe7tLLbEfsb85y6dy3XEDx1M/yzT GCOzVeIG88U7Xv/2HPjmnCofm83LEnpmlW/zxydxbXssZnLFnfq5KY5x5YQdr891qQvs/rR8 fryNafRf4yl9h4p+H2S1ijTd8qcx4O4yjhjfIx72qX777sUwbT7+9nn/pgS+uc8uJeXsuHLp 9x2/jExx85qCC3scu+69jJzKsqWvUSbhjeWDg+Hr5N7M5vjSp8RSnJFoqMVcVJwIANtkL9/a AgAA X-CMS-MailID: 20240529125356epcas2p218eee16c01039ef5f0d5c8706825485d X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240529125356epcas2p218eee16c01039ef5f0d5c8706825485d References: <20240529124234.1430707-1-minwoo.im@samsung.com> Received-SPF: pass client-ip=203.254.224.34; envelope-from=minwoo.im@samsung.com; helo=mailout4.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.036, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org VI and VQ resources cover queue resources in each VFs in SR-IOV. Current maximum I/O queue pair size is 0xffff, we can expand them to cover the full number of I/O queue pairs. This patch also fixed Identify Secondary Controller List overflow due to expand of number of secondary controllers. Reviewed-by: Klaus Jensen Signed-off-by: Minwoo Im --- hw/nvme/ctrl.c | 8 ++++---- hw/nvme/nvme.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 90a58e71bd..b957debdc3 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8460,10 +8460,10 @@ static Property nvme_props[] = { params.sriov_vq_flexible, 0), DEFINE_PROP_UINT16("sriov_vi_flexible", NvmeCtrl, params.sriov_vi_flexible, 0), - DEFINE_PROP_UINT8("sriov_max_vi_per_vf", NvmeCtrl, - params.sriov_max_vi_per_vf, 0), - DEFINE_PROP_UINT8("sriov_max_vq_per_vf", NvmeCtrl, - params.sriov_max_vq_per_vf, 0), + DEFINE_PROP_UINT32("sriov_max_vi_per_vf", NvmeCtrl, + params.sriov_max_vi_per_vf, 0), + DEFINE_PROP_UINT32("sriov_max_vq_per_vf", NvmeCtrl, + params.sriov_max_vq_per_vf, 0), DEFINE_PROP_BOOL("msix-exclusive-bar", NvmeCtrl, params.msix_exclusive_bar, false), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index d8ec4bad6a..b0b2739802 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -534,8 +534,8 @@ typedef struct NvmeParams { uint16_t sriov_max_vfs; uint16_t sriov_vq_flexible; uint16_t sriov_vi_flexible; - uint8_t sriov_max_vq_per_vf; - uint8_t sriov_max_vi_per_vf; + uint32_t sriov_max_vq_per_vf; + uint32_t sriov_max_vi_per_vf; bool msix_exclusive_bar; } NvmeParams;