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a=openpgp-sha256; l=1353; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=XJAR3RhvR6FBsC5FKjrD7WCfWMohl/ns3r5JO/+tsoQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVz/kn/rVhKP/nSfnxh7HbhW6UrixRpuSxntJE vrqc8YRV/OJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlc/5AAKCRCLPIo+Aiko 1cl2B/9JiJiHKmCt/kp2lc1Bs2Aj198PlJeFrJFQRKGYVfiuJGiXG3SRFp5GScaGofluy5AYMuh TL2t/QwGkPjENIJ3VgpMmQuxKe94gTcrMS8JmBDdyfadRp1WzfMgjJPyf94SzDqjhYryv7FvvGi OK4huUdszexdL/AX+AjsWpz4PRLKoXz8DwdQt/1gj6MNBYTd8BRqFLWsfLENFTERDfGIZc/ugTh LaLwcKoGaCzrh/5kwCfkcGdEfLY+WnPamlodKiidwhBLNg9rfZsFvaAc3PIC8aYyR7CDs8kZ894 ppjyoyPVeqQ6dVQ+ooG6EqMbtUCVty6X9Fwx0G8urberEgb3 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The only platform remaining in qcom,gcc-other.yaml is MDM9607. Drop the stale mentioning of gcc-msm8953.h include and rename the schema file accordingly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/{qcom,gcc-other.yaml => qcom,gcc-mdm9607.yaml} | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml similarity index 87% rename from Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml rename to Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml index 7d05f0f63cef..1264f3d55761 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only %YAML 1.2 --- -$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml# +$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller @@ -15,7 +15,6 @@ description: | domains. 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Wed, 29 May 2024 07:47:04 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:00 +0300 Subject: [PATCH v2 02/14] dt-bindings: clock: qcom,gcc: sort out power-domains support Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-qcom-gdscs-v2-2-69c63d0ae1e7@linaro.org> References: <20240529-qcom-gdscs-v2-0-69c63d0ae1e7@linaro.org> In-Reply-To: <20240529-qcom-gdscs-v2-0-69c63d0ae1e7@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Robert Marko , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=26891; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=bPqr/tmpdzAZE+dapnS+SoTmYdokt2fvmiYpWrU8c/w=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVz/kJtry00AUZn3s5bIVqNege8rWx9uZgCVYn JWhepWRF/OJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlc/5AAKCRCLPIo+Aiko 1RqtB/96ZWeombh7DDgl1sv0r9qJDIecO/ukfzJe9xJIbh8qaK5Gxx1PBS9xmsFOPO2LZ/ZOGSD dLOyKpTVR2hNudWn1Bqg3dqoCxtSoq/Df+gYoGYl7yW/1J45M8YcqPZFL9Fh1QCl/lK1W74u6RH BPf57wEzcSOwDOxthPOYEXtLR8q5FQkGbkiIQ4/k7grdTs1qC7xZiv64oe8BojKEYdeK2XF6+q1 3OGxSmkKonu5O1Q3gkoo6Vv/bHD2zsnYzhzeb0g9NLUvj8bJhwz3w/0aPIov1hY77piPegfXC+h lX9agy8RBy4vdcVVpz+wg1TZQ0sie0I1JFB6tPa3XdkCpv0f X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On some of Qualcomm platforms the Global Clock Controller (GCC) doesn't provide power domains. Move requirement for the '#power-domain-cells' out of the common qcom,gcc.yaml into individual schema files. For the platforms that do not provide power-domains, explicitly forbid having the '#power-domain-cells' property. Suggested-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,gcc.yaml | 1 - Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml | 3 ++- Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml | 1 + Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml | 1 + 46 files changed, 53 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 19211176ee0b..27df7e3e5bf3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -69,6 +69,8 @@ properties: const: 1 deprecated: true + '#power-domain-cells': false + required: - compatible @@ -81,7 +83,6 @@ examples: reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; thermal-sensor { compatible = "qcom,msm8960-tsens"; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml index d84608269080..0a0a26d9beab 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml @@ -51,6 +51,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml index fb3957d485f9..012048921f92 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml @@ -34,6 +34,8 @@ properties: - const: xo - const: sleep_clk + '#power-domain-cells': false + required: - compatible @@ -45,7 +47,6 @@ examples: compatible = "qcom,gcc-ipq4019"; reg = <0x1800000 0x60000>; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; clocks = <&xo>, <&sleep_clk>; clock-names = "xo", "sleep_clk"; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml index af5d883cfdc8..4d2614d4f368 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml @@ -36,6 +36,8 @@ properties: - const: xo - const: sleep_clk + '#power-domain-cells': false + required: - compatible - clocks @@ -51,7 +53,6 @@ examples: clocks = <&xo>, <&sleep_clk>; clock-names = "xo", "sleep_clk"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml index 93f3084b97c1..a71557395c01 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml @@ -46,6 +46,8 @@ properties: allOf: - $ref: /schemas/thermal/qcom-tsens.yaml# + '#power-domain-cells': false + required: - compatible - clocks @@ -65,7 +67,6 @@ examples: clock-names = "pxo", "cxo", "pll4"; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; tsens: thermal-sensor { compatible = "qcom,ipq8064-tsens"; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml index 2d44ddc45aab..38b9e4283900 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -39,6 +39,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml index 1264f3d55761..d7da30b0e7ee 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml @@ -27,6 +27,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml index c9e985548621..e03b6d0acdb6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml @@ -34,6 +34,8 @@ properties: - const: pxo - const: cxo + '#power-domain-cells': false + required: - compatible @@ -47,7 +49,6 @@ examples: reg = <0x900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; clocks = <&pxo_board>, <&cxo_board>; clock-names = "pxo", "cxo"; }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml index b91462587df5..ce1f5a60bd8c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml @@ -42,6 +42,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml index ad84c0f7680b..258b6b93deca 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml @@ -48,6 +48,7 @@ properties: required: - compatible + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml index fe9fd4cb185f..fe1f5f3ed992 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml @@ -42,6 +42,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml index 1927aecc86bc..929fafc84c19 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml @@ -41,6 +41,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml index 62d6f1fe1228..cd49704dcb95 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml @@ -49,6 +49,7 @@ required: - clocks - clock-names - vdd_gfx-supply + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml index 8f0f20c1442a..6b9c1d198b14 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml @@ -35,6 +35,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml index 97523cc1ecfb..013fd074a8d5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml @@ -50,6 +50,7 @@ properties: required: - compatible + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml index 58f7fb22c5c4..abae658c0ed9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml @@ -38,6 +38,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml index c9bec4656f6e..38c4c8c61b3a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml @@ -33,6 +33,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml index 7bc6c57e4d11..94755465c1fb 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -40,6 +40,7 @@ properties: required: - compatible + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml index 7aae21a76690..1847bbeaa9d1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml @@ -40,6 +40,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml index c4ca08d9ad5a..4e4f68b9f6d2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml @@ -51,6 +51,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml index a1085ef4fd05..b4784ecaf58d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml @@ -40,6 +40,7 @@ required: - clocks - clock-names - power-domains + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml index 5681e535fede..5cfde8a4de4e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml @@ -65,6 +65,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml index 52e7412aace5..724ce0491118 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml @@ -40,6 +40,7 @@ properties: required: - compatible + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml index 0595da0e8a42..ef0a20456e8a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml @@ -35,6 +35,7 @@ properties: required: - compatible + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml index 428e954d7638..30819f3d85c6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml @@ -34,6 +34,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml index 523e18d7f150..915449228668 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -39,6 +39,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml index a5ad0a3da397..ecb69c707f09 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml @@ -33,6 +33,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml index 8e37623788bd..a5a29dc75ae1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml @@ -33,6 +33,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml index d1b26ab48eaf..2280b859b2ad 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml @@ -35,6 +35,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml index 58ccb7df847c..1dcf97c0c064 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml @@ -34,6 +34,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml index 5d77c092be5b..979ff0a8bf68 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml @@ -36,6 +36,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml index b4fdde71ef18..594e87f5ba09 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml @@ -55,6 +55,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml index 75259f468d54..d848361beeb3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -49,6 +49,7 @@ required: - compatible - clocks - clock-names + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index 788825105f24..513d6fd89249 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -35,7 +35,6 @@ required: - reg - '#clock-cells' - '#reset-cells' - - '#power-domain-cells' additionalProperties: true diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml index ef84a0c95f7e..489d0fc5607c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml @@ -33,6 +33,8 @@ properties: - description: UNIPHY RX clock source - description: UNIPHY TX clk source + '#power-domain-cells': false + required: - compatible - clocks @@ -58,6 +60,5 @@ examples: <&uniphy_tx_clk>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml index 718fe0625424..adc30d84fa8f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -30,6 +30,8 @@ properties: - description: PCIE 2lane x1 PHY pipe clock source (For second lane) - description: USB PCIE wrapper pipe clock source + '#power-domain-cells': false + required: - compatible - clocks @@ -47,7 +49,6 @@ examples: <&pcie_2lane_phy_pipe_clk_x1>, <&usb_pcie_wrapper_pipe_clk>; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 944a0ea79cd6..ec349e279480 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -33,6 +33,8 @@ properties: - description: PCIE30 PHY3 pipe clock source - description: USB3 PHY pipe clock source + '#power-domain-cells': false + required: - compatible - clocks @@ -57,6 +59,5 @@ examples: <&usb3phy_0_cc_pipe_clk>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml index d712b1a87e25..86befef02650 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -31,6 +31,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml index 0f641c235b13..addbd323fa6d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml @@ -46,6 +46,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml index 98921fa236b1..567182aba300 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml @@ -41,6 +41,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml index 5953c8d92436..0ac92d7871e1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml @@ -32,6 +32,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml index 295d4bb1a966..147b75a21508 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml @@ -31,6 +31,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml index 0eb76d9d51c4..4d7bbbf4ce8a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml @@ -30,6 +30,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml index 0c706de31cf1..d83b64dcce4f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml @@ -34,6 +34,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml index b54761cc8674..976f29cce809 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml @@ -35,6 +35,7 @@ properties: required: - compatible - clocks + - '#power-domain-cells' allOf: - $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml index 14a796dbf8bc..5951a60ab081 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml @@ 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,gcc-mdm9615.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml new file mode 100644 index 000000000000..418dea31eb62 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains. + + See also:: + include/dt-bindings/clock/qcom,gcc-mdm9615.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + enum: + - qcom,gcc-mdm9615 + + clocks: + items: + - description: CXO clock + - description: PLL4 from LLC + + '#power-domain-cells': false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + clock-controller@900000 { + compatible = "qcom,gcc-mdm9615"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&cxo_board>, + <&lcc_pll4>; + }; +... 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Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 11e60b74c3c9..178a3b424670 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -684,7 +684,6 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-apq8064", "syscon"; reg = <0x00900000 0x4000>; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; clocks = <&cxo_board>, <&pxo_board>, From patchwork Wed May 29 14:47:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679038 Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BDCB17DE09 for ; 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Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8660.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi index 455ba4bf1bf4..a66c474cd1aa 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -113,7 +113,6 @@ tlmm: pinctrl@800000 { gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8660"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&pxo_board>, <&cxo_board>; From patchwork Wed May 29 14:47:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679039 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 710EC17F36E for ; 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Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 922f9e49468a..a9c6d2dbb460 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -129,7 +129,6 @@ msmgpio: pinctrl@800000 { gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8960"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&cxo_board>, From patchwork Wed May 29 14:47:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679040 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E2A91802B6 for ; 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a=openpgp-sha256; l=834; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=uKNrIp4viLGzK6BkL6K9w5oOIHrhcRnBTuSiYbEFQRc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVz/lGa0oUyHGlTplYCLm8gyadkAUiHdWEMPk1 UoB9ApWpc2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlc/5QAKCRCLPIo+Aiko 1X66B/4lbabGfq1tYTyadR39KhgQ0Sla22IOZcqOtwy+h1zftMjW7qJSJbAmuhTZIPlmDM2AMZX /BBthChJXZMQUNZ5ZvYRBlRcgVN1q6UjWW9iwfNDus9L3IdDIlXWBFl1SN4Uv04C78Bozwb0rUH f/548fFhxLwK7KhpLZK6Kmn3SK3WhndkvWhlf4Qf1zMIdqg9MA+TOdYimb4Tesk/4p2vzkj7bPY Nbm4oeEbaDBn9L8rKxJurFjSxPdZ4hJVb2FU8liSmoAoXBrT4mTXhNwIn5bsZsMU9bp+mT3C79N OVn72Uk5DdYmoEqYJr6inDaU0O82kKl1I3C5EDj4M/uCNjhi X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On IPQ4019 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 0fb65f2bbcdf..56415ab34083 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -187,7 +187,6 @@ intc: interrupt-controller@b000000 { gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq4019"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x1800000 0x60000>; clocks = <&xo>, <&sleep_clk>; From patchwork Wed May 29 14:47:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679041 Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3DC5180A8B for ; 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Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index f128510d8445..12cf85441a0b 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -519,7 +519,6 @@ gcc: clock-controller@900000 { reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; tsens: thermal-sensor { compatible = "qcom,ipq8064-tsens"; From patchwork Wed May 29 14:47:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679042 Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4DD5181B80 for ; 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a=openpgp-sha256; l=813; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=HJLaCV8kZeQsHgpVRROJnMjh9Abjsmo5qtkKQDyGFFM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVz/lhJHnhkiyUTgo58PJib3j9FrnjcDsRw0gK FMocrWoojeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlc/5QAKCRCLPIo+Aiko 1Tw+CACySY0s7eo0HUEnEvAm6Z/5r9Q7AgJw4mHiTRxx2GamFY6GDsMN2/azZG01/W+BfXW4jCi wjm2yMMn2OAtRx5bzj8YO7QwL116DmGOCTsTajiiLhGJZRcDd+Qp5wMgjcO0ER/YuhFo5kZrmS2 hTLue3bt2kVL4gUAfXk8EHej6g1tlQN3mM6uY0bHc1wQnbMWG2sCb8j7tvKPMK9WjbNnhpNR/Rt 3FEfZJPEc4IcvcCGVAH1dNZs60PoNGySckuXuSJEs5CDqN0oo1jHnWhENz8idpYH+R8XWTMk/X2 QxpdCEMN230/Z0vK9M3NMeE+yQfu4JBmwAJ67r04w+jbcV+E X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On MDM9615 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi index 34c60994d026..573feb3218c3 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -102,7 +102,6 @@ msmgpio: pinctrl@800000 { gcc: clock-controller@900000 { compatible = "qcom,gcc-mdm9615"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&cxo_board>, From patchwork Wed May 29 14:47:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679043 Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82C72181BBA for ; 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a=openpgp-sha256; l=728; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=8S+6nH4nNGx6YH6EGxuio5jjv/mOFbibmmgemtR1wWY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVz/ls6mHbeMql8Y/p1rvH9IlWbYrfAlIaY75L dAxf7yHLxmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlc/5QAKCRCLPIo+Aiko 1TC0CACMV4T/lO6KGuIdNUR+TtBrrlhZSuSSOzS2r1YOPvq2l+z6UAqhbTWl2uzWCYrp7NjoYz1 KPGiIK8Intt5bNqZFX6RX1phr1uXdDxeX0c7IcudtL46Ia+pEI7ah696cUc75HYjOrr1DreQ0Qp 6OE36mV2s+Q8d/jl8uJtThrM4mDMjV98S8V2CjWlBAQk0jc29tYwzYDHcVGQr5FVKQSVDSCfcHN jkx5ielaNYu2/6qM1YSs5f090CYO94zVbbRylCeiCMx5OjGQmf7OUNUOmYN1X0gl/spbRbX8u1i 2YxfxiLNrGhxbJnXu0MpTiDOY/D5ij+29N4aAcq0B1Ry2jfo X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On IPQ5018 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 32b178b639f0..7e6e2c121979 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -179,7 +179,6 @@ gcc: clock-controller@1800000 { <0>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; tcsr_mutex: hwlock@1905000 { From patchwork Wed May 29 14:47:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679044 Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FC01181D0B for ; Wed, 29 May 2024 14:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 29 May 2024 07:47:11 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2e98c45df0csm3791951fa.68.2024.05.29.07.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 07:47:11 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:09 +0300 Subject: [PATCH v2 11/14] arm64: dts: qcom: ipq5332: drop #power-domain-cells property of GCC Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-qcom-gdscs-v2-11-69c63d0ae1e7@linaro.org> References: <20240529-qcom-gdscs-v2-0-69c63d0ae1e7@linaro.org> In-Reply-To: <20240529-qcom-gdscs-v2-0-69c63d0ae1e7@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Robert Marko , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=766; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=PEHi7ElPElAQh4wpEEgIk9SSCUfmS0J4zLyn6bxTemU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVz/mRDt0AMJZqMVl/b8bAz7RVeHcmiPgq6uEl lPnCg6XBAOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlc/5gAKCRCLPIo+Aiko 1T5YCACco0POIcKCzu0sS/jEmLLULHh2w/LZ5e8eMvMidHYOre9vmjPu9VdpdFRUXuJDFV9oZLa NK17p9gny79n2SOkiEd+YBmQ6uyZBL8+4lx2SaS/GoRh0uy8o3TSchqHwNcFAmWD+VARfGZ+eEn kOr/Wtq4Onnu67cK1gFpATKSe+lmIi9T6u9LK2aCh+vSP9F9tOinJu6K13bmoDRMCgPemwsyzCE b7+GgpkavEJmXnlqWXabApuuSr06RfD8qGCvn2k25/39Wb7EW8jJ8b6xe5V5YpOmERsurbopWE7 oRwZmplnGMcjAqBweLwTz/tbJ1HHKXDbT+2Ssgvz7UKOxHQx X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On IPQ5332 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 770d9c2fb456..573656587c0d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -208,7 +208,6 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; clocks = <&xo_board>, <&sleep_clk>, <0>, From patchwork Wed May 29 14:47:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679045 Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 419C21836CA for ; Wed, 29 May 2024 14:47:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp-sha256; l=728; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=l9/pjpwSgGhOfTvCCVgGXrF5ytqftHSPNCBAeSrsRJw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVz/m9fbxT42WuFyPW7QGWT4BDkthauaUC8Z3R X5pimtbeN+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlc/5gAKCRCLPIo+Aiko 1WfzB/wPvAM008paf09rL8lePXHSYRgKJvSjQqQvncraTGjSQsxci13/FCxjyllgAykgRnMV4Th 9vKco4HLAfKtMq6uREBPmLUsBXzFauxGLjVaJgYFjAsD6RmJACkJBOqlRmXqd4Tz/eEPJYzbtj4 xDk+ybYUPlRyNRh03lETGWOiD/uLTwfR5oYVu9NZ496Kt/NxnlBkWkznwbaB662sexiP6fXv5wK mnDKZaI3DGJmoTiQ8sz4EwVVPBjkMqWkI/UyOyz+ASy2r4tta8qn7tUqAc+00gdusac667mDwii z0SBeTy9dzN+9YoMkSlI00cxJKrdRmFupNgaCB5Vg/WnhP/1 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On IPQ9574 the Global Clock Controller (GCC) doesn't provide power domains. Drop the #power-domain-cells property from the controller device node. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index ded02bc39275..d21937b09b4b 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -315,7 +315,6 @@ gcc: clock-controller@1800000 { <0>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; tcsr_mutex: hwlock@1905000 { From patchwork Wed May 29 14:47:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679046 Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 164E91836E4 for ; Wed, 29 May 2024 14:47:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 29 May 2024 07:47:13 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2e98c45df0csm3791951fa.68.2024.05.29.07.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 07:47:12 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:11 +0300 Subject: [PATCH v2 13/14] arm64: dts: qcom: ipq6018: fix GCC node name Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-qcom-gdscs-v2-13-69c63d0ae1e7@linaro.org> References: <20240529-qcom-gdscs-v2-0-69c63d0ae1e7@linaro.org> In-Reply-To: <20240529-qcom-gdscs-v2-0-69c63d0ae1e7@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Robert Marko , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=759; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=XAt6DL1VR9hVvuY+93ZuaPQtdbqMKNXUv5SdCXSc/Gk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVz/mo7DOZ24IcjHMnwKdD9EIgRuh835+zXHuz 8wUO7QPMciJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlc/5gAKCRCLPIo+Aiko 1WoxCACd8LgA7msfrqZUx/eJhT15wHk6itqVWHjmgo9yCaHRjrdx7h/ObJ1Ns209J/6TlQp/PaT 4mCCtbzMXocLGVq3s6Ht4YPYAU/rQTXSvbpyoXOsf1ofRjPAGB55X913pYeMsdIwr3KlMu7Yi0B LTzIEyZRd9WdvfRQKusxhpca0w5kCzgbx87/hlc6MXXmK9h97HrkP9r5CNxlc3yAzhaEeCDicpg 7qZtPYxyVy/uvUbvdba+q22xF8BmqMgHTIR5TTDO63cE0xWRIH+Urj5TPCvFo6uVjpY42eJ9/Jt huISK9ewri28gQInf8iRejl5qZpWC56PulJ1RLtQh9oznIaw X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Device nodes should have generic names. Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 17ab6c475958..a84cf62d843c 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -396,7 +396,7 @@ qpic_pins: qpic-state { }; }; - gcc: gcc@1800000 { + gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq6018"; reg = <0x0 0x01800000 0x0 0x80000>; clocks = <&xo>, <&sleep_clk>; From patchwork Wed May 29 14:47:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13679047 Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDC34184112 for ; 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Wed, 29 May 2024 07:47:14 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2e98c45df0csm3791951fa.68.2024.05.29.07.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 07:47:13 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 29 May 2024 17:47:12 +0300 Subject: [PATCH v2 14/14] arm64: dts: qcom: ipq8074: fix GCC node name Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240529-qcom-gdscs-v2-14-69c63d0ae1e7@linaro.org> References: <20240529-qcom-gdscs-v2-0-69c63d0ae1e7@linaro.org> In-Reply-To: <20240529-qcom-gdscs-v2-0-69c63d0ae1e7@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Robert Marko , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=737; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=rRrgn9wRVOiElWPDaUjrdPE8GcJ80QnHEQvUPT4yYv8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmVz/mI0ik9cKZl/9SuqJ+p8yQWhrIMDSNMV0OP fuaSU3f/BeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZlc/5gAKCRCLPIo+Aiko 1WD+B/9euLN7JRxLEjwdqITHOmrE/YulvXTtO2q7Q/Jd+9OO3nBBX7EKmNtb1HVb5xaLjsm1sZm 1hJOcvuuyT+AcMaLiZ6SRKN8Yg1P6WBR1K0BCBc0P+mdoDJ1tM6n7QgatxD4TwlPm77HASxJ5LP WK93PR127/AEP0iq0og8tXg0Pc6oOLQ/+KwlxLHcDnngFWVVXZteTl/l39R5J7iJ9eY8SCoPCBD 5Eq7G/JvZkzHLPL5oJC7ur+F4ho/JcPKMFGafh1rKZnoQcxYjhSdVwp/fIpa7ePGpl+pUz6WsGp dUA6ex8ME/3qOH9U4UN4+6Qu8xl5Nr0TsUUtNgybI2TtRock X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Device nodes should have generic names. Use 'clock-controller@' as a GCC node name instead of a non-generic 'gcc@'. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5d42de829e75..27cf8d50f254 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -363,7 +363,7 @@ qpic_pins: qpic-state { }; }; - gcc: gcc@1800000 { + gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; clocks = <&xo>,